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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Ok. Please allow me to clarify my description.=20 "high memory" in this context means the memory region just below the less t= han 4GiB DRAM limit. In a platform BIOS, it means the memory just below TOL= UD (Top of Low Usable DRAM). Usually, the BIOS will reserve a chunk of memory just below TOLUD, includin= g ReservedMemory, ACPI-NVS, ACPI-Reclaim, RuntimeData, RuntimeCode. As such= the OS can use the reset memory as a continuous memory region. "low memory" in this context means the memory region below the "high memory= " defined above. From OS perspective, there will be a hole in the continuou= s memory region. Technically, OS shall handle that. But the best practice t= old us we should avoid that as much as possible. We have experience that if= we put too many holes, some OSes will refuse to boot. From OS perspective,= the BIOS should put all BIOS-reserved memory together. Here, the initial mailbox is in "low memory", because we cannot predict how= many virtual-DRAM the VMM will allocate for the OVMF. We cannot predict wh= ere is the TOLUD. And we have to put the final mailbox (reserved) to "high memory" to avoid c= reating a hole for OS. If you look at the whole firmware code, relocation is quite usual design pa= ttern in firmware. For example, PEI HOB, SMM init, CPU AP Loop, ACPI table,= BootScript, etc. Thank you Yao Jiewen > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Gerd > Hoffmann > Sent: Friday, October 15, 2021 1:46 PM > To: Yao, Jiewen > Cc: devel@edk2.groups.io; Xu, Min M ; Ard Biesheuvel > ; Justen, Jordan L = ; > Brijesh Singh ; Erdem Aktas > ; James Bottomley ; Tom > Lendacky > Subject: Re: [edk2-devel] [PATCH V2 21/28] OvmfPkg: Update PlatformPei to > support TDX >=20 > Hi, >=20 > > The original mailbox location is in low memory. If we do not relocate > > to high memory, then the OS will see a hole in low memory. >=20 > Well, both low and high memory to be exact. qemu maps the whole > firmware image below 4G, and mirrors the topmost 128k (including > memfd + reset vector) below 1M. >=20 > Given that TDX starts the processor in 32bit mode, so it doesn't need > the 16bit entry @ f000:fff0, I assumed TDX completely ignores the low > memory mapping and uses only the high memory mapping. >=20 > So you are telling me this is not the case? >=20 > take care, > Gerd >=20 >=20 >=20 >=20 >=20