From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web10.36456.1639542732891168425 for ; Tue, 14 Dec 2021 20:32:13 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@intel.com header.s=intel header.b=LxKpqg5Z; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: zhiguang.liu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639542732; x=1671078732; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=1I0OLZLApufckssDAN8rpX9ERZ8WImQTz8jeH4hdg8k=; b=LxKpqg5ZlFj+weAdNk0M7gTliyAMgbWQqspKCv9d88KkdnVF7kndk4SK 5elsJHj3F4s8ZvtEfMQjy3DaVGqi1aD0IL6QdQhRBOHoiVleMmwpLdKeh jyIu/QZVwJ1MtIWSkPwowDXYDvecfW+IkKIUNLocF8sPYhReowUxhCxEX LGoenjeTEBQ5/HzNc4/d2IHzp/tCJly4TlLmbDhoQ/uv7ABivTEkjuWp/ Nguma/i8/NswtY+TeK/DTR0xMpRIeLEjOBL4vB0LUs74eoaR4LmnHrK/e dZUpiKgdUIggwf3sk7xTqXBd88SXmoBNnZlPim77jz73jhc/kmJ6oMjSU w==; X-IronPort-AV: E=McAfee;i="6200,9189,10198"; a="237881576" X-IronPort-AV: E=Sophos;i="5.88,207,1635231600"; d="scan'208";a="237881576" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Dec 2021 20:32:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,207,1635231600"; d="scan'208";a="584044382" Received: from orsmsx602.amr.corp.intel.com ([10.22.229.15]) by fmsmga004.fm.intel.com with ESMTP; 14 Dec 2021 20:32:12 -0800 Received: from orsmsx608.amr.corp.intel.com (10.22.229.21) by ORSMSX602.amr.corp.intel.com (10.22.229.15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20; Tue, 14 Dec 2021 20:32:11 -0800 Received: from ORSEDG601.ED.cps.intel.com (10.7.248.6) by orsmsx608.amr.corp.intel.com (10.22.229.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.20 via Frontend Transport; Tue, 14 Dec 2021 20:32:11 -0800 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (104.47.55.102) by edgegateway.intel.com (134.134.137.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2308.20; Tue, 14 Dec 2021 20:32:11 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HbQtHiJBjdwU4dm5XqoZqVhoMBRmAhuWdRVoZvI4dERzXamch+u9esjl0z1bcgHsUKihPO1MfEknpzPQjS2UC4Ri/nVUiukE9eYbrbv3sIRdV7jdlojwrv2NYkuXAape2gj71X0N40kiC5YskpsCdLK8+M75NkvZqSskJQ8nO+dLvoZRoPSvvyCzuu4GS38L7EOWJHLwIUIghG0AhUYEMZn26fz2NDzY+QB9KYPzy9tPAexyBS/blTXxX2oeMQLn3cVZ2DqzHIS7LnqXWF9ViCGbby2ThJcgTUgmR70hXaeeV78IxbtDN+JmRprW0JiT0ukX1du8NjPOBFmz9OY+8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=k2jG6ipmOQHUWslrfdaBGjV8VY4kI7CgMqG9I5slKak=; b=GqJFMcB0wyifSyBoekCxI/Q0WytbJdNioHWu4ZXZ812RXJFP5m8hIqvp2CnhKqddXUYUp/kcUAAvlQFtBsBzD2vNQRUhXVJTVZM0nSP9VthOLpjckhU9LlOxxhBTgZaRPtZA5cg6Jn524X0rympCxtkzir/+vZTLuJAdM58KOdNKPg+5+IuMTqamj2NqTzVQnL2vRjU3OMwoDpeoiBzGY6PsWrVuOX/LNf+AyDMdwcdjSS8+sFHInpISD9S/MTZLr34P0gqnhVaIzcMWudTR6NVXpSHQjX4qXZpWDOqFhVQxdfEvsp6o21pZ/YvoUD3dOahLrA3P9eb5KMpTvPTExw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=k2jG6ipmOQHUWslrfdaBGjV8VY4kI7CgMqG9I5slKak=; b=B4b9I3sKOQrJXTLMnICepmx/vnV6I339QSlatAVX350hD7xg+o6m0sMYfuprtl0UFs5nLEYRBG9qk2ROlNEX8zZCR6SIC3XtdHHOowqty3gQ5WsqRC/Dv5K/hiQM36H3JVbfnI+dBTvKwsYjwdt/NV1Dn+ChaGzpIH+695ZeNqs= Received: from PH0PR11MB5048.namprd11.prod.outlook.com (2603:10b6:510:3d::14) by PH0PR11MB5029.namprd11.prod.outlook.com (2603:10b6:510:30::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4778.11; Wed, 15 Dec 2021 04:32:10 +0000 Received: from PH0PR11MB5048.namprd11.prod.outlook.com ([fe80::7890:f8d1:fc4a:87f3]) by PH0PR11MB5048.namprd11.prod.outlook.com ([fe80::7890:f8d1:fc4a:87f3%3]) with mapi id 15.20.4778.018; Wed, 15 Dec 2021 04:32:10 +0000 From: "Zhiguang Liu" To: "Chu, Maggie" , "devel@edk2.groups.io" CC: "Gao, Liming" , "Kinney, Michael D" Subject: Re: [PATCH] MdePkg: Add registers of boot partition feature Thread-Topic: [PATCH] MdePkg: Add registers of boot partition feature Thread-Index: AQHX7APNde7iIX9dZ06O6gWWzGJSVKwzALJQ Date: Wed, 15 Dec 2021 04:32:10 +0000 Message-ID: References: <20211208071749.1990-1-maggie.chu@intel.com> In-Reply-To: <20211208071749.1990-1-maggie.chu@intel.com> Accept-Language: en-US, zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 91ec98e2-cb43-45de-cdd6-08d9bf83dc29 x-ms-traffictypediagnostic: PH0PR11MB5029:EE_ x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:9508; x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: +hpNWCT+F+vXmp0xzd0R4yQ6CmBaY1+Rd8OHwhDjFEjMZ13+8H812XlPIAbwe+iGBbyz8K6WOS6WDBfsezhYvg88383Wj4nHwkxcW/u1x1ctL56zg4VcxOPE5NxRvvHejyf0yuNRf+1tkHnfHXB9KFTa2DSW0zveCnJvyfpBYb+1IOIKoJII0PkhU8uNtVO/FnkkxpCphgpJfiu9Yy9XOsZTHa59Wa96cVs38ASoxsqCCX6C0E2VwmO6cK11EoAwfSfcTzm1ssgf309GaY7R70lMDdi7wxBMuakXFR30jiKLZ/YH/fi6xG4ajojkxaexNfbwZaGpJRM4N69qSSSp/tJmwfh2f2IYYcbkqv0IJhQ19ner8z1kYIgFJnPu05GtBuxJypD1+/OiJXcW2WYdyOZjTTKy+GdnFFrL9Zr5oqPTaq+exhLn7idUuaV+5CKcGA+WtqAUaT1pA0c/OdCS46p4NoGsNIvsIAkS/Zq7j1JmVm4kicctQyrLjjr7IdcJ7+zbHskZCeQZ8ZMqDqBJd6DZdMNuxXAkO986Aarrwp3sJUsDNpZ7zrTZkk3Pjz+Eo7fjBdWDD6kBX9iTht/ZZDpoRuDjsK+Xx6B1jMBshIjzl6QIrNnCuSBx47a9UgH20zoI25Lo7DJuzIPYCZzigRCX7vJwxKxQh2bAf8CheRqiv+ezhEezrHgZjygk29OXpiVxaSJB+BdFdcSUCN/LiVgpzo9RThBzftnogFbhHHL3cDiqO2+N3X+D+UTu7wf70aI3mdiaMOCkl5xWegvSL4ZzkxgE24cIcDF0v/DJpSE= x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PH0PR11MB5048.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(366004)(316002)(966005)(71200400001)(33656002)(55016003)(186003)(7696005)(508600001)(8936002)(76116006)(2906002)(86362001)(38100700002)(8676002)(122000001)(52536014)(5660300002)(9686003)(6506007)(66946007)(83380400001)(66446008)(64756008)(66556008)(38070700005)(26005)(107886003)(53546011)(66476007)(54906003)(82960400001)(4326008)(110136005);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?IiAJ2LhYByWrHW2C8HoOzUkzMIX43k5t73kwRYEzcgXLB7yAI25VYLT2QBC0?= =?us-ascii?Q?jBmP6nfiOlw5VqafkGRU61WCn2MdCF462sUEj+ZWcvYByHVAHaNrlN1qmqJG?= =?us-ascii?Q?bd5GH3cxEtaI4XSHAubmiCA9WePrMjrK8symV4bfpvLSJjDk00Z0t/2Yboif?= =?us-ascii?Q?yWPWJ63Rb9mcOiDKHA5JekQGKBNkKeAMvDI11AyiPqn1CScN3e4kjmegRJhX?= =?us-ascii?Q?JJ3kzY2FxsjcWbj8UZqm36/GtDY1SkbU5kg52meCxJjpBqMbO6J3JcVSbbBO?= =?us-ascii?Q?vNVoBo5o5aNYcpXz28kOkB5dsb1kGzImj255Y/pJsFqZBRTWnYDDe8Q+W4FH?= =?us-ascii?Q?ygmcSAPebk19N1iHS/udKlYBE56tTUatCw6lhP8Hfew7wdVcf87MQei1gnyj?= =?us-ascii?Q?OqGqEmdUfqevDB7XsRZ/nWXl4Wl1UuFkm1g9iHbxwhcrukXNNaYJT89879q+?= =?us-ascii?Q?mJQSCJbhE5bl2hmCKpb2bNixcjECAxlqMmO27d10kL5GwlGy1Nb/waww0HSe?= =?us-ascii?Q?G54YJrQDzwgVb/LBT1NdkXk6HWdtlpeLp8pDLaWAW3Fm0G55EUwLn2YrbFFt?= =?us-ascii?Q?LDpB/FS+K3GW35R3OoIQly8+XyQmE1igB/P/n2rI1us1+BDIhGjlDwoFYejw?= =?us-ascii?Q?G9KY4/dlJdbaI/4VxFgYPJd/VlIdD5EqwmWMU/NwEsWEgNKnOlUO7e0JNkwO?= =?us-ascii?Q?5YBOeZFuPmCsVF8iKtLFMXUu9VmE0cSBwG2Eha9wKuIhSIVhIvkID8O9fjdV?= =?us-ascii?Q?aXNF2TYhAFq8Dfi5DniP6334YVatfAkkGqWupPRKz6Qd5vvy/henLiooldl0?= =?us-ascii?Q?tF2NDJlG0Up3fYs9Ir8TcYpTDb+DThdpD5Yd+MTbDvXabqZKLUdICO5aSYCZ?= =?us-ascii?Q?iOg2yIHMNU6uTCDZtfBJHLLj78PgoN9Qvylap7oAfCXVHSGFzuTk2MXZCcKl?= =?us-ascii?Q?NPpitXdxRy1NY2cvoPT22ZBrDir/pbwTZvieGdbjwsJN6GQnX2dS+k361QnT?= =?us-ascii?Q?tspQP+HCsYCSnb1wHe1AHoa8yX69QIvVpAlKyQ1YUfxpsapyLjzXJaDJri9+?= =?us-ascii?Q?u+QZ22y1QsUq1FsPsHyKTozyZcJ9bbkfWWmEd/hP8I0DzrgLwyCailR6NWGB?= =?us-ascii?Q?qT3z9XPPkeA7kCGLNVab+/U7WzWma/Oh3DbbAmhcfjd7/XcUC27iR77WxcvV?= =?us-ascii?Q?QlZa5SOFQLNGmAQjJPHDclkveClWi2wLEpOdsl0UTAfFGej6mC8mskif5A6F?= =?us-ascii?Q?sFQnoHTmdA775fJxbJhfGy1gxSzZsjo4cy7QyPrORyzhIExsNZ7YNC1Ad7kc?= =?us-ascii?Q?LoOVd+3qMt6IWipv8Do7DygbhIDBguViTIqTej+mhq+OOJzTA/aTBaZnURgf?= =?us-ascii?Q?+buFaPb15MMF7GoCRQd8wATTu9yqbzi7PQ3ddEn51q13A249nbee1mPtSWOq?= =?us-ascii?Q?jwmgbwedIK/GvZmokOv3kCk87tc7hE3EYLebn2mZRIfo74v15IkpWqGZnlEB?= =?us-ascii?Q?0SbOPM99J1I84UqjZxNGmoEWjyTqGQbakLBih3U5AXj4Hxefdi67ZtkpX1+e?= =?us-ascii?Q?d5V/0rOooedrvSZPaDp5c0/+USokcl/RrdCZ1yZx9dkkso7zfHYZ/WX1fnvL?= =?us-ascii?Q?ww=3D=3D?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB5048.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 91ec98e2-cb43-45de-cdd6-08d9bf83dc29 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Dec 2021 04:32:10.3689 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: UArEFF/kAccDBPlbWom+PBylKgbflwuLSDfeY19jp6JmrfYf45/YPcWCkRcEouD08etergnDb9T/OfJ0VlltYQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR11MB5029 Return-Path: zhiguang.liu@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable I have checked that the change follows NVM Express 1.4 Spec=20 Reviewed-by: Zhiguang Liu -----Original Message----- From: Chu, Maggie =20 Sent: Wednesday, December 8, 2021 3:18 PM To: devel@edk2.groups.io Cc: Liming Gao ; Kinney, Michael D ; Liu, Zhiguang Subject: [PATCH] MdePkg: Add registers of boot partition feature REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3757 Add registers of boot partition feature which defined in NVM Express 1.4 Sp= ec Cc: Liming Gao Cc: Michael D Kinney Cc: Zhiguang Liu Signed-off-by: Maggie Chu --- MdePkg/Include/IndustryStandard/Nvme.h | 113 ++++++++++++++++++++----- 1 file changed, 92 insertions(+), 21 deletions(-) diff --git a/MdePkg/Include/IndustryStandard/Nvme.h b/MdePkg/Include/Indust= ryStandard/Nvme.h index 7d4aee9dc8..8387183e4f 100644 --- a/MdePkg/Include/IndustryStandard/Nvme.h +++ b/MdePkg/Include/IndustryStandard/Nvme.h @@ -2,11 +2,12 @@ Definitions based on NVMe spec. version 1.1. =20 (C) Copyright 2016 Hewlett Packard Enterprise Development LP
- Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 @par Specification Reference: NVMe Specification 1.1 + NVMe Specification 1.4 =20 **/ =20 @@ -18,18 +19,21 @@ // // controller register offsets // -#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities -#define NVME_VER_OFFSET 0x0008 // Version -#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set -#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear -#define NVME_CC_OFFSET 0x0014 // Controller Configuration -#define NVME_CSTS_OFFSET 0x001c // Controller Status -#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset -#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes -#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Ad= dress -#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Ad= dress -#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Tai= l Doorbell -#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) Hea= d Doorbell +#define NVME_CAP_OFFSET 0x0000 // Controller Capabilities +#define NVME_VER_OFFSET 0x0008 // Version +#define NVME_INTMS_OFFSET 0x000c // Interrupt Mask Set +#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear +#define NVME_CC_OFFSET 0x0014 // Controller Configuration +#define NVME_CSTS_OFFSET 0x001c // Controller Status +#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset +#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes +#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base A= ddress +#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base A= ddress +#define NVME_BPINFO_OFFSET 0x0040 // Boot Partition Information +#define NVME_BPRSEL_OFFSET 0x0044 // Boot Partition Read Select +#define NVME_BPMBL_OFFSET 0x0048 // Boot Partition Memory Buffer = Location +#define NVME_SQ0_OFFSET 0x1000 // Submission Queue 0 (admin) Ta= il Doorbell +#define NVME_CQ0_OFFSET 0x1004 // Completion Queue 0 (admin) He= ad Doorbell =20 // // These register offsets are defined as 0x1000 + (N * (4 << CAP.DSTRD)) @@ -51,11 +55,14 @@ typedef struct { UINT8 To; // Timeout UINT16 Dstrd : 4; UINT16 Nssrs : 1; // NVM Subsystem Reset Supported NSSRS - UINT16 Css : 4; // Command Sets Supported - Bit 37 - UINT16 Rsvd3 : 7; - UINT8 Mpsmin : 4; - UINT8 Mpsmax : 4; - UINT8 Rsvd4; + UINT16 Css:8; // Command Sets Supported - Bit 37 + UINT16 Bps:1; // Boot Partition Support - Bit 45 in NVMe1.4 + UINT16 Rsvd3:2; + UINT8 Mpsmin:4; + UINT8 Mpsmax:4; + UINT8 Pmrs:1; + UINT8 Cmbs:1; + UINT8 Rsvd4:6; } NVME_CAP; =20 // @@ -115,7 +122,36 @@ typedef struct { #define NVME_ACQ UINT64 =20 // -// 3.1.11 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission= Queue y Tail Doorbell +// 3.1.13 Offset 40h: BPINFO - Boot Partition Information +// +typedef struct { + UINT32 Bpsz:15; // Boot Partition Size + UINT32 Rsvd1:9; + UINT32 Brs:2; // Boot Read Status + UINT32 Rsvd2:5; + UINT32 Abpid:1; // Active Boot Partition ID +} NVME_BPINFO; + +// +// 3.1.14 Offset 44h: BPRSEL - Boot Partition Read Select +// +typedef struct { + UINT32 Bprsz:10; // Boot Partition Read Size + UINT32 Bprof:20; // Boot Partition Read Offset + UINT32 Rsvd1:1; + UINT32 Bpid:1; // Boot Partition Identifier +} NVME_BPRSEL; + +// +// 3.1.15 Offset 48h: BPMBL - Boot Partition Memory Buffer Location (Optio= nal) +// +typedef struct { + UINT64 Rsvd1:12; + UINT64 Bmbba:52; // Boot Partition Memory Buffer Base Address +} NVME_BPMBL; + +// +// 3.1.25 Offset (1000h + ((2y) * (4 << CAP.DSTRD))): SQyTDBL - Submission= Queue y Tail Doorbell // typedef struct { UINT16 Sqt; @@ -353,7 +389,7 @@ typedef struct { UINT8 Avscc; /* Admin Vendor Specific Command Configurati= on */ UINT8 Apsta; /* Autonomous Power State Transition Attribu= tes */ // - // Below fields before Rsvd2 are defined in NVM Express 1.3 Spec + // Below fields before Rsvd2 are defined in NVM Express 1.4 Spec // UINT16 Wctemp; /* Warning Composite Temperature Thres= hold */ UINT16 Cctemp; /* Critical Composite Temperature Thre= shold */ @@ -361,7 +397,12 @@ typedef struct { UINT32 Hmpre; /* Host Memory Buffer Preferred Size *= / UINT32 Hmmin; /* Host Memory Buffer Minimum Size */ UINT8 Tnvmcap[16]; /* Total NVM Capacity */ - UINT8 Rsvd2[216]; /* Reserved as of NVM Express */ + UINT8 Unvmcap[16]; /* Unallocated NVM Capacity */ + UINT32 Rpmbs; /* Replay Protected Memory Block Suppo= rt */ + UINT16 Edstt; /* Extended Device Self-test Time */ + UINT8 Dsto; /* Device Self-test Options */ + UINT8 Fwug; /* Firmware Update Granularity */ + UINT8 Rsvd2[192]; /* Reserved as of Nvm Express 1.4 Spec= */ // // NVM Command Set Attributes // @@ -433,6 +474,35 @@ typedef struct { UINT8 VendorData[3712]; /* Vendor specific data */ } NVME_ADMIN_NAMESPACE_DATA; =20 +// +// RPMB Device Configuration Block Data Structure as of Nvm Express 1.4 Sp= ec +// +typedef struct { + UINT8 Bppe; /* Boot Partition Protection Enable */ + UINT8 Bpl; /* Boot Partition Lock */ + UINT8 Nwpac; /* Namespace Write Protection Authentication= Control */ + + UINT8 Rsvd1[509]; /* Reserved as of Nvm Express 1.4 Spec */ +} NVME_RPMB_CONFIGURATION_DATA; + +#define RPMB_FRAME_STUFF_BYTES 223 + +// +// RPMB Data Frame as of Nvm Express 1.4 Spec +// +typedef struct { + UINT8 Sbakamc[RPMB_FRAME_STUFF_BYTES]; /* [222-N:00] Stuff Bytes= */ + /* [222:222-(N-1)] Authen= tication Key or Message Authentication Code (MAC) */ + UINT8 Rpmbt; /* RPMB Target */ + UINT64 Nonce[2]; + UINT32 Wcounter; /* Write Counter */ + UINT32 Address; /* Starting address of da= ta to be programmed to or read from the RPMB. */ + UINT32 Scount; /* Sector Count */ + UINT16 Result; + UINT16 Rpmessage; /* Request/Response Messa= ge */ +// UINT8 *Data; /* Data to be written or = read by signed access where M =3D 512 * Sector Count. */ +} NVME_RPMB_DATA_FRAME; + // // NvmExpress Admin Identify Cmd // @@ -564,6 +634,7 @@ typedef struct { #define LID_ERROR_INFO 0x1 #define LID_SMART_INFO 0x2 #define LID_FW_SLOT_INFO 0x3 + #define LID_BP_INFO 0x15 UINT32 Rsvd1 : 8; UINT32 Numd : 12; /* Number of Dwords */ UINT32 Rsvd2 : 4; /* Reserved as of Nvm Express 1.1 Spec */ --=20 2.26.2.windows.1