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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Gerd Sorry for responding late. Using 5level paging when the below two conditions are both true: 1. CPU support 5level paging 2. Platform choose to use 5level paging. (by specifing macro USE_5_LEVEL_= PAGE_TABLE) There is an assumption that if platform choose to use 5level paging, then 5= level paging should be supported by CPU. (Platform should know its CPU capa= bility) So condition#1 is actually depends on condition#2. The condition#2 is decided at build time. If Platform choose to use 4level paging at build time, we can save 4K space= by not creating the 5 level page. We can check the Cr4. LA57 to know if 4G - 12k is 4level or 5level paging w= hen debugging after reset vector. In a word, current way can save 4K space in flash when using 4level paging. Please let me know if you have any other concern or consideration about thi= s. Thanks. Thanks Zhiguang > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Gerd > Hoffmann > Sent: Monday, April 3, 2023 7:56 PM > To: Liu, Zhiguang > Cc: devel@edk2.groups.io; Dong, Eric ; Ni, Ray > ; Kumar, Rahul R ; De, > Debkumar ; West, Catharine > > Subject: Re: [edk2-devel] [PATCH 2/2] UefiCpuPkg: Support 5 level page > table in ResetVector >=20 > On Mon, Apr 03, 2023 at 05:28:14PM +0800, Zhiguang Liu wrote: > > Use a macro USE_5_LEVEL_PAGE_TABLE to determine whether to create > > 5 level page table. Whether creating it or not, the highest level page > > table address is fixed. >=20 > Can we create the 5level page table unconditionally? >=20 > We should have the PML5 table @ fixed at 4G - 12k and the PML4 table fixe= d > at 4G - 16k then. Then ideally check processor capabilities and decide a= t > runtime whenever to use 4level or 5level paging. >=20 > thanks, > Gerd >=20 >=20 >=20 >=20 >=20