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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Correct a typo in commit message inline. Thanks Zhiguang > -----Original Message----- > From: Liu, Zhiguang > Sent: Wednesday, April 26, 2023 4:13 PM > To: devel@edk2.groups.io > Cc: Liu, Zhiguang ; Dong, Eric > ; Ni, Ray ; Kumar, Rahul R > ; Gerd Hoffmann ; De, > Debkumar ; West, Catharine > > Subject: [PATCH v2 1/2] UefiCpuPkg/ResetVector: Modify Page Table in > ResetVector >=20 > In ResetVector, if create page table, its highest address is fixed becaus= e after > page table, code layout is fixed(4K for normal code, and another 4K only > contains reset vector code). > Today's implementation organizes the page table as following if 1G page > table is used: > 4G-16K: PML4 page (PML4[0] points to 4G-12K) > 4G-12K: PDP page > CR3 is set to 4G-16K > When 2M page table is used, the layout is as following: > 4G-32K: PML4 page (PML4[0] points to 4G-28K) > 4G-28K: PDP page (PDP entries point to PD pages) > 4G-24K: PD page mapping 0-1G > 4G-20K: PD page mapping 1-2G > 4G-16K: PD page mapping 2-3G > 4G-12K: PD page mapping 3-4G > CR3 is set to 4G-32K > CR3 doesn't point to a fixed location which is a bit hard to debug at run= time. >=20 > The new page table layout will always put PML4 in highest address When 1G > page table is used, the layout is as following: > 4G-16K: PDP page > 4G-12K: PML4 page (PML4[0] points to 4G-16K) When 2M page table is used= , > the layout is as following: > 4G-32K: PD page mapping 0-1G > 4G-28K: PD page mapping 1-2G > 4G-24K: PD page mapping 2-3G > 4G-20K: PD page mapping 3-4G > 4G-16K: PDP page (PDP entries point to PD pages) > 4G-12K: PML4 page (PML4[0] points to 4G-16K) > CR3 is always set to 4G-16K Zhiguang: This should be "CR3 is always set to 4G-12K" > So, this patch can improve debuggability by make sure the init > CR3 pointting to a fixed address(4G-12K). >=20 > Cc: Eric Dong > Cc: Ray Ni > Cc: Rahul Kumar > Cc: Gerd Hoffmann > Cc: Debkumar De > Cc: Catharine West > Signed-off-by: Zhiguang Liu > --- > .../ResetVector/Vtf0/Ia32/PageTables64.asm | 3 +- > UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 1 + > .../ResetVector/Vtf0/X64/PageTables1G.asm | 29 ++++++------- > .../ResetVector/Vtf0/X64/PageTables2M.asm | 43 +++++++++---------- > 4 files changed, 37 insertions(+), 39 deletions(-) >=20 > diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm > b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm > index 87a4125d4b..717e380892 100644 > --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm > +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm > @@ -16,8 +16,9 @@ SetCr3ForPageTables64: >=20 > ; > ; These pages are built into the ROM image in X64/PageTables.asm > + ; Highest level PageTable is at the highest address > ; > - mov eax, ADDR_OF(TopLevelPageDirectory) > + mov eax, ADDR_OF(PML4Table) > mov cr3, eax >=20 > OneTimeCallRet SetCr3ForPageTables64 diff --git > a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb > b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb > index bdea1fb875..4b972a90a5 100644 > --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb > +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb > @@ -44,6 +44,7 @@ > %include "X64/PageTables2M.asm" > %endif > %endif > +EndOfPageTables: >=20 > %ifdef DEBUG_PORT80 > %include "Port80Debug.asm" > diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm > b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm > index 19bd3d5a92..a0f477b5b0 100644 > --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm > +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables1G.asm > @@ -2,7 +2,7 @@ > ; @file > ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 > (512GB) ; -; Copyright (c) 2021, Intel Corporation. All rights reserved.=
> +; Copyright (c) 2023, Intel Corporation. All rights reserved.
> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; Linear-Address Transla= tion > to a 1-GByte Page ; > @@ -22,32 +22,29 @@ BITS 64 > PAGE_PRESENT + \ > PAGE_SIZE) >=20 > -%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) -%define > PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) > +%define PGTBLS_OFFSET(x) ((x) - StartOfPageTables) >=20 > -%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ > +%define PDP(offset) (ADDR_OF(StartOfPageTables) + (offset) + \ > PAGE_PDP_ATTR) >=20 > %define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR) >=20 > ALIGN 16 > - > -TopLevelPageDirectory: > - > - ; > - ; Top level Page Directory Pointers (1 * 512GB entry) > - ; > - DQ PDP(0x1000) > - > - TIMES 0x1000-PGTBLS_OFFSET($) DB 0 > +StartOfPageTables: > ; > - ; Next level Page Directory Pointers (512 * 1GB entries =3D> 512GB) > + ; Page-directory pointer table Pointers (512 * 1GB entries =3D> 512G= B) > + ; Contains one page > ; > %assign i 0 > %rep 512 > DQ PDP_1G(i) > %assign i i+1 > %endrep > - TIMES 0x2000-PGTBLS_OFFSET($) DB 0 >=20 > -EndOfPageTables: > +PML4Table: > + ; > + ; PML4 table Pointers (1 * 512GB entry) > + ; > + DQ PDP(0) > + > + TIMES 0x2000-PGTBLS_OFFSET($) DB 0 > diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm > b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm > index b97df384ac..0200825876 100644 > --- a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm > +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables2M.asm > @@ -2,7 +2,7 @@ > ; @file > ; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x100000000 (4G= B) ; > -; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.
> +; Copyright (c) 2008 - 2023, Intel Corporation. All rights > +reserved.
> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; > ;-----------------------------------------------------------------------= ------- > @@ -21,40 +21,39 @@ BITS 64 > PAGE_READ_WRITE + \ > PAGE_PRESENT) >=20 > -%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) -%define > PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) > +%define PGTBLS_OFFSET(x) ((x) - StartOfPageTables) >=20 > -%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ > +%define PDP(offset) (ADDR_OF(StartOfPageTables) + (offset) + \ > PAGE_PDP_ATTR) > %define PTE_2MB(x) ((x << 21) + PAGE_2M_PDE_ATTR) >=20 > -TopLevelPageDirectory: > +ALIGN 16 > +StartOfPageTables: >=20 > ; > - ; Top level Page Directory Pointers (1 * 512GB entry) > + ; Page Table Entries (2048 * 2MB entries =3D> 4GB) > + ; Contains 4 pages > ; > - DQ PDP(0x1000) > - > +%assign i 0 > +%rep 0x800 > + DQ PTE_2MB(i) > + %assign i i+1 > +%endrep >=20 > ; > - ; Next level Page Directory Pointers (4 * 1GB entries =3D> 4GB) > + ; Page-directory pointer table Pointers (4 * 1GB entries =3D> 4GB) > + ; here is at offset 0x4000 from StartOfPageTables > ; > - TIMES 0x1000-PGTBLS_OFFSET($) DB 0 > - > + DQ PDP(0) > + DQ PDP(0x1000) > DQ PDP(0x2000) > DQ PDP(0x3000) > - DQ PDP(0x4000) > - DQ PDP(0x5000) > + TIMES 0x5000-PGTBLS_OFFSET($) DB 0 >=20 > +PML4Table: > ; > - ; Page Table Entries (2048 * 2MB entries =3D> 4GB) > + ; PML4 table Pointers (1 * 512GB entry) > ; > - TIMES 0x2000-PGTBLS_OFFSET($) DB 0 > - > -%assign i 0 > -%rep 0x800 > - DQ PTE_2MB(i) > - %assign i i+1 > -%endrep > + DQ PDP(0x4000) >=20 > -EndOfPageTables: > + TIMES 0x6000-PGTBLS_OFFSET($) DB 0 > -- > 2.31.1.windows.1