Re: [edk2-devel] [PATCH V5 2/2] OvmfPkg/ResetVector: Enable Intel TDX in ResetVector of Ovmf

["Min Xu" <min.m.xu@intel.com>]

On September 2, 2021 3:18 PM, Gerd Hoffmann wrote:
>   Hi,
> 
> > > Sure.  And I think we should add proper 5-level paging support to
> > > the current ovmf implementation instead of adding hacks to the tdx code.
> > My understanding is that we should first add 5-level paging support in
> OVMF, right?
> 
> Well, the page table setup should be in common code not tdx code as 5-level
> paging isn't something tdx-specific.
Agree.
> 
> I'd suggest to add this to OvmfPkg/ResetVector/Ia32/PageTables64.asm.
> Reserve one more page, setup the tables for 5-level paging by inserting a
> level 5 page directory.
In the current patch a page (defined by PcdOvmfSecGhcbPageTableBase) reserved in MEMFD
is used as the 5-level page directory.
Now One new page will be reserved in MEMFD to hold the level 5 page directory. Like below:
0x00C000|0x001000
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupSize

+0x00D000|0x001000
+gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPml5Base|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPml5Size
> 
> When using 5-level paging let cr3 point to the first page (level 5 pagedir),
> when using 4-level paging let cr3 point to the second page (level 4 pagedir).
Yes. CPUID.(EAX=07H, ECX=0):ECX[bit 16] will be used to check if 5-level paging
is supported.
> 
> Can be part of this patch series, just make it a separate patch for easier
> review.
Sure.
> 
> Whenever we should enable 5-level paging even in non-tdx mode or use 5-
> level paging only with tdx is a separate question.  We can continue to use 4-
> level paging in non-tdx mode for now and discuss that later.
Agree. 
> 
> I'm not sure which implications this would have for booting older kernels,
> when handing over control to a OS kernel without 5-level paging support but
> 5-level paging enabled (non-issue for tdx as this requires a new tdx-aware
> guest kernel anyway ...).

Thanks! 
Min