From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 11C687803CF for ; Fri, 15 Sep 2023 13:29:27 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=Wklqgq1Q9eKk0Sftvs7K0oO/sZC6YG+oUBvBErHU89g=; c=relaxed/simple; d=groups.io; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:From:To:CC:Subject:Thread-Topic:Thread-Index:Date:Message-ID:References:In-Reply-To:Accept-Language:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1694784566; v=1; b=EmMfojnQbXXu8ZJmP7bt3gIvBXm21SGhh+P+TkABvQ8tAhduakbYL1LK4va4lWHjmehMVmgC ejCLl2gDfQxedg8nQISRsCUGFVf8k7kQVOs0RolVyP/ZIA6de7GPG4vqG27irbVncghlVY15MtS QL2J/WfvBLLZkXGVck+/L2nY= X-Received: by 127.0.0.2 with SMTP id hAjWYY7687511xeWwIgufCCE; Fri, 15 Sep 2023 06:29:26 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web10.20531.1694784566245114643 for ; Fri, 15 Sep 2023 06:29:26 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10834"; a="378160906" X-IronPort-AV: E=Sophos;i="6.02,149,1688454000"; d="scan'208";a="378160906" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2023 06:29:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10834"; a="835212445" X-IronPort-AV: E=Sophos;i="6.02,149,1688454000"; d="scan'208";a="835212445" X-Received: from orsmsx601.amr.corp.intel.com ([10.22.229.14]) by FMSMGA003.fm.intel.com with ESMTP/TLS/AES256-GCM-SHA384; 15 Sep 2023 06:29:25 -0700 X-Received: from orsmsx610.amr.corp.intel.com (10.22.229.23) by ORSMSX601.amr.corp.intel.com (10.22.229.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Fri, 15 Sep 2023 06:29:25 -0700 X-Received: from orsmsx601.amr.corp.intel.com (10.22.229.14) by ORSMSX610.amr.corp.intel.com (10.22.229.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Fri, 15 Sep 2023 06:29:24 -0700 X-Received: from ORSEDG602.ED.cps.intel.com (10.7.248.7) by orsmsx601.amr.corp.intel.com (10.22.229.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32 via Frontend Transport; Fri, 15 Sep 2023 06:29:24 -0700 X-Received: from NAM11-BN8-obe.outbound.protection.outlook.com (104.47.58.169) by edgegateway.intel.com (134.134.137.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.32; Fri, 15 Sep 2023 06:29:24 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=e80VKKdBpgnM5ceU2aAYpx+UfJmn5cOmaPB45GGmVAyAUH9yJOpKstBsFV3UuUOaF6ZXT6MJmh1Tuyx4htkAXa89OFRNVebb7i09nGsPRNGbWTkHck4r1XQKL9oryIGWO/Z6Q2ApdnKZRMrJ+QFo902aioquULfH+SJrEl46n+IOJop7kVRObKuXssJUAwO4YVd2GqJKFiG57t1FuFgf2scj1Xb6Ns3hva2GZOvpSQdIc63gMOgqjNwsthyOy2/27o00KmoYqYgWErpz9hDUvIrQU1i2jilysEljUrjBcEzwfEEcqsf6HsjQoJCMU/iaF5C7HDRgsI+rm9AnWISUPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=M/Ouyw/g+rhBcQEAuOIVUnfV53LzzLfLDnQFlIGor0s=; b=laa0DQHVAyNMhmBQ91PH/CCTiVDoZgvO01EzQlZREJZu+XQ5lmqVfvzbWcQcQ8/3LnkXjDzJxDONyuSxJHwH9jS/07XIVgUWznP6jwTBk17i624wNdpM98C0tx9NOuw/aToXVB7lMbplLWh+gqNbBaNaNwsM52GKtTbUc2s8QaZGGvGGDiKcFsTIp81fF4itZ11eAkjZvROpM6Hg2MznCAyS9ho3pbztbxhjJkNP2hjpcKDXoZkZjBAncvjyhVMGbSOZrk/gFeNKT7bLqbdHclrMPpZm4CHM8Q60EFEDhOXaPzu2FzplMzKGBxhhjijkG5cPI9rngRlla/DuGsE06A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none X-Received: from PH0PR11MB5626.namprd11.prod.outlook.com (2603:10b6:510:ee::15) by LV3PR11MB8578.namprd11.prod.outlook.com (2603:10b6:408:1b3::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6768.31; Fri, 15 Sep 2023 13:29:21 +0000 X-Received: from PH0PR11MB5626.namprd11.prod.outlook.com ([fe80::68a8:9cc5:ec4d:ca44]) by PH0PR11MB5626.namprd11.prod.outlook.com ([fe80::68a8:9cc5:ec4d:ca44%7]) with mapi id 15.20.6792.021; Fri, 15 Sep 2023 13:29:21 +0000 From: "Chuang, Rosen" To: "Chaganty, Rangasai V" , "Kasbekar, Saloni" , "devel@edk2.groups.io" CC: "Desimone, Nathaniel L" Subject: Re: [edk2-devel] [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules Thread-Topic: [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules Thread-Index: AQHZ54+VlN4wnIjjC0aZYLwus7SMDrAbX/6AgACCG0A= Date: Fri, 15 Sep 2023 13:29:21 +0000 Message-ID: References: <098cac7875de63b7734b48e8cd233901ed456cd2.1694752605.git.saloni.kasbekar@intel.com> In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PH0PR11MB5626:EE_|LV3PR11MB8578:EE_ x-ms-office365-filtering-correlation-id: c1890acb-38df-40da-d57d-08dbb5efc558 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam-message-info: Jfb1z5tyWctLog0MhlMkTnNFNddLtNLVFuVe+zM1Ss4Y9B1uOEKPox+49zqXzSQq3uFg2evu+ohsbAdWiroCbwdU1rP+4E6Ps3Umxorz5PE6P14wqAPPI0HoMt6wAMOMQu4e1IxLuYf/4BLWpLBgDWzyhRMNnDocn/K6/hdUs39KGD3YuptSC04XYRsZG+FX7cJhrcNAIMWwxz9eQDoePLdbk+6xcBa2+kNi2v+h8zihhzQH7A0xWbi2L72Hi+1Wit3QGymVm47hq6TcLr92xgL1Hk6eLHzH+EEivRBJtrI9kylqjOnRxbLnYCag3rdqaBNY74XE2/PfPWCLJB22Giza6BqI/7ST41rVINpxRLwzVoWKR9e5a4rLftvor/tnKg/bnz22HZ8HunLi65XFRzJi6J764lMPARe4vH3j8GjGuE+4vPm9mG8XiSGqGgu7ECSs3gG3cKfL0fXdjXxS3Qu43fQwS7DEU0zU6DmIOosUL9fXZsvcfPHdJEWQBwcYpSc46grMK+QQWYNfRvbfbBQZmROKGXX7hWLM9H17Ngc975EiHGEZCQl15/e+FjO8kU6b3leFp+YiPG+CyLe8uUKJUdCIuMkoUfuhpAkEJFMWN05C65Wp2oFNkG1qy7T0 x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?bcfALDTgqUwYhWbf39uemCixQoWm6Mtaqm/KvM6Ztx0yIrHfxQzIyUhG2Cdf?= =?us-ascii?Q?bjezXsiZanVrV9to7Ah6+evWOniGaeQvp6H0c2jF54/jwPyiHLAjKdn82BOw?= =?us-ascii?Q?LAbTwhsf2+OvCWA+XbuIsP81qIVtPaLM6DimeQODs5soFuGM91AdrVEcMbgh?= =?us-ascii?Q?Z9dzlak1+X5+7IYOVlL6qfrHl8EaVF83J7zG6nkHfIApbCsDnTcS51Z0F5mL?= =?us-ascii?Q?H43Jnj2092v4j5TMxfSDNlHsSHGVYS0Mj6QRWcqjwOr+sv/LQjPGG16mN//Z?= =?us-ascii?Q?vVAsf0EubwvXxS6KO+gTUPsYmN3FbZVN70to3yysOL+qCIjklEdBEZ1P5rV+?= =?us-ascii?Q?o4gcECT670KaCVBPyluBF1Lh0+jt4zXkyAUrmvkqNfRq1hZBp1IDvtMxDx0g?= =?us-ascii?Q?Rlttu1ep8t4oGHlcaZEbyFO1+VPG2t5NzNY92ph/f7oXpaBkAbPAP82Koccq?= =?us-ascii?Q?100TyHntRtANwam68k2n54YTrNIa0o2gmMvkoOmdUjdMpWJEiOCVSX3QLjw/?= =?us-ascii?Q?Gsid176LNCdIIGdgfqTCRxw/2OAOzwtfDRfNNd+Y1z77jcTfYe4X36jIaFC/?= =?us-ascii?Q?YlVD+bCjJB+GR3hg05hACyF/jnJp6NQC2nhOUAEw4/rMX+zivtfboOhNynJn?= =?us-ascii?Q?9DCxPaEPWvNp8XZskAu7MhWdkDYIfiDn6ZEn4eDBvr3T7+hy1FoOpA5PlKW7?= =?us-ascii?Q?qKNKe+RfWY8+2v1SIhWhmT060m8DQ6Rx+VKk+gRcZpQXEQvHNSuWPZtrCFZG?= =?us-ascii?Q?haH+WrSrzfzgxWd1+c9vhEMxdH9oAUk+W2h2Vm3dFsrQa0QLveqqP6ciP3e6?= =?us-ascii?Q?WWxcFmQJKFA2/D8jCM1ZNWrolVSdE4GG83ivBZx132xpb34gbL7Quydh3NBV?= =?us-ascii?Q?+umIFZsweRcbQxL0vYe25NoGNLaYZldpKBUY8GOEG48+cN089xMYgyMH+MYi?= =?us-ascii?Q?HDnL5mROK1hxh+p4jgbYNOpg3RBOSz1CUNrs8yQv6jt3fIWjUyeKTgUDlGDd?= =?us-ascii?Q?vCUapoA4pto+k/Vt0A5nt+JSfBF1zCbTeIGbSRKAa9amw1PDgER1Ly1N/X28?= =?us-ascii?Q?7TpQDdPkPGE3DA9UiLheNVFg040yGsPRlYwQPkvhdcI9YK4gQuFa9ZkAQOP1?= =?us-ascii?Q?aig7lj4PEWQzWkqGvbYs5AyzKkD68KqlyRARrwNMoEBuI2xFbAC1ityqLlGk?= =?us-ascii?Q?637/BFcSclh3oMsbWTJApX6xu5CAvVcXueyZxbqmyNG9OcR3SlLUYZgFSmEF?= =?us-ascii?Q?ld7xunyE6LuoJ1w21vDu/rBrsA4us1l0XVtoeSZMhu94iMz43a72Ecachln/?= =?us-ascii?Q?rdFI5uCf60tmj1hlWvnBN4xUoRI7BShAej42ts4n7VIz90M6PtlvUDZLKgF1?= =?us-ascii?Q?53d4nio9zVwMc5nHjCWsNmDYL+3N1UOJlZwIKvXKbFite2CnjZFSmYNBCs3d?= =?us-ascii?Q?hgtblgBimhc1a+iHl/JBYC3aYeg7cKMjRi/7S0Kwtim/o3WqX07U8z1q1JTr?= =?us-ascii?Q?GI8x/y2TW8liMDNj3lJKXl00H9oPaphCqqyvbU188OSqpkNhZj1/WD1vvh3W?= =?us-ascii?Q?Edf83ZJ8U0N7lkY0H2/Ew5Vd9cbtNVKFM7NBh9SJ?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB5626.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c1890acb-38df-40da-d57d-08dbb5efc558 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Sep 2023 13:29:21.5783 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: LlFKZu/r7XY8G9a7ZdXU7LnsJv1LfPR3CAKuS1ef77azz57Qh3sRi70lyyn+zf+ZSut/4j7siXoBESYeQeMRtQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR11MB8578 X-OriginatorOrg: intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rosen.chuang@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: otxuJVx8Zu7cn249Ck2lrT6gx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=EmMfojnQ; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Reviewed-by: Rosen Chuang -----Original Message----- From: Chaganty, Rangasai V =20 Sent: Friday, September 15, 2023 1:44 PM To: Kasbekar, Saloni ; devel@edk2.groups.io Cc: Desimone, Nathaniel L ; Chuang, Rosen <= rosen.chuang@intel.com> Subject: RE: [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and Inclu= dePrivate modules Reviewed-by: Sai Chaganty -----Original Message----- From: Kasbekar, Saloni Sent: Thursday, September 14, 2023 9:46 PM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Chuang, Rosen Subject: [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePr= ivate modules Adds the following modules: - AdlPch/Include - AdlPch/IncludePrivate - AdlPch/Library - AdlPch DSCs - IncludePrivate Cc: Sai Chaganty Cc: Nate DeSimone Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../Fru/AdlPch/CommonLib.dsc | 29 ++ .../AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc | 10 + .../AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc | 7 + .../Fru/AdlPch/Include/PchBdfAssignment.h | 81 +++++ .../Fru/AdlPch/Include/PchLimits.h | 47 +++ .../Fru/AdlPch/Include/PchPcieRpInfo.h | 17 ++ .../Fru/AdlPch/Include/PchReservedResources.h | 13 + .../AdlPch/Include/= PchReservedResourcesAdpP.h | 36 +++ .../IncludePrivate/Register/PchPcrRegs.h | 59 ++++ .../IncludePrivate/Register/PchRegsLpcAdl.h | 30 ++ .../PeiDxeSmmPchInfoLib/PchInfoLibAdl.c | 223 ++++++++++++++ .../PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h | 44 +++ .../PeiDxeSmmPchInfoLibAdl.inf | 37 +++ .../AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc | 7 + .../AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc | 12 + .../IncludePrivate/RegisterAccess.h | 288 ++++++++++++++++++ 16 files changed, 940 insertions(+) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.= dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/Pc= hBdfAssignment.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/Pc= hLimits.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/Pc= hPcieRpInfo.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/Pc= hReservedResources.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/Pc= hReservedResourcesAdpP.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePri= vate/Register/PchPcrRegs.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePri= vate/Register/PchRegsLpcAdl.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/Pe= iDxeSmmPchInfoLib/PchInfoLibAdl.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/Pe= iDxeSmmPchInfoLib/PchInfoLibPrivate.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/Pe= iDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/Regist= erAccess.h diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc b/S= ilicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc new file mode 100644 index 0000000000..3f508f83a1 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc @@ -0,0 +1,29 @@ +## @file +# Component description file for the AlderLake PCH Common FRU libraries. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + =20 + PchPcrLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/Library/PeiDxeSmmPchPcrL + ib/PeiDxeSmmPchPcrLib.inf + PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPrivate/Pei + DxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf + =20 + P2SbSidebandAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPriva + te/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf + + =20 + EspiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Espi/Library/PeiDxeSmmEspiLib/P + eiDxeSmmEspiLib.inf + + + =20 + PmcLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiD + xeSmmPmcLib.inf + PmcPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/LibraryPrivate/PeiDxe + SmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf + =20 + SpiCommonLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/LibraryPrivate/BaseSpi + CommonLib/BaseSpiCommonLib.inf + GpioLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/P + eiDxeSmmGpioLib.inf + PchDmiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PchDmi/LibraryPrivate/PeiDxeS + mmPchDmiLib/PeiDxeSmmPchDmiLib.inf + + =20 + GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiD + xeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf + =20 + PchPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/Library/PeiDxeSmmPc + hPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf + + + # + # Common FRU Libraries + # + =20 + PchInfoLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlPch/Library/PeiDxeSmmPchInfoL + ib/PeiDxeSmmPchInfoLibAdl.inf + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc b/Silicon= /Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc new file mode 100644 index 0000000000..b443611d9a --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc @@ -0,0 +1,10 @@ +## @file +# Component description file for the AlderLake PCH DXE FRU drivers. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + $(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Smm/SpiSmm.inf + + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc b/Sili= con/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc new file mode 100644 index 0000000000..e350b8e643 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc @@ -0,0 +1,7 @@ +# @file +# Component description file for the AlderLake PCH DXE FRU libraries. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + =20 +GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/BaseG +pioHelpersLibNull/BaseGpioHelpersLibNull.inf diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAss= ignment.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssi= gnment.h new file mode 100644 index 0000000000..b8af6d7624 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignm +++ ent.h @@ -0,0 +1,81 @@ +/** @file + Header file for AlderLake PCH devices PCI Bus Device Function map. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef=20 +_PCH_BDF_ASSIGNMENT_H_ #define _PCH_BDF_ASSIGNMENT_H_ + +#define NOT_PRESENT 0xFF + +// +// PCH PCIe Controllers +// +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_2 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_3 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_4 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_6 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_7 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_8 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_10 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_11 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_12 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_14 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_15 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_16 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_18 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_19 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_20 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_22 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_23 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_24 27 +#ifdef PCH_ADPP +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 NOT_PRESENT +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 NOT_PRESENT +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 NOT_PRESENT +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 NOT_PRESENT +#else +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 26 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 26 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 26 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 26 +#endif + +// +// USB3 (XHCI) Controller PCI config +// +#define PCI_DEVICE_NUMBER_PCH_XHCI 20 +#define PCI_FUNCTION_NUMBER_PCH_XHCI 0 + + + + +// +// LPC Controller (D31:F0) +// +#define PCI_DEVICE_NUMBER_PCH_LPC 31 +#define PCI_FUNCTION_NUMBER_PCH_LPC 0 + +// +// Primary to Sideband (P2SB) Bridge (D31:F1) // +#define PCI_DEVICE_NUMBER_PCH_P2SB 31 +#define PCI_FUNCTION_NUMBER_PCH_P2SB 1 + + + +// +// SPI Controller (D31:F5) +// +#define PCI_DEVICE_NUMBER_PCH_SPI 31 +#define PCI_FUNCTION_NUMBER_PCH_SPI 5 + + +#endif // _PCH_BDF_ASSIGNMENT_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits= .h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h new file mode 100644 index 0000000000..dad3a9a073 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h @@ -0,0 +1,47 @@ +/** @file + Build time limits of PCH resources. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef=20 +_PCH_LIMITS_H_ #define _PCH_LIMITS_H_ +/* + * Defines povided in this file are indended to be used only where=20 +static value + * is needed. They are set to values which allow to accomodate multiple=20 +projects + * needs. Where runtime usage is possible please used dedicated=20 +functions from + * PchInfoLib to retrieve accurate values */ + + + +// +// PCIe limits +// +#define PCH_MAX_PCIE_ROOT_PORTS 28 +#define PCH_MAX_PCIE_CONTROLLERS 7 + +// +// PCIe clocks limits +// +#define PCH_MAX_PCIE_CLOCKS 18 + +// +// DMI lanes +// +#define PCH_MAX_DMI_LANES 8 + +// +// SerialIo limits +// +#define PCH_MAX_SERIALIO_I2C_CONTROLLERS 8 +#define PCH_MAX_SERIALIO_SPI_CONTROLLERS 7 +#define PCH_MAX_SERIALIO_SPI_CHIP_SELECTS 2 +#define PCH_MAX_SERIALIO_UART_CONTROLLERS 7 + +// +// Number of eSPI slaves +// +#define PCH_MAX_ESPI_SLAVES 2 + +#endif // _PCH_LIMITS_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRp= Info.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo= .h new file mode 100644 index 0000000000..9276b61e1f --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo +++ .h @@ -0,0 +1,17 @@ +/** @file + Pcie Root Port info header + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _PCH_PCIERP_INFO_H_ +#define _PCH_PCIERP_INFO_H_ + +// +// Number of PCIe ports per PCIe controller // +#define PCH_PCIE_CONTROLLER_PORTS 4u + + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReserv= edResources.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchRes= ervedResources.h new file mode 100644 index 0000000000..f4adfab74f --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedRe +++ sources.h @@ -0,0 +1,13 @@ +/** @file + PCH preserved MMIO resource definitions. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _PCH_PRESERVED_RESOURCES_H_ +#define _PCH_PRESERVED_RESOURCES_H_ +#include "PchReservedResourcesAdpP.h" + +#endif // _PCH_PRESERVED_RESOURCES_H_ + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReserv= edResourcesAdpP.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/Pc= hReservedResourcesAdpP.h new file mode 100644 index 0000000000..69aac29cea --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedRe +++ sourcesAdpP.h @@ -0,0 +1,36 @@ +/** @file + PCH preserved MMIO resource definitions. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef=20 +_PCH_PRESERVED_RESOURCES_ADP_P_H_ +#define _PCH_PRESERVED_RESOURCES_ADP_P_H_ + +/** + Detailed recommended static allocation + +-----------------------------------------------------------------------= --+ + | PCH preserved MMIO range, 32 MB, from 0xFC800000 to 0xFE7FFFFF = | + +-----------------------------------------------------------------------= --+ + | Size | Start | End | Usage = | + | 8 MB | 0xFC800000 | 0xFCFFFFFF | TraceHub SW BAR = | + | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG = | + | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR = | + | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 = | + | 176 KB | 0xFE020000 | 0xFE04BFFF | SerialIo BAR in ACPI mode = | + | 400 KB | 0xFE04C000 | 0xFE0AFFFF | Unused = | + | 64 KB | 0xFE0B0000 | 0xFE0BFFFF | eSPI LGMR BAR = | + | 64 KB | 0xFE0C0000 | 0xFE0CFFFF | eSPI2 SEGMR BAR = | + | 192 KB | 0xFE0D0000 | 0xFE0FFFFF | Unused = | + | 1 MB | 0xFE100000 | 0xFE1FFFFF | TraceHub MTB BAR = | + | 2 MB | 0xFE200000 | 0xFE3FFFFF | TraceHub FW BAR = | + | 2 MB | 0xFE400000 | 0xFE5FFFFF | Unused = | + | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address = | + =20 ++---------------------------------------------------------------------- +---+ +**/ +#define PCH_PCR_BASE_ADDRESS 0xFD000000 ///< SBREG MMIO bas= e address +#define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR MMIO = base address +#define PCH_SPI_BASE_ADDRESS 0xFE010000 ///< SPI BAR0 MMIO = base address + +#endif // _PCH_PRESERVED_RESOURCES_ADP_P_H_ + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Re= gister/PchPcrRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludeP= rivate/Register/PchPcrRegs.h new file mode 100644 index 0000000000..fe548dae4b --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Regist +++ er/PchPcrRegs.h @@ -0,0 +1,59 @@ +/** @file + Register names for PCH private chipset register + +Conventions: + + - Register definition format: + =20 + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re + gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name= . + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _PCH_REGS_PCR_H_ +#define _PCH_REGS_PCR_H_ + + +/** + Definition for SBI PID + The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI pro= gramming as well. +**/ +#define PID_DMI 0x88 +#define PID_ESPISPI 0x72 +#define PID_SPF 0x85 +#define PID_SPE 0x84 +#define PID_SPD 0x83 +#define PID_SPC 0x82 +#define PID_SPB 0x81 +#define PID_SPA 0x80 +#define PID_GPIOCOM0 0x6E +#define PID_GPIOCOM1 0x6D +#define PID_GPIOCOM2 0x6C +#define PID_GPIOCOM4 0x6A +#define PID_GPIOCOM5 0x69 + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Re= gister/PchRegsLpcAdl.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Inclu= dePrivate/Register/PchRegsLpcAdl.h new file mode 100644 index 0000000000..8b1a01036e --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Regist +++ er/PchRegsLpcAdl.h @@ -0,0 +1,30 @@ +/** @file + Register names for ADL PCH LPC/eSPI device + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef=20 +_PCH_REGS_LPC_ADL_H_ #define _PCH_REGS_LPC_ADL_H_ + +// +// ADL PCH-P/M LPC Device IDs +// +#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_0 0x5180 ///< LP= C/eSPI Controller +#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_1 0x5181 ///< LP= C/eSPI Controller P SuperSKU +#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_2 0x5182 ///< LP= C/eSPI Controller P Premium +#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_3 0x5183 ///< LP= C/eSPI Controller Placeholder +#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_4 0x5184 ///< LP= C/eSPI Controller +#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_5 0x5185 ///< LP= C/eSPI Controller + + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmm= PchInfoLib/PchInfoLibAdl.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/L= ibrary/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c new file mode 100644 index 0000000000..c74d665533 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchI +++ nfoLib/PchInfoLibAdl.c @@ -0,0 +1,223 @@ +/** @file + Pch information library for ADL. + + All function in this library is available for PEI, DXE, and SMM, But=20 + do not support UEFI RUNTIME environment call. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include =20 +#include #include #include=20 + #include #include=20 + #include #include=20 + #include #include=20 + #include #include=20 + #include #include=20 + #include #include=20 + #include "PchInfoLibPrivate.h" + + +/** + Return LPC Device Id + + @retval PCH_LPC_DEVICE_ID PCH Lpc Device ID +**/ +UINT16 +PchGetLpcDid ( + VOID + ) +{ + UINT64 LpcBaseAddress; + + LpcBaseAddress =3D LpcPciCfgBase (); + + return PciSegmentRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET); } + +/** + Return Pch Series + + @retval PCH_SERIES Pch Series +**/ +PCH_SERIES +PchSeries ( + VOID + ) +{ + PCH_SERIES PchSer; + static PCH_SERIES PchSeries =3D PCH_UNKNOWN_SERIES; + + if (PchSeries !=3D PCH_UNKNOWN_SERIES) { + return PchSeries; + } + + PchSer =3D PchSeriesFromLpcDid (PchGetLpcDid ()); + + PchSeries =3D PchSer; + + return PchSer; +} + +/** + Return Pch stepping type + + @retval PCH_STEPPING Pch stepping type +**/ +PCH_STEPPING +PchStepping ( + VOID + ) +{ + UINT8 RevId; + UINT64 LpcBaseAddress; + static PCH_STEPPING PchStepping =3D PCH_STEPPING_MAX; + + if (PchStepping !=3D PCH_STEPPING_MAX) { + return PchStepping; + } + + LpcBaseAddress =3D LpcPciCfgBase (); + RevId =3D PciSegmentRead8 (LpcBaseAddress + PCI_REVISION_ID_OFFSET); + + RevId =3D PchSteppingFromRevId (RevId); + + PchStepping =3D RevId; + + return RevId; +} + +/** + Check if this is PCH P series + + @retval TRUE It's PCH P series + @retval FALSE It's not PCH P series +**/ +BOOLEAN +IsPchP ( + VOID + ) +{ + return (PchSeries () =3D=3D PCH_P); +} + +/** + return support status for P2SB PCR 20-bit addressing + + @retval TRUE + @retval FALSE +**/ +BOOLEAN +IsP2sb20bPcrSupported ( + VOID + ) +{ + return FALSE; +} + +/** + Determine Pch Series based on Device Id + + @param[in] LpcDeviceId Lpc Device Id + + @retval PCH_SERIES Pch Series +**/ +PCH_SERIES +PchSeriesFromLpcDid ( + IN UINT16 LpcDeviceId + ) +{ + return PCH_P; +} + +/** + Determine Pch Stepping based on Revision ID + + @param[in] RevId Pch Revision Id + + @retval PCH_STEPPING Pch Stepping +**/ +PCH_STEPPING +PchSteppingFromRevId ( + IN UINT8 RevId + ) +{ + return RevId; +} + + +/** + Check if this is PCH LP series + + @retval TRUE It's PCH LP series + @retval FALSE It's not PCH LP series +**/ +BOOLEAN +IsPchLp ( + VOID + ) +{ + return (PchSeries () =3D=3D PCH_LP || PchSeries () =3D=3D PCH_P || PchSe= ries=20 +() =3D=3D PCH_M || PchSeries () =3D=3D PCH_N ); } +/** + Get RST mode supported by the silicon + + @retval RST_MODE RST mode supported by silicon +**/ + +GLOBAL_REMOVE_IF_UNREFERENCED +struct PCH_SKU_STRING mSkuStrs[] =3D { + // + // ADL PCH LPC Device IDs + // + {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_0, "ADL SKU 0"}, + {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_1, "P Super SKU (SSKU)"}, + {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_2, "P Premium"}, + {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_3, "ADL No UFS"}, + {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_4, "ADL SKU 4"}, + {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_5, "ADL SKU 5"}, + + {0xFFFF, NULL} +}; + +/** + Get Pch Maximum Pcie Root Port Number + + @retval Pch Maximum Pcie Root Port Number **/ +UINT8 +GetPchMaxPciePortNum ( + VOID + ) +{ + switch (PchSeries ()) { + case PCH_P: + case PCH_N: + return 12; + case PCH_S: + return 28; + default: + return 0; + } +} + +/** + Get Pch Maximum Serial IO I2C controllers number + + @retval Pch Maximum Serial IO I2C controllers number **/ +UINT8 +GetPchMaxSerialIoI2cControllersNum ( + VOID + ) +{ + return 8; +} diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmm= PchInfoLib/PchInfoLibPrivate.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlP= ch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h new file mode 100644 index 0000000000..a4bd4d5aa7 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchI +++ nfoLib/PchInfoLibPrivate.h @@ -0,0 +1,44 @@ +/** @file + Private header for PCH Info Lib. + + All function in this library is available for PEI, DXE, and SMM, But=20 + do not support UEFI RUNTIME environment call. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +/** + Structure for PCH SKU string mapping +**/ +struct PCH_SKU_STRING { + UINT16 Id; + CHAR8 *String; +}; + +extern struct PCH_SKU_STRING mSkuStrs[]; + +/** + Determine Pch Series based on Device Id + + @param[in] LpcDeviceId Lpc Device Id + + @retval PCH_SERIES Pch Series +**/ +PCH_SERIES +PchSeriesFromLpcDid ( + IN UINT16 LpcDeviceId + ); + +/** + Determine Pch Stepping based on Revision ID + + @param[in] RevId Pch Revision Id + + @retval PCH_STEPPING Pch Stepping +**/ +PCH_STEPPING +PchSteppingFromRevId ( + IN UINT8 RevId + ); + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmm= PchInfoLib/PeiDxeSmmPchInfoLibAdl.inf b/Silicon/Intel/AlderlakeSiliconPkg/F= ru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf new file mode 100644 index 0000000000..28a6863aed --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchI +++ nfoLib/PeiDxeSmmPchInfoLibAdl.inf @@ -0,0 +1,37 @@ +## @file +# PCH information library for Alderlake PCH. +# +# All function in this library is available for PEI, DXE, and SMM, #=20 +But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchInfoLibAdl +FILE_GUID =3D F5B0CBB7-4AFC-4535-A5EC-D9ECEDA24DC5 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchInfoLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PrintLib +PciSegmentLib +PmcPrivateLib +PcdLib + + +[Packages] +MdePkg/MdePkg.dec +AlderlakeSiliconPkg/SiPkg.dec + + +[Sources] +PchInfoLibAdl.c diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc b/Silicon= /Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc new file mode 100644 index 0000000000..8a923554dd --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc @@ -0,0 +1,7 @@ +## @file +# Component description file for the AlderLake PCH PEI FRU drivers. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc b/Sili= con/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc new file mode 100644 index 0000000000..ebe2bbfda0 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc @@ -0,0 +1,12 @@ +## @file +# Component description file for the AlderLake PCH PEI FRU libraries. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + =20 + SpiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib. + inf + + =20 + GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiG + pioHelpersLib/PeiGpioHelpersLib.inf + + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAcces= s.h b/Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h new file mode 100644 index 0000000000..25a0ba49d2 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h @@ -0,0 +1,288 @@ +/** @file + Header file for register access. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#ifndef _REGISTER_ACCESS_H_ +#define _REGISTER_ACCESS_H_ + +typedef struct _REGISTER_ACCESS REGISTER_ACCESS; + +/** + Reads an 8-bit register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + + @return The 8-bit register value specified by Offset **/ typedef +UINT8 +(*REG_READ8) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset + ); + +/** + Writes an 8-bit register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] Value Value to write to register + + @return The 8-bit register value written to register **/ typedef +UINT8 +(*REG_WRITE8) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT8 Value + ); + +/** + Performs an 8-bit or on the register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank =20 + @param[in] OrData Data with which register should be OR-ed + + @return The 8-bit register value written to register **/ typedef +UINT8 +(*REG_OR8) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT8 OrData + ); + +/** + Performs an 8-bit and on the register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] AndData Data with which register should be AND-ed + + @return The 8-bit register value written to register **/ typedef +UINT8 +(*REG_AND8) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT8 AndData + ); + +/** + Performs an 8-bit and then or on the register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] AndData Data with which register should be AND-ed + @param[in] OrData Data with which register should be OR-ed + + @return The 8-bit register value written to register **/ typedef +UINT8 +(*REG_AND_THEN_OR8) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT8 AndData, + IN UINT8 OrData + ); + +/** + Reads a 16-bit register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + + @return The 16-bit register value specified by Offset **/ typedef +UINT16 +(*REG_READ16) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset + ); + +/** + Writes a 16-bit register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] Value Value to write to register + + @return The 16-bit register value written to register **/ typedef +UINT16 +(*REG_WRITE16) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT16 Value + ); + +/** + Performs a 16-bit or on the register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank =20 + @param[in] OrData Data with which register should be OR-ed + + @return The 16-bit register value written to register **/ typedef +UINT16 +(*REG_OR16) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT16 OrData + ); + +/** + Performs a 16-bit and on the register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] AndData Data with which register should be AND-ed + + @return The 16-bit register value written to register **/ typedef +UINT16 +(*REG_AND16) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT16 AndData + ); + +/** + Performs a 16-bit and then or on the register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] AndData Data with which register should be AND-ed + @param[in] OrData Data with which register should be OR-ed + + @return The 16-bit register value written to register **/ typedef +UINT16 +(*REG_AND_THEN_OR16) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Reads a 32-bit register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + + @return The 32-bit register value specified by Offset **/ typedef +UINT32 +(*REG_READ32) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset + ); + +/** + Writes a 32-bit register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] Value Value to write to register + + @return The 32-bit register value written to register **/ typedef +UINT32 +(*REG_WRITE32) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT32 Value + ); + +/** + Performs a 32-bit or on the register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank =20 + @param[in] OrData Data with which register should be OR-ed + + @return The 32-bit register value written to register **/ typedef +UINT32 +(*REG_OR32) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT32 OrData + ); + +/** + Performs a 32-bit and on the register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] AndData Data with which register should be AND-ed + + @return The 32-bit register value written to register **/ typedef +UINT32 +(*REG_AND32) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT32 AndData + ); + +/** + Performs a 32-bit and then or on the register + + @param[in] This Pointer to REGISTER_ACCESS + @param[in] Offset Offset of the register in the register bank + @param[in] AndData Data with which register should be AND-ed + @param[in] OrData Data with which register should be OR-ed + + @return The 32-bit register value written to register **/ typedef +UINT32 +(*REG_AND_THEN_OR32) ( + IN REGISTER_ACCESS *This, + IN UINT32 Offset, + IN UINT32 AndData, + IN UINT32 OrData + ); + +struct _REGISTER_ACCESS { + REG_READ8 Read8; + REG_WRITE8 Write8; + REG_OR8 Or8; + REG_AND8 And8; + REG_AND_THEN_OR8 AndThenOr8; + + REG_READ16 Read16; + REG_WRITE16 Write16; + REG_OR16 Or16; + REG_AND16 And16; + REG_AND_THEN_OR16 AndThenOr16; + + REG_READ32 Read32; + REG_WRITE32 Write32; + REG_OR32 Or32; + REG_AND32 And32; + REG_AND_THEN_OR32 AndThenOr32; +}; + +#endif -- 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108727): https://edk2.groups.io/g/devel/message/108727 Mute This Topic: https://groups.io/mt/101373953/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-