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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rosen.chuang@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: VAWSthuYDlX16dlHt9Id7VW8x7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=BTSsb+ND; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") Reviewed-by: Rosen Chuang < rosen.chuang@intel.com> Thanks, Rosen -----Original Message----- From: Kasbekar, Saloni =20 Sent: Saturday, August 5, 2023 1:38 AM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Oram, Isaac W ; Chuang, Rosen Subject: [PATCH v2 1/7] AlderlakeSiliconPkg: Add package and library instan= ces Create the AlderlakeSiliconPkg to provide an initial package for silicon in= itialization code for Alder Lake (ADL) products. Add the following librarie= s - - BasePciSegmentMultiSegLibPci - BaseSiConfigBlockLib - PeiPostMemSiliconPolicyInitLib - PeiPreMemSiliconPolicyInitLib Cc: Sai Chaganty Cc: Nate DeSimone Cc: Isaac Oram Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../BasePciSegmentMultiSegLibPci.inf | 37 ++ .../BasePciSegmentMultiSegLibPci.uni | 14 + .../PciSegmentLib.c | 597 ++++++++++++++++++ .../BaseSiConfigBlockLib.c | 87 +++ .../BaseSiConfigBlockLib.inf | 32 + .../PeiPostMemSiliconPolicyInitLib.c | 94 +++ .../PeiPostMemSiliconPolicyInitLib.inf | 36 ++ .../PeiPreMemSiliconPolicyInitLib.c | 98 +++ .../PeiPreMemSiliconPolicyInitLib.inf | 36 ++ 9 files changed, 1031 insertions(+) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/BasePciSegmen= tMultiSegLibPci/BasePciSegmentMultiSegLibPci.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/BasePciSegmen= tMultiSegLibPci/BasePciSegmentMultiSegLibPci.uni create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/BasePciSegmen= tMultiSegLibPci/PciSegmentLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/BaseSiConfigB= lockLib/BaseSiConfigBlockLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/BaseSiConfigB= lockLib/BaseSiConfigBlockLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/PeiPostMemSil= iconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/PeiPostMemSil= iconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/PeiPreMemSili= conPolicyInitLib/PeiPreMemSiliconPolicyInitLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Library/PeiPreMemSili= conPolicyInitLib/PeiPreMemSiliconPolicyInitLib.inf diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Library/BasePciSegmentMultiS= egLibPci/BasePciSegmentMultiSegLibPci.inf b/Silicon/Intel/AlderlakeSiliconP= kg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.inf new file mode 100644 index 0000000000..f3764d0187 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Library/BasePciSegmentMultiSegLi +++ bPci/BasePciSegmentMultiSegLibPci.inf @@ -0,0 +1,37 @@ +## @file +# Instance of PCI Segment Library based on PCI Library. +# +# PCI Segment Library that layers on top of the PCI Library which only=20 +# supports segment 0 and segment 1 PCI configuration access. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BasePciSegmentMultiSegLibPci + MODULE_UNI_FILE =3D BasePciSegmentMultiSegLibPci.uni + FILE_GUID =3D AC65B409-DF03-466e-8D2B-6FCE1079F0B2 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PciSegmentLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[Sources] + PciSegmentLib.c + +[Packages] + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + +[LibraryClasses] + BaseLib + PciLib + DebugLib + PcdLib diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Library/BasePciSegmentMultiS= egLibPci/BasePciSegmentMultiSegLibPci.uni b/Silicon/Intel/AlderlakeSiliconP= kg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.uni new file mode 100644 index 0000000000..dd8d74bee8 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Library/BasePciSegmentMultiSegLi +++ bPci/BasePciSegmentMultiSegLibPci.uni @@ -0,0 +1,14 @@ +// /** @file +// Instance of PCI Segment Library based on PCI Library. +// +// PCI Segment Library that layers on top of the PCI Library which only=20 +// supports segment 0 and segment 1 PCI configuration access. +// +// Copyright (c) 2022, Intel Corporation. All rights reserved.
+// SPDX-License-Identifier: BSD-2-Clause-Patent +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Instance of PCI S= egment Library based on PCI Library." + +#string STR_MODULE_DESCRIPTION #language en-US "PCI Segment Libra= ry that layers on top of the PCI Library which only supports segment 0 and = segment 1 PCI configuration access." diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Library/BasePciSegmentMultiS= egLibPci/PciSegmentLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Library/BasePc= iSegmentMultiSegLibPci/PciSegmentLib.c new file mode 100644 index 0000000000..9bcb388016 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Library/BasePciSegmentMultiSegLi +++ bPci/PciSegmentLib.c @@ -0,0 +1,597 @@ +/** @file + PCI Segment Library that layers on top of the PCI Library which only + supports segment 0 and segment 1 PCI configuration access. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#include +#include +#include +#include +#include + +/** + Assert the validity of a PCI Segment address. + A valid PCI Segment address should not contain 1's in bits 28..31 and=20 +33..63 + and the segment should be 0 or 1. + + @param A The address to validate. + @param M Additional bits to assert to be zero. + +**/ +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \ + ASSERT (((A) & (0xfffffffef0000000ULL | (M))) =3D=3D 0) + +/** + Convert the PCI Segment library address to PCI library address. + From ICL generation support the multiple segment, and the segment=20 +number start from BIT28, + So we convert the Segment Number offset from BIT32 to BIT28 + + @param A The address to convert. +**/ +#define PCI_SEGMENT_TO_PCI_ADDRESS(A) ((UINTN) (UINT32) ((A) |=20 +((RShiftU64 ((A) & BIT32, 4))))) + + + +/** + Reads an 8-bit PCI configuration register. + + Reads and returns the 8-bit PCI configuration register specified by Addr= ess. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register. + + @return The 8-bit PCI configuration register specified by Address. + +**/ +UINT8 +EFIAPI +PciSegmentRead8 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + + return PciRead8 (PCI_SEGMENT_TO_PCI_ADDRESS (Address)); } + +/** + Writes an 8-bit PCI configuration register. + + Writes the 8-bit PCI configuration register specified by Address with th= e value specified by Value. + Value is returned. This function must guarantee that all PCI read and w= rite operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Devic= e, Function, and Register. + @param Value The value to write. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentWrite8 ( + IN UINT64 Address, + IN UINT8 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); + + return PciWrite8 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), Value); } + +/** + Performs a bitwise OR of an 8-bit PCI configuration register with an 8-b= it value. + + Reads the 8-bit PCI configuration register specified by Address, =20 + performs a bitwise OR between the read result and the value specified=20 + by OrData, and writes the result to the 8-bit PCI configuration register= specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentOr8 ( + IN UINT64 Address, + IN UINT8 OrData + ) +{ + return PciWrite8 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), (UINT8)=20 +(PciSegmentRead8 (Address) | OrData)); } + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-= bit value. + + Reads the 8-bit PCI configuration register specified by Address, =20 + performs a bitwise AND between the read result and the value specified=20 + by AndData, and writes the result to the 8-bit PCI configuration registe= r specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register. + @param AndData The value to AND with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentAnd8 ( + IN UINT64 Address, + IN UINT8 AndData + ) +{ + return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address)=20 +& AndData)); } + +/** + Performs a bitwise AND of an 8-bit PCI configuration register with an=20 +8-bit value, + followed a bitwise OR with another 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, =20 + performs a bitwise AND between the read result and the value specified=20 + by AndData, performs a bitwise OR between the result of the AND=20 + operation and the value specified by OrData, and writes the result to th= e 8-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT8 +EFIAPI +PciSegmentAndThenOr8 ( + IN UINT64 Address, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address)=20 +& AndData) | OrData)); } + +/** + Reads a 16-bit PCI configuration register. + + Reads and returns the 16-bit PCI configuration register specified by Add= ress. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register. + + @return The 16-bit PCI configuration register specified by Address. + +**/ +UINT16 +EFIAPI +PciSegmentRead16 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); + + return PciRead16 (PCI_SEGMENT_TO_PCI_ADDRESS (Address)); } + +/** + Writes a 16-bit PCI configuration register. + + Writes the 16-bit PCI configuration register specified by Address with t= he value specified by Value. + Value is returned. This function must guarantee that all PCI read and w= rite operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Devic= e, Function, and Register. + @param Value The value to write. + + @return The parameter of Value. + +**/ +UINT16 +EFIAPI +PciSegmentWrite16 ( + IN UINT64 Address, + IN UINT16 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); + + return PciWrite16 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), Value); } + +/** + Performs a bitwise OR of a 16-bit PCI configuration register with + a 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address,=20 + performs a bitwise OR between the read result and the value specified=20 + by OrData, and writes the result to the 16-bit PCI configuration=20 + register specified by Address. The value written to the PCI=20 + configuration register is returned. This function must guarantee that=20 + all PCI read and write operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device, F= unction and + Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written back to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentOr16 ( + IN UINT64 Address, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16=20 +(Address) | OrData)); } + +/** + Performs a bitwise AND of a 16-bit PCI configuration register with a=20 +16-bit value, + followed a bitwise OR with another 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, =20 + performs a bitwise AND between the read result and the value specified=20 + by AndData, performs a bitwise OR between the result of the AND=20 + operation and the value specified by OrData, and writes the result to th= e 16-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT16 +EFIAPI +PciSegmentAndThenOr16 ( + IN UINT64 Address, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16=20 +(Address) & AndData) | OrData)); } + +/** + Reads a 32-bit PCI configuration register. + + Reads and returns the 32-bit PCI configuration register specified by Add= ress. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register. + + @return The 32-bit PCI configuration register specified by Address. + +**/ +UINT32 +EFIAPI +PciSegmentRead32 ( + IN UINT64 Address + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); + + return PciRead32 (PCI_SEGMENT_TO_PCI_ADDRESS (Address)); } + +/** + Writes a 32-bit PCI configuration register. + + Writes the 32-bit PCI configuration register specified by Address with t= he value specified by Value. + Value is returned. This function must guarantee that all PCI read and w= rite operations are serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Devic= e, Function, and Register. + @param Value The value to write. + + @return The parameter of Value. + +**/ +UINT32 +EFIAPI +PciSegmentWrite32 ( + IN UINT64 Address, + IN UINT32 Value + ) +{ + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); + + return PciWrite32 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), Value); } + +/** + Performs a bitwise OR of a 32-bit PCI configuration register with a 32-b= it value. + + Reads the 32-bit PCI configuration register specified by Address, =20 + performs a bitwise OR between the read result and the value specified=20 + by OrData, and writes the result to the 32-bit PCI configuration registe= r specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentOr32 ( + IN UINT64 Address, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) |=20 +OrData); } + +/** + Performs a bitwise AND of a 32-bit PCI configuration register with a=20 +32-bit value, + followed a bitwise OR with another 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, =20 + performs a bitwise AND between the read result and the value specified=20 + by AndData, performs a bitwise OR between the result of the AND=20 + operation and the value specified by OrData, and writes the result to th= e 32-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are = serialized. + + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). + + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. + + @return The value written to the PCI configuration register. + +**/ +UINT32 +EFIAPI +PciSegmentAndThenOr32 ( + IN UINT64 Address, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) &=20 +AndData) | OrData); } +/** + Reads a range of PCI configuration registers into a caller supplied buff= er. + + Reads the range of PCI configuration registers specified by=20 + StartAddress and Size into the buffer specified by Buffer. This=20 + function only allows the PCI configuration registers from a single=20 + PCI function to be read. Size is returned. When possible 32-bit PCI=20 + configuration read cycles are used to read from StartAdress to=20 + StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit=20 + PCI configuration read cycles may be used at the beginning and the end o= f the range. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Segment,= Bus, Device, + Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer receiving the data read. + + @return Size + +**/ +UINTN +EFIAPI +PciSegmentReadBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + OUT VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); ASSERT=20 + (((StartAddress & 0xFFF) + Size) <=3D 0x1000); + + if (Size =3D=3D 0) { + return Size; + } + + ASSERT (Buffer !=3D NULL); + if (Buffer =3D=3D NULL) { + return 0; + } + + // + // Save Size for return + // + ReturnValue =3D Size; + + if ((StartAddress & BIT0) !=3D 0) { + // + // Read a byte if StartAddress is byte aligned + // + *(volatile UINT8 *)Buffer =3D PciSegmentRead8 (StartAddress); + StartAddress +=3D sizeof (UINT8); + Size -=3D sizeof (UINT8); + Buffer =3D (UINT8*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16) && (StartAddress & BIT1) !=3D 0) { + // + // Read a word if StartAddress is word aligned + // + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + 1; + } + + while (Size >=3D sizeof (UINT32)) { + // + // Read as many double words as possible + // + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress)); + StartAddress +=3D sizeof (UINT32); + Size -=3D sizeof (UINT32); + Buffer =3D (UINT32*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT16)) { + // + // Read the last remaining word if exist + // + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*)Buffer + 1; + } + + if (Size >=3D sizeof (UINT8)) { + // + // Read the last remaining byte if exist + // + *(volatile UINT8 *)Buffer =3D PciSegmentRead8 (StartAddress); } + + return ReturnValue; +} + +/** + Copies the data in a caller supplied buffer to a specified range of=20 +PCI + configuration space. + + Writes the range of PCI configuration registers specified by=20 + StartAddress and Size from the buffer specified by Buffer. This=20 + function only allows the PCI configuration registers from a single=20 + PCI function to be written. Size is returned. When possible 32-bit=20 + PCI configuration write cycles are used to write from StartAdress to=20 + StartAddress + Size. Due to alignment restrictions, 8-bit and 16-bit=20 + PCI configuration write cycles may be used at the beginning and the end = of the range. + + If any reserved bits in StartAddress are set, then ASSERT(). + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). + If Size > 0 and Buffer is NULL, then ASSERT(). + + @param StartAddress The starting address that encodes the PCI Segment,= Bus, Device, + Function and Register. + @param Size The size in bytes of the transfer. + @param Buffer The pointer to a buffer containing the data to wri= te. + + @return The parameter of Size. + +**/ +UINTN +EFIAPI +PciSegmentWriteBuffer ( + IN UINT64 StartAddress, + IN UINTN Size, + IN VOID *Buffer + ) +{ + UINTN ReturnValue; + + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0); ASSERT=20 + (((StartAddress & 0xFFF) + Size) <=3D 0x1000); + + if (Size =3D=3D 0) { + return 0; + } + + ASSERT (Buffer !=3D NULL); + if (Buffer =3D=3D NULL) { + return 0; + } + + // + // Save Size for return + // + ReturnValue =3D Size; + + if ((StartAddress & BIT0) !=3D 0) { + // + // Write a byte if StartAddress is byte aligned + // + PciSegmentWrite8 (StartAddress, *(UINT8*) Buffer); + StartAddress +=3D sizeof (UINT8); + Size -=3D sizeof (UINT8); + Buffer =3D (UINT8*) Buffer + 1; + } + + if (Size >=3D sizeof (UINT16) && (StartAddress & BIT1) !=3D 0) { + // + // Write a word if StartAddress is word aligned + // + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*) Buffer + 1; + } + + while (Size >=3D sizeof (UINT32)) { + // + // Write as many double words as possible + // + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer)); + StartAddress +=3D sizeof (UINT32); + Size -=3D sizeof (UINT32); + Buffer =3D (UINT32*) Buffer + 1; + } + + if (Size >=3D sizeof (UINT16)) { + // + // Write the last remaining word if exist + // + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer)); + StartAddress +=3D sizeof (UINT16); + Size -=3D sizeof (UINT16); + Buffer =3D (UINT16*) Buffer + 1; + } + + if (Size >=3D sizeof (UINT8)) { + // + // Write the last remaining byte if exist + // + PciSegmentWrite8 (StartAddress, *(UINT8*) Buffer); } + + return ReturnValue; +} diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Library/BaseSiConfigBlockLib= /BaseSiConfigBlockLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Library/BaseSiC= onfigBlockLib/BaseSiConfigBlockLib.c new file mode 100644 index 0000000000..93290d8371 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Library/BaseSiConfigBlockLib/Bas +++ eSiConfigBlockLib.c @@ -0,0 +1,87 @@ +/** @file + This file is BaseSiConfigBlockLib library is used to add config=20 +blocks + to config block header. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include=20 + #include #include=20 + #include #include=20 + #include + + +/** + GetComponentConfigBlockTotalSize get config block table total size. + + @param[in] ComponentBlocks Component blocks array + @param[in] TotalBlockCount Number of blocks + + @retval Size of config block table +**/ +UINT16 +EFIAPI +GetComponentConfigBlockTotalSize ( + IN COMPONENT_BLOCK_ENTRY *ComponentBlocks, + IN UINT16 TotalBlockCount + ) +{ + UINT16 TotalBlockSize; + UINT16 BlockCount; + + TotalBlockSize =3D 0; + for (BlockCount =3D 0 ; BlockCount < TotalBlockCount; BlockCount++) { + TotalBlockSize +=3D (UINT32) ComponentBlocks[BlockCount].Size; } + + return TotalBlockSize; +} + +/** + AddComponentConfigBlocks add all config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add config blocks + @param[in] ComponentBlocks Config blocks array + @param[in] TotalBlockCount Number of blocks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +AddComponentConfigBlocks ( + IN VOID *ConfigBlockTableAddress, + IN COMPONENT_BLOCK_ENTRY *ComponentBlocks, + IN UINT16 TotalBlockCount + ) +{ + UINT16 BlockCount; + VOID *ConfigBlockPointer; + CONFIG_BLOCK ConfigBlockBuf; + EFI_STATUS Status; + + Status =3D EFI_SUCCESS; + + // + // Initialize ConfigBlockPointer to NULL + // + ConfigBlockPointer =3D NULL; + // + // Loop to identify each config block from ComponentBlocks[] Table=20 +and add each of them + // + for (BlockCount =3D 0; BlockCount < TotalBlockCount; BlockCount++) { + ZeroMem (&ConfigBlockBuf, sizeof (CONFIG_BLOCK)); + CopyMem (&(ConfigBlockBuf.Header.GuidHob.Name), ComponentBlocks[BlockC= ount].Guid, sizeof (EFI_GUID)); + ConfigBlockBuf.Header.GuidHob.Header.HobLength =3D ComponentBlocks[Blo= ckCount].Size; + ConfigBlockBuf.Header.Revision =3D ComponentBlocks[Blo= ckCount].Revision; + ConfigBlockPointer =3D (VOID *)&ConfigBlockBuf; + Status =3D AddConfigBlock ((VOID *)ConfigBlockTableAddress, (VOID *)&C= onfigBlockPointer); + ASSERT_EFI_ERROR (Status); + if (ComponentBlocks[BlockCount].LoadDefault !=3D NULL) { + ComponentBlocks[BlockCount].LoadDefault (ConfigBlockPointer); + } + } + return Status; +} diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Library/BaseSiConfigBlockLib= /BaseSiConfigBlockLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Library/BaseS= iConfigBlockLib/BaseSiConfigBlockLib.inf new file mode 100644 index 0000000000..097095ef0d --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Library/BaseSiConfigBlockLib/Bas +++ eSiConfigBlockLib.inf @@ -0,0 +1,32 @@ +## @file +# Component description file for the BaseSiConfigBlockLib library. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D BaseSiConfigBlockLib +FILE_GUID =3D 6C068D0F-F48E-48CB-B369-433E507AF4A2 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D SiConfigBlockLib + + +[LibraryClasses] +DebugLib +IoLib +ConfigBlockLib + + +[Packages] +MdePkg/MdePkg.dec +AlderlakeSiliconPkg/SiPkg.dec + + +[Sources] +BaseSiConfigBlockLib.c + + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Library/PeiPostMemSiliconPol= icyInitLib/PeiPostMemSiliconPolicyInitLib.c b/Silicon/Intel/AlderlakeSilico= nPkg/Library/PeiPostMemSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLib.= c new file mode 100644 index 0000000000..a9d6c7e265 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Library/PeiPostMemSiliconPolicyI +++ nitLib/PeiPostMemSiliconPolicyInitLib.c @@ -0,0 +1,94 @@ +/** @file + This library initialize Silicon Policy for PostMemory. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include=20 + #include #include=20 + #include #include=20 + #include + +/** + Performs silicon post-mem policy initialization. + + The returned data must be used as input data for=20 + SiliconPolicyDonePostMem (), and SiliconPolicyUpdateLib.SiliconPolicyUpd= atePostMem (). + + @param[in, out] Policy Pointer to policy. + @return the initialized policy. +**/ +VOID * +EFIAPI +SiliconPolicyInitPostMem ( + IN OUT VOID *Policy + ) +{ + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicyPpi; + PEI_SI_DEFAULT_POLICY_INIT_PPI *PeiSiDefaultPolicyInitPpi; + + DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in=20 + Post-Memory...\n")); + + ASSERT (Policy =3D=3D NULL); + SiPolicyPpi =3D NULL; + PeiSiDefaultPolicyInitPpi =3D NULL; + + // + // Locate Policy init PPI to install default silicon policy // =20 + Status =3D PeiServicesLocatePpi ( + &gSiDefaultPolicyInitPpiGuid, + 0, + NULL, + (VOID **) &PeiSiDefaultPolicyInitPpi + ); + ASSERT_EFI_ERROR (Status); + if (PeiSiDefaultPolicyInitPpi !=3D NULL) { + Status =3D PeiSiDefaultPolicyInitPpi->PeiPolicyInit (); + ASSERT_EFI_ERROR (Status); + if (Status =3D=3D EFI_SUCCESS) { + Status =3D PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + } + } + + if (SiPolicyPpi =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create default policy!\n")); + return NULL; + } + + + return SiPolicyPpi; +} + +/** + The silicon post-mem policy is finalized. + Silicon code can do initialization based upon the policy data. + + The input Policy must be returned by SiliconPolicyInitPostMem(). + + @param[in] Policy Pointer to policy. + @retval RETURN_SUCCESS The policy is handled consumed by silicon code. +**/ +RETURN_STATUS +EFIAPI +SiliconPolicyDonePostMem ( + IN VOID *Policy + ) +{ + EFI_STATUS Status; + + Status =3D SiInstallPolicyReadyPpi (); + ASSERT_EFI_ERROR (Status); + DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in=20 + Post-Memory\n")); + + return Status; +} diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Library/PeiPostMemSiliconPol= icyInitLib/PeiPostMemSiliconPolicyInitLib.inf b/Silicon/Intel/AlderlakeSili= conPkg/Library/PeiPostMemSiliconPolicyInitLib/PeiPostMemSiliconPolicyInitLi= b.inf new file mode 100644 index 0000000000..b13d63d337 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Library/PeiPostMemSiliconPolicyI +++ nitLib/PeiPostMemSiliconPolicyInitLib.inf @@ -0,0 +1,36 @@ +## @file +# Component information file for Silicon Policy Init Library # This=20 +library implements Silicon Policy Initialization for PostMemory. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiPostMemSiliconPolicyInitLib + FILE_GUID =3D 20B51FFB-93D3-4546-9F13-2C91AEEF9212 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconPolicyInitLib + +[LibraryClasses] + BaseLib + PcdLib + PeiServicesLib + DebugLib + SiPolicyLib + +[Packages] + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + +[Sources] + PeiPostMemSiliconPolicyInitLib.c + +[Ppis] + gSiDefaultPolicyInitPpiGuid + gEfiPeiMpServicesPpiGuid + +[Depex] + gSiDefaultPolicyInitPpiGuid diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Library/PeiPreMemSiliconPoli= cyInitLib/PeiPreMemSiliconPolicyInitLib.c b/Silicon/Intel/AlderlakeSiliconP= kg/Library/PeiPreMemSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.c new file mode 100644 index 0000000000..74fb47a73d --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Library/PeiPreMemSiliconPolicyIn +++ itLib/PeiPreMemSiliconPolicyInitLib.c @@ -0,0 +1,98 @@ +/** @file + This library initialize Silicon Policy for PreMemory. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include=20 + #include #include=20 + #include #include=20 + + + +/** + Performs silicon pre-mem policy initialization. + + The returned data must be used as input data for=20 + SiliconPolicyDonePreMem (), and SiliconPolicyUpdateLib.SiliconPolicyUpda= tePreMem (). + + @param[in, out] Policy Pointer to policy. + @return the initialized policy. +**/ +VOID * +EFIAPI +SiliconPolicyInitPreMem ( + IN OUT VOID *Policy + ) +{ + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI =20 +*PeiPreMemSiDefaultPolicyInitPpi; + + DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in=20 + Pre-Memory...\n")); + + ASSERT (Policy =3D=3D NULL); + SiPreMemPolicyPpi =3D NULL; + PeiPreMemSiDefaultPolicyInitPpi =3D NULL; + + // + // Locate Policy init PPI to install default silicon policy // =20 + Status =3D PeiServicesLocatePpi ( + &gSiPreMemDefaultPolicyInitPpiGuid, + 0, + NULL, + (VOID **) &PeiPreMemSiDefaultPolicyInitPpi + ); + ASSERT_EFI_ERROR (Status); + if (PeiPreMemSiDefaultPolicyInitPpi !=3D NULL) { + Status =3D PeiPreMemSiDefaultPolicyInitPpi->PeiPreMemPolicyInit (); + ASSERT_EFI_ERROR (Status); + if (Status =3D=3D EFI_SUCCESS) { + Status =3D PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + } + } + + if (SiPreMemPolicyPpi =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create default policy!\n")); + return NULL; + } + + return SiPreMemPolicyPpi; +} + +/** + The silicon pre-mem policy is finalized. + Silicon code can do initialization based upon the policy data. + + The input Policy must be returned by SiliconPolicyInitPreMem(). + + @param[in] Policy Pointer to policy. + @retval RETURN_SUCCESS The policy is handled consumed by silicon code. +**/ +RETURN_STATUS +EFIAPI +SiliconPolicyDonePreMem ( + IN VOID *Policy + ) +{ + EFI_STATUS Status; + // + // Install PreMem Policy Ready PPI + // While installs PreMemPolicyReadyPpi, RC assumes the Policy is=20 +ready and finalized. So please + // update and override any setting before calling this function. + // + Status =3D SiPreMemInstallPolicyReadyPpi (); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in=20 + Pre-Memory\n")); + + return Status; +} diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Library/PeiPreMemSiliconPoli= cyInitLib/PeiPreMemSiliconPolicyInitLib.inf b/Silicon/Intel/AlderlakeSilico= nPkg/Library/PeiPreMemSiliconPolicyInitLib/PeiPreMemSiliconPolicyInitLib.in= f new file mode 100644 index 0000000000..d5ce714ce5 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Library/PeiPreMemSiliconPolicyIn +++ itLib/PeiPreMemSiliconPolicyInitLib.inf @@ -0,0 +1,36 @@ +## @file +# Component information file for Silicon Policy Init Library # This=20 +library implements Silicon Policy Initialization for PreMemory. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiPreMemSiliconPolicyInitLib + FILE_GUID =3D 1FB4B175-0BB6-4137-A4AC-EA48FCE83862 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconPolicyInitLib + +[LibraryClasses] + BaseLib + PeiServicesLib + DebugLib + SiPolicyLib + +[Packages] + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + +[Sources] + PeiPreMemSiliconPolicyInitLib.c + +[Pcd] + +[Ppis] + gSiPreMemDefaultPolicyInitPpiGuid + +[Depex] + gSiPreMemDefaultPolicyInitPpiGuid -- 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#107779): https://edk2.groups.io/g/devel/message/107779 Mute This Topic: https://groups.io/mt/100551000/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-