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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rosen.chuang@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 6nueeWm8ORHXWXoOlLOGymmpx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="YCS/0ng+"; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Reviewed-by: Rosen Chuang < rosen.chuang@intel.com> -----Original Message----- From: Kasbekar, Saloni =20 Sent: Wednesday, August 2, 2023 6:18 AM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Oram, Isaac W ; Chuang, Rosen Subject: [PATCH v2 6/6] AlderlakeOpenBoardPkg: Add Library Instances Adds the following libraries - BasePlatformHookLib - PeiBoardConfigLib - PeiGetFvInfoLib - SmmSpiFlashCommonLib Cc: Sai Chaganty Cc: Nate DeSimone Cc: Isaac Oram Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../BasePlatformHookLib/BasePlatformHookLib.c | 38 ++++ .../BasePlatformHookLib.inf | 44 ++++ .../PeiBoardConfigLib/PeiBoardConfigLib.c | 136 +++++++++++ .../PeiBoardConfigLib/PeiBoardConfigLib.inf | 56 +++++ .../Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c | 89 ++++++++ .../PeiGetFvInfoLib/PeiGetFvInfoLib.inf | 34 +++ .../SmmSpiFlashCommonLib.inf | 49 ++++ .../SmmSpiFlashCommonLib/SpiFlashCommon.c | 215 ++++++++++++++++++ .../SpiFlashCommonSmmLib.c | 60 +++++ 9 files changed, 721 insertions(+) create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatfo= rmHookLib/BasePlatformHookLib.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatfo= rmHookLib/BasePlatformHookLib.inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardCo= nfigLib/PeiBoardConfigLib.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardCo= nfigLib/PeiBoardConfigLib.inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvIn= foLib/PeiGetFvInfoLib.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvIn= foLib/PeiGetFvInfoLib.inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlas= hCommonLib/SmmSpiFlashCommonLib.inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlas= hCommonLib/SpiFlashCommon.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlas= hCommonLib/SpiFlashCommonSmmLib.c diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookL= ib/BasePlatformHookLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/Bas= ePlatformHookLib/BasePlatformHookLib.c new file mode 100644 index 0000000000..cccb1e18cc --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/B +++ asePlatformHookLib.c @@ -0,0 +1,38 @@ +/** @file + Platform Hook Library instances + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + + +/** + Performs platform specific initialization required for the CPU to=20 +access + the hardware associated with a SerialPortLib instance. This function=20 +does + not initialize the serial port hardware itself. Instead, it=20 +initializes + hardware devices that are required for the CPU to access the serial=20 +port + hardware. This function may be called more than once. + + @retval RETURN_SUCCESS The platform specific initialization succee= ded. + @retval RETURN_DEVICE_ERROR The platform specific initialization could = not be completed. + +**/ +RETURN_STATUS +EFIAPI +PlatformHookSerialPortInitialize ( + VOID + ) +{ + + // + // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2E= h/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h. + // + PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange)); =20 + PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding)); + + return RETURN_SUCCESS; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookL= ib/BasePlatformHookLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/B= asePlatformHookLib/BasePlatformHookLib.inf new file mode 100644 index 0000000000..b77724d5ab --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/B +++ asePlatformHookLib.inf @@ -0,0 +1,44 @@ +### @file +# Platform Hook Library instance for Alderlake Mobile/Desktop CRB. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D BasePlatformHookLib + FILE_GUID =3D E22ADCC6-ED90-4A90-9837-C8E7FF9E963D + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D PlatformHookLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC # + +[LibraryClasses] + BaseLib + IoLib + PciSegmentLib + PciLib + PchCycleDecodingLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec + AlderlakeSiliconPkg/SiPkg.dec + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + +[FixedPcd] + gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES + gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES + +[Sources] + BasePlatformHookLib.c diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib= /PeiBoardConfigLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoar= dConfigLib/PeiBoardConfigLib.c new file mode 100644 index 0000000000..a9674bdd22 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/Pei +++ BoardConfigLib.c @@ -0,0 +1,136 @@ +/** @file + Implementation of PeiBoardConfigLib. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + + +VOID +EFIAPI +InternalUpdateRvpBoardConfig ( + IN OUT UINT16 BoardId + ) +{ + // + // Update Board Type/Platform Type/Platform Flavor + // + switch (BoardId) { + case BoardIdAdlPDdr5Rvp: + if(PcdSet64S (PcdAcpiDefaultOemTableId, ACPI_OEM_TABLE_ID_ADL_P_M) != =3D EFI_SUCCESS) + { + DEBUG ((DEBUG_INFO, "Set PcdAcpiDefaultOemTableId error!!!\n")); + } + break; + } + DEBUG ((DEBUG_INFO, "PcdAcpiDefaultOemTableId is 0x%llX\n", PcdGet64=20 +(PcdAcpiDefaultOemTableId))); } + +/** + Procedure to detect current board HW configuration. + +**/ +VOID +GetBoardConfig ( + VOID + ) +{ + UINT16 BoardId; + + // + // Get Platform Info and fill the PCD // + BoardId =3D BoardIdAdlPDdr5Rvp; + PcdSet16S (PcdBoardId, BoardId); + // + // update RVP board config + // + InternalUpdateRvpBoardConfig (BoardId); + + DEBUG ((DEBUG_INFO, "Platform Information:\n")); DEBUG ((DEBUG_INFO,=20 + "BoardID: 0x%x\n", BoardId)); + +} + +/** + Count the number of GPIO settings in the Table. + + @param[in] GpioTable The pointer of GPIO config table + @param[out] GpioCount The number of GPIO config entries +**/ +VOID +GetGpioTableSize ( + GPIO_INIT_CONFIG *GpioTable, + OUT UINT16 *GpioCount + ) +{ + *GpioCount =3D 0; + if(GpioTable !=3D NULL) { + while (GpioTable[*GpioCount].GpioPad !=3D 0 && *GpioCount < MAX_GPIO_P= INS) { + DEBUG ((DEBUG_INFO, "GpioTable[%d]->GpioPad =3D %x \n", *GpioCount, = GpioTable[*GpioCount].GpioPad)); + (*GpioCount) ++; + } + } else { + DEBUG ((DEBUG_INFO, "GpioTable is NULL\n")); + } + DEBUG ((DEBUG_INFO, "GetGpioTableSize() GpioCount =3D %d\n",=20 +*GpioCount)); } + +/** + Configures GPIO + + @param[in] GpioTable Point to Platform Gpio table + @param[in] GpioTableCount Number of Gpio table entries **/ STATIC=20 +VOID ConfigureGpio ( + IN GPIO_INIT_CONFIG *GpioTable, + IN UINT16 GpioTableCount + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n")); + + Status =3D GpioConfigurePads (GpioTableCount, GpioTable); =20 + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); } + +/** + Configure GPIO Before Memory is initialized. + + @param[in] GpioTable Pointer to Gpio table **/ VOID GpioInit ( + IN GPIO_INIT_CONFIG *GpioTable + ) +{ + UINT16 GpioCount; + + if (GpioTable !=3D 0) { + GpioCount =3D 0; + GetGpioTableSize (GpioTable, &GpioCount); + if (GpioCount !=3D 0) { + ConfigureGpio ((VOID *) GpioTable, (UINTN) GpioCount); + } + } +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib= /PeiBoardConfigLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBo= ardConfigLib/PeiBoardConfigLib.inf new file mode 100644 index 0000000000..1f78e9a0ba --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/Pei +++ BoardConfigLib.inf @@ -0,0 +1,56 @@ +### @file +# Component information file for BaseBoardConfigLib. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiBoardConfigLib + FILE_GUID =3D AA9812A8-1BA6-40AD-A846-50D0BC29C38C + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BoardConfigLib|PEIM + +[LibraryClasses] + DebugLib + PcdLib + PostCodeLib + TimerLib + PeiServicesLib + PmcLib + GpioLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec + +[Sources] + PeiBoardConfigLib.c + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId ## PRODUCES ## = CONSUMES + gBoardModuleTokenSpaceGuid.PcdBoardId ## PRODUCES ## = CONSUMES + gBoardModuleTokenSpaceGuid.PcdBoardBomId ## PRODUCES ## = CONSUMES + gBoardModuleTokenSpaceGuid.PcdBoardRev ## PRODUCES ## = CONSUMES + gBoardModuleTokenSpaceGuid.PcdSpdPresent ## PRODUCES ## = CONSUMES + + # GPIO Group Tier + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0 + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1 + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2 + + gBoardModuleTokenSpaceGuid.PcdDisableVpdGpioTable + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem + +[Depex] + gEfiPeiReadOnlyVariable2PpiGuid diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/P= eiGetFvInfoLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInf= oLib/PeiGetFvInfoLib.c new file mode 100644 index 0000000000..d9ed1c5064 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGe +++ tFvInfoLib.c @@ -0,0 +1,89 @@ +/** @file + Helper Library for PEI Graphics PEIM + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +/** + PeiGetSectionFromFv finds the file in FV and gets file Address and=20 +Size + + @param[in] NameGuid - File GUID + @param[out] Address - Pointer to the File Address + @param[out] Size - Pointer to File Size + + @retval EFI_SUCCESS Successfull in reading the section fr= om FV + @retval EFI_NOT_FOUND File not found +**/ +EFI_STATUS +EFIAPI +PeiGetSectionFromFv ( + IN CONST EFI_GUID NameGuid, + OUT VOID **Address, + OUT UINT32 *Size + ) +{ + EFI_STATUS Status; + EFI_PEI_FIRMWARE_VOLUME_PPI *FvPpi; + EFI_FV_FILE_INFO FvFileInfo; + PEI_CORE_FV_HANDLE *CoreFvHandle; + EFI_PEI_FILE_HANDLE FileHandle; + EFI_GUID *FileGuid; + EFI_COMMON_SECTION_HEADER *Section; + EFI_HOB_GUID_TYPE *GuidHob; + VOID *HobData; + + Status =3D PeiServicesLocatePpi( + &gEfiFirmwareFileSystem2Guid, + 0, + NULL, + (VOID **)&FvPpi + ); + ASSERT_EFI_ERROR(Status); + + GuidHob =3D GetFirstGuidHob (&gPlatformInitFvLocationGuid); if=20 + (GuidHob !=3D NULL) { + HobData =3D *(VOID **)GET_GUID_HOB_DATA(GuidHob); + CoreFvHandle =3D (PEI_CORE_FV_HANDLE *) HobData; + + // + // File typically resides in current FV or previous FV, so searching b= oth of them. + // + Status =3D FvPpi->FindFileByName (FvPpi, &NameGuid,=20 + &CoreFvHandle->FvHandle, &FileHandle); + + if (!EFI_ERROR(Status) && FileHandle !=3D NULL) { + + DEBUG((DEBUG_INFO, "Find SectionByType \n")); + + Status =3D FvPpi->FindSectionByType(FvPpi, EFI_SECTION_RAW, FileHand= le, (VOID **)&FileGuid); + if (!EFI_ERROR(Status)) { + + DEBUG((DEBUG_INFO, "GetFileInfo \n")); + + Status =3D FvPpi->GetFileInfo(FvPpi, FileHandle, &FvFileInfo); + Section =3D (EFI_COMMON_SECTION_HEADER *)FvFileInfo.Buffer; + + if (IS_SECTION2(Section)) { + ASSERT(SECTION2_SIZE(Section) > 0x00FFFFFF); + *Size =3D SECTION2_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HE= ADER2); + *Address =3D ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEAD= ER2)); + } else { + *Size =3D SECTION_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEA= DER); + *Address =3D ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEAD= ER)); + } + return EFI_SUCCESS; + } + } + } else { + DEBUG ((DEBUG_INFO, "Hob not found\n")); + } + return EFI_NOT_FOUND; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/P= eiGetFvInfoLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvI= nfoLib/PeiGetFvInfoLib.inf new file mode 100644 index 0000000000..1701fb15fe --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGe +++ tFvInfoLib.inf @@ -0,0 +1,34 @@ +### @file +# Component description file for PeiGetFvInfo library. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiGetFvInfoLib + FILE_GUID =3D C2584BE4-2CCD-418C-9205-A2031CE75861 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + LIBRARY_CLASS =3D PeiGetFvInfoLib + +[LibraryClasses] + BaseMemoryLib + BaseLib + DebugLib + DebugPrintErrorLevelLib + HobLib + PeiServicesLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec + +[Sources] + PeiGetFvInfoLib.c + +[Guids] + gPlatformInitFvLocationGuid ## CONSUMES diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommon= Lib/SmmSpiFlashCommonLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library= /SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf new file mode 100644 index 0000000000..cf6ca0d0ab --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/ +++ SmmSpiFlashCommonLib.inf @@ -0,0 +1,49 @@ +### @file +# SMM Library instance of Spi Flash Common Library Class # +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SmmSpiFlashCommonLib + FILE_GUID =3D 9632D96E-E849-4217-9217-DC500B8AAE47 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D DXE_SMM_DRIVER + LIBRARY_CLASS =3D SpiFlashCommonLib|DXE_SMM_DRIVER + CONSTRUCTOR =3D SmmSpiFlashCommonLibConstructor +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[LibraryClasses] + IoLib + MemoryAllocationLib + BaseLib + UefiLib + SmmServicesTableLib + BaseMemoryLib + DebugLib + +[Packages] + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec + +[Pcd] + gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES + +[Sources] + SpiFlashCommonSmmLib.c + SpiFlashCommon.c + +[Protocols] + gPchSmmSpiProtocolGuid ## CONSUMES + +[Depex.X64.DXE_SMM_DRIVER] + gPchSmmSpiProtocolGuid diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommon= Lib/SpiFlashCommon.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiF= lashCommonLib/SpiFlashCommon.c new file mode 100644 index 0000000000..3f7c52ac73 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/ +++ SpiFlashCommon.c @@ -0,0 +1,215 @@ +/** @file + Wrap EFI_SPI_PROTOCOL to provide some library level interfaces + for module use. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#include +#include + +PCH_SPI_PROTOCOL *mSpiProtocol; + +// +// Variables for boottime and runtime usage. +// +UINTN mBiosAreaBaseAddress =3D 0; +UINTN mBiosSize =3D 0; +UINTN mBiosOffset =3D 0; + +/** + Enable block protection on the Serial Flash device. + + @retval EFI_SUCCESS Operation is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashLock ( + VOID + ) +{ + EFI_STATUS Status; + + Status =3D EFI_SUCCESS; + + return Status; +} + +/** + Read NumBytes bytes of data from the address specified by + PAddress into Buffer. + + @param[in] Address The starting physical address of the read. + @param[in,out] NumBytes On input, the number of bytes to read. On = output, the number + of bytes actually read. + @param[out] Buffer The destination data buffer for the read. + + @retval EFI_SUCCESS Operation is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashRead ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + OUT UINT8 *Buffer + ) +{ + ASSERT ((NumBytes !=3D NULL) && (Buffer !=3D NULL)); + if ((NumBytes =3D=3D NULL) || (Buffer =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + // + // This function is implemented specifically for those platforms //=20 + at which the SPI device is memory mapped for read. So this //=20 + function just do a memory copy for Spi Flash Read. + // + CopyMem (Buffer, (VOID *) Address, *NumBytes); + + return EFI_SUCCESS; +} + +/** + Write NumBytes bytes of data from Buffer to the address specified by + PAddresss. + + @param[in] Address The starting physical address of the wri= te. + @param[in,out] NumBytes On input, the number of bytes to write. = On output, + the actual number of bytes written. + @param[in] Buffer The source data buffer for the write. + + @retval EFI_SUCCESS Operation is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + @retval EFI_INVALID_PARAMETER Invalid parameter. + @retval EFI_BAD_BUFFER_SIZE DataSectionSize in BGUP header e= xceeds the + size ofBIOS Guard script=20 + buffer + +**/ +EFI_STATUS +EFIAPI +SpiFlashWrite ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + UINTN Offset; + UINT32 Length; + UINT32 RemainingBytes; + + ASSERT ((NumBytes !=3D NULL) && (Buffer !=3D NULL)); if ((NumBytes =3D= =3D=20 + NULL) || (Buffer =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + ASSERT (Address >=3D mBiosAreaBaseAddress); if (Address <=20 + mBiosAreaBaseAddress) { + return EFI_INVALID_PARAMETER; + } + + Offset =3D Address - mBiosAreaBaseAddress; + + ASSERT ((*NumBytes + Offset) <=3D mBiosSize); if ((*NumBytes + Offset)= =20 + > mBiosSize) { + return EFI_INVALID_PARAMETER; + } + + Status =3D EFI_SUCCESS; + RemainingBytes =3D *NumBytes; + + while (RemainingBytes > 0) { + if (RemainingBytes > SECTOR_SIZE_4KB) { + Length =3D SECTOR_SIZE_4KB; + } else { + Length =3D RemainingBytes; + } + Status =3D mSpiProtocol->FlashWrite ( + mSpiProtocol, + FlashRegionBios, + (UINT32) Offset, + Length, + Buffer + ); + if (EFI_ERROR (Status)) { + break; + } + RemainingBytes -=3D Length; + Offset +=3D Length; + Buffer +=3D Length; + } + + // + // Actual number of bytes written + // + *NumBytes -=3D RemainingBytes; + + return Status; +} + +/** + Erase the block starting at Address. + + @param[in] Address The starting physical address of the block t= o be erased. + This library assume that caller garantee tha= t the PAddress + is at the starting address of this block. + @param[in] NumBytes On input, the number of bytes of the logical= block to be erased. + On output, the actual number of bytes erased= . + + @retval EFI_SUCCESS. Operation is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + @retval EFI_INVALID_PARAMETER Invalid parameter. + +**/ +EFI_STATUS +EFIAPI +SpiFlashBlockErase ( + IN UINTN Address, + IN UINTN *NumBytes + ) +{ + EFI_STATUS Status; + UINTN Offset; + UINTN RemainingBytes; + + ASSERT (NumBytes !=3D NULL); + if (NumBytes =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + ASSERT (Address >=3D mBiosAreaBaseAddress); if (Address <=20 + mBiosAreaBaseAddress) { + return EFI_INVALID_PARAMETER; + } + + Offset =3D Address - mBiosAreaBaseAddress; + + ASSERT ((*NumBytes % SECTOR_SIZE_4KB) =3D=3D 0); if ((*NumBytes %=20 + SECTOR_SIZE_4KB) !=3D 0) { + return EFI_INVALID_PARAMETER; + } + + ASSERT ((*NumBytes + Offset) <=3D mBiosSize); if ((*NumBytes + Offset)= =20 + > mBiosSize) { + return EFI_INVALID_PARAMETER; + } + + Status =3D EFI_SUCCESS; + RemainingBytes =3D *NumBytes; + + Status =3D mSpiProtocol->FlashErase ( + mSpiProtocol, + FlashRegionBios, + (UINT32) Offset, + (UINT32) RemainingBytes + ); + return Status; +} + diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommon= Lib/SpiFlashCommonSmmLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/S= mmSpiFlashCommonLib/SpiFlashCommonSmmLib.c new file mode 100644 index 0000000000..897d85743a --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/ +++ SpiFlashCommonSmmLib.c @@ -0,0 +1,60 @@ +/** @file + SMM Library instance of SPI Flash Common Library Class + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ + +#include +#include + +extern PCH_SPI_PROTOCOL *mSpiProtocol; + +extern UINTN mBiosAreaBaseAddress; +extern UINTN mBiosSize; +extern UINTN mBiosOffset; + +/** + The library constructuor. + + The function does the necessary initialization work for this library =20 + instance. + + @param[in] ImageHandle The firmware allocated handle for the UEFI= image. + @param[in] SystemTable A pointer to the EFI system table. + + @retval EFI_SUCCESS The function always return EFI_SUCCESS for= now. + It will ASSERT on error for debug version. + @retval EFI_ERROR Please reference LocateProtocol for error = code details. +**/ +EFI_STATUS +EFIAPI +SmmSpiFlashCommonLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINT32 BaseAddr; + UINT32 RegionSize; + + mBiosAreaBaseAddress =3D (UINTN) PcdGet32 (PcdBiosAreaBaseAddress); + mBiosSize =3D (UINTN) PcdGet32 (PcdBiosSize); + + // + // Locate the SMM SPI protocol. + // + Status =3D gSmst->SmmLocateProtocol ( + &gPchSmmSpiProtocolGuid, + NULL, + (VOID **) &mSpiProtocol + ); + ASSERT_EFI_ERROR (Status); + + mSpiProtocol->GetRegionAddress (mSpiProtocol, FlashRegionBios,=20 + &BaseAddr, &RegionSize); mBiosOffset =3D BaseAddr; + + return Status; +} -- 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#107584): https://edk2.groups.io/g/devel/message/107584 Mute This Topic: https://groups.io/mt/100494313/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-