* [edk2-devel] [PATCH v2 1/6] AlderlakeOpenBoardPkg: Add package and headers
@ 2023-08-01 22:17 Saloni Kasbekar
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 2/6] AlderlakeOpenBoardPkg: Add modules Saloni Kasbekar
` (6 more replies)
0 siblings, 7 replies; 18+ messages in thread
From: Saloni Kasbekar @ 2023-08-01 22:17 UTC (permalink / raw)
To: devel
Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Isaac Oram,
Rosen Chuang
Create the AlderlakeOpenBoardPkg to provide board support code. The
package supports Alderlake Mobile board with LPDDR4. The package
serves as a support package in the EDK II Minimum Platform design.
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Include/Library/BoardConfigLib.h | 59 ++++
.../Include/Library/PeiGetFvInfoLib.h | 29 ++
.../Include/Library/SpiFlashCommon.h | 99 ++++++
.../Include/PlatformBoardConfig.h | 93 ++++++
.../Include/PlatformBoardId.h | 21 ++
.../Include/PlatformGpioConfig.h | 18 +
.../Include/PlatformPostCode.h | 39 +++
.../Include/PolicyUpdateMacro.h | 48 +++
.../AlderlakeOpenBoardPkg/OpenBoardPkg.dec | 307 ++++++++++++++++++
9 files changed, 713 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h
new file mode 100644
index 0000000000..3a07563c5d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h
@@ -0,0 +1,59 @@
+/** @file
+ Function prototype of BoardConfigLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _BOARD_CONFIG_LIB_H_
+#define _BOARD_CONFIG_LIB_H_
+
+#include <Library/GpioLib.h>
+#include <PlatformBoardConfig.h>
+
+#define SIZE_OF_FIELD(TYPE, Field) (sizeof (((TYPE *)0)->Field))
+
+#define SIZE_OF_TABLE(TABLE, TYPE) (sizeof (TABLE) / sizeof (TYPE))
+
+#define BOARD_CONFIG PLATFORM_INFO
+
+#define PRE_MEM 0
+#define POST_MEM 1
+#define EARLY_PRE_MEM 2
+
+/**
+ Procedure to detect current board HW configuration.
+
+**/
+VOID
+EFIAPI
+GetBoardConfig (
+ VOID
+ );
+
+
+/**
+ Count the number of GPIO settings in the Table.
+
+ @param[in] GpioTable The pointer of GPIO config table
+ @param[out] GpioCount The number of GPIO config entries
+**/
+VOID
+GetGpioTableSize (
+ GPIO_INIT_CONFIG *GpioTable,
+ OUT UINT16 *GpioCount
+ );
+
+
+/**
+ Configure GPIO pads in PEI phase.
+
+ @param[in] GpioTable Pointer to Gpio table
+**/
+VOID
+GpioInit (
+ IN GPIO_INIT_CONFIG *GpioTable
+ );
+
+#endif // _BOARD_CONFIG_LIB_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h
new file mode 100644
index 0000000000..f2e5a77787
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h
@@ -0,0 +1,29 @@
+/** @file
+ Header file for PeiGetFvInfoLib..
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PEI_GET_FV_INFO_LIB_H_
+#define _PEI_GET_FV_INFO_LIB_H_
+
+/**
+ PeiGetSectionFromFv finds the file in FV and gets file Address and Size
+
+ @param[in] NameGuid - File GUID
+ @param[out] Address - Pointer to the File Address
+ @param[out] Size - Pointer to File Size
+
+ @retval EFI_SUCCESS Successfull in reading the section from FV
+**/
+EFI_STATUS
+EFIAPI
+PeiGetSectionFromFv (
+ IN CONST EFI_GUID NameGuid,
+ OUT VOID **Address,
+ OUT UINT32 *Size
+ );
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h
new file mode 100644
index 0000000000..76ba3a8094
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h
@@ -0,0 +1,99 @@
+/** @file
+ The header file includes the common header files, defines
+ internal structure and functions used by SpiFlashCommonLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SPI_FLASH_COMMON_H__
+#define __SPI_FLASH_COMMON_H__
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/Spi.h>
+
+#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size
+/**
+ Enable block protection on the Serial Flash device.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashLock (
+ VOID
+ );
+
+/**
+ Read NumBytes bytes of data from the address specified by
+ PAddress into Buffer.
+
+ @param[in] Address The starting physical address of the read.
+ @param[in,out] NumBytes On input, the number of bytes to read. On output, the number
+ of bytes actually read.
+ @param[out] Buffer The destination data buffer for the read.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashRead (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Write NumBytes bytes of data from Buffer to the address specified by
+ PAddresss.
+
+ @param[in] Address The starting physical address of the write.
+ @param[in,out] NumBytes On input, the number of bytes to write. On output,
+ the actual number of bytes written.
+ @param[in] Buffer The source data buffer for the write.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashWrite (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Erase the block starting at Address.
+
+ @param[in] Address The starting physical address of the block to be erased.
+ This library assume that caller garantee that the PAddress
+ is at the starting address of this block.
+ @param[in] NumBytes On input, the number of bytes of the logical block to be erased.
+ On output, the actual number of bytes erased.
+
+ @retval EFI_SUCCESS. Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashBlockErase (
+ IN UINTN Address,
+ IN UINTN *NumBytes
+ );
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h
new file mode 100644
index 0000000000..f9ac991eb4
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h
@@ -0,0 +1,93 @@
+/** @file
+ Header file for Platform Boards Configurations.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PLATFORM_BOARD_CONFIG_H
+#define _PLATFORM_BOARD_CONFIG_H
+
+#include <ConfigBlock.h>
+#include <PchPolicyCommon.h>
+#include <MemoryConfig.h>
+#include <Library/GpioConfig.h>
+
+#define MAX_GPIO_PINS 130
+
+//
+// ACPI table information used to update tables thru PCD
+//
+#define ACPI_OEM_TABLE_ID_ADL_P_M 0x4D2D502D4C4441 //ADL-P-M
+
+#pragma pack(1)
+
+typedef struct {
+ UINT8 ClkReqNumber : 4;
+ UINT8 ClkReqSupported : 1;
+ UINT8 DeviceResetPadActiveHigh : 1;
+ UINT32 DeviceResetPad;
+} ROOT_PORT_CLK_INFO;
+
+typedef struct {
+ UINT8 Section;
+ UINT8 Pin;
+} EXPANDER_GPIO_CONFIG;
+
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved[3]; // alignment for COMMON_GPIO_CONFIG
+ union {
+ UINT32 Pin;
+ EXPANDER_GPIO_CONFIG Expander;
+ } u;
+} BOARD_GPIO_CONFIG;
+
+// Do not change the encoding. It must correspond with PCH_PCIE_CLOCK_USAGE from PCH RC.
+#define NOT_USED 0xFF
+#define LAN_CLOCK 0x70
+#define PCIE_PEG 0x40
+#define PCIE_PCH 0x00
+
+typedef struct {
+ UINT32 ClockUsage;
+ UINT32 ClkReqSupported;
+} PCIE_CLOCK_CONFIG;
+
+typedef union {
+ UINT64 Blob;
+ BOARD_GPIO_CONFIG BoardGpioConfig;
+ ROOT_PORT_CLK_INFO Info;
+ PCIE_CLOCK_CONFIG PcieClock;
+} PCD64_BLOB;
+
+// Having Max CLK config to support both ADL P and ALD S
+#define PCH_MAX_PCIE_CLOCKS_SBC 18
+
+//seamless board configurations
+typedef struct {
+ UINT32 ClockUsage[PCH_MAX_PCIE_CLOCKS_SBC];
+} PCIE_CLOCKS_USAGE;
+
+#define SPD_DATA_SIZE 1024
+
+//SBC MRC DQS
+typedef struct {
+ UINT8 DqsMapCpu2Dram[8][2];
+} MRC_DQS;
+
+//SBC MRC DQ
+typedef struct {
+ UINT8 DqMapCpu2Dram[8][2][8];
+} MRC_DQ;
+
+//SBC SPD DATA
+typedef struct {
+ BOOLEAN OverrideSpd;
+ UINT8 SpdData[SPD_DATA_SIZE];
+} SPD_DATA;
+
+#pragma pack()
+
+#endif // _PLATFORM_BOARD_CONFIG_H
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h
new file mode 100644
index 0000000000..51b317ffec
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h
@@ -0,0 +1,21 @@
+/** @file
+Defines Platform BoardIds
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PLATFORM_BOARD_ID_H_
+#define _PLATFORM_BOARD_ID_H_
+
+//
+// Alderlake Sku IDs
+//
+#define SkuIdAdlPDdr5Rvp 0x000012
+#define AdlPSkuType 2
+
+// Alderlake P Board IDs
+#define BoardIdAdlPDdr5Rvp 0x12
+
+#endif // _PLATFORM_BOARD_ID_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h
new file mode 100644
index 0000000000..d8a4c2ab77
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h
@@ -0,0 +1,18 @@
+/** @file
+Defines Platform GPIO Configuration Arrary
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/GpioLib.h>
+
+#ifndef _PLATFORM_GPIO_CONFIG_H_
+#define _PLATFORM_GPIO_CONFIG_H_
+
+typedef struct {
+ GPIO_INIT_CONFIG GpioConfig[0];
+} GPIO_INIT_CONFIG_ARRAY;
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h
new file mode 100644
index 0000000000..4dbdd8e391
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h
@@ -0,0 +1,39 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PLATFORMPOSTCODE_H_
+#define _PLATFORMPOSTCODE_H_
+
+//
+// GENERAL USAGE GUIDELINES
+//
+
+/**
+[definition]
+PostCode = XYZZ
+X - "D"=premem, "9"=postmem, "8"=SMM, "7"=DXE
+Y - "6"=platform driver, "5"=board driver
+ZZ - "00"=entry, "7F"=exit
+ - 1 - board init premem: entry/exit (0xD500/0xD57F)
+ - 2 - platform init premem: entry/exit (0xD600/0xD67F)
+ - 3 - board init postmem: entry/exit (0x9500/0x957F)
+ - 4 - platform init postmem: entry/exit (0x9600/0x967F)
+ - 5 - board init DXE: entry/exit (0x7500/0x757F)
+ - 6 - platform init DXE: entry/exit (0x7600/0x767F)
+ - 7 - platform SMM init: entry/exit (0x8600/0x867F)
+ - 8 - BIOS S3 entry (0xB503) means BioS PC 03, to differentiate with ACPI _PTS PC
+ - 9 - BIOS S4 entry (0xB504) means BioS PC 04, to differentiate with ACPI _PTS PC
+ - 10 - BIOS S5 entry (0B505) means BioS PC 05, to differentiate with ACPI _PTS PC
+*/
+
+#define PLATFORM_INIT_PREMEM_ENTRY 0xD600
+#define PLATFORM_INIT_PREMEM_EXIT 0xD67F
+#define PLATFORM_INIT_POSTMEM_ENTRY 0x9600
+#define PLATFORM_INIT_POSTMEM_EXIT 0x967F
+#define PLATFORM_SMM_INIT_ENTRY 0x8600
+#define PLATFORM_SMM_INIT_EXIT 0x867F
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h
new file mode 100644
index 0000000000..c9ace9d910
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h
@@ -0,0 +1,48 @@
+/** @file
+ Macros for platform to update different types of policy.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _POLICY_UPDATE_MACRO_H_
+#define _POLICY_UPDATE_MACRO_H_
+
+#ifdef UPDATE_POLICY
+#undef UPDATE_POLICY
+#endif
+
+#ifdef COPY_POLICY
+#undef COPY_POLICY
+#endif
+
+#ifdef GET_POLICY
+#undef GET_POLICY
+#endif
+
+#ifdef AND_POLICY
+#undef AND_POLICY
+#endif
+
+#ifdef OR_POLICY
+#undef OR_POLICY
+#endif
+
+#define UPDATE_POLICY(UpdField, ConfigField, Value) ConfigField = Value;
+#define COPY_POLICY(UpdField, ConfigField, Value, Size) CopyMem (ConfigField, Value, Size);
+#define GET_POLICY(UpdField, ConfigField, Value) Value = ConfigField;
+#define AND_POLICY(UpdField, ConfigField, Value) ConfigField &= Value;
+#define OR_POLICY(UpdField, ConfigField, Value) ConfigField |= Value;
+//
+// Compare Policy Default and Setup Default when FirstBoot and RvpSupport
+//
+
+#define COMPARE_AND_UPDATE_POLICY(UpdField, ConfigField, Value) {\
+ UPDATE_POLICY(UpdField, ConfigField, Value);\
+}
+#define COMPARE_UPDATE_POLICY_ARRAY(UpdField, ConfigField, Value, ArrayIndex) {\
+ UPDATE_POLICY(UpdField, ConfigField, Value);\
+}
+
+#endif //_POLICY_UPDATE_MACRO_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec
new file mode 100644
index 0000000000..0f0ed386f6
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec
@@ -0,0 +1,307 @@
+## @file
+#
+# The DEC files are used by the utilities that parse DSC and
+# INF files to generate AutoGen.c and AutoGen.h files
+# for the build infrastructure.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+DEC_SPECIFICATION = 0x00010017
+PACKAGE_NAME = OpenBoardPkg
+PACKAGE_VERSION = 0.1
+PACKAGE_GUID = A840FA72-FBF7-4357-B301-DAE2233F14AB
+
+[Includes]
+Include
+
+[Guids]
+ gBoardModuleTokenSpaceGuid = {0x72d1fff7, 0xa42a, 0x4219, {0xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}}
+ gPlatformModuleTokenSpaceGuid = {0x69d13bf0, 0xaf91, 0x4d96, {0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}}
+ gPlatformInitFvLocationGuid = {0xa564010a, 0x1d90, 0x4b1c, {0x8d, 0x10, 0xcb, 0xba, 0xff, 0xb2, 0x55, 0x42}}
+ gVpdFfsGuid = {0x338FA35A, 0xCA4A, 0x4DBC, {0xA6, 0xF4, 0x9B, 0xD1, 0x59, 0x3B, 0x61, 0xBC}}
+ gMemoryConfigVariableGuid = {0xc94f8c4d, 0x9b9a, 0x45fe, {0x8a, 0x55, 0x23, 0x8b, 0x67, 0x30, 0x26, 0x43}}
+
+#
+# FvImage File
+#
+ gFvAdvancedFileGuid = {0xAD198BA5, 0xC330, 0x41CD, {0xB0, 0x97, 0x16, 0x48, 0x83, 0x28, 0xB7, 0x98}}
+ gFvOsBootFileGuid = {0xB9020753, 0x84A8, 0x4BB6, {0x94, 0x7C, 0xCE, 0x7D, 0x41, 0xF5, 0xCE, 0x39}}
+ gFvUefiBootFileGuid = {0x9E21FD93, 0x9C72, 0x4c15, {0x8C, 0x4B, 0xE7, 0x7F, 0x1D, 0xB2, 0xD7, 0x92}}
+ gTianoLogoGuid = {0x7BB28B99, 0x61BB, 0x11D5, {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}}
+
+ # gUefiShellFileGuid is FILE GUID for MinUefiShell.inf/UefiShell.inf/Shell.inf.
+ gUefiShellFileGuid = {0x7c04a583, 0x9e3e, 0x4f1c, {0xad, 0x65, 0xe0, 0x52, 0x68, 0xd0, 0xb4, 0xd1}}
+
+[Ppis]
+ gReadyForGopConfigPpiGuid = {0x5f252c18, 0x1781, 0x4290, {0xa7, 0xb6, 0xfd, 0x99, 0x63, 0x4c, 0x6a, 0x8a}}
+
+[PcdsFixedAtBuild, PcdsPatchableInModule]
+##
+## PcdSmbiosOemTypeFirmwareVersionInfo determines the SMBIOS OEM type (0x80 to 0xFF) defined in SMBIOS,
+## values 0-0x7F will be treated as disable FVI reporting.
+## FVI structure uses it as SMBIOS OEM type to provide version information.
+##
+gPlatformModuleTokenSpaceGuid.PcdSmbiosOemTypeFirmwareVersionInfo|0xDD|UINT8|0x20000001
+
+[PcdsFixedAtBuild]
+ gBoardModuleTokenSpaceGuid.PcdDefaultBoardId|0|UINT16|0x10101009
+
+ gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x10001010
+ gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|0x10001011
+
+ ##
+ ## The Flash PCDs will be patched based on FDF definitions during build.
+ ## Set them to 0 here to prevent confusion.
+ ##
+
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase|0x00000000|UINT32|0x20000040
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize|0x00000000|UINT32|0x20000041
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset|0x00000000|UINT32|0x20000042
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase|0x00000000|UINT32|0x2000004C
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize|0x00000000|UINT32|0x2000004D
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalOffset|0x00000000|UINT32|0x2000004E
+
+ gBoardModuleTokenSpaceGuid.PcdFlashObbSize|0x00000000|UINT32|0xF0000A53
+ gBoardModuleTokenSpaceGuid.PcdFlashIbbOffset|0x00000000|UINT32|0xF0000A58
+ gBoardModuleTokenSpaceGuid.PcdFlashIbbSize|0x00000000|UINT32|0xF0000A59
+ gBoardModuleTokenSpaceGuid.PcdFlashFvRsvdOffset|0x00000000|UINT32|0x20000A5E
+ gBoardModuleTokenSpaceGuid.PcdFlashFvRsvdSize|0x00000000|UINT32|0x20000A5F
+ gBoardModuleTokenSpaceGuid.PcdFlashIbbROffset|0x00000000|UINT32|0x20000A61
+
+#(ACPI.inf)
+ gPlatformModuleTokenSpaceGuid.PcdApicLocalAddress|0xFEE00000|UINT64|0x9000000B
+ gPlatformModuleTokenSpaceGuid.PcdApicIoAddress|0xFEC00000|UINT64|0x9000000D
+ gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012
+ gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013
+ gPlatformModuleTokenSpaceGuid.PcdApicIoIdPch|0x02|UINT8|0x9000001E
+
+#(BaseMmioInitLib.inf)
+gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress|0xFEDA0000|UINT64|0x90000003
+gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress|0xFEDA1000|UINT64|0x90000005
+
+## This PCD specifies whether StatusCode is reported via SerialIoUart
+gPlatformModuleTokenSpaceGuid.PcdStatusCodeUseSerialIoUart|FALSE|BOOLEAN|0xFF000002
+
+## This flag is used to initialize debug output interface.
+# BIT0 - RAM debug interface.
+# BIT1 - UART debug interface.
+# BIT2 - USB debug interface.
+# BIT3 - USB3 debug interface.
+# BIT4 - Serial IO debug interface.
+# BIT5 - TraceHub debug interface.
+# BIT6 - Reserved.
+# BIT7 - CMOS control.
+gPlatformModuleTokenSpaceGuid.PcdStatusCodeFlags|0x82|UINT8|0xF0000111
+
+gPlatformModuleTokenSpaceGuid.PcdGttMmAddress|0xAF000000|UINT64|0x9000000F
+gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress|0xB0000000|UINT64|0x90000010
+
+gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress|0xFED80000|UINT64|0x90000009
+
+gPlatformModuleTokenSpaceGuid.PcdLzmaEnable |FALSE|BOOLEAN|0xF000002B
+
+[PcdsDynamic]
+ # DRAM Configuration
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000174
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000175
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2Dram|0|UINT32|0x00000072
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2DramSize|0|UINT16|0x00000073
+
+ # SPD Address Table
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000199
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x0000019A
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x0000019B
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x0000019C
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable4|0|UINT8|0x0000019D
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable5|0|UINT8|0x0000019E
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable6|0|UINT8|0x0000019F
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable7|0|UINT8|0x000001A0
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable8|0|UINT8|0x000001A1
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable9|0|UINT8|0x000001A2
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable10|0|UINT8|0x000001A3
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable11|0|UINT8|0x000001A4
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable12|0|UINT8|0x000001A5
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable13|0|UINT8|0x000001A6
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable14|0|UINT8|0x000001A7
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable15|0|UINT8|0x000001A8
+
+ # Root Port Clock Info
+ gBoardModuleTokenSpaceGuid.PcdPcieClock0|0|UINT64|0x0000009E
+ gBoardModuleTokenSpaceGuid.PcdPcieClock1|0|UINT64|0x0000009F
+ gBoardModuleTokenSpaceGuid.PcdPcieClock2|0|UINT64|0x000000A0
+ gBoardModuleTokenSpaceGuid.PcdPcieClock3|0|UINT64|0x000000A1
+ gBoardModuleTokenSpaceGuid.PcdPcieClock4|0|UINT64|0x000000A2
+ gBoardModuleTokenSpaceGuid.PcdPcieClock5|0|UINT64|0x000000A3
+ gBoardModuleTokenSpaceGuid.PcdPcieClock6|0|UINT64|0x000000A4
+ gBoardModuleTokenSpaceGuid.PcdPcieClock7|0|UINT64|0x000000A5
+ gBoardModuleTokenSpaceGuid.PcdPcieClock8|0|UINT64|0x000000A6
+ gBoardModuleTokenSpaceGuid.PcdPcieClock9|0|UINT64|0x000000A7
+ gBoardModuleTokenSpaceGuid.PcdPcieClock10|0|UINT64|0x000000A8
+ gBoardModuleTokenSpaceGuid.PcdPcieClock11|0|UINT64|0x000000A9
+ gBoardModuleTokenSpaceGuid.PcdPcieClock12|0|UINT64|0x000000AA
+ gBoardModuleTokenSpaceGuid.PcdPcieClock13|0|UINT64|0x000000AB
+ gBoardModuleTokenSpaceGuid.PcdPcieClock14|0|UINT64|0x000000AC
+ gBoardModuleTokenSpaceGuid.PcdPcieClock15|0|UINT64|0x000000AD
+ gBoardModuleTokenSpaceGuid.PcdPcieClock16|0|UINT64|0x000000AE
+ gBoardModuleTokenSpaceGuid.PcdPcieClock17|0|UINT64|0x000000AF
+
+
+ # GPIO Group Tier
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0|0|UINT32|0x000000E9
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1|0|UINT32|0x000000EA
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2|0|UINT32|0x000000EB
+
+ # Display DDI
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable|0|UINT32|0x00100033
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize|0|UINT16|0x00100034
+
+ # MISC
+ gBoardModuleTokenSpaceGuid.PcdStackBase|0x0|UINT32|0x40000A10
+ gBoardModuleTokenSpaceGuid.PcdStackSize|0x0|UINT32|0x40000A11
+
+ # SA Misc Configuration
+ gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066
+ gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|0x00000067
+ gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMask|0|UINT8|0x0000A103
+ gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMaskEcc|0|UINT8|0x0000A104
+ gBoardModuleTokenSpaceGuid.PcdSaMiscDisableMrcRetrainingOnRtcPowerLoss|0|UINT8|0x0000A105
+
+ # Board Information
+ gBoardModuleTokenSpaceGuid.PcdSpdPresent|FALSE|BOOLEAN|0x00101012
+ gBoardModuleTokenSpaceGuid.PcdBoardRev|0x0|UINT16|0x00101016
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId|0x0|UINT16|0x00101017
+ gBoardModuleTokenSpaceGuid.PcdBoardId|0|UINT16|0x00101018
+ gBoardModuleTokenSpaceGuid.PcdSkuType|0x0|UINT8|0x0010101F
+
+ # MRC Config
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x00000A68
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x00000A69
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x00000A6A
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x00000A6B
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x00000A6C
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0x00000A6D
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALSE|BOOLEAN|0x00000A6E
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLEAN|0x00000A6F
+ gBoardModuleTokenSpaceGuid.PcdMrcLp5CccConfig|0|UINT8|0x00000A73
+ gBoardModuleTokenSpaceGuid.PcdMrcCmdMirror|0|UINT8|0x00000A74
+ gBoardModuleTokenSpaceGuid.PcdRootPortIndex|0xFF|UINT8|0x00000A78
+
+ # Pch SerialIo I2c Pads Termination
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm|0x1|UINT8|0x00000020
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm|0x1|UINT8|0x00000021
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm|0x1|UINT8|0x00000022
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm|0x1|UINT8|0x00000023
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm|0x1|UINT8|0x00000030
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm|0x1|UINT8|0x00000031
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c6PadInternalTerm|0x1|UINT8|0x00000032
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c7PadInternalTerm|0x1|UINT8|0x00000033
+
+[PcdsDynamicEx]
+# Flag to Disable Vpd Gpio
+gBoardModuleTokenSpaceGuid.PcdDisableVpdGpioTable|FALSE|BOOLEAN|0x50000015
+# Pre-Mem GPIO table
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem|{0}|GPIO_INIT_CONFIG_ARRAY|0x50000017 {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioLib.h
+ PlatformGpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+ gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|{0}|GPIO_INIT_CONFIG[]|0x50000018 {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioLib.h
+ Library/GpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# GPIO table
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTable|{0}|GPIO_INIT_CONFIG_ARRAY|0x50000019 {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioLib.h
+ PlatformGpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+ gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable|{0}|GPIO_INIT_CONFIG[]|0x5000001C {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# PCIE CLOCKS USAGE
+ gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|{0}|PCIE_CLOCKS_USAGE|0x50000022 {
+ <HeaderFiles>
+ PlatformBoardConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+#SBC SPD DATA
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData|{0}|SPD_DATA|0x50000025 {
+ <HeaderFiles>
+ PlatformBoardConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# SBC MRC DQS MAPPING
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcDqsMapCpu2Dram|{0}|MRC_DQS|0x50000026 {
+ <HeaderFiles>
+ PlatformBoardConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# SBC MRC DQ MAPPING
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcDqMapCpu2Dram|{0}|MRC_DQ|0x50000027 {
+ <HeaderFiles>
+ PlatformBoardConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# ACPI data
+ gBoardModuleTokenSpaceGuid.PcdBoardAcpiData|{0}|VOID*|0x5000001A
+
+# Early Pre-Mem GPIO table
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem|{0}|GPIO_INIT_CONFIG_ARRAY|0x5000001B {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioLib.h
+ PlatformGpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderLakeOpenBoardPkg/OpenBoardPkg.dec
+}
+[PcdsDynamic, PcdsDynamicEx]
+
+[PcdsPatchableInModule]
+
+[PcdsFeatureFlag]
+ gBoardModuleTokenSpaceGuid.PcdIntelGopEnable |FALSE|BOOLEAN|0xF0000B54
--
2.36.1.windows.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [edk2-devel] [PATCH v2 2/6] AlderlakeOpenBoardPkg: Add modules
2023-08-01 22:17 [edk2-devel] [PATCH v2 1/6] AlderlakeOpenBoardPkg: Add package and headers Saloni Kasbekar
@ 2023-08-01 22:17 ` Saloni Kasbekar
2023-08-02 17:46 ` Chaganty, Rangasai V
2023-08-04 0:42 ` Chuang, Rosen
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add libraries Saloni Kasbekar
` (5 subsequent siblings)
6 siblings, 2 replies; 18+ messages in thread
From: Saloni Kasbekar @ 2023-08-01 22:17 UTC (permalink / raw)
To: devel
Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Isaac Oram,
Rosen Chuang
Adds the following modules:
-BiosInfo
-OpenBoardPlatformInit
-SBCVpdStructurePcd
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c | 196 +++++++++++++++
.../BiosInfo/BiosInfo.inf | 84 +++++++
.../OpenBoardPlatformInitPostMem.c | 233 ++++++++++++++++++
.../OpenBoardPlatformInitPostMem.inf | 75 ++++++
.../SBCVpdStructurePcd/AllStructPCD.dsc | 19 ++
.../GpioTableAdlPPostMem.dsc | 40 +++
.../GpioTableAdlPPreMem.dsc | 29 +++
.../MrcDqDqsSPD/AdlPSpdMap.dsc | 138 +++++++++++
.../PcieClocks/AdlPPcieClocks.dsc | 31 +++
9 files changed, 845 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
new file mode 100644
index 0000000000..64462900de
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
@@ -0,0 +1,196 @@
+/** @file
+ PEIM to provide BiosInfo structure listing up all firmware volume's base addresses, sizes,
+ attributes, and information associated to the firmware volume.
+ Primarily the structure is used on FIT table creation and Bpm.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Guid/BiosInfo.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/FirmwareInterfaceTable.h>
+#include <Ppi/FirmwareVolumeInfoMeasurementExcluded.h>
+#include <Library/MemoryAllocationLib.h>
+
+#define BASE_FV_SIZE 10
+
+#define FSP_WRAPPER_FV_SIZE 3
+
+#define TSN_MAC_ADDRESS_FV_SIZE 0
+
+#define BIOS_INFO_STRUCT_SIZE (BASE_FV_SIZE + FSP_WRAPPER_FV_SIZE + TSN_MAC_ADDRESS_FV_SIZE)
+
+
+/*
+ BIOS_INFO structure is the base of the firmware volume layout for Intel platform BIOS implementation
+ so security checker module can run based on the structure and throw warnings, error or deadloop
+ when any unexpected firmware volumes are detected.
+
+ BIOS_INFO is recommended to support full entries of firmware volumes present in a flash
+ with right type, attribute, version, flash map base address and size,
+ all associated information which is defined by BIOS_INFO_STRUCT structure.
+ - IBB firmware volumes, which are expected to be measured or/and verified
+ by hardware base security solution to meet SecureBoot chain of trust
+ (Intel BootGuard for example), have attribute 0x0.
+ - Post IBB firmware volumes, which are expected to be measured or/and verified
+ by BIOS (TCG code for measurement, RSA2048SHA256Sign algorithm for verification for example),
+ have attribute BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB.
+ - Else, follows Firmware Interface Table specification.
+*/
+#pragma pack (1)
+typedef struct {
+ BIOS_INFO_HEADER Header;
+ BIOS_INFO_STRUCT Entry[BIOS_INFO_STRUCT_SIZE];
+} BIOS_INFO;
+#pragma pack ()
+
+GLOBAL_REMOVE_IF_UNREFERENCED BIOS_INFO mBiosInfo = {
+ {
+ BIOS_INFO_SIGNATURE,
+ BIOS_INFO_STRUCT_SIZE,
+ 0,
+ },
+ {
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashNvStorageVariableSize) + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize),
+ FixedPcdGet32 (PcdFlashNvStorageVariableBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvAdvancedSize),
+ FixedPcdGet32 (PcdFlashFvAdvancedBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvOptionalSize),
+ FixedPcdGet32 (PcdFlashFvOptionalBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvSecuritySize),
+ FixedPcdGet32 (PcdFlashFvSecurityBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvOsBootSize),
+ FixedPcdGet32 (PcdFlashFvOsBootBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvUefiBootSize),
+ FixedPcdGet32 (PcdFlashFvUefiBootBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvPostMemorySize),
+ FixedPcdGet32 (PcdFlashFvPostMemoryBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFirmwareBinariesSize),
+ FixedPcdGet32 (PcdFlashFvFirmwareBinariesBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspSSize),
+ FixedPcdGet32 (PcdFlashFvFspSBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspMSize),
+ FixedPcdGet32 (PcdFlashFvFspMBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspTSize),
+ FixedPcdGet32 (PcdFlashFvFspTBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvPreMemorySize),
+ FixedPcdGet32 (PcdFlashFvPreMemoryBase)
+ },
+ {
+ FIT_TYPE_01_MICROCODE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_MICROCODE_WHOLE_REGION,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashMicrocodeFvSize),
+ FixedPcdGet32 (PcdFlashMicrocodeFvBase)
+ },
+ }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mBiosInfoPpiList = {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gBiosInfoGuid,
+ &mBiosInfo
+};
+
+/**
+ Installs BiosInfo Ppi.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS Install the BiosInfo Ppi successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+BiosInfoEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ VOID *HobData;
+
+ //
+ // Install PPI, so that other PEI module can add dependency.
+ //
+ Status = PeiServicesInstallPpi (&mBiosInfoPpiList);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Build hob, so that DXE module can also get the data.
+ //
+ HobData = BuildGuidHob (&gBiosInfoGuid, sizeof (mBiosInfo));
+ ASSERT (HobData != NULL);
+ if (HobData == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ CopyMem (HobData, &mBiosInfo, sizeof (mBiosInfo));
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
new file mode 100644
index 0000000000..b11451807a
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
@@ -0,0 +1,84 @@
+### @file
+# Module Information description file for BIOS Info PEIM.
+# The module provides BiosInfo structure listing up all firmware volume's base addresses,
+# sizes, attributes, those information associated to each firmware volume.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BiosInfo
+ FILE_GUID = 4A4CA1C6-871C-45BB-8801-6910A7AA5807
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = BiosInfoEntryPoint
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES IA32 X64
+#
+
+[LibraryClasses]
+ PeimEntryPoint
+ PeiServicesLib
+ PeiServicesTablePointerLib
+ HobLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+
+[Pcd]
+ gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize ## CONSUMES
+
+[Sources]
+ BiosInfo.c
+
+[Guids]
+ gBiosInfoGuid ## PRODUCES
+
+[Depex]
+ gEfiPeiMasterBootModePpiGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c
new file mode 100644
index 0000000000..4fab4ad8e6
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c
@@ -0,0 +1,233 @@
+/** @file
+ Source code file for OpenBoard Platform Init PEI module
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Register/Msr.h>
+#include <CpuRegs.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/EndOfPeiPhase.h>
+#include <Library/MtrrLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Guid/SmramMemoryReserve.h>
+#include <Library/ConfigBlockLib.h>
+#include <Ppi/SiPolicy.h>
+#include <PchPolicyCommon.h>
+#include <Library/SiPolicyLib.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <Protocol/FirmwareVolumeBlock.h>
+#include <Library/PostCodeLib.h>
+#include <PlatformPostCode.h>
+#include <Ppi/Spi.h>
+#include <Library/MtrrLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Register/PchRegs.h>
+#include <PlatformBoardId.h>
+#include <Core/Pei/PeiMain.h>
+#include <Library/PchPciBdfLib.h>
+#include <Ppi/GraphicsPlatformPolicyPpi.h>
+#include <Library/PeiGetFvInfoLib.h>
+
+
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitEndOfPei (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiEndOfPeiSignalPpiGuid,
+ (EFI_PEIM_NOTIFY_ENTRY_POINT) OpenBoardPlatformInitEndOfPei
+};
+
+EFI_STATUS
+EFIAPI
+GetPeiPlatformLidStatus (
+ OUT LID_STATUS *CurrentLidStatus
+ );
+
+EFI_STATUS
+EFIAPI
+GetVbtData (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ );
+
+PEI_GRAPHICS_PLATFORM_POLICY_PPI PeiGraphicsPlatform = {
+ PEI_GRAPHICS_PLATFORM_POLICY_REVISION,
+ GetPeiPlatformLidStatus,
+ GetVbtData
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPeiGraphicsPlatformPpi = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gPeiGraphicsPlatformPpiGuid,
+ &PeiGraphicsPlatform
+};
+
+EFI_STATUS
+EFIAPI
+GetVbtData (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ )
+{
+ EFI_GUID FileGuid;
+ EFI_GUID BmpImageGuid;
+ VOID *Buffer;
+ UINT32 Size;
+
+ Size = 0;
+ Buffer = NULL;
+
+
+ DEBUG((DEBUG_INFO, "GetVbtData Entry\n"));
+
+ CopyMem (&BmpImageGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid), sizeof(BmpImageGuid));
+
+ CopyMem(&FileGuid, &BmpImageGuid, sizeof(FileGuid));
+ PeiGetSectionFromFv(FileGuid, &Buffer, &Size);
+ if (Buffer == NULL) {
+ DEBUG((DEBUG_ERROR, "Could not locate VBT\n"));
+ } else {
+ DEBUG ((DEBUG_INFO, "GetVbtData Buffer is 0x%x\n", Buffer));
+ DEBUG ((DEBUG_INFO, "GetVbtData Size is 0x%x\n", Size));
+ *VbtAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer;
+ *VbtSize = Size;
+ }
+ DEBUG((DEBUG_INFO, "GetVbtData exit\n"));
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function will return Lid Status in PEI phase.
+
+ @param[out] CurrentLidStatus
+
+ @retval EFI_SUCCESS
+ @retval EFI_UNSUPPORTED
+**/
+
+EFI_STATUS
+EFIAPI
+GetPeiPlatformLidStatus (
+ OUT LID_STATUS *CurrentLidStatus
+ )
+{
+ DEBUG ((DEBUG_INFO, "LidStatus Unsupported\n"));
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Configure PciHostBridge related PCDs
+**/
+VOID
+ConfigurePciHostBridgePcds (
+ VOID
+ )
+{
+ //
+ // Provide 256GB available above 4GB MMIO resource
+ // limited to use single variable MTRR to cover this above 4GB MMIO region.
+ //
+ PcdSet64S (PcdPciReservedMemAbove4GBBase, BASE_256GB);
+ PcdSet64S (PcdPciReservedMemAbove4GBLimit, BASE_256GB + SIZE_256GB - 1);
+ if (PcdGet64 (PcdPciReservedMemAbove4GBBase) < PcdGet64 (PcdPciReservedMemAbove4GBLimit)) {
+ DEBUG ((DEBUG_INFO, " PCI space that above 4GB MMIO is from 0x%lX", PcdGet64 (PcdPciReservedMemAbove4GBBase)));
+ DEBUG ((DEBUG_INFO, " to 0x%lX\n", PcdGet64 (PcdPciReservedMemAbove4GBLimit)));
+ }
+}
+
+/**
+ This function handles PlatformInit task at the end of PEI
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this function.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval others
+**/
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitEndOfPei (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ //
+ // Configure PciHostBridge related PCDs before DXE phase
+ //
+ ConfigurePciHostBridgePcds ();
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Platform Init PEI module entry point
+
+ @param[in] FileHandle Not used.
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
+**/
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitPostMemEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ PEI_CORE_INSTANCE *PrivateData;
+ UINTN CurrentFv;
+ PEI_CORE_FV_HANDLE *CoreFvHandle;
+ VOID *HobData;
+
+ PostCode (PLATFORM_INIT_POSTMEM_ENTRY);
+
+ //
+ // Build a HOB to show current FV location for SA policy update code to consume.
+ //
+ PrivateData = PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices);
+ CurrentFv = PrivateData->CurrentPeimFvCount;
+ CoreFvHandle = &(PrivateData->Fv[CurrentFv]);
+
+ HobData = BuildGuidHob (
+ &gPlatformInitFvLocationGuid,
+ sizeof (VOID *)
+ );
+ ASSERT (HobData != NULL);
+ CopyMem (HobData, (VOID *) &CoreFvHandle, sizeof (VOID *));
+
+ //
+ // Install mPeiGraphicsPlatformPpi
+ //
+ DEBUG ((DEBUG_INFO, "Install mPeiGraphicsPlatformPpi \n"));
+ Status = PeiServicesInstallPpi (&mPeiGraphicsPlatformPpi);
+
+ //
+ // Performing PlatformInitEndOfPei after EndOfPei PPI produced
+ //
+ Status = PeiServicesNotifyPpi (&mEndOfPeiNotifyList);
+ PostCode (PLATFORM_INIT_POSTMEM_EXIT);
+
+ return Status;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
new file mode 100644
index 0000000000..b2bfd97f8a
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
@@ -0,0 +1,75 @@
+### @file
+# Component information file for the OpenBoard Platform Init PEI module.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = OpenBoardPlatformInitPostMem
+ FILE_GUID = 314EE04C-1106-4DC6-ACBC-CF19C0DBC5CC
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = OpenBoardPlatformInitPostMemEntryPoint
+
+[LibraryClasses]
+ PeimEntryPoint
+ DebugLib
+ IoLib
+ MemoryAllocationLib
+ BaseMemoryLib
+ HobLib
+ PeiServicesLib
+ PciSegmentLib
+ MtrrLib
+ PchInfoLib
+ PostCodeLib
+ SiPolicyLib
+ FspCommonLib
+ PcdLib
+ PchPciBdfLib
+ GpioLib
+ PeiGetFvInfoLib
+
+[Packages]
+ AlderlakeSiliconPkg/SiPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ AlderLakeFspBinPkg/Client/AlderLakeP/AlderLakeFspBinPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+ OpenBoardPlatformInitPostMem.c
+
+[Ppis]
+ gEfiEndOfPeiSignalPpiGuid ## CONSUMES
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+ gPeiGraphicsPlatformPpiGuid ## PRODUCES
+ gFspSiliconInitDonePpiGuid ## CONSUMES
+
+[Protocols]
+
+[Guids]
+ gEfiSmmSmramMemoryGuid ## CONSUMES
+ gPlatformInitFvLocationGuid ## PRODUCES
+
+[Depex]
+ gEfiPeiMemoryDiscoveredPpiGuid
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIobase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIoLimit ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciSegmentCount ## CONSUMES
+
+ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUMES
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc
new file mode 100644
index 0000000000..9215a026ae
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc
@@ -0,0 +1,19 @@
+## @file
+# Include All Board Gpio configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+!include $(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
+!include $(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
+
+
+# PCIe clock mapping
+!include $(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
+
+# MRC DQS DQ and SPD mapping
+!include $(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
+
+
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
new file mode 100644
index 0000000000..3eb8c276b5
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
@@ -0,0 +1,40 @@
+## @file
+# GPIO definition table for Alderlake P
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+###
+### !!! GPIOs designated to Native Functions shall not be configured by Platform Code.
+### Native Pins shall be configured by Silicon Code (based on BIOS policies setting) or soft straps(set by CSME in FITc).
+###
+###
+
+
+#mGpioTableAdlPDdr5Rvp
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable|*|{CODE({
+ // CPU M.2 SSD1
+ {GPIO_VER2_LP_GPP_F20, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD1 RESET
+
+ // CPU M.2 SSD2
+ {GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 PWREN
+ {GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, // CPU SSD2 RESET
+
+ // X4 Pcie Slot for Gen3 and Gen 4
+ {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}},//ONBOARD_X4_PCIE_SLOT1_RESET_N
+
+ // PCH M.2 SSD
+ {GPIO_VER2_LP_GPP_D16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_PCH_SSD_PWREN
+ {GPIO_VER2_LP_GPP_H0, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_SSD_RST_N
+
+ // EC
+ {GPIO_VER2_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSmi,GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //EC_SMI_N
+ {GPIO_VER2_LP_GPP_F9, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //EC_SLP_S0_CS_N
+
+ {0x0} // terminator
+})}
+
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
new file mode 100644
index 0000000000..7bf8571c27
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
@@ -0,0 +1,29 @@
+## @file
+# Alderlake P RVP GPIO definition table for Pre-Memory Initialization
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+###
+### !!! GPIOs designated to Native Functions shall not be configured by Platform Code.
+### Native Pins shall be configured by Silicon Code (based on BIOS policies setting) or soft straps(set by CSME in FITc).
+###
+###
+
+# mGpioTablePreMemAdlPDdr5Rvp
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
+ // CPU M.2 SSD
+ { GPIO_VER2_LP_GPP_F20, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } }, //CPU SSD RESET
+
+ // CPU M.2 SSD2
+ {GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 PWREN
+ {GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 RESET
+
+ // X4 Pcie Slot for Gen3 and Gen 4
+ {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}},//ONBOARD_X4_PCIE_SLOT1_RESET_N
+
+ {0x0} // terminator
+})}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
new file mode 100644
index 0000000000..096cc380cd
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
@@ -0,0 +1,138 @@
+## @file
+# ADL P SPD DATA configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData|*|{CODE(
+{
+// DDR5 1Rx16 - 4800 MHz
+ 1,
+ {0x30, ///< 0 1024 SPD bytes total
+ 0x08, ///< 1 SPD Revision 0.8
+ 0x12, ///< 2 DRAM Type: DDR5 SDRAM
+ 0x03, ///< 3 Module Type: Not Hybrid (DRAM only) / SO-DIMM Solution
+ 0x04, ///< 4 Monolithic SDRAM, 16 Gb SDRAM density
+ 0x00, ///< 5 16 Rows, 10 Columns
+ 0x40, ///< 6 x16 SDRAM I/O Width
+ 0x42, ///< 7 4 Bank Groups, 4 Banks per Bank Group
+ 0x00, ///< 8 Secondary SDRAM Density and Package
+ 0x00, ///< 9 Secondary SDRAM Addressing
+ 0x00, ///< 10 Secondary SDRAM I/O Width
+ 0x00, ///< 11 Secondary BankGroups and Banks per Bank Group
+ 0x60, ///< 12 PPR Supported, One row per bank group, Soft PPR Supported
+ 0x00, ///< 13 Commercial Temperature Grade, 0 to 85 C
+ 0x00, ///< 14 Reserved
+ 0x00, ///< 15 Reserved
+ 0x00, ///< 16 SDRAM Nominal Voltage VDD: 1.1V
+ 0x00, ///< 17 SDRAM Nominal Voltage VDDQ: 1.1V
+ 0x00, ///< 18 SDRAM Nominal Voltage VPP: 1.8V
+ 0x00, ///< 19 Reserved
+ 0xA1, ///< 20 tCKAVGmin LSB
+ 0x01, ///< 21 tCKAVGmin MSB
+ 0xE8, ///< 22 tCKAVGmax LSB
+ 0x03, ///< 23 tCKAVGmax MSB
+ 0x72, ///< 24 CAS Latencies supported (First Byte) : 32, 30, 28, 22
+ 0x15, ///< 25 CAS Latencies supported (Second Byte): 44, 40, 36
+ 0x00, ///< 26 CAS Latencies supported (Third Byte) :
+ 0x00, ///< 27 CAS Latencies supported (Fourth Byte):
+ 0x00, ///< 28 CAS Latencies supported (Fifth Byte) :
+ 0x00, ///< 29 Reserved
+ 0x1E, ///< 30 Minimum CAS Latency (tAAmin) LSB
+ 0x41, ///< 31 Minimum CAS Latency (tAAmin) MSB
+ 0x1E, ///< 32 Minimum RAS-to-CAS delay (tRCDmin) LSB
+ 0x41, ///< 33 Minimum RAS-to-CAS delay (tRCDmin) MSB
+ 0x1E, ///< 34 Minimum Row Precharge delay (tRPmin) LSB
+ 0x41, ///< 35 Minimum Row Precharge delay (tRPmin) MSB
+ 0x00, ///< 36 Minimum Active to Precharge delay (tRASmin) LSB
+ 0x7D, ///< 37 Minimum Active to Precharge delay (tRASmin) MSB
+ 0x1E, ///< 38 Minimum Active to Active/Refresh delay (tRCmin) LSB
+ 0xBE, ///< 39 Minimum Active to Active/Refresh delay (tRCmin) MSB
+ 0x30, ///< 40 Minimum Write Recovery time (tWRmin) LSB
+ 0x75, ///< 41 Minimum Write Recovery time (tWRmin) MSB
+ 0x27, ///< 42 Refresh Recovery Delay (tRFC1min) LSB
+ 0x01, ///< 43 Refresh Recovery Delay (tRFC1min) MSB
+ 0xA0, ///< 44 Refresh Recovery Delay (tRFC2min) MSB
+ 0x00, ///< 45 Refresh Recovery Delay (tRFC2min) MSB
+ 0x82, ///< 46 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0x00, ///< 47 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0, 0, ///< 48 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0, 0, 0, 0, 0, 0, ///< 120 - 125
+ 0x47, ///< 126 CRC Bytes 0 - 127 LSB
+ 0xAE, ///< 127 CRC Bytes 0 - 127 MSB
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, ///< 190 - 191
+ 0x08, ///< 192 SPD Revision for Module Information: 0.8
+ 0x00, ///< 193 Reserved
+ 0xC2, ///< 194 SPD Manufacturer ID First Byte
+ 0xC4, ///< 195 SPD Manufacturer ID Second Byte
+ 0x80, ///< 196 SPD Device Type
+ 0x00, ///< 197 SPD Device Revision
+ 0x80, ///< 198 PMIC0 Manufacturer ID First Byte
+ 0xB3, ///< 199 PMIC0 Manufacturer ID Second Byte
+ 0x80, ///< 200 PMIC0 Device Type
+ 0x11, ///< 201 PMIC0 Device Revision
+ 0, 0, 0, 0, ///< 202 - 205 PMIC1
+ 0, 0, 0, 0, ///< 206 - 209 PMIC2
+ 0x80, ///< 210 Thermal Sensors Manufacturer ID First Byte
+ 0xB3, ///< 211 Thermal Sensors Manufacturer ID First Byte
+ 0x80, ///< 212 Thermal Sensors Device Type
+ 0x11, ///< 213 Thermal Sensors Device Revision
+ 0, 0, 0, 0, 0, 0, ///< 214 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0x0F, ///< 230 Module Nominal Height
+ 0x10, ///< 231 Module Nominal Thickness
+ 0x00, ///< 232 Reference Raw Card Used
+ 0x01, ///< 233 1 Row of DRAM on Module
+ 0x01, ///< 234 1 Rank, 8 bits SDRAM data width per channel
+ 0x22, ///< 235 2 Channels per DIMM, 32 bits per Channel
+ 0, 0, 0, 0, ///< 236 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 320 - 329
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 330 - 339
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 340 - 349
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 350 - 359
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ///< 440 - 445
+ 0x9C, ///< 446 CRC for Bytes 128 - 253 LSB
+ 0xAD, ///< 447 CRC for Bytes 128 - 253 MSB
+ 0, 0, ///< 448 - 449
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
+ 0, 0 ///< 510 - 511
+ ///< Ignore bytes 512-1023, @todo_adl: support 1024 bytes SPD array
+}})}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
new file mode 100644
index 0000000000..57106e92c4
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
@@ -0,0 +1,31 @@
+## @file
+# Alderlake P Pcie Clock configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
+{{
+ PCIE_PEG, // CPU M.2 SSD 1
+ PCIE_PCH + 8, // PCH M.2 SSD
+ PCIE_PCH + 4,
+ PCIE_PEG + 1, // X8 DG/DG2
+ PCIE_PEG + 2, // CPU M.2 SSD 2
+ PCIE_PCH + 5, // M.2 KEY B WWAN - PCIe P6
+ LAN_CLOCK,
+ // Default Case:
+ // - PCIe P7 mapped to GBELAN
+ // - PCIe P8 mapped to x4 PCIe DT Slot (Pair 1)
+ PCIE_PCH + 7, // x4 PCIe DT Slot (x1)
+ // Reworked Case: with rework and soft strap changes
+ // - PCIe P7 mapped to x4 PCIe DT Slot (Pair 2)
+ // - PCIe P8 mapped to x4 PCIe DT Slot (Pair 1)
+ // PCIE_PCH + 6, // x4 PCIe DT Slot (x2)
+ NOT_USED,
+ NOT_USED
+}}
+)}
--
2.36.1.windows.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [edk2-devel] [PATCH v2 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add libraries
2023-08-01 22:17 [edk2-devel] [PATCH v2 1/6] AlderlakeOpenBoardPkg: Add package and headers Saloni Kasbekar
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 2/6] AlderlakeOpenBoardPkg: Add modules Saloni Kasbekar
@ 2023-08-01 22:17 ` Saloni Kasbekar
2023-08-02 18:10 ` Chaganty, Rangasai V
2023-08-04 0:48 ` Chuang, Rosen
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 4/6] AlderlakeOpenBoardPkg: Add ACPI module Saloni Kasbekar
` (4 subsequent siblings)
6 siblings, 2 replies; 18+ messages in thread
From: Saloni Kasbekar @ 2023-08-01 22:17 UTC (permalink / raw)
To: devel
Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Isaac Oram,
Rosen Chuang
Adds the following library instances:
- BoardAcpiLib
- BoardInitLib
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../SmmAlderlakePRvpAcpiEnableLib.c | 50 +++++
.../SmmMultiBoardAcpiSupportLib.c | 88 ++++++++
.../SmmMultiBoardAcpiSupportLib.inf | 41 ++++
.../BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 134 ++++++++++++
.../BoardInitLib/Pei/BoardPchInitPreMemLib.c | 104 +++++++++
.../BoardInitLib/Pei/BoardSaConfigPreMem.h | 73 +++++++
.../BoardInitLib/Pei/BoardSaInitPreMemLib.c | 160 ++++++++++++++
.../Library/BoardInitLib/Pei/PeiDetect.c | 62 ++++++
.../BoardInitLib/Pei/PeiInitPostMemLib.c | 100 +++++++++
.../BoardInitLib/Pei/PeiInitPreMemLib.c | 202 ++++++++++++++++++
.../Pei/PeiMultiBoardInitPostMemLib.c | 45 ++++
.../Pei/PeiMultiBoardInitPostMemLib.inf | 53 +++++
.../Pei/PeiMultiBoardInitPreMemLib.c | 89 ++++++++
.../Pei/PeiMultiBoardInitPreMemLib.inf | 149 +++++++++++++
14 files changed, 1350 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmAlderlakePRvpAcpiEnableLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardPchInitPreMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaConfigPreMem.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaInitPreMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiDetect.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPostMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPreMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmAlderlakePRvpAcpiEnableLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmAlderlakePRvpAcpiEnableLib.c
new file mode 100644
index 0000000000..8dfc04c5f5
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmAlderlakePRvpAcpiEnableLib.c
@@ -0,0 +1,50 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardId.h>
+
+/**
+ Enable Board Acpi
+
+ @param[in] EnableSci Enable SCI if EnableSci parameters is True.
+
+ @retval EFI_SUCCESS The function always return successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ // enable additional board register
+ return EFI_SUCCESS;
+}
+
+/**
+ Disable Board Acpi
+
+ @param[in] DisableSci Disable SCI if DisableSci parameters is True.
+
+ @retval EFI_SUCCESS The function always return successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ // enable additional board register
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
new file mode 100644
index 0000000000..ea0f7c966b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
@@ -0,0 +1,88 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/MultiBoardAcpiSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+AdlBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+AdlBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+MultiBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ SiliconEnableAcpi (EnableSci);
+ return AdlBoardEnableAcpi (EnableSci);
+}
+
+EFI_STATUS
+EFIAPI
+MultiBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ SiliconDisableAcpi (DisableSci);
+ return AdlBoardDisableAcpi (DisableSci);
+}
+
+BOARD_ACPI_ENABLE_FUNC mBoardAcpiEnableFunc = {
+ MultiBoardEnableAcpi,
+ MultiBoardDisableAcpi,
+};
+
+/**
+ The constructor function to register mBoardAcpiEnableFunc function.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS This constructor always return EFI_SUCCESS.
+ It will ASSERT on errors.
+**/
+EFI_STATUS
+EFIAPI
+SmmMultiBoardAcpiSupportLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ return RegisterBoardAcpiEnableFunc (&mBoardAcpiEnableFunc);
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
new file mode 100644
index 0000000000..8a418bc8da
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
@@ -0,0 +1,41 @@
+## @file
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SmmMultiBoardAcpiSupportLib
+ FILE_GUID = 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_SMM_DRIVER
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = SmmMultiBoardAcpiSupportLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciLib
+ PchCycleDecodingLib
+ PchPciBdfLib
+ PmcLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ SmmAlderlakePRvpAcpiEnableLib.c
+ SmmSiliconAcpiEnableLib.c
+ SmmMultiBoardAcpiSupportLib.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
new file mode 100644
index 0000000000..fbe745ad36
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
@@ -0,0 +1,134 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PmcLib.h>
+#include <Library/PchPciBdfLib.h>
+#include <Register/PchRegs.h>
+#include <Register/PchRegsLpc.h>
+#include <Register/PmcRegs.h>
+#include <Register/RtcRegs.h>
+
+/**
+ Clear Port 80h
+
+ Disables the SW SMI Timer.
+ ACPI events are disabled and ACPI event status is cleared.
+
+ Disable port 60/64 SMI trap if they are enabled
+
+ Disable PM sources except power button
+ Clear status bits
+
+ Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+
+ Enable SCI
+**/
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+
+ UINT32 SmiEn;
+ UINT32 SmiSts;
+ UINT32 ULKMC;
+ UINTN LpcBaseAddress;
+ UINT16 AcpiBaseAddr;
+ UINT32 Pm1Cnt;
+
+ LpcBaseAddress = LpcPciCfgBase ();
+
+ //
+ // Get the ACPI Base Address
+ //
+ AcpiBaseAddr = PmcGetAcpiBase();
+
+ //
+ // Clear Port 80h
+ //
+ IoWrite8 (0x80, 0);
+
+ //
+ // Disable SW SMI Timer and clean the status
+ //
+ SmiEn = IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN);
+ SmiEn &= ~(B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB);
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN, SmiEn);
+
+ SmiSts = IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS);
+ SmiSts |= B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS, SmiSts);
+
+ //
+ // Disable port 60/64 SMI trap if they are enabled
+ //
+ ULKMC = MmioRead32 (LpcBaseAddress + R_LPC_CFG_ULKMC) & ~(B_LPC_CFG_ULKMC_60REN | B_LPC_CFG_ULKMC_60WEN | B_LPC_CFG_ULKMC_64REN | B_LPC_CFG_ULKMC_64WEN | B_LPC_CFG_ULKMC_A20PASSEN);
+ MmioWrite32 (LpcBaseAddress + R_LPC_CFG_ULKMC, ULKMC);
+
+ //
+ // Disable PM sources except power button
+ //
+ IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_EN, B_ACPI_IO_PM1_EN_PWRBTN);
+
+ //
+ // Clear PM status except Power Button status for RapidStart Resume
+ //
+ IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_STS, 0xFEFF);
+
+ //
+ // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+ //
+ IoWrite8 (R_RTC_IO_INDEX_ALT, R_RTC_IO_REGD);
+ IoWrite8 (R_RTC_IO_TARGET_ALT, 0x0);
+
+ //
+ // Enable SCI
+ //
+ if (EnableSci) {
+ Pm1Cnt = IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);
+ Pm1Cnt |= B_ACPI_IO_PM1_CNT_SCI_EN;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt);
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+
+ UINT16 AcpiBaseAddr;
+ UINT32 Pm1Cnt;
+
+ //
+ // Get the ACPI Base Address
+ //
+ AcpiBaseAddr = PmcGetAcpiBase();
+ //
+ // Disable SCI
+ //
+ if (DisableSci) {
+ Pm1Cnt = IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);
+ Pm1Cnt &= ~B_ACPI_IO_PM1_CNT_SCI_EN;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt);
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardPchInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardPchInitPreMemLib.c
new file mode 100644
index 0000000000..13ad444f8b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardPchInitPreMemLib.c
@@ -0,0 +1,104 @@
+/** @file
+ Source code for the board PCH configuration Pcd init functions for Pre-Memory Init phase.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BoardConfigLib.h>
+#include <Include/PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Library/PcdLib.h>
+#include <PlatformBoardId.h>
+#include <Library/PchInfoLib.h>
+/**
+ Board Root Port Clock Info configuration init function for PEI pre-memory phase.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+AdlPRootPortClkInfoInit (
+ VOID
+ )
+{
+ PCD64_BLOB Clock[PCH_MAX_PCIE_CLOCKS];
+ UINT32 Index;
+ PCIE_CLOCKS_USAGE *PcieClocks;
+
+ PcieClocks = NULL;
+
+ //
+ //The default clock assignment will be NOT_USED, which corresponds to PchClockUsageNotUsed. This will prevent clocks drawing Power by default.
+ //If Platform code doesn't contain port-clock map for a given board, the clocks will be NOT_USED, preventing PCIe devices not to operate.
+ //To prevent this, remember to provide port-clock map for every board.
+ //
+ for (Index = 0; Index < PCH_MAX_PCIE_CLOCKS; Index++) {
+ Clock[Index].PcieClock.ClkReqSupported = TRUE;
+ Clock[Index].PcieClock.ClockUsage = NOT_USED;
+ }
+
+ ///
+ /// Assign ClkReq signal to root port. (Base 0)
+ /// For LP, Set 0 - 5
+ /// For H, Set 0 - 15
+ /// Note that if GbE is enabled, ClkReq assigned to GbE will not be available for Root Port.
+ ///
+
+ PcieClocks = PcdGetPtr(VpdPcdPcieClkUsageMap);
+ if (PcieClocks == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Clock[0].PcieClock.ClockUsage = PcieClocks->ClockUsage[0];
+ Clock[1].PcieClock.ClockUsage = PcieClocks->ClockUsage[1];
+ Clock[2].PcieClock.ClockUsage = PcieClocks->ClockUsage[2];
+ Clock[3].PcieClock.ClockUsage = PcieClocks->ClockUsage[3];
+ Clock[4].PcieClock.ClockUsage = PcieClocks->ClockUsage[4];
+ Clock[5].PcieClock.ClockUsage = PcieClocks->ClockUsage[5];
+ Clock[6].PcieClock.ClockUsage = PcieClocks->ClockUsage[6];
+ Clock[7].PcieClock.ClockUsage = PcieClocks->ClockUsage[7];
+ Clock[8].PcieClock.ClockUsage = PcieClocks->ClockUsage[8];
+ Clock[9].PcieClock.ClockUsage = PcieClocks->ClockUsage[9];
+
+ PcdSet64S (PcdPcieClock0, Clock[ 0].Blob);
+ PcdSet64S (PcdPcieClock1, Clock[ 1].Blob);
+ PcdSet64S (PcdPcieClock2, Clock[ 2].Blob);
+ PcdSet64S (PcdPcieClock3, Clock[ 3].Blob);
+ PcdSet64S (PcdPcieClock4, Clock[ 4].Blob);
+ PcdSet64S (PcdPcieClock5, Clock[ 5].Blob);
+ PcdSet64S (PcdPcieClock6, Clock[ 6].Blob);
+ PcdSet64S (PcdPcieClock7, Clock[ 7].Blob);
+ PcdSet64S (PcdPcieClock8, Clock[ 8].Blob);
+ PcdSet64S (PcdPcieClock9, Clock[ 9].Blob);
+ PcdSet64S (PcdPcieClock10, Clock[10].Blob);
+ PcdSet64S (PcdPcieClock11, Clock[11].Blob);
+ PcdSet64S (PcdPcieClock12, Clock[12].Blob);
+ PcdSet64S (PcdPcieClock13, Clock[13].Blob);
+ PcdSet64S (PcdPcieClock14, Clock[14].Blob);
+ PcdSet64S (PcdPcieClock15, Clock[15].Blob);
+ return EFI_SUCCESS;
+}
+
+/**
+ Board GPIO Group Tier configuration init function for PEI pre-memory phase.
+**/
+VOID
+AdlPGpioGroupTierInit (
+ VOID
+ )
+{
+ //
+ // GPIO Group Tier
+ //
+ PcdSet32S (PcdGpioGroupToGpeDw0, 0);
+ PcdSet32S (PcdGpioGroupToGpeDw1, 0);
+ PcdSet32S (PcdGpioGroupToGpeDw2, 0);
+
+ return;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaConfigPreMem.h b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaConfigPreMem.h
new file mode 100644
index 0000000000..c79555cde8
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaConfigPreMem.h
@@ -0,0 +1,73 @@
+/** @file
+ PEI Boards Configurations for PreMem phase.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _BOARD_SA_CONFIG_PRE_MEM_H_
+#define _BOARD_SA_CONFIG_PRE_MEM_H_
+
+#include <Ppi/SiPolicy.h>
+#include <Library/BoardConfigLib.h>
+
+#define SA_MRC_MAX_RCOMP_TARGETS (5)
+
+//
+// Reference RCOMP resistors on motherboard - MRC will set automatically
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 AdlPRcompResistorZero = 0;
+
+//
+// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - MRC will set automatically
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetAdlP[SA_MRC_MAX_RCOMP_TARGETS] = { 0, 0, 0, 0, 0 };
+
+//
+// DQ byte mapping to CMD/CTL/CLK, from the CPU side
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 DqByteMapAdlP[2][6][2] = {
+ // Channel 0:
+ {
+ { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+ { 0x0F, 0xF0 }, // Cmd CAA goes to Bytes[3:0], Cmd CAB goes to Byte[7:4]
+ { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ },
+ // Channel 1:
+ {
+ { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+ { 0x0F, 0xF0 }, // Cmd CAA goes to Bytes[3:0], Cmd CAB goes to Byte[7:4]
+ { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ }
+};
+
+//
+// Display DDI settings for Adl-P Ddr5 Rvp Edp + DP
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mAdlPDdr5RvpDisplayDdiConfig[16] = {
+ DdiPortEdp, // DDI Port A Config : DdiPortDisabled = No LFP is Connected, DdiPortEdp = eDP, DdiPortMipiDsi = MIPI DSI
+ DdiPortDisabled, // DDI Port B Config : DdiPortDisabled = No LFP is Connected, DdiPortEdp = eDP, DdiPortMipiDsi = MIPI DSI
+ DdiHpdDisable, // DDI Port A HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdEnable, // DDI Port B HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port C HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port 1 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port 2 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port 3 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port 4 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiDisable, // DDI Port A DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port B DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port C DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port 1 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port 2 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port 3 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable // DDI Port 4 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+};
+
+#endif // _BOARD_SA_CONFIG_PRE_MEM_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaInitPreMemLib.c
new file mode 100644
index 0000000000..e42c8fb5f8
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaInitPreMemLib.c
@@ -0,0 +1,160 @@
+/** @file
+ Source code for the board SA configuration Pcd init functions in Pre-Memory init phase.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BoardSaConfigPreMem.h"
+#include <Library/CpuPlatformLib.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+/**
+ MRC configuration init function for PEI pre-memory phase.
+
+ @param[in] VOID
+
+ @retval VOID
+**/
+VOID
+AdlPSaMiscConfigInit (
+ VOID
+ )
+{
+ PcdSet8S (PcdSaMiscUserBd, 6);
+ return;
+}
+
+/**
+ Board Memory Init related configuration init function for PEI pre-memory phase.
+
+ @param[in] VOID
+
+ @retval VOID
+**/
+VOID
+AdlPMrcConfigInit (
+ VOID
+ )
+{
+ UINT16 BoardId;
+ BOOLEAN ExternalSpdPresent;
+ MRC_DQS *MrcDqs;
+ MRC_DQ *MrcDq;
+ SPD_DATA *SpdData;
+
+ BoardId = PcdGet16(PcdBoardId);
+
+ // SPD is the same size for all boards
+ PcdSet16S (PcdMrcSpdDataSize, 512);
+
+ ExternalSpdPresent = PcdGetBool (PcdSpdPresent);
+
+ // Assume internal SPD is used
+ PcdSet8S (PcdMrcSpdAddressTable0, 0);
+ PcdSet8S (PcdMrcSpdAddressTable1, 0);
+ PcdSet8S (PcdMrcSpdAddressTable2, 0);
+ PcdSet8S (PcdMrcSpdAddressTable3, 0);
+ PcdSet8S (PcdMrcSpdAddressTable4, 0);
+ PcdSet8S (PcdMrcSpdAddressTable5, 0);
+ PcdSet8S (PcdMrcSpdAddressTable6, 0);
+ PcdSet8S (PcdMrcSpdAddressTable7, 0);
+ PcdSet8S (PcdMrcSpdAddressTable8, 0);
+ PcdSet8S (PcdMrcSpdAddressTable9, 0);
+ PcdSet8S (PcdMrcSpdAddressTable10, 0);
+ PcdSet8S (PcdMrcSpdAddressTable11, 0);
+ PcdSet8S (PcdMrcSpdAddressTable12, 0);
+ PcdSet8S (PcdMrcSpdAddressTable13, 0);
+ PcdSet8S (PcdMrcSpdAddressTable14, 0);
+ PcdSet8S (PcdMrcSpdAddressTable15, 0);
+
+ // Check for external SPD presence
+ if (ExternalSpdPresent) {
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ PcdSet8S (PcdMrcSpdAddressTable0, 0xA0);
+ PcdSet8S (PcdMrcSpdAddressTable1, 0xA2);
+ PcdSet8S (PcdMrcSpdAddressTable8, 0xA4);
+ PcdSet8S (PcdMrcSpdAddressTable9, 0xA6);
+ break;
+ default:
+ break;
+ }
+ }
+
+ // Setting the default DQ Byte Map. It may be overriden to board specific settings below.
+ PcdSet32S (PcdMrcDqByteMap, (UINTN) DqByteMapAdlP);
+ PcdSet16S (PcdMrcDqByteMapSize, sizeof (DqByteMapAdlP));
+
+ // ADL uses the same RCOMP resistors for all DDR types
+ PcdSet32S (PcdMrcRcompResistor, (UINTN) AdlPRcompResistorZero);
+
+ // Use default RCOMP target values for all boards
+ PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetAdlP);
+
+ // Default is NIL
+ PcdSetBoolS (PcdMrcDqPinsInterleavedControl, TRUE);
+ PcdSetBoolS (PcdMrcDqPinsInterleaved, FALSE);
+
+ // DqsMapCpu2Dram is the same size for all boards
+ PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (MRC_DQS));
+ // DqMapCpu2Dram is the same size for all boards
+ PcdSet16S (PcdMrcDqMapCpu2DramSize, sizeof (MRC_DQ));
+ PcdSet8S (PcdMrcLp5CccConfig, 0x0);
+
+ // CPU-DRAM DQ mapping
+ MrcDq = PcdGetPtr (VpdPcdMrcDqMapCpu2Dram);
+ if (MrcDq != NULL) {
+ PcdSet32S (PcdMrcDqMapCpu2Dram, (UINTN)MrcDq->DqMapCpu2Dram);
+ }
+
+ // CPU-DRAM DQS mapping
+ MrcDqs = PcdGetPtr (VpdPcdMrcDqsMapCpu2Dram);
+ if (MrcDqs != NULL) {
+ PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN)MrcDqs->DqsMapCpu2Dram);
+ }
+
+ // DRAM SPD Data
+ SpdData = PcdGetPtr (VpdPcdMrcSpdData);
+ if (SpdData != NULL) {
+ if (SpdData->OverrideSpd == TRUE) {
+ PcdSet32S (PcdMrcSpdData, (UINTN)SpdData->SpdData);
+ }
+ }
+
+ return;
+}
+
+/**
+ SA Display DDI configuration init function for PEI pre-memory phase.
+
+ @param[in] VOID
+
+ @retval VOID
+**/
+VOID
+AdlPSaDisplayConfigInit (
+ VOID
+ )
+{
+ UINT16 BoardId;
+
+ BoardId = PcdGet16 (PcdBoardId);
+
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ DEBUG ((DEBUG_INFO, "DDI Configuration ADLP Edp DP\n"));
+ PcdSet32S (PcdSaDisplayConfigTable, (UINTN) mAdlPDdr5RvpDisplayDdiConfig);
+ PcdSet16S (PcdSaDisplayConfigTableSize, sizeof (mAdlPDdr5RvpDisplayDdiConfig));
+ break;
+ default:
+ break;
+ }
+
+ return;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiDetect.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiDetect.c
new file mode 100644
index 0000000000..5ad8e56f4d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiDetect.c
@@ -0,0 +1,62 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <Library/BoardConfigLib.h>
+
+BOOLEAN
+IsAdlP (
+ VOID
+ )
+{
+ UINT16 BoardId;
+ BoardId = PcdGet16 (PcdBoardId);
+ if (BoardId == 0) {
+ DEBUG ((DEBUG_INFO, "Let's get Board information first ...\n"));
+ GetBoardConfig ();
+ BoardId = PcdGet16 (PcdBoardId);
+ }
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ DEBUG ((DEBUG_INFO, "AlderLake P Board detected\n"));
+
+ // set sku type to ADL P
+ PcdSet8S (PcdSkuType, AdlPSkuType);
+ return TRUE;
+ break;
+ default:
+ return FALSE;
+ }
+}
+
+EFI_STATUS
+EFIAPI
+AdlPBoardDetect (
+ VOID
+ )
+{
+ UINTN SkuId;
+ SkuId = 0;
+
+ if (LibPcdGetSku () != 0) {
+ return EFI_SUCCESS;
+ }
+
+ DEBUG ((DEBUG_INFO, "AlderLakeP Board Detection Callback\n"));
+
+ if (IsAdlP ()) {
+ SkuId = (UINTN) (PcdGet16 (PcdBoardBomId) << 16) | (PcdGet16 (PcdBoardRev) << 8) | (PcdGet16 (PcdBoardId));
+ LibPcdSetSku (SkuId);
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ }
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPostMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPostMemLib.c
new file mode 100644
index 0000000000..51201bb300
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPostMemLib.c
@@ -0,0 +1,100 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <Library/BoardConfigLib.h>
+#include <Library/GpioLib.h>
+#include <Library/IoLib.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PchInfoLib.h>
+#include <Library/HobLib.h>
+
+
+
+/**
+ Alderlake P boards configuration init function for PEI post memory phase.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlPInit (
+ VOID
+ )
+{
+ UINT16 GpioCount;
+ UINTN Size;
+ EFI_STATUS Status;
+ GPIO_INIT_CONFIG *GpioTable;
+ //
+ // GPIO Table Init
+ //
+ Status = EFI_SUCCESS;
+ GpioCount = 0;
+ Size = 0;
+ GpioTable = NULL;
+ //
+ // GPIO Table Init
+ //
+ //
+ // GPIO Table Init, Update PostMem GPIO table to PcdBoardGpioTable
+ //
+ GpioTable = (GPIO_INIT_CONFIG *)PcdGetPtr(VpdPcdBoardGpioTable);
+
+ GetGpioTableSize (GpioTable, &GpioCount);
+ //
+ // Increase GpioCount for the zero terminator.
+ //
+ GpioCount ++;
+ Size = (UINTN) (GpioCount * sizeof (GPIO_INIT_CONFIG));
+ Status = PcdSetPtrS (PcdBoardGpioTable, &Size, GpioTable);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/**
+ Configures GPIO
+
+ @param[in] GpioTable Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+
+**/
+VOID
+ConfigureGpio (
+ IN GPIO_INIT_CONFIG *GpioDefinition,
+ IN UINT16 GpioTableCount
+ )
+{
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
+
+ GpioConfigurePads (GpioTableCount, GpioDefinition);
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
+}
+
+/**
+ Configure GPIO, TouchPanel, HDA, PMC, TBT etc.
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeSiliconInit (
+ VOID
+ )
+{
+ AdlPInit ();
+ GpioInit (PcdGetPtr (PcdBoardGpioTable));
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPreMemLib.c
new file mode 100644
index 0000000000..0b7db476a1
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPreMemLib.c
@@ -0,0 +1,202 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/BiosIdLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PciLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiLib.h>
+#include <Guid/MemoryOverwriteControl.h>
+#include <PlatformBoardConfig.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Register/PmcRegs.h>
+#include <Library/PmcLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/GpioLib.h>
+#include <Library/BoardConfigLib.h>
+#include <Library/TimerLib.h>
+#include <PlatformBoardId.h>
+#include <Library/IoLib.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <Library/PchInfoLib.h>
+
+/**
+ Get Vpd binary address
+
+ Parse through each FV for VPD FFS file and return the address
+
+ @retval Address on VPD FFS detection else returns 0
+
+**/
+UINTN
+EFIAPI
+GetVpdFfsAddress (
+ )
+{
+ EFI_STATUS Status;
+ VOID *Address;
+ UINTN Instance;
+ EFI_PEI_FV_HANDLE VolumeHandle;
+ EFI_PEI_FILE_HANDLE FileHandle;
+
+ Address = NULL;
+
+ VolumeHandle = NULL;
+ Instance = 0;
+ while (TRUE) {
+ //
+ // Traverse all firmware volume instances.
+ //
+ Status = PeiServicesFfsFindNextVolume (Instance, &VolumeHandle);
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+
+ FileHandle = NULL;
+ Status = PeiServicesFfsFindFileByName (&gVpdFfsGuid, VolumeHandle, &FileHandle);
+ if (!EFI_ERROR (Status)) {
+ //
+ // Search RAW section.
+ //
+ Status = PeiServicesFfsFindSectionData (EFI_SECTION_RAW, FileHandle, &Address);
+ if (!EFI_ERROR (Status)) {
+ return (UINTN)Address;
+ }
+ }
+
+ //
+ // Search the next volume.
+ //
+ Instance++;
+ }
+
+ DEBUG ((DEBUG_ERROR, " PEI get VPD address: %r\n", EFI_NOT_FOUND));
+ return 0;
+}
+
+/**
+ Alderlake P boards configuration init function for PEI pre-memory phase.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlPInitPreMem (
+ VOID
+ )
+{
+ UINTN VpdBaseAddress;
+
+ VpdBaseAddress = (UINTN) PcdGet64 (PcdVpdBaseAddress64);
+ DEBUG ((DEBUG_INFO, "VpdFfsAddress: %x\n", VpdBaseAddress));
+ if (VpdBaseAddress == 0) {
+ VpdBaseAddress= (UINTN) GetVpdFfsAddress();
+ PcdSet64S (PcdVpdBaseAddress64,VpdBaseAddress);
+ DEBUG ((DEBUG_INFO, "VpdFfsAddress updated: %x\n", VpdBaseAddress));
+ }
+ PcdSet32S (PcdStackBase, PcdGet32 (PcdTemporaryRamBase) + PcdGet32 (PcdTemporaryRamSize) - (PcdGet32 (PcdFspTemporaryRamSize) + PcdGet32 (PcdFspReservedBufferSize)));
+ PcdSet32S (PcdStackSize, PcdGet32 (PcdFspTemporaryRamSize));
+
+ return EFI_SUCCESS;
+}
+
+
+VOID
+AdlPMrcConfigInit (
+ VOID
+ );
+
+VOID
+AdlPSaMiscConfigInit (
+ VOID
+ );
+
+VOID
+AdlPSaDisplayConfigInit (
+ VOID
+ );
+
+EFI_STATUS
+AdlPRootPortClkInfoInit (
+ VOID
+ );
+
+VOID
+AdlPGpioGroupTierInit (
+ VOID
+ );
+
+
+/**
+ A hook for board-specific initialization prior to memory initialization.
+
+ @retval EFI_SUCCESS The board initialization was successful.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeMemoryInit (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "AdlPBoardInitBeforeMemoryInit\n"));
+
+ AdlPInitPreMem ();
+
+ AdlPGpioGroupTierInit ();
+
+ AdlPMrcConfigInit ();
+ AdlPSaMiscConfigInit ();
+ Status = AdlPRootPortClkInfoInit ();
+ AdlPSaDisplayConfigInit ();
+ if (PcdGetPtr (PcdBoardGpioTableEarlyPreMem) != 0) {
+ GpioInit (PcdGetPtr (PcdBoardGpioTableEarlyPreMem));
+
+ MicroSecondDelay (15 * 1000); // 15 ms Delay
+ }
+ // Configure GPIO Before Memory
+ GpioInit (PcdGetPtr (PcdBoardGpioTablePreMem));
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This board service initializes board-specific debug devices.
+
+ @retval EFI_SUCCESS Board-specific debug initialization was successful.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardDebugInit (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "AdlPBoardDebugInit\n"));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This board service detects the boot mode.
+
+ @retval EFI_BOOT_MODE The boot mode.
+**/
+EFI_BOOT_MODE
+EFIAPI
+AdlPBoardBootModeDetect (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "AdlPBoardBootModeDetect\n"));
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c
new file mode 100644
index 0000000000..aa9809d126
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c
@@ -0,0 +1,45 @@
+/** @file
+ PEI Multi-Board Initialization in Post-Memory PEI Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeSiliconInit (
+ VOID
+ );
+
+
+BOARD_POST_MEM_INIT_FUNC mAdlPBoardInitFunc = {
+ AdlPBoardInitBeforeSiliconInit,
+ NULL,
+};
+
+EFI_STATUS
+EFIAPI
+PeiAdlPMultiBoardInitLibConstructor (
+ VOID
+ )
+{
+ UINT8 SkuType;
+ SkuType = PcdGet8 (PcdSkuType);
+
+ if (SkuType==AdlPSkuType) {
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ return RegisterBoardPostMemInit (&mAdlPBoardInitFunc);
+ }
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf
new file mode 100644
index 0000000000..a4dbc9294d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf
@@ -0,0 +1,53 @@
+## @file
+# Component information file for Alderlake Multi-Board Initialization in PEI post memory phase.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiAdlPMultiBoardInitLib
+ FILE_GUID = C7D39F17-E5BA-41D9-8DFE-FF9017499280
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = PeiAdlPMultiBoardInitLibConstructor
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PcdLib
+ MultiBoardInitSupportLib
+ PciSegmentLib
+ GpioLib
+ HobLib
+ BoardConfigLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ SecurityPkg/SecurityPkg.dec
+
+[Sources]
+ PeiInitPostMemLib.c
+ PeiMultiBoardInitPostMemLib.c
+
+[Pcd]
+ # Board GPIO Table
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
+
+ # TPM interrupt
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable ## CONSUMES
+ #Misc Config
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId
+
+ gBoardModuleTokenSpaceGuid.PcdBoardId
+ gBoardModuleTokenSpaceGuid.PcdSkuType
+ gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c
new file mode 100644
index 0000000000..fa45e86ac2
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c
@@ -0,0 +1,89 @@
+/** @file
+ PEI Multi-Board Initialization in Pre-Memory PEI Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BoardConfigLib.h>
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+AdlPBoardDetect (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+AdlPMultiBoardDetect (
+ VOID
+ );
+
+EFI_BOOT_MODE
+EFIAPI
+AdlPBoardBootModeDetect (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+AdlPBoardDebugInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeMemoryInit (
+ VOID
+ );
+
+BOARD_DETECT_FUNC mAdlPBoardDetectFunc = {
+ AdlPMultiBoardDetect
+};
+
+BOARD_PRE_MEM_INIT_FUNC mAdlPBoardPreMemInitFunc = {
+ AdlPBoardDebugInit,
+ AdlPBoardBootModeDetect,
+ AdlPBoardInitBeforeMemoryInit,
+ NULL, // BoardInitAfterMemoryInit
+ NULL, // BoardInitBeforeTempRamExit
+ NULL, // BoardInitAfterTempRamExit
+};
+
+EFI_STATUS
+EFIAPI
+AdlPMultiBoardDetect (
+ VOID
+ )
+{
+ UINT8 SkuType;
+ DEBUG ((DEBUG_INFO, " In AdlPMultiBoardDetect \n"));
+
+ AdlPBoardDetect ();
+
+ SkuType = PcdGet8 (PcdSkuType);
+ if (SkuType==AdlPSkuType) {
+ RegisterBoardPreMemInit (&mAdlPBoardPreMemInitFunc);
+ } else {
+ DEBUG ((DEBUG_WARN,"Not a Valid Alderlake P Board\n"));
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+PeiAdlPMultiBoardInitPreMemLibConstructor (
+ VOID
+ )
+{
+ return RegisterBoardDetect (&mAdlPBoardDetectFunc);
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf
new file mode 100644
index 0000000000..ea2b64050d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf
@@ -0,0 +1,149 @@
+## @file
+# Component information file for PEI Alderlake P Board Init Pre-Mem Library
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiAdlPMultiBoardInitPreMemLib
+ FILE_GUID = EA05BD43-136F-45EE-BBBA-27D75817574F
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = PeiAdlPMultiBoardInitPreMemLibConstructor
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PcdLib
+ MultiBoardInitSupportLib
+ PeiLib
+ BoardConfigLib
+ PchInfoLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+
+[Sources]
+ PeiInitPreMemLib.c
+ PeiMultiBoardInitPreMemLib.c
+ PeiDetect.c
+ BoardSaInitPreMemLib.c
+ BoardPchInitPreMemLib.c
+
+[Pcd]
+ # SA Misc Config
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
+
+ # SPD Address Table
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable4
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable5
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable6
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable7
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable8
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable9
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable10
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable11
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable12
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable13
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable14
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable15
+
+ #MRC Config
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2DramSize
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2Dram
+ gBoardModuleTokenSpaceGuid.PcdMrcLp5CccConfig
+ gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd
+
+ #Board Information
+ gBoardModuleTokenSpaceGuid.PcdSpdPresent
+ gBoardModuleTokenSpaceGuid.PcdBoardRev
+ gBoardModuleTokenSpaceGuid.PcdBoardId
+ gBoardModuleTokenSpaceGuid.PcdSkuType
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
+ gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem
+ gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcDqsMapCpu2Dram
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcDqMapCpu2Dram
+
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES
+
+ gBoardModuleTokenSpaceGuid.PcdStackBase
+ gBoardModuleTokenSpaceGuid.PcdStackSize
+
+ #SA GPIO Config
+ gBoardModuleTokenSpaceGuid.PcdRootPortIndex
+
+ # PCIe Clock Info
+ gBoardModuleTokenSpaceGuid.PcdPcieClock0
+ gBoardModuleTokenSpaceGuid.PcdPcieClock1
+ gBoardModuleTokenSpaceGuid.PcdPcieClock2
+ gBoardModuleTokenSpaceGuid.PcdPcieClock3
+ gBoardModuleTokenSpaceGuid.PcdPcieClock4
+ gBoardModuleTokenSpaceGuid.PcdPcieClock5
+ gBoardModuleTokenSpaceGuid.PcdPcieClock6
+ gBoardModuleTokenSpaceGuid.PcdPcieClock7
+ gBoardModuleTokenSpaceGuid.PcdPcieClock8
+ gBoardModuleTokenSpaceGuid.PcdPcieClock9
+ gBoardModuleTokenSpaceGuid.PcdPcieClock10
+ gBoardModuleTokenSpaceGuid.PcdPcieClock11
+ gBoardModuleTokenSpaceGuid.PcdPcieClock12
+ gBoardModuleTokenSpaceGuid.PcdPcieClock13
+ gBoardModuleTokenSpaceGuid.PcdPcieClock14
+ gBoardModuleTokenSpaceGuid.PcdPcieClock15
+
+
+ # GPIO Group Tier
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2
+
+
+
+ # WWAN Full Card Power Off and reset pins
+ gBoardModuleTokenSpaceGuid.PcdDisableVpdGpioTable
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem ## PRODUCES
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem ## PRODUCES
+
+
+ # Display DDI
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## PRODUCES
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress64 ## CONSUMES
+
+[Guids]
+ gFspNonVolatileStorageHobGuid
+ gEfiMemoryOverwriteControlDataGuid
+ gVpdFfsGuid
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
--
2.36.1.windows.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [edk2-devel] [PATCH v2 4/6] AlderlakeOpenBoardPkg: Add ACPI module
2023-08-01 22:17 [edk2-devel] [PATCH v2 1/6] AlderlakeOpenBoardPkg: Add package and headers Saloni Kasbekar
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 2/6] AlderlakeOpenBoardPkg: Add modules Saloni Kasbekar
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add libraries Saloni Kasbekar
@ 2023-08-01 22:17 ` Saloni Kasbekar
2023-08-02 20:25 ` Chaganty, Rangasai V
2023-08-04 0:48 ` Chuang, Rosen
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module Saloni Kasbekar
` (3 subsequent siblings)
6 siblings, 2 replies; 18+ messages in thread
From: Saloni Kasbekar @ 2023-08-01 22:17 UTC (permalink / raw)
To: devel
Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Isaac Oram,
Rosen Chuang
Adds the MinDsdt driver
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Acpi/MinDsdt/MinDsdt.asl | 68 +++++
.../Acpi/MinDsdt/MinDsdt.c | 232 ++++++++++++++++++
.../Acpi/MinDsdt/MinDsdt.inf | 48 ++++
3 files changed, 348 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl
new file mode 100644
index 0000000000..be110145bc
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl
@@ -0,0 +1,68 @@
+/** @file
+ ACPI minimum DSDT table
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+DefinitionBlock (
+ "DSDT.aml",
+ "DSDT",
+ 0x01, // DSDT revision.
+ // A Revision field value greater than or equal to 2 signifies that integers
+ // declared within the Definition Block are to be evaluated as 64-bit values
+ "INTEL ", // OEM ID (6 byte string)
+ "MIN ",// OEM table ID (8 byte string)
+ 0x00 // OEM version of DSDT table (4 byte Integer)
+)
+
+// BEGIN OF ASL SCOPE
+{
+ Scope(\_SB) {
+ //---------------------------------------------------------------------------
+ // Begin PCI tree object scope
+ //---------------------------------------------------------------------------
+ Device(PCI0) { // PCI Bridge "Host Bridge"
+ Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy
+ Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't understand the new HID
+ Name(_SEG, 0)
+ Method(^BN00, 0){ return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope
+ Method(_BBN, 0){ return(BN00()) } // Bus number, optional for the Root PCI Bus
+ Name(_UID, 0x0000) // Unique Bus ID, optional
+ Name(BUF0,ResourceTemplate()
+ {
+ //
+ // PCI Configuration Registers ( 0x0CF8 - 0x0CFF )
+ //
+ Io(Decode16,0x0CF8,0x0CF8,1,0x08)
+ //
+ // PCI MMIO space
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
+ ReadWrite,0x00,0x00,0x00,0x00,0x00,,,PM01)
+ })
+ Method(_CRS,0,Serialized)
+ {
+ //
+ // Create pointers to Memory Sizing values.
+ //
+ CreateDwordField(BUF0, ^PM01._MIN,M1MN)
+ CreateDwordField(BUF0, ^PM01._MAX,M1MX)
+ CreateDwordField(BUF0, ^PM01._LEN,M1LN)
+
+ //
+ // Set Memory Size Values. TLUD represents bits 31:20 of phyical
+ // TOM, so shift these bits into the correct position and fix up
+ // the Memory Region available to PCI.
+ //
+ Subtract (FixedPcdGet32(PcdPciReservedMemLimit),FixedPcdGet32(PcdPciReservedMemBase),M1LN)
+ Store (FixedPcdGet32(PcdPciReservedMemBase), M1MN)
+ Subtract (FixedPcdGet32(PcdPciReservedMemLimit), 1, M1MX)
+
+ Return(BUF0)
+ }
+ }
+ }
+}// End of ASL File
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c
new file mode 100644
index 0000000000..08709a43cd
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c
@@ -0,0 +1,232 @@
+/** @file
+ Min DSDT Driver
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <IndustryStandard/Acpi.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include <Protocol/FirmwareVolume2.h>
+#include <Protocol/AcpiTable.h>
+
+//
+// Function implementations
+//
+
+/**
+ Locate the first instance of a protocol. If the protocol requested is an
+ FV protocol, then it will return the first FV that contains the ACPI table
+ storage file.
+
+ @param[in] Protocol The protocol to find.
+ @param[in] FfsGuid The FFS that contains the ACPI table.
+ @param[out] Instance Return pointer to the first instance of the protocol.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NOT_FOUND The protocol could not be located.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.
+**/
+EFI_STATUS
+LocateSupportProtocol (
+ IN EFI_GUID *Protocol,
+ IN EFI_GUID *FfsGuid,
+ OUT VOID **Instance
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN NumberOfHandles;
+ EFI_FV_FILETYPE FileType;
+ UINT32 FvStatus;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINTN Size;
+ UINTN Index;
+
+ //
+ // Locate protocol.
+ //
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ Protocol,
+ NULL,
+ &NumberOfHandles,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // Defined errors at this time are not found and out of resources.
+ //
+ return Status;
+ }
+
+ //
+ // Looking for FV with ACPI storage file
+ //
+ for (Index = 0; Index < NumberOfHandles; Index++) {
+
+ //
+ // Get the protocol on this handle
+ // This should not fail because of LocateHandleBuffer
+ //
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ Protocol,
+ Instance
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // See if it has the ACPI storage file
+ //
+ Size = 0;
+ FvStatus = 0;
+ Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile (
+ *Instance,
+ FfsGuid,
+ NULL,
+ &Size,
+ &FileType,
+ &Attributes,
+ &FvStatus
+ );
+
+ //
+ // If we found it, then we are done
+ //
+ if (Status == EFI_SUCCESS) {
+ break;
+ }
+ }
+
+ //
+ // Our exit status is determined by the success of the previous operations
+ // If the protocol was found, Instance already points to it.
+ //
+ //
+ // Free any allocated buffers
+ //
+ FreePool (HandleBuffer);
+
+ return Status;
+}
+
+/**
+ Publish ACPI table from FV.
+
+ @param[in] FfsGuid The FFS that contains the ACPI table.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+PublishAcpiTablesFromFv (
+ IN EFI_GUID *FfsGuid
+ )
+{
+ EFI_STATUS Status;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+ EFI_ACPI_COMMON_HEADER *CurrentTable;
+ UINT32 FvStatus;
+ UINTN Size;
+ UINTN TableHandle;
+ INTN Instance;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+
+ Instance = 0;
+ TableHandle = 0;
+ CurrentTable = NULL;
+ FwVol = NULL;
+
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **)&AcpiTable);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Locate the firmware volume protocol
+ //
+ Status = LocateSupportProtocol (
+ &gEfiFirmwareVolume2ProtocolGuid,
+ FfsGuid,
+ (VOID **) &FwVol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Read tables from the storage file.
+ //
+
+ while (Status == EFI_SUCCESS) {
+ Status = FwVol->ReadSection (
+ FwVol,
+ FfsGuid,
+ EFI_SECTION_RAW,
+ Instance,
+ (VOID **) &CurrentTable,
+ &Size,
+ &FvStatus
+ );
+
+ if (!EFI_ERROR (Status)) {
+
+ //
+ // Add the table
+ //
+ TableHandle = 0;
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ CurrentTable,
+ CurrentTable->Length,
+ &TableHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Increment the instance
+ //
+ Instance++;
+ CurrentTable = NULL;
+ }
+ }
+
+ //
+ // Finished
+ //
+ return EFI_SUCCESS;
+}
+
+/**
+ ACPI Platform driver installation function.
+
+ @param[in] ImageHandle Handle for this drivers loaded image protocol.
+ @param[in] SystemTable EFI system table.
+
+ @retval EFI_SUCCESS The driver installed without error.
+ @retval EFI_ABORTED The driver encountered an error and could not complete installation of
+ the ACPI tables.
+
+**/
+EFI_STATUS
+EFIAPI
+InstallMinDsdt (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = PublishAcpiTablesFromFv (&gEfiCallerIdGuid);
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf
new file mode 100644
index 0000000000..f257140754
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf
@@ -0,0 +1,48 @@
+### @file
+# Component information file for Minimal DSDT module
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+# @par Glossary:
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = MinDsdt
+ FILE_GUID = 8EB04370-482C-4505-AA27-7EB226A5729F
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InstallMinDsdt
+
+[Sources.common]
+ MinDsdt.c
+ MinDsdt.asl
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ DebugLib
+ PcdLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ BaseMemoryLib
+ MemoryAllocationLib
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid ## CONSUMES
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+
+[Pcd]
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit
+
+[Depex]
+ gEfiAcpiTableProtocolGuid AND
+ gEfiFirmwareVolume2ProtocolGuid
+
--
2.36.1.windows.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [edk2-devel] [PATCH v2 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module
2023-08-01 22:17 [edk2-devel] [PATCH v2 1/6] AlderlakeOpenBoardPkg: Add package and headers Saloni Kasbekar
` (2 preceding siblings ...)
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 4/6] AlderlakeOpenBoardPkg: Add ACPI module Saloni Kasbekar
@ 2023-08-01 22:17 ` Saloni Kasbekar
2023-08-02 20:35 ` Chaganty, Rangasai V
2023-08-04 0:48 ` Chuang, Rosen
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 6/6] AlderlakeOpenBoardPkg: Add Library Instances Saloni Kasbekar
` (2 subsequent siblings)
6 siblings, 2 replies; 18+ messages in thread
From: Saloni Kasbekar @ 2023-08-01 22:17 UTC (permalink / raw)
To: devel
Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Isaac Oram,
Rosen Chuang
Adds the following libraries within the Policy module
- DxeSiliconPolicyUpdateLib
- PeiPolicyUpdateLib
- PeiSiliconPolicyUpdateLib
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../DxeSaPolicyInit.c | 64 +++
.../DxeSiliconPolicyUpdateLate.c | 78 ++++
.../DxeSiliconPolicyUpdateLib.inf | 53 +++
.../PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c | 114 +++++
.../PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h | 31 ++
.../PeiCpuPolicyUpdatePreMem.c | 93 +++++
.../PeiPolicyUpdateLib/PeiPchPolicyUpdate.c | 210 ++++++++++
.../PeiPolicyUpdateLib/PeiPchPolicyUpdate.h | 24 ++
.../PeiPchPolicyUpdatePreMem.c | 124 ++++++
.../PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf | 208 ++++++++++
.../PeiPolicyUpdateLib/PeiSaPolicyUpdate.c | 214 ++++++++++
.../PeiPolicyUpdateLib/PeiSaPolicyUpdate.h | 27 ++
.../PeiSaPolicyUpdatePreMem.c | 389 ++++++++++++++++++
.../PeiSiliconPolicyUpdateLib.inf | 65 +++
.../PeiSiliconPolicyUpdatePostMem.c | 39 ++
.../PeiSiliconPolicyUpdatePreMem.c | 37 ++
16 files changed, 1770 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
new file mode 100644
index 0000000000..da2f568e07
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
@@ -0,0 +1,64 @@
+/** @file
+ This file initialises and Installs GopPolicy Protocol.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/GraphicsInfoLib.h>
+#include <Protocol/SaPolicy.h>
+
+EFI_STATUS
+EFIAPI
+CreateSaDxeConfigBlocks (
+ IN OUT VOID **SaPolicy
+ );
+
+EFI_STATUS
+EFIAPI
+SaInstallPolicyProtocol (
+ IN EFI_HANDLE ImageHandle,
+ IN VOID *SaPolicy
+ );
+
+/**
+ Initialize SA DXE Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SaPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+ SA_POLICY_PROTOCOL *SaPolicy;
+
+ //
+ // Call CreateSaDxeConfigBlocks to create & initialize platform policy structure
+ // and get all Intel default policy settings.
+ //
+ Status = CreateSaDxeConfigBlocks (&SaPolicy);
+ DEBUG ((DEBUG_INFO, "SaPolicy->TableHeader.NumberOfBlocks = 0x%x\n ", SaPolicy->TableHeader.NumberOfBlocks));
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Install SaInstallPolicyProtocol.
+ // While installed, RC assumes the Policy is ready and finalized. So please
+ // update and override any setting before calling this function.
+ //
+ Status = SaInstallPolicyProtocol (ImageHandle, SaPolicy);
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
new file mode 100644
index 0000000000..11a9950124
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
@@ -0,0 +1,78 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+/**
+ Initialize SA DXE Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SaPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ );
+
+/**
+ Initilize Intel Silicon DXE Platform Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SiliconPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ );
+
+/**
+ Performs silicon late policy update.
+
+ The meaning of Policy is defined by silicon code.
+ It could be the raw data, a handle, a Protocol, etc.
+
+ The input Policy must be returned by SiliconPolicyDoneLate().
+
+ In FSP or non-FSP path, the board may use additional way to get
+ the silicon policy data field based upon the input Policy.
+
+ @param[in, out] Policy Pointer to policy.
+
+ @return the updated policy.
+**/
+VOID *
+EFIAPI
+SiliconPolicyUpdateLate (
+ IN OUT VOID *Policy
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+
+ //
+ // SystemAgent Dxe Platform Policy Initialization
+ //
+ Status = SaPolicyInitDxe (gImageHandle);
+ DEBUG ((DEBUG_INFO, "SystemAgent Dxe Platform Policy Initialization status: %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
new file mode 100644
index 0000000000..54b4d7b17d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
@@ -0,0 +1,53 @@
+## @file
+# Component information file for Silicon Policy Update Library
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = DxeSiliconUpdateLib
+ FILE_GUID = C523609D-E354-416B-B24F-33468D4BD21D
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconPolicyUpdateLib
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ PcdLib
+ DebugLib
+ UefiBootServicesTableLib
+ MemoryAllocationLib
+ DxeSaPolicyLib
+ UefiLib
+ ConfigBlockLib
+ GraphicsInfoLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ DxeSiliconPolicyUpdateLate.c
+ DxeSaPolicyInit.c
+
+[Pcd]
+ gBoardModuleTokenSpaceGuid.PcdIntelGopEnable
+ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid
+ gPlatformModuleTokenSpaceGuid.PcdSmbiosOemTypeFirmwareVersionInfo ## CONSUMES
+
+[Protocols]
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+ gSaPolicyProtocolGuid ## CONSUMES
+ gDxeSiPolicyProtocolGuid ## PRODUCES
+ gGopPolicyProtocolGuid ## PRODUCES
+
+[Depex]
+ gEfiVariableArchProtocolGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c
new file mode 100644
index 0000000000..1ee4bdd038
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c
@@ -0,0 +1,114 @@
+/** @file
+ CPU PEI Policy Update & initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+#include "PeiCpuPolicyUpdate.h"
+#include <Library/ConfigBlockLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/HobLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Library/Tpm12CommandLib.h>
+#include <Library/Tpm2CommandLib.h>
+#include <PolicyUpdateMacro.h>
+
+/*
+ Get the uCode region from PCD settings, and copy the patches to memory.
+ This function is used to replace CpuLocateMicrocodePatch due to that function can not works
+ with uCode update new design.
+ In current uCode update solution, there are some padding data between uCode patches,
+ the algorithm in CpuLocateMicrocodePatch can not handle this.
+ Besides that, in CpuLocateMicrocodePatch function, the scan algorithm just find the first
+ correct uCode patch which is not the highest version uCode.
+ This function just copy the uCode region to memory, and in later, the CpuMpInit driver
+ will load the correct patch for CPU.
+
+ @param[out] RegionAddress Pointer to the uCode array.
+ @param[out] RegionSize Size of the microcode FV.
+
+ @retval EFI_SUCCESS Find uCode patch region and success copy the data to memory.
+ @retval EFI_NOT_FOUND Something wrong with uCode region.
+ @retval EFI_OUT_OF_RESOUCES Memory allocation fail.
+ @retval EFI_INVALID_PARAMETER RegionAddres or RegionSize is NULL.
+
+*/
+EFI_STATUS
+SearchMicrocodeRegion (
+ OUT UINTN *RegionAddress,
+ OUT UINTN *RegionSize
+ )
+{
+ UINTN MicrocodeStart;
+ UINTN MicrocodeEnd;
+ UINT8 *MemoryBuffer;
+
+ if (RegionAddress == NULL || RegionSize == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *RegionAddress = 0;
+ *RegionSize = 0;
+
+ if ((FixedPcdGet32 (PcdFlashFvMicrocodeBase) == 0) || (FixedPcdGet32 (PcdFlashFvMicrocodeSize) == 0)) {
+ return EFI_NOT_FOUND;
+ }
+
+ MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeBase) + (UINTN) FixedPcdGet32 (PcdMicrocodeOffsetInFv);
+ MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeBase) + (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeSize);
+ *RegionSize = MicrocodeEnd - MicrocodeStart;
+
+ DEBUG ((DEBUG_INFO, "[SearchMicrocodeRegion]: Microcode Region Address = %x, Size = %d\n", MicrocodeStart, *RegionSize));
+
+ MemoryBuffer = AllocatePages (EFI_SIZE_TO_PAGES (*RegionSize));
+ ASSERT (MemoryBuffer != NULL);
+ if (MemoryBuffer == NULL) {
+ DEBUG ((DEBUG_ERROR, "Failed to allocate enough memory for Microcode Patch.\n"));
+ return EFI_OUT_OF_RESOURCES;
+ } else {
+ CopyMem (MemoryBuffer, (UINT8 *)MicrocodeStart, *RegionSize);
+ *RegionAddress = (UINTN)MemoryBuffer;
+ DEBUG ((DEBUG_INFO, "Copy whole uCode region to memory, address = %x, size = %d\n", RegionAddress, *RegionSize));
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function performs CPU PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicy (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ SI_POLICY_PPI *SiPolicyPpi;
+ CPU_CONFIG *CpuConfig;
+
+ DEBUG ((DEBUG_INFO, "Update PeiCpuPolicyUpdate Pos-Mem Start\n"));
+
+ SiPolicyPpi = NULL;
+ CpuConfig = NULL;
+
+ Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID *) &CpuConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = SearchMicrocodeRegion (
+ (UINTN *)&CpuConfig->MicrocodePatchAddress,
+ (UINTN *)&CpuConfig->MicrocodePatchRegionSize
+ );
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h
new file mode 100644
index 0000000000..b003481db0
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h
@@ -0,0 +1,31 @@
+/** @file
+ Header file for PEI CpuPolicyUpdate.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_CPU_POLICY_UPDATE_H_
+#define _PEI_CPU_POLICY_UPDATE_H_
+
+#include <PiPei.h>
+#include <Ppi/SiPolicy.h>
+#include <Ppi/Wdt.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <PlatformBoardId.h>
+#include <Library/BaseCryptLib.h>
+#include <Register/Cpuid.h>
+#include <Register/Msr.h>
+#include <Ppi/MasterBootMode.h>
+#include <Library/PeiServicesLib.h>
+#include "PeiPchPolicyUpdate.h"
+#include <Library/CpuPlatformLib.h>
+
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..b23e2ceceb
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c
@@ -0,0 +1,93 @@
+/** @file
+ This file is SampleCode of the library for Intel CPU PEI Policy initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "PeiCpuPolicyUpdate.h"
+#include <Library/ConfigBlockLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/FirmwareBootMediaLib.h>
+#include <Library/HobLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/PmcLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Library/SpiLib.h>
+#include <Ppi/Spi.h>
+#include <Register/CommonMsr.h>
+#include <Register/PchRegs.h>
+#include <PlatformBoardConfig.h>
+#include <PolicyUpdateMacro.h>
+
+#define GET_OCCUPIED_SIZE(ActualSize, Alignment) \
+ ((ActualSize) + (((Alignment) - ((ActualSize) & ((Alignment) - 1))) & ((Alignment) - 1)))
+
+
+/**
+ This function performs CPU PEI Policy initialization in Pre-memory.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ CPU_SECURITY_PREMEM_CONFIG *CpuSecurityPreMemConfig;
+ CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ UINT32 MaxLogicProcessors;
+ UINT16 BiosSize;
+ UINT16 BiosMemSizeInMb;
+ FW_BOOT_MEDIA_TYPE FwBootMediaType;
+ MSR_CORE_THREAD_COUNT_REGISTER MsrCoreThreadCount;
+ UINT8 AllCoreCount;
+ UINT8 AllSmallCoreCount;
+ UINT32 DisablePerCoreMask;
+
+ DEBUG ((DEBUG_INFO, "Update PeiCpuPolicyUpdate Pre-Mem Start\n"));
+
+ SiPreMemPolicyPpi = NULL;
+ CpuSecurityPreMemConfig = NULL;
+ CpuConfigLibPreMemConfig = NULL;
+ BiosSize = 0;
+ BiosMemSizeInMb = 0;
+ FwBootMediaType = FwBootMediaMax;
+ AllCoreCount = 0;
+ AllSmallCoreCount = 0;
+ DisablePerCoreMask = 0;
+
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuSecurityPreMemConfigGuid, (VOID *) &CpuSecurityPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPreMemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SkipStopPbet, CpuSecurityPreMemConfig->SkipStopPbet, FALSE);
+
+ SpiServiceInit ();
+ DEBUG ((DEBUG_INFO, "BIOS Guard PCD and Policy are disabled\n"));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.BiosGuard, CpuSecurityPreMemConfig->BiosGuard, CPU_FEATURE_DISABLE);
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.CpuRatio, CpuConfigLibPreMemConfig->CpuRatio, 0);
+
+ ///
+ /// Set PcdCpuMaxLogicalProcessorNumber to max number of logical processors enabled
+ /// Read MSR_CORE_THREAD_COUNT (0x35) to check the total active Threads
+ ///
+ MsrCoreThreadCount.Uint64 = AsmReadMsr64 (MSR_CORE_THREAD_COUNT);
+ MaxLogicProcessors = MsrCoreThreadCount.Bits.Threadcount;
+ DEBUG ((DEBUG_INFO, "MaxLogicProcessors = %d\n", MaxLogicProcessors));
+
+ PcdSetEx32S (&gUefiCpuPkgTokenSpaceGuid, PcdCpuMaxLogicalProcessorNumber, MaxLogicProcessors);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
new file mode 100644
index 0000000000..1c0cf6bee0
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
@@ -0,0 +1,210 @@
+/** @file
+ This file is SampleCode of the library for Intel PCH PEI Policy initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Guid/FmpCapsule.h>
+#include <Guid/GlobalVariable.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioConfig.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <ConfigBlock.h>
+#include <Ppi/Spi.h>
+#include <PlatformBoardConfig.h>
+#include <PolicyUpdateMacro.h>
+#include <SerialIoDevices.h>
+#include <Pins/GpioPinsVer2Lp.h>
+
+/**
+ This is helper function for getting I2C Pads Internal Termination settings from Pcd
+
+ @param[in] Index I2C Controller Index
+**/
+UINT8
+STATIC
+GetSerialIoI2cPadsTerminationFromPcd (
+ IN UINT8 Index
+ )
+{
+ switch (Index) {
+ case 0:
+ return PcdGet8 (PcdPchSerialIoI2c0PadInternalTerm);
+ case 1:
+ return PcdGet8 (PcdPchSerialIoI2c1PadInternalTerm);
+ case 2:
+ return PcdGet8 (PcdPchSerialIoI2c2PadInternalTerm);
+ case 3:
+ return PcdGet8 (PcdPchSerialIoI2c3PadInternalTerm);
+ case 4:
+ return PcdGet8 (PcdPchSerialIoI2c4PadInternalTerm);
+ case 5:
+ return PcdGet8 (PcdPchSerialIoI2c5PadInternalTerm);
+ case 6:
+ return PcdGet8 (PcdPchSerialIoI2c6PadInternalTerm);
+ case 7:
+ return PcdGet8 (PcdPchSerialIoI2c7PadInternalTerm);
+ default:
+ ASSERT (FALSE); // Invalid I2C Controller Index
+ }
+ return 0;
+}
+
+/**
+ This function performs PCH Serial IO Platform Policy initialization
+
+ @param[in] SiPolicy Pointer to SI_POLICY_PPI
+ @param[in] FspsUpd A VOID pointer
+**/
+VOID
+UpdateSerialIoConfig (
+ IN SI_POLICY_PPI *SiPolicy,
+ IN VOID *FspsUpd
+ )
+{
+ UINT8 Index;
+ SERIAL_IO_CONFIG *SerialIoConfig;
+ EFI_STATUS Status;
+
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOID *) &SerialIoConfig);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ //
+ // I2C
+ //
+ for (Index = 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PchSerialIoI2cPadsTermination[Index], SerialIoConfig->I2cDeviceConfig[Index].PadTermination, GetSerialIoI2cPadsTerminationFromPcd (Index));
+ }
+
+ if (IsPchP ()) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[0], SerialIoConfig->I2cDeviceConfig[0].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[1], SerialIoConfig->I2cDeviceConfig[1].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[2], SerialIoConfig->I2cDeviceConfig[2].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[3], SerialIoConfig->I2cDeviceConfig[3].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[4], SerialIoConfig->I2cDeviceConfig[4].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[5], SerialIoConfig->I2cDeviceConfig[5].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[6], SerialIoConfig->I2cDeviceConfig[6].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[7], SerialIoConfig->I2cDeviceConfig[7].Mode, 0);
+ }
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[0], SerialIoConfig->UartDeviceConfig[0].Mode, 2);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[1], SerialIoConfig->UartDeviceConfig[1].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[2], SerialIoConfig->UartDeviceConfig[2].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[3], SerialIoConfig->UartDeviceConfig[3].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[4], SerialIoConfig->UartDeviceConfig[4].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[5], SerialIoConfig->UartDeviceConfig[5].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[6], SerialIoConfig->UartDeviceConfig[6].Mode, 0);
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[0], SerialIoConfig->UartDeviceConfig[0].Attributes.AutoFlow, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[1], SerialIoConfig->UartDeviceConfig[1].Attributes.AutoFlow, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[2], SerialIoConfig->UartDeviceConfig[2].Attributes.AutoFlow, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[3], SerialIoConfig->UartDeviceConfig[3].Attributes.AutoFlow, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[4], SerialIoConfig->UartDeviceConfig[4].Attributes.AutoFlow, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[5], SerialIoConfig->UartDeviceConfig[5].Attributes.AutoFlow, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[6], SerialIoConfig->UartDeviceConfig[6].Attributes.AutoFlow, 0);
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[0], SerialIoConfig->UartDeviceConfig[0].PowerGating, 2);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[1], SerialIoConfig->UartDeviceConfig[1].PowerGating, 2);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[2], SerialIoConfig->UartDeviceConfig[2].PowerGating, 2);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[3], SerialIoConfig->UartDeviceConfig[3].PowerGating, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[4], SerialIoConfig->UartDeviceConfig[4].PowerGating, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[5], SerialIoConfig->UartDeviceConfig[5].PowerGating, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[6], SerialIoConfig->UartDeviceConfig[6].PowerGating, 0);
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[0], SerialIoConfig->UartDeviceConfig[0].DmaEnable, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[1], SerialIoConfig->UartDeviceConfig[1].DmaEnable, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[2], SerialIoConfig->UartDeviceConfig[2].DmaEnable, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[3], SerialIoConfig->UartDeviceConfig[3].DmaEnable, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[4], SerialIoConfig->UartDeviceConfig[4].DmaEnable, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[5], SerialIoConfig->UartDeviceConfig[5].DmaEnable, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[6], SerialIoConfig->UartDeviceConfig[6].DmaEnable, 0);
+
+}
+
+
+/**
+ Update PCIe Root Port Configuration
+
+ @param[in] SiPolicy Pointer to SI_POLICY_PPI
+ @param[in] FspsUpd Pointer to FspsUpd structure
+ // @param[in] PchSetup Pointer to PCH_SETUP buffer
+ // @param[in] SetupVariables Pointer to SETUP_DATA buffer
+**/
+VOID
+UpdatePcieRpConfig (
+ IN SI_POLICY_PPI *SiPolicy,
+ IN VOID *FspsUpd
+ )
+{
+ UINT8 Index;
+ EFI_STATUS Status;
+ PCH_PCIE_CONFIG *PchPcieConfig;
+ UINTN MaxPciePorts;
+
+ MaxPciePorts = GetPchMaxPciePortNum ();
+
+ PchPcieConfig = NULL;
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gPchPcieConfigGuid, (VOID *) &PchPcieConfig);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ //
+ // PCI express config
+ //
+ for (Index = 0; Index < MaxPciePorts; Index++) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpMaxPayload[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.MaxPayload, PchPcieMaxPayload256);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpPhysicalSlotNumber[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PhysicalSlotNumber, (UINT8) Index);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpClkReqDetect[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.ClkReqDetect, TRUE);
+ }
+}
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicy (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ VOID *FspsUpd;
+ SI_POLICY_PPI *SiPolicy;
+ VOID *FspmUpd;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ CPU_SECURITY_PREMEM_CONFIG *CpuSecurityPreMemConfig;
+
+ DEBUG ((DEBUG_INFO, "Update PeiPchPolicyUpdate Pos-Mem Start\n"));
+
+ FspsUpd = NULL;
+ FspmUpd = NULL;
+ SiPolicy = NULL;
+ CpuSecurityPreMemConfig = NULL;
+ SiPreMemPolicyPpi = NULL;
+
+ Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicy);
+ ASSERT_EFI_ERROR (Status);
+
+ UpdatePcieRpConfig (SiPolicy, FspsUpd);
+ UpdateSerialIoConfig (SiPolicy, FspsUpd);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h
new file mode 100644
index 0000000000..133660c59e
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h
@@ -0,0 +1,24 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_PCH_POLICY_UPDATE_H_
+#define _PEI_PCH_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <PiPei.h>
+#include <PlatformBoardId.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/ConfigBlockLib.h>
+#include <PlatformBoardConfig.h>
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..47ecd41b39
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
@@ -0,0 +1,124 @@
+/** @file
+ This file is SampleCode of the library for Intel PCH PEI Policy initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Guid/GlobalVariable.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <PolicyUpdateMacro.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <PchDmiConfig.h>
+
+VOID
+UpdatePcieClockInfo (
+ PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig,
+ IN VOID *FspmUpd,
+ UINTN Index,
+ UINT64 Data
+ )
+{
+ PCD64_BLOB Pcd64;
+
+ Pcd64.Blob = Data;
+ DEBUG ((DEBUG_INFO, "UpdatePcieClockInfo ClkIndex %x ClkUsage %x, Supported %x\n", Index, Pcd64.PcieClock.ClockUsage, Pcd64.PcieClock.ClkReqSupported));
+
+ UPDATE_POLICY (((FSPM_UPD *)FspmUpd)->FspmConfig.PcieClkSrcUsage[Index], PcieRpPreMemConfig->PcieClock[Index].Usage, (UINT8)Pcd64.PcieClock.ClockUsage);
+ UPDATE_POLICY (((FSPM_UPD *)FspmUpd)->FspmConfig.PcieClkSrcClkReq[Index], PcieRpPreMemConfig->PcieClock[Index].ClkReq, Pcd64.PcieClock.ClkReqSupported ? (UINT8)Index : 0xFF);
+}
+
+/**
+ Update PcieRp pre mem policies.
+
+ @param[in] SiPreMemPolicy Pointer to SI_PREMEM_POLICY_PPI
+ @param[in] FspsUpm Pointer to FSPM_UPD
+ @param[in] PchSetup Pointer to PCH_SETUP
+**/
+STATIC
+VOID
+UpdatePcieRpPreMemPolicy (
+ IN SI_PREMEM_POLICY_PPI *SiPreMemPolicy,
+ IN VOID *FspmUpd
+ )
+{
+ UINT32 RpIndex;
+ UINT32 RpEnabledMask;
+ PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig;
+ EFI_STATUS Status;
+
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfigGuid, (VOID *) &PcieRpPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ GET_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PcieRpEnableMask, PcieRpPreMemConfig->RpEnabledMask, RpEnabledMask);
+
+ for (RpIndex = 0; RpIndex < GetPchMaxPciePortNum (); RpIndex ++) {
+ RpEnabledMask |= (UINT32) (1 << RpIndex);
+ }
+ // RpEnabledMask value is related with Setup value, Need to check Policy Default
+ COMPARE_AND_UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PcieRpEnableMask, PcieRpPreMemConfig->RpEnabledMask, RpEnabledMask);
+
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 0, PcdGet64(PcdPcieClock0));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 1, PcdGet64(PcdPcieClock1));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 2, PcdGet64(PcdPcieClock2));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 3, PcdGet64(PcdPcieClock3));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 4, PcdGet64(PcdPcieClock4));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 5, PcdGet64(PcdPcieClock5));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 6, PcdGet64(PcdPcieClock6));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 7, PcdGet64(PcdPcieClock7));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 8, PcdGet64(PcdPcieClock8));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 9, PcdGet64(PcdPcieClock9));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 10, PcdGet64(PcdPcieClock10));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 11, PcdGet64(PcdPcieClock11));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 12, PcdGet64(PcdPcieClock12));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 13, PcdGet64(PcdPcieClock13));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 14, PcdGet64(PcdPcieClock14));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 15, PcdGet64(PcdPcieClock15));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 16, PcdGet64(PcdPcieClock16));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 17, PcdGet64(PcdPcieClock17));
+
+}
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ VOID *FspmUpd;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicy;
+
+ DEBUG ((DEBUG_INFO, "Update PeiPchPolicyUpdate Pre-Mem Start\n"));
+
+ FspmUpd = NULL;
+ SiPreMemPolicy = NULL;
+
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicy);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ UpdatePcieRpPreMemPolicy (SiPreMemPolicy, FspmUpd);
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
new file mode 100644
index 0000000000..844e4c9967
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
@@ -0,0 +1,208 @@
+### @file
+# Module Information file for PEI PolicyUpdateLib Library
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiPolicyUpdateLib
+ FILE_GUID = D42F5BB8-E0CE-47BD-8C52-476C79055FC6
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = PeiPolicyUpdateLib|PEIM PEI_CORE SEC
+
+[LibraryClasses]
+ HobLib
+ BaseCryptLib
+ CpuPlatformLib
+ IoLib
+ ConfigBlockLib
+ MemoryAllocationLib
+ PeiServicesTablePointerLib
+ PcdLib
+ Tpm2CommandLib
+ Tpm12CommandLib
+ Tpm2DeviceLib
+ Tpm12DeviceLib
+ BoardConfigLib
+ PciSegmentLib
+ SiPolicyLib
+ PeiServicesLib
+ FirmwareBootMediaLib
+ SpiLib
+ BmpSupportLib
+ PeiGetFvInfoLib
+ TimerLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ CryptoPkg/CryptoPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+
+[FixedPcd]
+ gBoardModuleTokenSpaceGuid.PcdDefaultBoardId ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdMchBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdGttMmAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress ## CONSUMES
+
+ gBoardModuleTokenSpaceGuid.PcdBoardId ## CONSUMES
+
+ # SA Misc Config
+ gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2Dram ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2DramSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcLp5CccConfig ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcCmdMirror ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMask ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMaskEcc ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaMiscDisableMrcRetrainingOnRtcPowerLoss ## CONSUMES
+
+ # Display DDI
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## CONSUMES
+
+ # PCIE RTD3 GPIO
+ gBoardModuleTokenSpaceGuid.PcdRootPortIndex ## CONSUMES
+
+ # SPD Address Table
+ gBoardModuleTokenSpaceGuid.PcdSpdPresent ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable4 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable5 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable6 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable7 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable8 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable9 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable10 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable11 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable12 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable13 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable14 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable15 ## CONSUMES
+
+
+ # PCIe Clock Info
+ gBoardModuleTokenSpaceGuid.PcdPcieClock0 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock1 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock2 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock3 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock4 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock5 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock6 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock7 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock8 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock9 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock10 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock11 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock12 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock13 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock14 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock15 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock16 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock17 ## CONSUMES
+
+
+ # Pch SerialIo I2c Pads Termination
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c6PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c7PadInternalTerm ## CONSUMES
+
+ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem ## CONSUMES
+
+[Sources]
+ PeiPchPolicyUpdatePreMem.c
+ PeiPchPolicyUpdate.c
+ PeiCpuPolicyUpdatePreMem.c
+ PeiCpuPolicyUpdate.c
+ PeiSaPolicyUpdate.c
+ PeiSaPolicyUpdatePreMem.c
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+ gWdtPpiGuid ## CONSUMES
+ gPchSpiPpiGuid ## CONSUMES
+ gSiPolicyPpiGuid ## CONSUMES
+ gSiPreMemPolicyPpiGuid ## CONSUMES
+ gFspmArchConfigPpiGuid ## PRODUCES
+ gReadyForGopConfigPpiGuid ## PRODUCES
+ gPeiGraphicsPlatformPpiGuid ## CONSUMES
+ gPeiGraphicsFramebufferReadyPpiGuid ## CONSUMES
+
+[Guids]
+ gEfiGlobalVariableGuid ## CONSUMES
+ gMemoryConfigVariableGuid ## CONSUMES
+ gEfiCapsuleVendorGuid ## CONSUMES
+ gEfiMemoryTypeInformationGuid ## CONSUMES
+ gEfiMemoryOverwriteControlDataGuid ## CONSUMES
+ gSiPreMemConfigGuid ## CONSUMES
+ gSiConfigGuid ## CONSUMES
+ gCpuSecurityPreMemConfigGuid ## CONSUMES
+ gCpuConfigLibPreMemConfigGuid ## CONSUMES
+ gCpuConfigGuid ## CONSUMES
+ gVmdPeiConfigGuid ## CONSUMES
+ gCpuPcieRpPrememConfigGuid ## CONSUMES
+ gVmdInfoHobGuid ## CONSUMES
+ gPciePreMemConfigGuid ## CONSUMES
+ gPlatformInitFvLocationGuid ## CONSUMES
+ gHostBridgePeiPreMemConfigGuid ## CONSUMES
+ gEfiGraphicsInfoHobGuid ## CONSUMES
+ gPchDmiPreMemConfigGuid ## CONSUMES
+ gGraphicsPeiConfigGuid ## CONSUMES
+ gMemoryConfigGuid ## CONSUMES
+ gMemoryConfigNoCrcGuid ## CONSUMES
+ gPchPcieConfigGuid ## CONSUMES
+ gSerialIoConfigGuid ## CONSUMES
+ gPcieRpPreMemConfigGuid ## CONSUMES
+ gSaMiscPeiPreMemConfigGuid ## CONSUMES
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c
new file mode 100644
index 0000000000..c62b0a14ef
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c
@@ -0,0 +1,214 @@
+/** @file
+Do Platform Stage System Agent initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/BmpSupportLib.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiGetFvInfoLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Protocol/GraphicsOutput.h>
+
+#include <CpuPcieConfig.h>
+#include <CpuPcieHob.h>
+#include <IndustryStandard/Bmp.h>
+#include <PolicyUpdateMacro.h>
+#include <Guid/GraphicsInfoHob.h>
+
+#include <VmdPeiConfig.h>
+#include <Ppi/GraphicsPlatformPolicyPpi.h>
+
+
+EFI_STATUS
+EFIAPI
+PeiGraphicsPolicyUpdateCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_GRAPHICS_INFO_HOB *PlatformGraphicsOutput;
+ EFI_PEI_HOB_POINTERS Hob;
+ UINT8 *HobStart;
+ GRAPHICS_PEI_CONFIG *GtConfig;
+ SI_POLICY_PPI *SiPolicyPpi;
+
+ PlatformGraphicsOutput = NULL;
+ HobStart = NULL;
+
+ GtConfig = NULL;
+ SiPolicyPpi = NULL;
+ Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *) &GtConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
+ HobStart = Hob.Raw;
+
+ if (!EFI_ERROR (Status)) {
+ if (HobStart != NULL) {
+ if ((Hob.Raw = GetNextGuidHob (&gEfiGraphicsInfoHobGuid, HobStart)) != NULL) {
+ DEBUG ((DEBUG_INFO, "Found EFI_PEI_GRAPHICS_INFO_HOB\n"));
+ PlatformGraphicsOutput = GET_GUID_HOB_DATA (Hob.Guid);
+ }
+ }
+ }
+
+ if (PlatformGraphicsOutput != NULL) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.HorizontalResolution, GtConfig->HorizontalResolution, PlatformGraphicsOutput->GraphicsMode.HorizontalResolution);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.VerticalResolution, GtConfig->VerticalResolution, PlatformGraphicsOutput->GraphicsMode.VerticalResolution);
+ } else {
+ DEBUG ((DEBUG_INFO, "Not able to find EFI_PEI_GRAPHICS_INFO_HOB\n"));
+ }
+
+ return Status;
+}
+
+STATIC
+EFI_PEI_NOTIFY_DESCRIPTOR mPeiGfxPolicyUpdateNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gPeiGraphicsFramebufferReadyPpiGuid,
+ PeiGraphicsPolicyUpdateCallback
+};
+
+/**
+ UpdatePeiSaPolicy performs SA PEI Policy initialization
+
+ @retval EFI_SUCCESS The policy is installed and initialized.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicy (
+ VOID
+ )
+{
+ EFI_GUID BmpImageGuid;
+ EFI_STATUS Status;
+ EFI_GUID FileGuid;
+ VOID *Buffer;
+ UINT32 Size;
+ VOID *VmdVariablePtr;
+ GRAPHICS_PEI_CONFIG *GtConfig;
+ SI_POLICY_PPI *SiPolicyPpi;
+ CPU_PCIE_CONFIG *CpuPcieRpConfig;
+ VMD_PEI_CONFIG *VmdPeiConfig;
+ EFI_PEI_PPI_DESCRIPTOR *ReadyForGopConfigPpiDesc;
+ VOID *VbtPtr;
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Blt;
+ UINTN BltSize;
+ UINTN Height;
+ UINTN Width;
+
+ DEBUG ((DEBUG_INFO, "Update PeiSaPolicyUpdate Pos-Mem Start\n"));
+
+ Size = 0;
+ Blt = NULL;
+ BltSize = 0;
+
+ GtConfig = NULL;
+ SiPolicyPpi = NULL;
+ CpuPcieRpConfig = NULL;
+ VmdVariablePtr = NULL;
+ Buffer = NULL;
+
+ Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *) &GtConfig);
+ ASSERT_EFI_ERROR(Status);
+
+
+
+ VmdPeiConfig = NULL;
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gVmdPeiConfigGuid, (VOID *) &VmdPeiConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ CopyMem(&BmpImageGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid), sizeof(BmpImageGuid));
+
+ if (!EFI_ERROR (Status)) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SkipFspGop, GtConfig->SkipFspGop, 0x0);
+ Buffer = NULL;
+
+ CopyMem(&FileGuid, &BmpImageGuid, sizeof(FileGuid));
+ PeiGetSectionFromFv(FileGuid, &Buffer, &Size);
+ if (Buffer == NULL) {
+ DEBUG((DEBUG_ERROR, "Could not locate VBT\n"));
+ }
+
+ GtConfig->GraphicsConfigPtr = Buffer;
+ DEBUG ((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", GtConfig->GraphicsConfigPtr));
+ DEBUG ((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size));
+ GET_POLICY ((VOID *) ((FSPS_UPD *) FspsUpd)->FspsConfig.GraphicsConfigPtr, GtConfig->GraphicsConfigPtr, VbtPtr);
+
+ //
+ // Install ReadyForGopConfig PPI to trigger PEI phase GopConfig callback.
+ //
+ ReadyForGopConfigPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+ if (ReadyForGopConfigPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+ ReadyForGopConfigPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ ReadyForGopConfigPpiDesc->Guid = &gReadyForGopConfigPpiGuid;
+ ReadyForGopConfigPpiDesc->Ppi = VbtPtr;
+ Status = PeiServicesInstallPpi (ReadyForGopConfigPpiDesc);
+
+ Status = TranslateBmpToGopBlt (
+ Buffer,
+ Size,
+ &Blt,
+ &BltSize,
+ &Height,
+ &Width
+ );
+
+ if (Status == EFI_BUFFER_TOO_SMALL) {
+ Blt = NULL;
+ Status = TranslateBmpToGopBlt (
+ Buffer,
+ Size,
+ &Blt,
+ &BltSize,
+ &Height,
+ &Width
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "TranslateBmpToGopBlt, Status = %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+ }
+
+ //
+ // Initialize Blt, BltSize
+ //
+ GtConfig->BltBufferAddress = Blt;
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.BltBufferSize, GtConfig->BltBufferSize, BltSize);
+
+ DEBUG ((DEBUG_INFO, "Calling mPeiGfxPolicyUpdateNotifyList\n"));
+ Status = PeiServicesNotifyPpi (&mPeiGfxPolicyUpdateNotifyList);
+
+ }
+
+ //
+ // VMD related settings from setup variable
+ //
+ COMPARE_AND_UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.VmdEnable, VmdPeiConfig->VmdEnable, 0);
+ VmdPeiConfig->VmdVariablePtr = VmdVariablePtr;
+ DEBUG ((DEBUG_INFO, "VmdVariablePtr from PeiGetSectionFromFv is 0x%x\n", VmdVariablePtr));
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h
new file mode 100644
index 0000000000..64f97b672b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h
@@ -0,0 +1,27 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_SA_POLICY_UPDATE_H_
+#define _PEI_SA_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <Ppi/SiPolicy.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <Ppi/Wdt.h>
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+#include "PeiPchPolicyUpdate.h"
+#include <Library/PcdLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/SiPolicyLib.h>
+
+#define WDT_TIMEOUT 60
+
+#endif
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..a4ceda76c3
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
@@ -0,0 +1,389 @@
+/** @file
+Do Platform Stage System Agent initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include "MemoryConfig.h"
+#include <Guid/MemoryOverwriteControl.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/GpioLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Register/CommonMsr.h>
+#include <Register/Cpuid.h>
+#include <Register/Msr.h>
+#include <CpuRegs.h>
+#include <HostBridgeConfig.h>
+#include <PlatformBoardConfig.h>
+#include <PolicyUpdateMacro.h>
+#include <SaDataHob.h>
+#include <Ppi/FspmArchConfigPpi.h>
+
+///
+/// Memory Reserved should be between 125% to 150% of the Current required memory
+/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resume issues.
+///
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
+ { EfiACPIReclaimMemory, FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemorySize) }, // ASL
+ { EfiACPIMemoryNVS, FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize) }, // ACPI NVS (including S3 related)
+ { EfiReservedMemoryType, FixedPcdGet32 (PcdPlatformEfiReservedMemorySize) }, // BIOS Reserved (including S3 related)
+ { EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize) }, // Runtime Service Data
+ { EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize) }, // Runtime Service Code
+ { EfiMaxMemoryType, 0 }
+};
+
+#define PEI_MIN_MEMORY_SIZE (10 * 0x800000) // 80MB
+
+/**
+ UpdatePeiSaPolicyPreMem performs SA PEI Policy initialization
+
+ @retval EFI_SUCCESS The policy is installed and initialized.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
+ UINTN VariableSize;
+ SA_MEMORY_RCOMP *RcompData;
+ WDT_PPI *gWdtPei;
+ UINT8 WdtTimeout;
+
+ UINT8 Index;
+ UINTN DataSize;
+ EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1];
+ EFI_BOOT_MODE BootMode;
+ UINT8 MorControl;
+ UINT64 PlatformMemorySize;
+ VOID *MemorySavedData;
+ VOID *NullSpdPtr;
+ UINT32 RpEnabledMask;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ MEMORY_CONFIGURATION *MemConfig;
+ SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
+ MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;
+ EFI_PEI_PPI_DESCRIPTOR *FspmArchConfigPpiDesc;
+ FSPM_ARCH_CONFIG_PPI *FspmArchConfigPpi;
+ HOST_BRIDGE_PREMEM_CONFIG *HostBridgePreMemConfig;
+ UINT16 AdjustedMmioSize;
+ UINT8 SaDisplayConfigTable[16];
+ EFI_BOOT_MODE SysBootMode;
+ UINT32 ProcessorTraceTotalMemSize;
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
+ UINT32 CapsuleSupportMemSize;
+
+ DEBUG ((DEBUG_INFO, "Update PeiSaPolicyUpdate Pre-Mem Start\n"));
+ ZeroMem ((VOID*) SaDisplayConfigTable, sizeof (SaDisplayConfigTable));
+ WdtTimeout = 0;
+ SysBootMode = 0;
+ RcompData = NULL;
+ PlatformMemorySize = 0;
+ RpEnabledMask = 0;
+ SiPreMemPolicyPpi = NULL;
+ MemConfig = NULL;
+ MemConfigNoCrc = NULL;
+
+
+ MiscPeiPreMemConfig = NULL;
+ HostBridgePreMemConfig = NULL;
+ FspmArchConfigPpi = NULL;
+
+ ProcessorTraceTotalMemSize = 0;
+ CapsuleSupportMemSize = 0;
+
+ AdjustedMmioSize = PcdGet16 (PcdSaMiscMmioSizeAdjustment);
+
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gHostBridgePeiPreMemConfigGuid, (VOID *) &HostBridgePreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigGuid, (VOID *) &MemConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);
+ ASSERT_EFI_ERROR(Status);
+
+ RcompData = MemConfigNoCrc->RcompData;
+
+ //
+ // Locate system configuration variable
+ //
+ Status = PeiServicesLocatePpi(
+ &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
+ 0, // INSTANCE
+ NULL, // EFI_PEI_PPI_DESCRIPTOR
+ (VOID **) &VariableServices // PPI
+ );
+ ASSERT_EFI_ERROR(Status);
+
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Initialize S3 Data variable (S3DataPtr)
+ //
+ VariableSize = 0;
+ MemorySavedData = NULL;
+ Status = VariableServices->GetVariable (
+ VariableServices,
+ L"MemoryConfig",
+ &gMemoryConfigVariableGuid,
+ NULL,
+ &VariableSize,
+ MemorySavedData
+ );
+ if (Status == EFI_BUFFER_TOO_SMALL) {
+ MemorySavedData = AllocateZeroPool (VariableSize);
+ ASSERT (MemorySavedData != NULL);
+
+ Status = VariableServices->GetVariable (
+ VariableServices,
+ L"MemoryConfig",
+ &gMemoryConfigVariableGuid,
+ NULL,
+ &VariableSize,
+ MemorySavedData
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Fail to retrieve Variable: MemoryConfig, Status = %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+ FspmArchConfigPpi = (FSPM_ARCH_CONFIG_PPI *) AllocateZeroPool (sizeof (FSPM_ARCH_CONFIG_PPI));
+ if (FspmArchConfigPpi == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+ FspmArchConfigPpi->Revision = 1;
+ FspmArchConfigPpi->NvsBufferPtr = MemorySavedData;
+ MiscPeiPreMemConfig->S3DataPtr = MemorySavedData;
+
+ FspmArchConfigPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+ if (FspmArchConfigPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+ FspmArchConfigPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ FspmArchConfigPpiDesc->Guid = &gFspmArchConfigPpiGuid;
+ FspmArchConfigPpiDesc->Ppi = FspmArchConfigPpi;
+
+ //
+ // Install FSP-M Arch Config PPI
+ //
+ Status = PeiServicesInstallPpi (FspmArchConfigPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+
+ VariableSize = sizeof (MorControl);
+ Status = VariableServices->GetVariable(
+ VariableServices,
+ MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME,
+ &gEfiMemoryOverwriteControlDataGuid,
+ NULL,
+ &VariableSize,
+ &MorControl
+ );
+ if (EFI_ERROR (Status)) {
+ MorControl = 0;
+ }
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.UserBd, MiscPeiPreMemConfig->UserBd, 0); // It's a CRB mobile board by default (btCRBMB)
+
+ MiscPeiPreMemConfig->TxtImplemented = 0;
+
+ if (PcdGet32 (PcdMrcRcompTarget)) {
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.RcompTarget, (VOID *)RcompData->RcompTarget, (VOID *)(UINTN)PcdGet32 (PcdMrcRcompTarget), sizeof (UINT16) * MRC_MAX_RCOMP_TARGETS);
+ }
+
+ if (PcdGetBool (PcdMrcDqPinsInterleavedControl)) {
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.DqPinsInterleaved, MemConfig->DqPinsInterleaved, PcdGetBool (PcdMrcDqPinsInterleaved));
+ }
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[0], MiscPeiPreMemConfig->SpdAddressTable[0], PcdGet8 (PcdMrcSpdAddressTable0));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[1], MiscPeiPreMemConfig->SpdAddressTable[1], PcdGet8 (PcdMrcSpdAddressTable1));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[2], MiscPeiPreMemConfig->SpdAddressTable[2], PcdGet8 (PcdMrcSpdAddressTable2));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[3], MiscPeiPreMemConfig->SpdAddressTable[3], PcdGet8 (PcdMrcSpdAddressTable3));
+ if (PcdGet8 (PcdMrcLp5CccConfig)) {
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.Lp5CccConfig, MemConfig->Lp5CccConfig, PcdGet8 (PcdMrcLp5CccConfig));
+ }
+
+
+ NullSpdPtr = AllocateZeroPool (SPD_DATA_SIZE);
+ ASSERT (NullSpdPtr != NULL);
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[4], MiscPeiPreMemConfig->SpdAddressTable[4], PcdGet8 (PcdMrcSpdAddressTable4));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[5], MiscPeiPreMemConfig->SpdAddressTable[5], PcdGet8 (PcdMrcSpdAddressTable5));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[6], MiscPeiPreMemConfig->SpdAddressTable[6], PcdGet8 (PcdMrcSpdAddressTable6));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[7], MiscPeiPreMemConfig->SpdAddressTable[7], PcdGet8 (PcdMrcSpdAddressTable7));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[8], MiscPeiPreMemConfig->SpdAddressTable[8], PcdGet8 (PcdMrcSpdAddressTable8));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[9], MiscPeiPreMemConfig->SpdAddressTable[9], PcdGet8 (PcdMrcSpdAddressTable9));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[10], MiscPeiPreMemConfig->SpdAddressTable[10], PcdGet8 (PcdMrcSpdAddressTable10));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[11], MiscPeiPreMemConfig->SpdAddressTable[11], PcdGet8 (PcdMrcSpdAddressTable11));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[12], MiscPeiPreMemConfig->SpdAddressTable[12], PcdGet8 (PcdMrcSpdAddressTable12));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[13], MiscPeiPreMemConfig->SpdAddressTable[13], PcdGet8 (PcdMrcSpdAddressTable13));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[14], MiscPeiPreMemConfig->SpdAddressTable[14], PcdGet8 (PcdMrcSpdAddressTable14));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[15], MiscPeiPreMemConfig->SpdAddressTable[15], PcdGet8 (PcdMrcSpdAddressTable15));
+ if (PcdGet32 (PcdMrcRcompResistor)) {
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.RcompResistor, RcompData->RcompResistor, (UINT8) PcdGet32 (PcdMrcRcompResistor));
+ }
+ if (PcdGet32 (PcdMrcDqsMapCpu2Dram)) {
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.DqsMapCpu2DramMc0Ch0, (VOID *)MemConfigNoCrc->DqDqsMap->DqsMapCpu2Dram, (VOID *)(UINTN)PcdGet32 (PcdMrcDqsMapCpu2Dram), sizeof (UINT8) * MEM_CFG_MAX_CONTROLLERS * MEM_CFG_MAX_CHANNELS * MEM_CFG_NUM_BYTES_MAPPED);
+ }
+ if (PcdGet32 (PcdMrcDqMapCpu2Dram)) {
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.DqMapCpu2DramMc0Ch0, (VOID *)MemConfigNoCrc->DqDqsMap->DqMapCpu2Dram, (VOID *)(UINTN)PcdGet32 (PcdMrcDqMapCpu2Dram), sizeof (UINT8) * MEM_CFG_MAX_CONTROLLERS * MEM_CFG_MAX_CHANNELS * MEM_CFG_NUM_BYTES_MAPPED * 8);
+ }
+ if (PcdGetBool (PcdSpdPresent)) {
+ // Clear SPD data so it can be filled in by the MRC init code
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr000, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][0][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr010, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][1][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr020, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][2][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr030, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][3][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr100, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][0][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr110, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][1][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr120, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][2][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr130, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][3][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ } else {
+ if (PcdGet32 (PcdMrcSpdData)) {
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr000, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr010, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr020, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][2][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr030, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][3][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr100, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr110, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr120, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][2][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr130, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][3][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ }
+ }
+
+ HostBridgePreMemConfig->MchBar = (UINTN) PcdGet64 (PcdMchBaseAddress);
+ HostBridgePreMemConfig->DmiBar = (UINTN) PcdGet64 (PcdDmiBaseAddress);
+ HostBridgePreMemConfig->EpBar = (UINTN) PcdGet64 (PcdEpBaseAddress);
+ HostBridgePreMemConfig->EdramBar = (UINTN) PcdGet64 (PcdEdramBaseAddress);
+ MiscPeiPreMemConfig->SmbusBar = (UINTN) PcdGet16 (PcdSmbusBaseAddress);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.TsegSize, MiscPeiPreMemConfig->TsegSize, PcdGet32 (PcdTsegSize));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.UserBd, MiscPeiPreMemConfig->UserBd, PcdGet8 (PcdSaMiscUserBd));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.DisableMrcRetrainingOnRtcPowerLoss,MiscPeiPreMemConfig->DisableMrcRetrainingOnRtcPowerLoss, PcdGet8(PcdSaMiscDisableMrcRetrainingOnRtcPowerLoss));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.MmioSizeAdjustment, HostBridgePreMemConfig->MmioSizeAdjustment, PcdGet16 (PcdSaMiscMmioSizeAdjustment));
+ //
+ // Display DDI Initialization ( default Native GPIO as per board during AUTO case)
+ //
+ CopyMem (SaDisplayConfigTable, (VOID *) (UINTN) PcdGet32 (PcdSaDisplayConfigTable), (UINTN)PcdGet16 (PcdSaDisplayConfigTableSize));
+
+ gWdtPei = NULL;
+ Status = PeiServicesLocatePpi(
+ &gWdtPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &gWdtPei
+ );
+ if (gWdtPei != NULL) {
+ WdtTimeout = gWdtPei->CheckStatus();
+ } else {
+ WdtTimeout = FALSE;
+ }
+
+ if ((WdtTimeout == FALSE)) {
+ //
+ // If USER custom profile is selected, we will start the WDT.
+ //
+ if (gWdtPei != NULL) {
+ Status = gWdtPei->ReloadAndStart(WDT_TIMEOUT);
+ }
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.VddVoltage, MemConfig->VddVoltage, 0); // Use platform default as the safe value.
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.VddqVoltage, MemConfig->VddqVoltage, 0); // Use platform default as the safe value.
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.VppVoltage, MemConfig->VppVoltage, 0); // Use platform default as the safe value.
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.Ratio, MemConfig->Ratio, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tCL, MemConfig->tCL, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tCWL, MemConfig->tCWL, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tFAW, MemConfig->tFAW, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRAS, MemConfig->tRAS, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRCDtRP, MemConfig->tRCDtRP, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tREFI, MemConfig->tREFI, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRFC, MemConfig->tRFC, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRRD, MemConfig->tRRD, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRTP, MemConfig->tRTP, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tWR, MemConfig->tWR, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tWTR, MemConfig->tWTR, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.NModeSupport, MemConfig->NModeSupport, 0);
+ }
+
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.CmdMirror, MemConfig->CmdMirror, PcdGet8 (PcdMrcCmdMirror)); // BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
+
+ // FirstDimmBitMask defines which DIMM should be populated first on a 2DPC board
+
+ COMPARE_AND_UPDATE_POLICY(((FSPM_UPD *)FspmUpd)->FspmConfig.FirstDimmBitMask, MemConfig->FirstDimmBitMask, PcdGet8(PcdSaMiscFirstDimmBitMask));
+ COMPARE_AND_UPDATE_POLICY(((FSPM_UPD *)FspmUpd)->FspmConfig.FirstDimmBitMaskEcc, MemConfig->FirstDimmBitMaskEcc, PcdGet8(PcdSaMiscFirstDimmBitMaskEcc));
+
+ //
+ // Update CleanMemory variable from Memory overwrite request value. Ignore if we are performing capsule update.
+ //
+ if ((BootMode != BOOT_ON_FLASH_UPDATE) && (BootMode != BOOT_ON_S3_RESUME)) {
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.CleanMemory, MemConfigNoCrc->CleanMemory, (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK));
+ }
+
+ DataSize = sizeof (MemoryData);
+ Status = VariableServices->GetVariable (
+ VariableServices,
+ EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
+ &gEfiMemoryTypeInformationGuid,
+ NULL,
+ &DataSize,
+ &MemoryData
+ );
+ ///
+ /// Accumulate maximum amount of memory needed
+ ///
+ PlatformMemorySize = MemConfigNoCrc->PlatformMemorySize;
+ AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, &Ebx.Uint32, NULL, NULL);
+
+ if (EFI_ERROR (Status)) {
+ ///
+ /// Use default value to avoid memory fragment.
+ /// OS boot/installation fails if there is not enough continuous memory available
+ ///
+ PlatformMemorySize = PEI_MIN_MEMORY_SIZE + ProcessorTraceTotalMemSize + CapsuleSupportMemSize;
+ DataSize = sizeof (mDefaultMemoryTypeInformation);
+ CopyMem (MemoryData, mDefaultMemoryTypeInformation, DataSize);
+ } else {
+ ///
+ /// Start with at least PEI_MIN_MEMORY_SIZE of memory for the DXE Core and the DXE Stack
+ ///
+ PlatformMemorySize = PEI_MIN_MEMORY_SIZE + ProcessorTraceTotalMemSize + CapsuleSupportMemSize;
+ }
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PlatformMemorySize, MemConfigNoCrc->PlatformMemorySize, PlatformMemorySize);
+
+ if (BootMode != BOOT_IN_RECOVERY_MODE) {
+ for (Index = 0; Index < DataSize / sizeof (EFI_MEMORY_TYPE_INFORMATION); Index++) {
+ PlatformMemorySize += MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE;
+ }
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PlatformMemorySize, MemConfigNoCrc->PlatformMemorySize, PlatformMemorySize);
+
+ ///
+ /// Build the GUID'd HOB for DXE
+ ///
+ BuildGuidDataHob (
+ &gEfiMemoryTypeInformationGuid,
+ MemoryData,
+ DataSize
+ );
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
new file mode 100644
index 0000000000..c2bdd599a8
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
@@ -0,0 +1,65 @@
+## @file
+# Provide Silicon policy update functionality.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SiliconPolicyUpdateLib
+ FILE_GUID = 34435831-33D7-4742-992F-3A3C7B860BC5
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconPolicyUpdateLib
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+################################################################################
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
+################################################################################
+
+[Sources]
+ PeiSiliconPolicyUpdatePreMem.c
+ PeiSiliconPolicyUpdatePostMem.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[LibraryClasses.IA32]
+ BaseMemoryLib
+ BaseLib
+ DebugLib
+ PeiServicesTablePointerLib
+ PeiServicesLib
+ PcdLib
+ PeiPolicyUpdateLib
+
+[FixedPcd]
+
+[Ppis]
+
+[Guids]
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c
new file mode 100644
index 0000000000..181b491c4c
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c
@@ -0,0 +1,39 @@
+/** @file
+ This file is SampleCode for Intel PEI Platform Policy initialization in post-memory.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+
+VOID
+EFIAPI
+SiliconPolicyUpdatePostMemFirmwareConfig (
+ VOID
+ )
+{
+ //
+ // Update and override all platform related and customized settings below.
+ //
+ UpdatePeiPchPolicy ();
+ UpdatePeiSaPolicy ();
+ UpdatePeiCpuPolicy ();
+}
+
+VOID *
+EFIAPI
+SiliconPolicyUpdatePostMem (
+ IN OUT VOID *Policy
+ )
+{
+ Policy = NULL;
+
+ SiliconPolicyUpdatePostMemFirmwareConfig ();
+
+ return Policy;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..42e6ac34c2
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c
@@ -0,0 +1,37 @@
+/** @file
+ This file is SampleCode for Intel PEI Platform Policy initialization in pre-memory.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+
+VOID
+EFIAPI
+SiliconPolicyUpdatePreMemFirmwareConfig (
+ VOID
+ )
+{
+ UpdatePeiPchPolicyPreMem ();
+ UpdatePeiSaPolicyPreMem ();
+ UpdatePeiCpuPolicyPreMem ();
+}
+
+
+VOID *
+EFIAPI
+SiliconPolicyUpdatePreMem (
+ IN OUT VOID *Policy
+ )
+{
+ Policy = NULL;
+
+ SiliconPolicyUpdatePreMemFirmwareConfig ();
+
+ return Policy;
+}
--
2.36.1.windows.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* [edk2-devel] [PATCH v2 6/6] AlderlakeOpenBoardPkg: Add Library Instances
2023-08-01 22:17 [edk2-devel] [PATCH v2 1/6] AlderlakeOpenBoardPkg: Add package and headers Saloni Kasbekar
` (3 preceding siblings ...)
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module Saloni Kasbekar
@ 2023-08-01 22:17 ` Saloni Kasbekar
2023-08-02 20:44 ` Chaganty, Rangasai V
2023-08-04 0:48 ` Chuang, Rosen
2023-08-02 17:25 ` [edk2-devel] [PATCH v2 1/6] AlderlakeOpenBoardPkg: Add package and headers Chaganty, Rangasai V
2023-08-04 0:40 ` Chuang, Rosen
6 siblings, 2 replies; 18+ messages in thread
From: Saloni Kasbekar @ 2023-08-01 22:17 UTC (permalink / raw)
To: devel
Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Isaac Oram,
Rosen Chuang
Adds the following libraries
- BasePlatformHookLib
- PeiBoardConfigLib
- PeiGetFvInfoLib
- SmmSpiFlashCommonLib
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../BasePlatformHookLib/BasePlatformHookLib.c | 38 ++++
.../BasePlatformHookLib.inf | 44 ++++
.../PeiBoardConfigLib/PeiBoardConfigLib.c | 136 +++++++++++
.../PeiBoardConfigLib/PeiBoardConfigLib.inf | 56 +++++
.../Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c | 89 ++++++++
.../PeiGetFvInfoLib/PeiGetFvInfoLib.inf | 34 +++
.../SmmSpiFlashCommonLib.inf | 49 ++++
.../SmmSpiFlashCommonLib/SpiFlashCommon.c | 215 ++++++++++++++++++
.../SpiFlashCommonSmmLib.c | 60 +++++
9 files changed, 721 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
new file mode 100644
index 0000000000..cccb1e18cc
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
@@ -0,0 +1,38 @@
+/** @file
+ Platform Hook Library instances
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi/UefiBaseType.h>
+#include <Library/PchCycleDecodingLib.h>
+
+
+/**
+ Performs platform specific initialization required for the CPU to access
+ the hardware associated with a SerialPortLib instance. This function does
+ not initialize the serial port hardware itself. Instead, it initializes
+ hardware devices that are required for the CPU to access the serial port
+ hardware. This function may be called more than once.
+
+ @retval RETURN_SUCCESS The platform specific initialization succeeded.
+ @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.
+
+**/
+RETURN_STATUS
+EFIAPI
+PlatformHookSerialPortInitialize (
+ VOID
+ )
+{
+
+ //
+ // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h.
+ //
+ PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));
+ PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));
+
+ return RETURN_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf
new file mode 100644
index 0000000000..b77724d5ab
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf
@@ -0,0 +1,44 @@
+### @file
+# Platform Hook Library instance for Alderlake Mobile/Desktop CRB.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BasePlatformHookLib
+ FILE_GUID = E22ADCC6-ED90-4A90-9837-C8E7FF9E963D
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = PlatformHookLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciSegmentLib
+ PciLib
+ PchCycleDecodingLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+
+[FixedPcd]
+ gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES
+
+[Sources]
+ BasePlatformHookLib.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c
new file mode 100644
index 0000000000..a9674bdd22
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c
@@ -0,0 +1,136 @@
+/** @file
+ Implementation of PeiBoardConfigLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PostCodeLib.h>
+#include <Library/TimerLib.h>
+#include <Library/GpioLib.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PmcLib.h>
+#include <Library/BoardConfigLib.h>
+
+
+
+VOID
+EFIAPI
+InternalUpdateRvpBoardConfig (
+ IN OUT UINT16 BoardId
+ )
+{
+ //
+ // Update Board Type/Platform Type/Platform Flavor
+ //
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ if(PcdSet64S (PcdAcpiDefaultOemTableId, ACPI_OEM_TABLE_ID_ADL_P_M) != EFI_SUCCESS)
+ {
+ DEBUG ((DEBUG_INFO, "Set PcdAcpiDefaultOemTableId error!!!\n"));
+ }
+ break;
+ }
+ DEBUG ((DEBUG_INFO, "PcdAcpiDefaultOemTableId is 0x%llX\n", PcdGet64 (PcdAcpiDefaultOemTableId)));
+}
+
+/**
+ Procedure to detect current board HW configuration.
+
+**/
+VOID
+GetBoardConfig (
+ VOID
+ )
+{
+ UINT16 BoardId;
+
+ //
+ // Get Platform Info and fill the PCD
+ //
+ BoardId = BoardIdAdlPDdr5Rvp;
+ PcdSet16S (PcdBoardId, BoardId);
+ //
+ // update RVP board config
+ //
+ InternalUpdateRvpBoardConfig (BoardId);
+
+ DEBUG ((DEBUG_INFO, "Platform Information:\n"));
+ DEBUG ((DEBUG_INFO, "BoardID: 0x%x\n", BoardId));
+
+}
+
+/**
+ Count the number of GPIO settings in the Table.
+
+ @param[in] GpioTable The pointer of GPIO config table
+ @param[out] GpioCount The number of GPIO config entries
+**/
+VOID
+GetGpioTableSize (
+ GPIO_INIT_CONFIG *GpioTable,
+ OUT UINT16 *GpioCount
+ )
+{
+ *GpioCount = 0;
+ if(GpioTable != NULL) {
+ while (GpioTable[*GpioCount].GpioPad != 0 && *GpioCount < MAX_GPIO_PINS) {
+ DEBUG ((DEBUG_INFO, "GpioTable[%d]->GpioPad = %x \n", *GpioCount, GpioTable[*GpioCount].GpioPad));
+ (*GpioCount) ++;
+ }
+ } else {
+ DEBUG ((DEBUG_INFO, "GpioTable is NULL\n"));
+ }
+ DEBUG ((DEBUG_INFO, "GetGpioTableSize() GpioCount = %d\n", *GpioCount));
+}
+
+/**
+ Configures GPIO
+
+ @param[in] GpioTable Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+**/
+STATIC
+VOID
+ConfigureGpio (
+ IN GPIO_INIT_CONFIG *GpioTable,
+ IN UINT16 GpioTableCount
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
+
+ Status = GpioConfigurePads (GpioTableCount, GpioTable);
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
+}
+
+/**
+ Configure GPIO Before Memory is initialized.
+
+ @param[in] GpioTable Pointer to Gpio table
+**/
+VOID
+GpioInit (
+ IN GPIO_INIT_CONFIG *GpioTable
+ )
+{
+ UINT16 GpioCount;
+
+ if (GpioTable != 0) {
+ GpioCount = 0;
+ GetGpioTableSize (GpioTable, &GpioCount);
+ if (GpioCount != 0) {
+ ConfigureGpio ((VOID *) GpioTable, (UINTN) GpioCount);
+ }
+ }
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf
new file mode 100644
index 0000000000..1f78e9a0ba
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf
@@ -0,0 +1,56 @@
+### @file
+# Component information file for BaseBoardConfigLib.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiBoardConfigLib
+ FILE_GUID = AA9812A8-1BA6-40AD-A846-50D0BC29C38C
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BoardConfigLib|PEIM
+
+[LibraryClasses]
+ DebugLib
+ PcdLib
+ PostCodeLib
+ TimerLib
+ PeiServicesLib
+ PmcLib
+ GpioLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ PeiBoardConfigLib.c
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardId ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardRev ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSpdPresent ## PRODUCES ## CONSUMES
+
+ # GPIO Group Tier
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2
+
+ gBoardModuleTokenSpaceGuid.PcdDisableVpdGpioTable
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem
+
+[Depex]
+ gEfiPeiReadOnlyVariable2PpiGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c
new file mode 100644
index 0000000000..d9ed1c5064
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c
@@ -0,0 +1,89 @@
+/** @file
+ Helper Library for PEI Graphics PEIM
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/PeiGetFvInfoLib.h>
+#include <Ppi/FirmwareVolume.h>
+#include <Pi/PiPeiCis.h>
+#include <Core/Pei/PeiMain.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/HobLib.h>
+
+/**
+ PeiGetSectionFromFv finds the file in FV and gets file Address and Size
+
+ @param[in] NameGuid - File GUID
+ @param[out] Address - Pointer to the File Address
+ @param[out] Size - Pointer to File Size
+
+ @retval EFI_SUCCESS Successfull in reading the section from FV
+ @retval EFI_NOT_FOUND File not found
+**/
+EFI_STATUS
+EFIAPI
+PeiGetSectionFromFv (
+ IN CONST EFI_GUID NameGuid,
+ OUT VOID **Address,
+ OUT UINT32 *Size
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_FIRMWARE_VOLUME_PPI *FvPpi;
+ EFI_FV_FILE_INFO FvFileInfo;
+ PEI_CORE_FV_HANDLE *CoreFvHandle;
+ EFI_PEI_FILE_HANDLE FileHandle;
+ EFI_GUID *FileGuid;
+ EFI_COMMON_SECTION_HEADER *Section;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ VOID *HobData;
+
+ Status = PeiServicesLocatePpi(
+ &gEfiFirmwareFileSystem2Guid,
+ 0,
+ NULL,
+ (VOID **)&FvPpi
+ );
+ ASSERT_EFI_ERROR(Status);
+
+ GuidHob = GetFirstGuidHob (&gPlatformInitFvLocationGuid);
+ if (GuidHob != NULL) {
+ HobData = *(VOID **)GET_GUID_HOB_DATA(GuidHob);
+ CoreFvHandle = (PEI_CORE_FV_HANDLE *) HobData;
+
+ //
+ // File typically resides in current FV or previous FV, so searching both of them.
+ //
+ Status = FvPpi->FindFileByName (FvPpi, &NameGuid, &CoreFvHandle->FvHandle, &FileHandle);
+
+ if (!EFI_ERROR(Status) && FileHandle != NULL) {
+
+ DEBUG((DEBUG_INFO, "Find SectionByType \n"));
+
+ Status = FvPpi->FindSectionByType(FvPpi, EFI_SECTION_RAW, FileHandle, (VOID **)&FileGuid);
+ if (!EFI_ERROR(Status)) {
+
+ DEBUG((DEBUG_INFO, "GetFileInfo \n"));
+
+ Status = FvPpi->GetFileInfo(FvPpi, FileHandle, &FvFileInfo);
+ Section = (EFI_COMMON_SECTION_HEADER *)FvFileInfo.Buffer;
+
+ if (IS_SECTION2(Section)) {
+ ASSERT(SECTION2_SIZE(Section) > 0x00FFFFFF);
+ *Size = SECTION2_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEADER2);
+ *Address = ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER2));
+ } else {
+ *Size = SECTION_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEADER);
+ *Address = ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER));
+ }
+ return EFI_SUCCESS;
+ }
+ }
+ } else {
+ DEBUG ((DEBUG_INFO, "Hob not found\n"));
+ }
+ return EFI_NOT_FOUND;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf
new file mode 100644
index 0000000000..1701fb15fe
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf
@@ -0,0 +1,34 @@
+### @file
+# Component description file for PeiGetFvInfo library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiGetFvInfoLib
+ FILE_GUID = C2584BE4-2CCD-418C-9205-A2031CE75861
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = PeiGetFvInfoLib
+
+[LibraryClasses]
+ BaseMemoryLib
+ BaseLib
+ DebugLib
+ DebugPrintErrorLevelLib
+ HobLib
+ PeiServicesLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ PeiGetFvInfoLib.c
+
+[Guids]
+ gPlatformInitFvLocationGuid ## CONSUMES
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
new file mode 100644
index 0000000000..cf6ca0d0ab
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
@@ -0,0 +1,49 @@
+### @file
+# SMM Library instance of Spi Flash Common Library Class
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SmmSpiFlashCommonLib
+ FILE_GUID = 9632D96E-E849-4217-9217-DC500B8AAE47
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_SMM_DRIVER
+ LIBRARY_CLASS = SpiFlashCommonLib|DXE_SMM_DRIVER
+ CONSTRUCTOR = SmmSpiFlashCommonLibConstructor
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[LibraryClasses]
+ IoLib
+ MemoryAllocationLib
+ BaseLib
+ UefiLib
+ SmmServicesTableLib
+ BaseMemoryLib
+ DebugLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+
+[Sources]
+ SpiFlashCommonSmmLib.c
+ SpiFlashCommon.c
+
+[Protocols]
+ gPchSmmSpiProtocolGuid ## CONSUMES
+
+[Depex.X64.DXE_SMM_DRIVER]
+ gPchSmmSpiProtocolGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
new file mode 100644
index 0000000000..3f7c52ac73
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
@@ -0,0 +1,215 @@
+/** @file
+ Wrap EFI_SPI_PROTOCOL to provide some library level interfaces
+ for module use.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+
+#include <Library/SpiFlashCommon.h>
+#include <Library/IoLib.h>
+
+PCH_SPI_PROTOCOL *mSpiProtocol;
+
+//
+// Variables for boottime and runtime usage.
+//
+UINTN mBiosAreaBaseAddress = 0;
+UINTN mBiosSize = 0;
+UINTN mBiosOffset = 0;
+
+/**
+ Enable block protection on the Serial Flash device.
+
+ @retval EFI_SUCCESS Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashLock (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+
+ return Status;
+}
+
+/**
+ Read NumBytes bytes of data from the address specified by
+ PAddress into Buffer.
+
+ @param[in] Address The starting physical address of the read.
+ @param[in,out] NumBytes On input, the number of bytes to read. On output, the number
+ of bytes actually read.
+ @param[out] Buffer The destination data buffer for the read.
+
+ @retval EFI_SUCCESS Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashRead (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ OUT UINT8 *Buffer
+ )
+{
+ ASSERT ((NumBytes != NULL) && (Buffer != NULL));
+ if ((NumBytes == NULL) || (Buffer == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // This function is implemented specifically for those platforms
+ // at which the SPI device is memory mapped for read. So this
+ // function just do a memory copy for Spi Flash Read.
+ //
+ CopyMem (Buffer, (VOID *) Address, *NumBytes);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Write NumBytes bytes of data from Buffer to the address specified by
+ PAddresss.
+
+ @param[in] Address The starting physical address of the write.
+ @param[in,out] NumBytes On input, the number of bytes to write. On output,
+ the actual number of bytes written.
+ @param[in] Buffer The source data buffer for the write.
+
+ @retval EFI_SUCCESS Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_BAD_BUFFER_SIZE DataSectionSize in BGUP header exceeds the
+ size ofBIOS Guard script buffer
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashWrite (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINTN Offset;
+ UINT32 Length;
+ UINT32 RemainingBytes;
+
+ ASSERT ((NumBytes != NULL) && (Buffer != NULL));
+ if ((NumBytes == NULL) || (Buffer == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ASSERT (Address >= mBiosAreaBaseAddress);
+ if (Address < mBiosAreaBaseAddress) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Offset = Address - mBiosAreaBaseAddress;
+
+ ASSERT ((*NumBytes + Offset) <= mBiosSize);
+ if ((*NumBytes + Offset) > mBiosSize) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = EFI_SUCCESS;
+ RemainingBytes = *NumBytes;
+
+ while (RemainingBytes > 0) {
+ if (RemainingBytes > SECTOR_SIZE_4KB) {
+ Length = SECTOR_SIZE_4KB;
+ } else {
+ Length = RemainingBytes;
+ }
+ Status = mSpiProtocol->FlashWrite (
+ mSpiProtocol,
+ FlashRegionBios,
+ (UINT32) Offset,
+ Length,
+ Buffer
+ );
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+ RemainingBytes -= Length;
+ Offset += Length;
+ Buffer += Length;
+ }
+
+ //
+ // Actual number of bytes written
+ //
+ *NumBytes -= RemainingBytes;
+
+ return Status;
+}
+
+/**
+ Erase the block starting at Address.
+
+ @param[in] Address The starting physical address of the block to be erased.
+ This library assume that caller garantee that the PAddress
+ is at the starting address of this block.
+ @param[in] NumBytes On input, the number of bytes of the logical block to be erased.
+ On output, the actual number of bytes erased.
+
+ @retval EFI_SUCCESS. Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashBlockErase (
+ IN UINTN Address,
+ IN UINTN *NumBytes
+ )
+{
+ EFI_STATUS Status;
+ UINTN Offset;
+ UINTN RemainingBytes;
+
+ ASSERT (NumBytes != NULL);
+ if (NumBytes == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ASSERT (Address >= mBiosAreaBaseAddress);
+ if (Address < mBiosAreaBaseAddress) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Offset = Address - mBiosAreaBaseAddress;
+
+ ASSERT ((*NumBytes % SECTOR_SIZE_4KB) == 0);
+ if ((*NumBytes % SECTOR_SIZE_4KB) != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ASSERT ((*NumBytes + Offset) <= mBiosSize);
+ if ((*NumBytes + Offset) > mBiosSize) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = EFI_SUCCESS;
+ RemainingBytes = *NumBytes;
+
+ Status = mSpiProtocol->FlashErase (
+ mSpiProtocol,
+ FlashRegionBios,
+ (UINT32) Offset,
+ (UINT32) RemainingBytes
+ );
+ return Status;
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
new file mode 100644
index 0000000000..897d85743a
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
@@ -0,0 +1,60 @@
+/** @file
+ SMM Library instance of SPI Flash Common Library Class
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+
+#include <Library/SpiFlashCommon.h>
+#include <Library/SmmServicesTableLib.h>
+
+extern PCH_SPI_PROTOCOL *mSpiProtocol;
+
+extern UINTN mBiosAreaBaseAddress;
+extern UINTN mBiosSize;
+extern UINTN mBiosOffset;
+
+/**
+ The library constructuor.
+
+ The function does the necessary initialization work for this library
+ instance.
+
+ @param[in] ImageHandle The firmware allocated handle for the UEFI image.
+ @param[in] SystemTable A pointer to the EFI system table.
+
+ @retval EFI_SUCCESS The function always return EFI_SUCCESS for now.
+ It will ASSERT on error for debug version.
+ @retval EFI_ERROR Please reference LocateProtocol for error code details.
+**/
+EFI_STATUS
+EFIAPI
+SmmSpiFlashCommonLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINT32 BaseAddr;
+ UINT32 RegionSize;
+
+ mBiosAreaBaseAddress = (UINTN) PcdGet32 (PcdBiosAreaBaseAddress);
+ mBiosSize = (UINTN) PcdGet32 (PcdBiosSize);
+
+ //
+ // Locate the SMM SPI protocol.
+ //
+ Status = gSmst->SmmLocateProtocol (
+ &gPchSmmSpiProtocolGuid,
+ NULL,
+ (VOID **) &mSpiProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ mSpiProtocol->GetRegionAddress (mSpiProtocol, FlashRegionBios, &BaseAddr, &RegionSize);
+ mBiosOffset = BaseAddr;
+
+ return Status;
+}
--
2.36.1.windows.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [edk2-devel] [PATCH v2 1/6] AlderlakeOpenBoardPkg: Add package and headers
2023-08-01 22:17 [edk2-devel] [PATCH v2 1/6] AlderlakeOpenBoardPkg: Add package and headers Saloni Kasbekar
` (4 preceding siblings ...)
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 6/6] AlderlakeOpenBoardPkg: Add Library Instances Saloni Kasbekar
@ 2023-08-02 17:25 ` Chaganty, Rangasai V
2023-08-04 0:40 ` Chuang, Rosen
6 siblings, 0 replies; 18+ messages in thread
From: Chaganty, Rangasai V @ 2023-08-02 17:25 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Oram, Isaac W, Chuang, Rosen
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Tuesday, August 01, 2023 3:18 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 1/6] AlderlakeOpenBoardPkg: Add package and headers
Create the AlderlakeOpenBoardPkg to provide board support code. The package supports Alderlake Mobile board with LPDDR4. The package serves as a support package in the EDK II Minimum Platform design.
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Include/Library/BoardConfigLib.h | 59 ++++
.../Include/Library/PeiGetFvInfoLib.h | 29 ++
.../Include/Library/SpiFlashCommon.h | 99 ++++++
.../Include/PlatformBoardConfig.h | 93 ++++++
.../Include/PlatformBoardId.h | 21 ++
.../Include/PlatformGpioConfig.h | 18 +
.../Include/PlatformPostCode.h | 39 +++
.../Include/PolicyUpdateMacro.h | 48 +++
.../AlderlakeOpenBoardPkg/OpenBoardPkg.dec | 307 ++++++++++++++++++
9 files changed, 713 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h
new file mode 100644
index 0000000000..3a07563c5d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLi
+++ b.h
@@ -0,0 +1,59 @@
+/** @file
+ Function prototype of BoardConfigLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _BOARD_CONFIG_LIB_H_
+#define _BOARD_CONFIG_LIB_H_
+
+#include <Library/GpioLib.h>
+#include <PlatformBoardConfig.h>
+
+#define SIZE_OF_FIELD(TYPE, Field) (sizeof (((TYPE *)0)->Field))
+
+#define SIZE_OF_TABLE(TABLE, TYPE) (sizeof (TABLE) / sizeof (TYPE))
+
+#define BOARD_CONFIG PLATFORM_INFO
+
+#define PRE_MEM 0
+#define POST_MEM 1
+#define EARLY_PRE_MEM 2
+
+/**
+ Procedure to detect current board HW configuration.
+
+**/
+VOID
+EFIAPI
+GetBoardConfig (
+ VOID
+ );
+
+
+/**
+ Count the number of GPIO settings in the Table.
+
+ @param[in] GpioTable The pointer of GPIO config table
+ @param[out] GpioCount The number of GPIO config entries
+**/
+VOID
+GetGpioTableSize (
+ GPIO_INIT_CONFIG *GpioTable,
+ OUT UINT16 *GpioCount
+ );
+
+
+/**
+ Configure GPIO pads in PEI phase.
+
+ @param[in] GpioTable Pointer to Gpio table **/ VOID GpioInit (
+ IN GPIO_INIT_CONFIG *GpioTable
+ );
+
+#endif // _BOARD_CONFIG_LIB_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h
new file mode 100644
index 0000000000..f2e5a77787
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoL
+++ ib.h
@@ -0,0 +1,29 @@
+/** @file
+ Header file for PeiGetFvInfoLib..
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PEI_GET_FV_INFO_LIB_H_
+#define _PEI_GET_FV_INFO_LIB_H_
+
+/**
+ PeiGetSectionFromFv finds the file in FV and gets file Address and
+Size
+
+ @param[in] NameGuid - File GUID
+ @param[out] Address - Pointer to the File Address
+ @param[out] Size - Pointer to File Size
+
+ @retval EFI_SUCCESS Successfull in reading the section from FV
+**/
+EFI_STATUS
+EFIAPI
+PeiGetSectionFromFv (
+ IN CONST EFI_GUID NameGuid,
+ OUT VOID **Address,
+ OUT UINT32 *Size
+ );
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h
new file mode 100644
index 0000000000..76ba3a8094
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommo
+++ n.h
@@ -0,0 +1,99 @@
+/** @file
+ The header file includes the common header files, defines
+ internal structure and functions used by SpiFlashCommonLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SPI_FLASH_COMMON_H__
+#define __SPI_FLASH_COMMON_H__
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h> #include
+<Library/UefiDriverEntryPoint.h> #include
+<Library/UefiBootServicesTableLib.h>
+#include <Protocol/Spi.h>
+
+#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size
+/**
+ Enable block protection on the Serial Flash device.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashLock (
+ VOID
+ );
+
+/**
+ Read NumBytes bytes of data from the address specified by
+ PAddress into Buffer.
+
+ @param[in] Address The starting physical address of the read.
+ @param[in,out] NumBytes On input, the number of bytes to read. On output, the number
+ of bytes actually read.
+ @param[out] Buffer The destination data buffer for the read.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashRead (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Write NumBytes bytes of data from Buffer to the address specified by
+ PAddresss.
+
+ @param[in] Address The starting physical address of the write.
+ @param[in,out] NumBytes On input, the number of bytes to write. On output,
+ the actual number of bytes written.
+ @param[in] Buffer The source data buffer for the write.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashWrite (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Erase the block starting at Address.
+
+ @param[in] Address The starting physical address of the block to be erased.
+ This library assume that caller garantee that the PAddress
+ is at the starting address of this block.
+ @param[in] NumBytes On input, the number of bytes of the logical block to be erased.
+ On output, the actual number of bytes erased.
+
+ @retval EFI_SUCCESS. Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashBlockErase (
+ IN UINTN Address,
+ IN UINTN *NumBytes
+ );
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h
new file mode 100644
index 0000000000..f9ac991eb4
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h
@@ -0,0 +1,93 @@
+/** @file
+ Header file for Platform Boards Configurations.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PLATFORM_BOARD_CONFIG_H
+#define _PLATFORM_BOARD_CONFIG_H
+
+#include <ConfigBlock.h>
+#include <PchPolicyCommon.h>
+#include <MemoryConfig.h>
+#include <Library/GpioConfig.h>
+
+#define MAX_GPIO_PINS 130
+
+//
+// ACPI table information used to update tables thru PCD //
+#define ACPI_OEM_TABLE_ID_ADL_P_M 0x4D2D502D4C4441 //ADL-P-M
+
+#pragma pack(1)
+
+typedef struct {
+ UINT8 ClkReqNumber : 4;
+ UINT8 ClkReqSupported : 1;
+ UINT8 DeviceResetPadActiveHigh : 1;
+ UINT32 DeviceResetPad;
+} ROOT_PORT_CLK_INFO;
+
+typedef struct {
+ UINT8 Section;
+ UINT8 Pin;
+} EXPANDER_GPIO_CONFIG;
+
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved[3]; // alignment for COMMON_GPIO_CONFIG
+ union {
+ UINT32 Pin;
+ EXPANDER_GPIO_CONFIG Expander;
+ } u;
+} BOARD_GPIO_CONFIG;
+
+// Do not change the encoding. It must correspond with PCH_PCIE_CLOCK_USAGE from PCH RC.
+#define NOT_USED 0xFF
+#define LAN_CLOCK 0x70
+#define PCIE_PEG 0x40
+#define PCIE_PCH 0x00
+
+typedef struct {
+ UINT32 ClockUsage;
+ UINT32 ClkReqSupported;
+} PCIE_CLOCK_CONFIG;
+
+typedef union {
+ UINT64 Blob;
+ BOARD_GPIO_CONFIG BoardGpioConfig;
+ ROOT_PORT_CLK_INFO Info;
+ PCIE_CLOCK_CONFIG PcieClock;
+} PCD64_BLOB;
+
+// Having Max CLK config to support both ADL P and ALD S #define
+PCH_MAX_PCIE_CLOCKS_SBC 18
+
+//seamless board configurations
+typedef struct {
+ UINT32 ClockUsage[PCH_MAX_PCIE_CLOCKS_SBC];
+} PCIE_CLOCKS_USAGE;
+
+#define SPD_DATA_SIZE 1024
+
+//SBC MRC DQS
+typedef struct {
+ UINT8 DqsMapCpu2Dram[8][2];
+} MRC_DQS;
+
+//SBC MRC DQ
+typedef struct {
+ UINT8 DqMapCpu2Dram[8][2][8];
+} MRC_DQ;
+
+//SBC SPD DATA
+typedef struct {
+ BOOLEAN OverrideSpd;
+ UINT8 SpdData[SPD_DATA_SIZE];
+} SPD_DATA;
+
+#pragma pack()
+
+#endif // _PLATFORM_BOARD_CONFIG_H
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h
new file mode 100644
index 0000000000..51b317ffec
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h
@@ -0,0 +1,21 @@
+/** @file
+Defines Platform BoardIds
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PLATFORM_BOARD_ID_H_
+#define _PLATFORM_BOARD_ID_H_
+
+//
+// Alderlake Sku IDs
+//
+#define SkuIdAdlPDdr5Rvp 0x000012
+#define AdlPSkuType 2
+
+// Alderlake P Board IDs
+#define BoardIdAdlPDdr5Rvp 0x12
+
+#endif // _PLATFORM_BOARD_ID_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h
new file mode 100644
index 0000000000..d8a4c2ab77
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h
@@ -0,0 +1,18 @@
+/** @file
+Defines Platform GPIO Configuration Arrary
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/GpioLib.h>
+
+#ifndef _PLATFORM_GPIO_CONFIG_H_
+#define _PLATFORM_GPIO_CONFIG_H_
+
+typedef struct {
+ GPIO_INIT_CONFIG GpioConfig[0];
+} GPIO_INIT_CONFIG_ARRAY;
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h
new file mode 100644
index 0000000000..4dbdd8e391
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h
@@ -0,0 +1,39 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PLATFORMPOSTCODE_H_
+#define _PLATFORMPOSTCODE_H_
+
+//
+// GENERAL USAGE GUIDELINES
+//
+
+/**
+[definition]
+PostCode = XYZZ
+X - "D"=premem, "9"=postmem, "8"=SMM, "7"=DXE Y - "6"=platform driver,
+"5"=board driver ZZ - "00"=entry, "7F"=exit
+ - 1 - board init premem: entry/exit (0xD500/0xD57F)
+ - 2 - platform init premem: entry/exit (0xD600/0xD67F)
+ - 3 - board init postmem: entry/exit (0x9500/0x957F)
+ - 4 - platform init postmem: entry/exit (0x9600/0x967F)
+ - 5 - board init DXE: entry/exit (0x7500/0x757F)
+ - 6 - platform init DXE: entry/exit (0x7600/0x767F)
+ - 7 - platform SMM init: entry/exit (0x8600/0x867F)
+ - 8 - BIOS S3 entry (0xB503) means BioS PC 03, to differentiate with
+ACPI _PTS PC
+ - 9 - BIOS S4 entry (0xB504) means BioS PC 04, to differentiate with
+ACPI _PTS PC
+ - 10 - BIOS S5 entry (0B505) means BioS PC 05, to differentiate with
+ACPI _PTS PC */
+
+#define PLATFORM_INIT_PREMEM_ENTRY 0xD600
+#define PLATFORM_INIT_PREMEM_EXIT 0xD67F
+#define PLATFORM_INIT_POSTMEM_ENTRY 0x9600 #define
+PLATFORM_INIT_POSTMEM_EXIT 0x967F
+#define PLATFORM_SMM_INIT_ENTRY 0x8600
+#define PLATFORM_SMM_INIT_EXIT 0x867F
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h
new file mode 100644
index 0000000000..c9ace9d910
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h
@@ -0,0 +1,48 @@
+/** @file
+ Macros for platform to update different types of policy.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _POLICY_UPDATE_MACRO_H_
+#define _POLICY_UPDATE_MACRO_H_
+
+#ifdef UPDATE_POLICY
+#undef UPDATE_POLICY
+#endif
+
+#ifdef COPY_POLICY
+#undef COPY_POLICY
+#endif
+
+#ifdef GET_POLICY
+#undef GET_POLICY
+#endif
+
+#ifdef AND_POLICY
+#undef AND_POLICY
+#endif
+
+#ifdef OR_POLICY
+#undef OR_POLICY
+#endif
+
+#define UPDATE_POLICY(UpdField, ConfigField, Value) ConfigField =
+Value; #define COPY_POLICY(UpdField, ConfigField, Value, Size) CopyMem
+(ConfigField, Value, Size); #define GET_POLICY(UpdField, ConfigField,
+Value) Value = ConfigField; #define AND_POLICY(UpdField, ConfigField,
+Value) ConfigField &= Value; #define OR_POLICY(UpdField, ConfigField,
+Value) ConfigField |= Value; // // Compare Policy Default and Setup
+Default when FirstBoot and RvpSupport //
+
+#define COMPARE_AND_UPDATE_POLICY(UpdField, ConfigField, Value) {\
+ UPDATE_POLICY(UpdField, ConfigField, Value);\ } #define
+COMPARE_UPDATE_POLICY_ARRAY(UpdField, ConfigField, Value, ArrayIndex)
+{\
+ UPDATE_POLICY(UpdField, ConfigField, Value);\ }
+
+#endif //_POLICY_UPDATE_MACRO_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec
new file mode 100644
index 0000000000..0f0ed386f6
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec
@@ -0,0 +1,307 @@
+## @file
+#
+# The DEC files are used by the utilities that parse DSC and # INF
+files to generate AutoGen.c and AutoGen.h files # for the build
+infrastructure.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+DEC_SPECIFICATION = 0x00010017
+PACKAGE_NAME = OpenBoardPkg
+PACKAGE_VERSION = 0.1
+PACKAGE_GUID = A840FA72-FBF7-4357-B301-DAE2233F14AB
+
+[Includes]
+Include
+
+[Guids]
+ gBoardModuleTokenSpaceGuid = {0x72d1fff7, 0xa42a, 0x4219, {0xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}}
+ gPlatformModuleTokenSpaceGuid = {0x69d13bf0, 0xaf91, 0x4d96, {0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}}
+ gPlatformInitFvLocationGuid = {0xa564010a, 0x1d90, 0x4b1c, {0x8d, 0x10, 0xcb, 0xba, 0xff, 0xb2, 0x55, 0x42}}
+ gVpdFfsGuid = {0x338FA35A, 0xCA4A, 0x4DBC, {0xA6, 0xF4, 0x9B, 0xD1, 0x59, 0x3B, 0x61, 0xBC}}
+ gMemoryConfigVariableGuid = {0xc94f8c4d, 0x9b9a, 0x45fe, {0x8a, 0x55, 0x23, 0x8b, 0x67, 0x30, 0x26, 0x43}}
+
+#
+# FvImage File
+#
+ gFvAdvancedFileGuid = {0xAD198BA5, 0xC330, 0x41CD, {0xB0, 0x97, 0x16, 0x48, 0x83, 0x28, 0xB7, 0x98}}
+ gFvOsBootFileGuid = {0xB9020753, 0x84A8, 0x4BB6, {0x94, 0x7C, 0xCE, 0x7D, 0x41, 0xF5, 0xCE, 0x39}}
+ gFvUefiBootFileGuid = {0x9E21FD93, 0x9C72, 0x4c15, {0x8C, 0x4B, 0xE7, 0x7F, 0x1D, 0xB2, 0xD7, 0x92}}
+ gTianoLogoGuid = {0x7BB28B99, 0x61BB, 0x11D5, {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}}
+
+ # gUefiShellFileGuid is FILE GUID for MinUefiShell.inf/UefiShell.inf/Shell.inf.
+ gUefiShellFileGuid = {0x7c04a583, 0x9e3e, 0x4f1c, {0xad, 0x65, 0xe0, 0x52, 0x68, 0xd0, 0xb4, 0xd1}}
+
+[Ppis]
+ gReadyForGopConfigPpiGuid = {0x5f252c18, 0x1781, 0x4290, {0xa7, 0xb6, 0xfd, 0x99, 0x63, 0x4c, 0x6a, 0x8a}}
+
+[PcdsFixedAtBuild, PcdsPatchableInModule] ## ##
+PcdSmbiosOemTypeFirmwareVersionInfo determines the SMBIOS OEM type
+(0x80 to 0xFF) defined in SMBIOS, ## values 0-0x7F will be treated as disable FVI reporting.
+## FVI structure uses it as SMBIOS OEM type to provide version information.
+##
+gPlatformModuleTokenSpaceGuid.PcdSmbiosOemTypeFirmwareVersionInfo|0xDD|
+UINT8|0x20000001
+
+[PcdsFixedAtBuild]
+ gBoardModuleTokenSpaceGuid.PcdDefaultBoardId|0|UINT16|0x10101009
+
+
+ gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x1000101
+ 0
+
+ gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|0x1000
+ 1011
+
+ ##
+ ## The Flash PCDs will be patched based on FDF definitions during build.
+ ## Set them to 0 here to prevent confusion.
+ ##
+
+
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase|0x00000000|U
+ INT32|0x20000040
+
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize|0x00000000|U
+ INT32|0x20000041
+
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset|0x00000000
+ |UINT32|0x20000042
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase|0x00000000|UINT32|0x
+ 2000004C
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize|0x00000000|UINT32|0x
+ 2000004D
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalOffset|0x00000000|UINT32|
+ 0x2000004E
+
+
+ gBoardModuleTokenSpaceGuid.PcdFlashObbSize|0x00000000|UINT32|0xF0000A5
+ 3
+
+ gBoardModuleTokenSpaceGuid.PcdFlashIbbOffset|0x00000000|UINT32|0xF0000
+ A58
+
+ gBoardModuleTokenSpaceGuid.PcdFlashIbbSize|0x00000000|UINT32|0xF0000A5
+ 9
+ gBoardModuleTokenSpaceGuid.PcdFlashFvRsvdOffset|0x00000000|UINT32|0x20
+ 000A5E
+ gBoardModuleTokenSpaceGuid.PcdFlashFvRsvdSize|0x00000000|UINT32|0x2000
+ 0A5F
+
+ gBoardModuleTokenSpaceGuid.PcdFlashIbbROffset|0x00000000|UINT32|0x2000
+ 0A61
+
+#(ACPI.inf)
+
+gPlatformModuleTokenSpaceGuid.PcdApicLocalAddress|0xFEE00000|UINT64|0x9
+000000B
+gPlatformModuleTokenSpaceGuid.PcdApicIoAddress|0xFEC00000|UINT64|0x9000
+000D
+ gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012
+
+gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013
+ gPlatformModuleTokenSpaceGuid.PcdApicIoIdPch|0x02|UINT8|0x9000001E
+
+#(BaseMmioInitLib.inf)
+gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress|0xFEDA0000|UINT64|0x900
+00003
+gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress|0xFEDA1000|UINT64|0x9000
+0005
+
+## This PCD specifies whether StatusCode is reported via SerialIoUart
+gPlatformModuleTokenSpaceGuid.PcdStatusCodeUseSerialIoUart|FALSE|BOOLEA
+N|0xFF000002
+
+## This flag is used to initialize debug output interface.
+# BIT0 - RAM debug interface.
+# BIT1 - UART debug interface.
+# BIT2 - USB debug interface.
+# BIT3 - USB3 debug interface.
+# BIT4 - Serial IO debug interface.
+# BIT5 - TraceHub debug interface.
+# BIT6 - Reserved.
+# BIT7 - CMOS control.
+gPlatformModuleTokenSpaceGuid.PcdStatusCodeFlags|0x82|UINT8|0xF0000111
+
+gPlatformModuleTokenSpaceGuid.PcdGttMmAddress|0xAF000000|UINT64|0x90000
+00F
+gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress|0xB0000000|UINT64|0x90000
+010
+
+gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress|0xFED80000|UINT64|0x9
+0000009
+
+gPlatformModuleTokenSpaceGuid.PcdLzmaEnable |FALSE|BOOLEAN|0xF000002B
+
+[PcdsDynamic]
+ # DRAM Configuration
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000174
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000175
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2Dram|0|UINT32|0x00000072
+
+gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2DramSize|0|UINT16|0x00000073
+
+ # SPD Address Table
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000199
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x0000019A
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x0000019B
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x0000019C
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable4|0|UINT8|0x0000019D
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable5|0|UINT8|0x0000019E
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable6|0|UINT8|0x0000019F
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable7|0|UINT8|0x000001A0
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable8|0|UINT8|0x000001A1
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable9|0|UINT8|0x000001A2
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable10|0|UINT8|0x000001A3
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable11|0|UINT8|0x000001A4
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable12|0|UINT8|0x000001A5
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable13|0|UINT8|0x000001A6
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable14|0|UINT8|0x000001A7
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable15|0|UINT8|0x000001A8
+
+ # Root Port Clock Info
+ gBoardModuleTokenSpaceGuid.PcdPcieClock0|0|UINT64|0x0000009E
+ gBoardModuleTokenSpaceGuid.PcdPcieClock1|0|UINT64|0x0000009F
+ gBoardModuleTokenSpaceGuid.PcdPcieClock2|0|UINT64|0x000000A0
+ gBoardModuleTokenSpaceGuid.PcdPcieClock3|0|UINT64|0x000000A1
+ gBoardModuleTokenSpaceGuid.PcdPcieClock4|0|UINT64|0x000000A2
+ gBoardModuleTokenSpaceGuid.PcdPcieClock5|0|UINT64|0x000000A3
+ gBoardModuleTokenSpaceGuid.PcdPcieClock6|0|UINT64|0x000000A4
+ gBoardModuleTokenSpaceGuid.PcdPcieClock7|0|UINT64|0x000000A5
+ gBoardModuleTokenSpaceGuid.PcdPcieClock8|0|UINT64|0x000000A6
+ gBoardModuleTokenSpaceGuid.PcdPcieClock9|0|UINT64|0x000000A7
+ gBoardModuleTokenSpaceGuid.PcdPcieClock10|0|UINT64|0x000000A8
+ gBoardModuleTokenSpaceGuid.PcdPcieClock11|0|UINT64|0x000000A9
+ gBoardModuleTokenSpaceGuid.PcdPcieClock12|0|UINT64|0x000000AA
+ gBoardModuleTokenSpaceGuid.PcdPcieClock13|0|UINT64|0x000000AB
+ gBoardModuleTokenSpaceGuid.PcdPcieClock14|0|UINT64|0x000000AC
+ gBoardModuleTokenSpaceGuid.PcdPcieClock15|0|UINT64|0x000000AD
+ gBoardModuleTokenSpaceGuid.PcdPcieClock16|0|UINT64|0x000000AE
+ gBoardModuleTokenSpaceGuid.PcdPcieClock17|0|UINT64|0x000000AF
+
+
+ # GPIO Group Tier
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0|0|UINT32|0x000000E9
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1|0|UINT32|0x000000EA
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2|0|UINT32|0x000000EB
+
+ # Display DDI
+
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable|0|UINT32|0x00100033
+
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize|0|UINT16|0x0010
+ 0034
+
+ # MISC
+ gBoardModuleTokenSpaceGuid.PcdStackBase|0x0|UINT32|0x40000A10
+ gBoardModuleTokenSpaceGuid.PcdStackSize|0x0|UINT32|0x40000A11
+
+ # SA Misc Configuration
+ gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066
+
+ gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|0x0000
+ 0067
+
+ gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMask|0|UINT8|0x0000A10
+ 3
+
+ gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMaskEcc|0|UINT8|0x0000
+ A104
+
+ gBoardModuleTokenSpaceGuid.PcdSaMiscDisableMrcRetrainingOnRtcPowerLoss
+ |0|UINT8|0x0000A105
+
+ # Board Information
+ gBoardModuleTokenSpaceGuid.PcdSpdPresent|FALSE|BOOLEAN|0x00101012
+ gBoardModuleTokenSpaceGuid.PcdBoardRev|0x0|UINT16|0x00101016
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId|0x0|UINT16|0x00101017
+ gBoardModuleTokenSpaceGuid.PcdBoardId|0|UINT16|0x00101018
+ gBoardModuleTokenSpaceGuid.PcdSkuType|0x0|UINT8|0x0010101F
+
+ # MRC Config
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x00000A68
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x00000A69
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x00000A6A
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x00000A6B
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x00000A6C
+
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0x00000A6
+ D
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALSE|BOOLEA
+ N|0x00000A6E
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLEAN|0x000
+ 00A6F
+ gBoardModuleTokenSpaceGuid.PcdMrcLp5CccConfig|0|UINT8|0x00000A73
+ gBoardModuleTokenSpaceGuid.PcdMrcCmdMirror|0|UINT8|0x00000A74
+ gBoardModuleTokenSpaceGuid.PcdRootPortIndex|0xFF|UINT8|0x00000A78
+
+ # Pch SerialIo I2c Pads Termination
+
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm|0x1|UINT8
+ |0x00000020
+
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm|0x1|UINT8
+ |0x00000021
+
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm|0x1|UINT8
+ |0x00000022
+
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm|0x1|UINT8
+ |0x00000023
+
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm|0x1|UINT8
+ |0x00000030
+
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm|0x1|UINT8
+ |0x00000031
+
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c6PadInternalTerm|0x1|UINT8
+ |0x00000032
+
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c7PadInternalTerm|0x1|UINT8
+ |0x00000033
+
+[PcdsDynamicEx]
+# Flag to Disable Vpd Gpio
+gBoardModuleTokenSpaceGuid.PcdDisableVpdGpioTable|FALSE|BOOLEAN|0x50000
+015
+# Pre-Mem GPIO table
+
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem|{0}|GPIO_INIT_CONFIG
+_ARRAY|0x50000017 {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioLib.h
+ PlatformGpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+
+gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|{0}|GPIO_INIT_CON
+FIG[]|0x50000018 {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioLib.h
+ Library/GpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# GPIO table
+
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTable|{0}|GPIO_INIT_CONFIG_ARRAY
+|0x50000019 {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioLib.h
+ PlatformGpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable|{0}|GPIO_INIT_CONFIG[]|
+0x5000001C {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# PCIE CLOCKS USAGE
+
+gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|{0}|PCIE_CLOCKS_USAGE|
+0x50000022 {
+ <HeaderFiles>
+ PlatformBoardConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+#SBC SPD DATA
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData|{0}|SPD_DATA|0x50000025 {
+ <HeaderFiles>
+ PlatformBoardConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# SBC MRC DQS MAPPING
+
+gBoardModuleTokenSpaceGuid.VpdPcdMrcDqsMapCpu2Dram|{0}|MRC_DQS|0x500000
+26 {
+ <HeaderFiles>
+ PlatformBoardConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# SBC MRC DQ MAPPING
+
+gBoardModuleTokenSpaceGuid.VpdPcdMrcDqMapCpu2Dram|{0}|MRC_DQ|0x50000027
+{
+ <HeaderFiles>
+ PlatformBoardConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# ACPI data
+ gBoardModuleTokenSpaceGuid.PcdBoardAcpiData|{0}|VOID*|0x5000001A
+
+# Early Pre-Mem GPIO table
+
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem|{0}|GPIO_INIT_C
+ONFIG_ARRAY|0x5000001B {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioLib.h
+ PlatformGpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderLakeOpenBoardPkg/OpenBoardPkg.dec
+}
+[PcdsDynamic, PcdsDynamicEx]
+
+[PcdsPatchableInModule]
+
+[PcdsFeatureFlag]
+ gBoardModuleTokenSpaceGuid.PcdIntelGopEnable |FALSE|BOOLEAN|0xF0000B54
--
2.36.1.windows.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [edk2-devel] [PATCH v2 2/6] AlderlakeOpenBoardPkg: Add modules
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 2/6] AlderlakeOpenBoardPkg: Add modules Saloni Kasbekar
@ 2023-08-02 17:46 ` Chaganty, Rangasai V
2023-08-04 0:42 ` Chuang, Rosen
1 sibling, 0 replies; 18+ messages in thread
From: Chaganty, Rangasai V @ 2023-08-02 17:46 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Oram, Isaac W, Chuang, Rosen
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Tuesday, August 01, 2023 3:18 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 2/6] AlderlakeOpenBoardPkg: Add modules
Adds the following modules:
-BiosInfo
-OpenBoardPlatformInit
-SBCVpdStructurePcd
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c | 196 +++++++++++++++
.../BiosInfo/BiosInfo.inf | 84 +++++++
.../OpenBoardPlatformInitPostMem.c | 233 ++++++++++++++++++
.../OpenBoardPlatformInitPostMem.inf | 75 ++++++
.../SBCVpdStructurePcd/AllStructPCD.dsc | 19 ++
.../GpioTableAdlPPostMem.dsc | 40 +++
.../GpioTableAdlPPreMem.dsc | 29 +++
.../MrcDqDqsSPD/AdlPSpdMap.dsc | 138 +++++++++++
.../PcieClocks/AdlPPcieClocks.dsc | 31 +++
9 files changed, 845 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
new file mode 100644
index 0000000000..64462900de
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
@@ -0,0 +1,196 @@
+/** @file
+ PEIM to provide BiosInfo structure listing up all firmware volume's
+base addresses, sizes,
+ attributes, and information associated to the firmware volume.
+ Primarily the structure is used on FIT table creation and Bpm.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Guid/BiosInfo.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/FirmwareInterfaceTable.h>
+#include <Ppi/FirmwareVolumeInfoMeasurementExcluded.h>
+#include <Library/MemoryAllocationLib.h>
+
+#define BASE_FV_SIZE 10
+
+#define FSP_WRAPPER_FV_SIZE 3
+
+#define TSN_MAC_ADDRESS_FV_SIZE 0
+
+#define BIOS_INFO_STRUCT_SIZE (BASE_FV_SIZE + FSP_WRAPPER_FV_SIZE +
+TSN_MAC_ADDRESS_FV_SIZE)
+
+
+/*
+ BIOS_INFO structure is the base of the firmware volume layout for
+Intel platform BIOS implementation
+ so security checker module can run based on the structure and throw
+warnings, error or deadloop
+ when any unexpected firmware volumes are detected.
+
+ BIOS_INFO is recommended to support full entries of firmware volumes
+present in a flash
+ with right type, attribute, version, flash map base address and size,
+ all associated information which is defined by BIOS_INFO_STRUCT structure.
+ - IBB firmware volumes, which are expected to be measured or/and verified
+ by hardware base security solution to meet SecureBoot chain of trust
+ (Intel BootGuard for example), have attribute 0x0.
+ - Post IBB firmware volumes, which are expected to be measured or/and verified
+ by BIOS (TCG code for measurement, RSA2048SHA256Sign algorithm for verification for example),
+ have attribute BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB.
+ - Else, follows Firmware Interface Table specification.
+*/
+#pragma pack (1)
+typedef struct {
+ BIOS_INFO_HEADER Header;
+ BIOS_INFO_STRUCT Entry[BIOS_INFO_STRUCT_SIZE]; } BIOS_INFO; #pragma
+pack ()
+
+GLOBAL_REMOVE_IF_UNREFERENCED BIOS_INFO mBiosInfo = {
+ {
+ BIOS_INFO_SIGNATURE,
+ BIOS_INFO_STRUCT_SIZE,
+ 0,
+ },
+ {
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashNvStorageVariableSize) + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize),
+ FixedPcdGet32 (PcdFlashNvStorageVariableBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvAdvancedSize),
+ FixedPcdGet32 (PcdFlashFvAdvancedBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvOptionalSize),
+ FixedPcdGet32 (PcdFlashFvOptionalBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvSecuritySize),
+ FixedPcdGet32 (PcdFlashFvSecurityBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvOsBootSize),
+ FixedPcdGet32 (PcdFlashFvOsBootBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvUefiBootSize),
+ FixedPcdGet32 (PcdFlashFvUefiBootBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvPostMemorySize),
+ FixedPcdGet32 (PcdFlashFvPostMemoryBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFirmwareBinariesSize),
+ FixedPcdGet32 (PcdFlashFvFirmwareBinariesBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspSSize),
+ FixedPcdGet32 (PcdFlashFvFspSBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspMSize),
+ FixedPcdGet32 (PcdFlashFvFspMBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspTSize),
+ FixedPcdGet32 (PcdFlashFvFspTBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvPreMemorySize),
+ FixedPcdGet32 (PcdFlashFvPreMemoryBase)
+ },
+ {
+ FIT_TYPE_01_MICROCODE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_MICROCODE_WHOLE_REGION,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashMicrocodeFvSize),
+ FixedPcdGet32 (PcdFlashMicrocodeFvBase)
+ },
+ }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mBiosInfoPpiList
+= {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gBiosInfoGuid,
+ &mBiosInfo
+};
+
+/**
+ Installs BiosInfo Ppi.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS Install the BiosInfo Ppi successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+BiosInfoEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ VOID *HobData;
+
+ //
+ // Install PPI, so that other PEI module can add dependency.
+ //
+ Status = PeiServicesInstallPpi (&mBiosInfoPpiList);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Build hob, so that DXE module can also get the data.
+ //
+ HobData = BuildGuidHob (&gBiosInfoGuid, sizeof (mBiosInfo));
+ ASSERT (HobData != NULL);
+ if (HobData == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ CopyMem (HobData, &mBiosInfo, sizeof (mBiosInfo));
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
new file mode 100644
index 0000000000..b11451807a
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
@@ -0,0 +1,84 @@
+### @file
+# Module Information description file for BIOS Info PEIM.
+# The module provides BiosInfo structure listing up all firmware
+volume's base addresses, # sizes, attributes, those information associated to each firmware volume.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BiosInfo
+ FILE_GUID = 4A4CA1C6-871C-45BB-8801-6910A7AA5807
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = BiosInfoEntryPoint
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES IA32 X64
+#
+
+[LibraryClasses]
+ PeimEntryPoint
+ PeiServicesLib
+ PeiServicesTablePointerLib
+ HobLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+
+[Pcd]
+ gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase ##
+CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize ## CONSUMES
+
+[Sources]
+ BiosInfo.c
+
+[Guids]
+ gBiosInfoGuid ## PRODUCES
+
+[Depex]
+ gEfiPeiMasterBootModePpiGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c
new file mode 100644
index 0000000000..4fab4ad8e6
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoa
+++ rdPlatformInitPei/OpenBoardPlatformInitPostMem.c
@@ -0,0 +1,233 @@
+/** @file
+ Source code file for OpenBoard Platform Init PEI module
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Register/Msr.h>
+#include <CpuRegs.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/EndOfPeiPhase.h>
+#include <Library/MtrrLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Guid/SmramMemoryReserve.h>
+#include <Library/ConfigBlockLib.h>
+#include <Ppi/SiPolicy.h>
+#include <PchPolicyCommon.h>
+#include <Library/SiPolicyLib.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <Protocol/FirmwareVolumeBlock.h> #include
+<Library/PostCodeLib.h> #include <PlatformPostCode.h> #include
+<Ppi/Spi.h> #include <Library/MtrrLib.h> #include
+<Library/PciSegmentLib.h> #include <Register/PchRegs.h> #include
+<PlatformBoardId.h> #include <Core/Pei/PeiMain.h> #include
+<Library/PchPciBdfLib.h> #include <Ppi/GraphicsPlatformPolicyPpi.h>
+#include <Library/PeiGetFvInfoLib.h>
+
+
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitEndOfPei (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK |
+EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiEndOfPeiSignalPpiGuid,
+ (EFI_PEIM_NOTIFY_ENTRY_POINT) OpenBoardPlatformInitEndOfPei };
+
+EFI_STATUS
+EFIAPI
+GetPeiPlatformLidStatus (
+ OUT LID_STATUS *CurrentLidStatus
+ );
+
+EFI_STATUS
+EFIAPI
+GetVbtData (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ );
+
+PEI_GRAPHICS_PLATFORM_POLICY_PPI PeiGraphicsPlatform = {
+ PEI_GRAPHICS_PLATFORM_POLICY_REVISION,
+ GetPeiPlatformLidStatus,
+ GetVbtData
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPeiGraphicsPlatformPpi = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gPeiGraphicsPlatformPpiGuid,
+ &PeiGraphicsPlatform
+};
+
+EFI_STATUS
+EFIAPI
+GetVbtData (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ )
+{
+ EFI_GUID FileGuid;
+ EFI_GUID BmpImageGuid;
+ VOID *Buffer;
+ UINT32 Size;
+
+ Size = 0;
+ Buffer = NULL;
+
+
+ DEBUG((DEBUG_INFO, "GetVbtData Entry\n"));
+
+ CopyMem (&BmpImageGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid),
+ sizeof(BmpImageGuid));
+
+ CopyMem(&FileGuid, &BmpImageGuid, sizeof(FileGuid));
+ PeiGetSectionFromFv(FileGuid, &Buffer, &Size); if (Buffer == NULL) {
+ DEBUG((DEBUG_ERROR, "Could not locate VBT\n")); } else {
+ DEBUG ((DEBUG_INFO, "GetVbtData Buffer is 0x%x\n", Buffer));
+ DEBUG ((DEBUG_INFO, "GetVbtData Size is 0x%x\n", Size));
+ *VbtAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer;
+ *VbtSize = Size;
+ }
+ DEBUG((DEBUG_INFO, "GetVbtData exit\n"));
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function will return Lid Status in PEI phase.
+
+ @param[out] CurrentLidStatus
+
+ @retval EFI_SUCCESS
+ @retval EFI_UNSUPPORTED
+**/
+
+EFI_STATUS
+EFIAPI
+GetPeiPlatformLidStatus (
+ OUT LID_STATUS *CurrentLidStatus
+ )
+{
+ DEBUG ((DEBUG_INFO, "LidStatus Unsupported\n"));
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Configure PciHostBridge related PCDs
+**/
+VOID
+ConfigurePciHostBridgePcds (
+ VOID
+ )
+{
+ //
+ // Provide 256GB available above 4GB MMIO resource
+ // limited to use single variable MTRR to cover this above 4GB MMIO region.
+ //
+ PcdSet64S (PcdPciReservedMemAbove4GBBase, BASE_256GB);
+ PcdSet64S (PcdPciReservedMemAbove4GBLimit, BASE_256GB + SIZE_256GB -
+1);
+ if (PcdGet64 (PcdPciReservedMemAbove4GBBase) < PcdGet64 (PcdPciReservedMemAbove4GBLimit)) {
+ DEBUG ((DEBUG_INFO, " PCI space that above 4GB MMIO is from 0x%lX", PcdGet64 (PcdPciReservedMemAbove4GBBase)));
+ DEBUG ((DEBUG_INFO, " to 0x%lX\n", PcdGet64
+(PcdPciReservedMemAbove4GBLimit)));
+ }
+}
+
+/**
+ This function handles PlatformInit task at the end of PEI
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this function.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval others
+**/
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitEndOfPei (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ //
+ // Configure PciHostBridge related PCDs before DXE phase
+ //
+ ConfigurePciHostBridgePcds ();
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Platform Init PEI module entry point
+
+ @param[in] FileHandle Not used.
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
+**/
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitPostMemEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ PEI_CORE_INSTANCE *PrivateData;
+ UINTN CurrentFv;
+ PEI_CORE_FV_HANDLE *CoreFvHandle;
+ VOID *HobData;
+
+ PostCode (PLATFORM_INIT_POSTMEM_ENTRY);
+
+ //
+ // Build a HOB to show current FV location for SA policy update code to consume.
+ //
+ PrivateData = PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices);
+ CurrentFv = PrivateData->CurrentPeimFvCount; CoreFvHandle =
+ &(PrivateData->Fv[CurrentFv]);
+
+ HobData = BuildGuidHob (
+ &gPlatformInitFvLocationGuid,
+ sizeof (VOID *)
+ );
+ ASSERT (HobData != NULL);
+ CopyMem (HobData, (VOID *) &CoreFvHandle, sizeof (VOID *));
+
+ //
+ // Install mPeiGraphicsPlatformPpi
+ //
+ DEBUG ((DEBUG_INFO, "Install mPeiGraphicsPlatformPpi \n")); Status =
+ PeiServicesInstallPpi (&mPeiGraphicsPlatformPpi);
+
+ //
+ // Performing PlatformInitEndOfPei after EndOfPei PPI produced //
+ Status = PeiServicesNotifyPpi (&mEndOfPeiNotifyList); PostCode
+ (PLATFORM_INIT_POSTMEM_EXIT);
+
+ return Status;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
new file mode 100644
index 0000000000..b2bfd97f8a
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoa
+++ rdPlatformInitPei/OpenBoardPlatformInitPostMem.inf
@@ -0,0 +1,75 @@
+### @file
+# Component information file for the OpenBoard Platform Init PEI module.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = OpenBoardPlatformInitPostMem
+ FILE_GUID = 314EE04C-1106-4DC6-ACBC-CF19C0DBC5CC
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = OpenBoardPlatformInitPostMemEntryPoint
+
+[LibraryClasses]
+ PeimEntryPoint
+ DebugLib
+ IoLib
+ MemoryAllocationLib
+ BaseMemoryLib
+ HobLib
+ PeiServicesLib
+ PciSegmentLib
+ MtrrLib
+ PchInfoLib
+ PostCodeLib
+ SiPolicyLib
+ FspCommonLib
+ PcdLib
+ PchPciBdfLib
+ GpioLib
+ PeiGetFvInfoLib
+
+[Packages]
+ AlderlakeSiliconPkg/SiPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ AlderLakeFspBinPkg/Client/AlderLakeP/AlderLakeFspBinPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+ OpenBoardPlatformInitPostMem.c
+
+[Ppis]
+ gEfiEndOfPeiSignalPpiGuid ## CONSUMES
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+ gPeiGraphicsPlatformPpiGuid ## PRODUCES
+ gFspSiliconInitDonePpiGuid ## CONSUMES
+
+[Protocols]
+
+[Guids]
+ gEfiSmmSmramMemoryGuid ## CONSUMES
+ gPlatformInitFvLocationGuid ## PRODUCES
+
+[Depex]
+ gEfiPeiMemoryDiscoveredPpiGuid
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIobase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIoLimit ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciSegmentCount ## CONSUMES
+
+ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUMES
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc
new file mode 100644
index 0000000000..9215a026ae
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructP
+++ CD.dsc
@@ -0,0 +1,19 @@
+## @file
+# Include All Board Gpio configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+!include
+$(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
+!include
+$(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
+
+
+# PCIe clock mapping
+!include
+$(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.
+dsc
+
+# MRC DQS DQ and SPD mapping
+!include
+$(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
+
+
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
new file mode 100644
index 0000000000..3eb8c276b5
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableA
+++ dlPPostMem.dsc
@@ -0,0 +1,40 @@
+## @file
+# GPIO definition table for Alderlake P #
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+###
+### !!! GPIOs designated to Native Functions shall not be configured by Platform Code.
+### Native Pins shall be configured by Silicon Code (based on BIOS policies setting) or soft straps(set by CSME in FITc).
+###
+###
+
+
+#mGpioTableAdlPDdr5Rvp
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable|*|{CODE({
+ // CPU M.2 SSD1
+ {GPIO_VER2_LP_GPP_F20, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD1 RESET
+
+ // CPU M.2 SSD2
+ {GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 PWREN
+ {GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, // CPU SSD2 RESET
+
+ // X4 Pcie Slot for Gen3 and Gen 4
+ {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}},//ONBOARD_X4_PCIE_SLOT1_RESET_N
+
+ // PCH M.2 SSD
+ {GPIO_VER2_LP_GPP_D16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_PCH_SSD_PWREN
+ {GPIO_VER2_LP_GPP_H0, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_SSD_RST_N
+
+ // EC
+ {GPIO_VER2_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSmi,GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //EC_SMI_N
+ {GPIO_VER2_LP_GPP_F9, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //EC_SLP_S0_CS_N
+
+ {0x0} // terminator
+})}
+
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
new file mode 100644
index 0000000000..7bf8571c27
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableA
+++ dlPPreMem.dsc
@@ -0,0 +1,29 @@
+## @file
+# Alderlake P RVP GPIO definition table for Pre-Memory Initialization
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+###
+### !!! GPIOs designated to Native Functions shall not be configured by Platform Code.
+### Native Pins shall be configured by Silicon Code (based on BIOS policies setting) or soft straps(set by CSME in FITc).
+###
+###
+
+# mGpioTablePreMemAdlPDdr5Rvp
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
+ // CPU M.2 SSD
+ { GPIO_VER2_LP_GPP_F20, { GpioPadModeGpio, GpioHostOwnAcpi,
+GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }
+}, //CPU SSD RESET
+
+ // CPU M.2 SSD2
+ {GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 PWREN
+ {GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 RESET
+
+ // X4 Pcie Slot for Gen3 and Gen 4
+ {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}},//ONBOARD_X4_PCIE_SLOT1_RESET_N
+
+ {0x0} // terminator
+})}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
new file mode 100644
index 0000000000..096cc380cd
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSP
+++ D/AdlPSpdMap.dsc
@@ -0,0 +1,138 @@
+## @file
+# ADL P SPD DATA configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData|*|{CODE(
+{
+// DDR5 1Rx16 - 4800 MHz
+ 1,
+ {0x30, ///< 0 1024 SPD bytes total
+ 0x08, ///< 1 SPD Revision 0.8
+ 0x12, ///< 2 DRAM Type: DDR5 SDRAM
+ 0x03, ///< 3 Module Type: Not Hybrid (DRAM only) / SO-DIMM Solution
+ 0x04, ///< 4 Monolithic SDRAM, 16 Gb SDRAM density
+ 0x00, ///< 5 16 Rows, 10 Columns
+ 0x40, ///< 6 x16 SDRAM I/O Width
+ 0x42, ///< 7 4 Bank Groups, 4 Banks per Bank Group
+ 0x00, ///< 8 Secondary SDRAM Density and Package
+ 0x00, ///< 9 Secondary SDRAM Addressing
+ 0x00, ///< 10 Secondary SDRAM I/O Width
+ 0x00, ///< 11 Secondary BankGroups and Banks per Bank Group
+ 0x60, ///< 12 PPR Supported, One row per bank group, Soft PPR Supported
+ 0x00, ///< 13 Commercial Temperature Grade, 0 to 85 C
+ 0x00, ///< 14 Reserved
+ 0x00, ///< 15 Reserved
+ 0x00, ///< 16 SDRAM Nominal Voltage VDD: 1.1V
+ 0x00, ///< 17 SDRAM Nominal Voltage VDDQ: 1.1V
+ 0x00, ///< 18 SDRAM Nominal Voltage VPP: 1.8V
+ 0x00, ///< 19 Reserved
+ 0xA1, ///< 20 tCKAVGmin LSB
+ 0x01, ///< 21 tCKAVGmin MSB
+ 0xE8, ///< 22 tCKAVGmax LSB
+ 0x03, ///< 23 tCKAVGmax MSB
+ 0x72, ///< 24 CAS Latencies supported (First Byte) : 32, 30, 28, 22
+ 0x15, ///< 25 CAS Latencies supported (Second Byte): 44, 40, 36
+ 0x00, ///< 26 CAS Latencies supported (Third Byte) :
+ 0x00, ///< 27 CAS Latencies supported (Fourth Byte):
+ 0x00, ///< 28 CAS Latencies supported (Fifth Byte) :
+ 0x00, ///< 29 Reserved
+ 0x1E, ///< 30 Minimum CAS Latency (tAAmin) LSB
+ 0x41, ///< 31 Minimum CAS Latency (tAAmin) MSB
+ 0x1E, ///< 32 Minimum RAS-to-CAS delay (tRCDmin) LSB
+ 0x41, ///< 33 Minimum RAS-to-CAS delay (tRCDmin) MSB
+ 0x1E, ///< 34 Minimum Row Precharge delay (tRPmin) LSB
+ 0x41, ///< 35 Minimum Row Precharge delay (tRPmin) MSB
+ 0x00, ///< 36 Minimum Active to Precharge delay (tRASmin) LSB
+ 0x7D, ///< 37 Minimum Active to Precharge delay (tRASmin) MSB
+ 0x1E, ///< 38 Minimum Active to Active/Refresh delay (tRCmin) LSB
+ 0xBE, ///< 39 Minimum Active to Active/Refresh delay (tRCmin) MSB
+ 0x30, ///< 40 Minimum Write Recovery time (tWRmin) LSB
+ 0x75, ///< 41 Minimum Write Recovery time (tWRmin) MSB
+ 0x27, ///< 42 Refresh Recovery Delay (tRFC1min) LSB
+ 0x01, ///< 43 Refresh Recovery Delay (tRFC1min) MSB
+ 0xA0, ///< 44 Refresh Recovery Delay (tRFC2min) MSB
+ 0x00, ///< 45 Refresh Recovery Delay (tRFC2min) MSB
+ 0x82, ///< 46 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0x00, ///< 47 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0, 0, ///< 48 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0, 0, 0, 0, 0, 0, ///< 120 - 125
+ 0x47, ///< 126 CRC Bytes 0 - 127 LSB
+ 0xAE, ///< 127 CRC Bytes 0 - 127 MSB
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, ///< 190 - 191
+ 0x08, ///< 192 SPD Revision for Module Information: 0.8
+ 0x00, ///< 193 Reserved
+ 0xC2, ///< 194 SPD Manufacturer ID First Byte
+ 0xC4, ///< 195 SPD Manufacturer ID Second Byte
+ 0x80, ///< 196 SPD Device Type
+ 0x00, ///< 197 SPD Device Revision
+ 0x80, ///< 198 PMIC0 Manufacturer ID First Byte
+ 0xB3, ///< 199 PMIC0 Manufacturer ID Second Byte
+ 0x80, ///< 200 PMIC0 Device Type
+ 0x11, ///< 201 PMIC0 Device Revision
+ 0, 0, 0, 0, ///< 202 - 205 PMIC1
+ 0, 0, 0, 0, ///< 206 - 209 PMIC2
+ 0x80, ///< 210 Thermal Sensors Manufacturer ID First Byte
+ 0xB3, ///< 211 Thermal Sensors Manufacturer ID First Byte
+ 0x80, ///< 212 Thermal Sensors Device Type
+ 0x11, ///< 213 Thermal Sensors Device Revision
+ 0, 0, 0, 0, 0, 0, ///< 214 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0x0F, ///< 230 Module Nominal Height
+ 0x10, ///< 231 Module Nominal Thickness
+ 0x00, ///< 232 Reference Raw Card Used
+ 0x01, ///< 233 1 Row of DRAM on Module
+ 0x01, ///< 234 1 Rank, 8 bits SDRAM data width per channel
+ 0x22, ///< 235 2 Channels per DIMM, 32 bits per Channel
+ 0, 0, 0, 0, ///< 236 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 320 - 329
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 330 - 339
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 340 - 349
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 350 - 359
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ///< 440 - 445
+ 0x9C, ///< 446 CRC for Bytes 128 - 253 LSB
+ 0xAD, ///< 447 CRC for Bytes 128 - 253 MSB
+ 0, 0, ///< 448 - 449
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
+ 0, 0 ///< 510 - 511
+ ///< Ignore bytes 512-1023, @todo_adl: support 1024 bytes SPD
+array }})}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
new file mode 100644
index 0000000000..57106e92c4
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks
+++ /AdlPPcieClocks.dsc
@@ -0,0 +1,31 @@
+## @file
+# Alderlake P Pcie Clock configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
+{{
+ PCIE_PEG, // CPU M.2 SSD 1
+ PCIE_PCH + 8, // PCH M.2 SSD
+ PCIE_PCH + 4,
+ PCIE_PEG + 1, // X8 DG/DG2
+ PCIE_PEG + 2, // CPU M.2 SSD 2
+ PCIE_PCH + 5, // M.2 KEY B WWAN - PCIe P6
+ LAN_CLOCK,
+ // Default Case:
+ // - PCIe P7 mapped to GBELAN
+ // - PCIe P8 mapped to x4 PCIe DT Slot (Pair 1)
+ PCIE_PCH + 7, // x4 PCIe DT Slot (x1)
+ // Reworked Case: with rework and soft strap changes
+ // - PCIe P7 mapped to x4 PCIe DT Slot (Pair 2)
+ // - PCIe P8 mapped to x4 PCIe DT Slot (Pair 1)
+ // PCIE_PCH + 6, // x4 PCIe DT Slot (x2)
+ NOT_USED,
+ NOT_USED
+}}
+)}
--
2.36.1.windows.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [edk2-devel] [PATCH v2 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add libraries
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add libraries Saloni Kasbekar
@ 2023-08-02 18:10 ` Chaganty, Rangasai V
2023-08-04 0:48 ` Chuang, Rosen
1 sibling, 0 replies; 18+ messages in thread
From: Chaganty, Rangasai V @ 2023-08-02 18:10 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Oram, Isaac W, Chuang, Rosen
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Tuesday, August 01, 2023 3:18 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add libraries
Adds the following library instances:
- BoardAcpiLib
- BoardInitLib
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../SmmAlderlakePRvpAcpiEnableLib.c | 50 +++++
.../SmmMultiBoardAcpiSupportLib.c | 88 ++++++++
.../SmmMultiBoardAcpiSupportLib.inf | 41 ++++
.../BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 134 ++++++++++++
.../BoardInitLib/Pei/BoardPchInitPreMemLib.c | 104 +++++++++
.../BoardInitLib/Pei/BoardSaConfigPreMem.h | 73 +++++++
.../BoardInitLib/Pei/BoardSaInitPreMemLib.c | 160 ++++++++++++++
.../Library/BoardInitLib/Pei/PeiDetect.c | 62 ++++++
.../BoardInitLib/Pei/PeiInitPostMemLib.c | 100 +++++++++
.../BoardInitLib/Pei/PeiInitPreMemLib.c | 202 ++++++++++++++++++
.../Pei/PeiMultiBoardInitPostMemLib.c | 45 ++++
.../Pei/PeiMultiBoardInitPostMemLib.inf | 53 +++++
.../Pei/PeiMultiBoardInitPreMemLib.c | 89 ++++++++
.../Pei/PeiMultiBoardInitPreMemLib.inf | 149 +++++++++++++
14 files changed, 1350 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmAlderlakePRvpAcpiEnableLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardPchInitPreMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaConfigPreMem.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaInitPreMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiDetect.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPostMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPreMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmAlderlakePRvpAcpiEnableLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmAlderlakePRvpAcpiEnableLib.c
new file mode 100644
index 0000000000..8dfc04c5f5
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAc
+++ piLib/SmmAlderlakePRvpAcpiEnableLib.c
@@ -0,0 +1,50 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardId.h>
+
+/**
+ Enable Board Acpi
+
+ @param[in] EnableSci Enable SCI if EnableSci parameters is True.
+
+ @retval EFI_SUCCESS The function always return successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ // enable additional board register
+ return EFI_SUCCESS;
+}
+
+/**
+ Disable Board Acpi
+
+ @param[in] DisableSci Disable SCI if DisableSci parameters is True.
+
+ @retval EFI_SUCCESS The function always return successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ // enable additional board register
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
new file mode 100644
index 0000000000..ea0f7c966b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAc
+++ piLib/SmmMultiBoardAcpiSupportLib.c
@@ -0,0 +1,88 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h> #include
+<Library/MultiBoardAcpiSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+AdlBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+AdlBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+MultiBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ SiliconEnableAcpi (EnableSci);
+ return AdlBoardEnableAcpi (EnableSci); }
+
+EFI_STATUS
+EFIAPI
+MultiBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ SiliconDisableAcpi (DisableSci);
+ return AdlBoardDisableAcpi (DisableSci); }
+
+BOARD_ACPI_ENABLE_FUNC mBoardAcpiEnableFunc = {
+ MultiBoardEnableAcpi,
+ MultiBoardDisableAcpi,
+};
+
+/**
+ The constructor function to register mBoardAcpiEnableFunc function.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS This constructor always return EFI_SUCCESS.
+ It will ASSERT on errors.
+**/
+EFI_STATUS
+EFIAPI
+SmmMultiBoardAcpiSupportLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ return RegisterBoardAcpiEnableFunc (&mBoardAcpiEnableFunc); }
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
new file mode 100644
index 0000000000..8a418bc8da
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAc
+++ piLib/SmmMultiBoardAcpiSupportLib.inf
@@ -0,0 +1,41 @@
+## @file
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> #
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SmmMultiBoardAcpiSupportLib
+ FILE_GUID = 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_SMM_DRIVER
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = SmmMultiBoardAcpiSupportLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC #
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciLib
+ PchCycleDecodingLib
+ PchPciBdfLib
+ PmcLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ SmmAlderlakePRvpAcpiEnableLib.c
+ SmmSiliconAcpiEnableLib.c
+ SmmMultiBoardAcpiSupportLib.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
new file mode 100644
index 0000000000..fbe745ad36
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAc
+++ piLib/SmmSiliconAcpiEnableLib.c
@@ -0,0 +1,134 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/BoardAcpiEnableLib.h> #include <Library/PcdLib.h>
+#include <Library/DebugLib.h> #include <Library/PmcLib.h> #include
+<Library/PchPciBdfLib.h> #include <Register/PchRegs.h> #include
+<Register/PchRegsLpc.h> #include <Register/PmcRegs.h> #include
+<Register/RtcRegs.h>
+
+/**
+ Clear Port 80h
+
+ Disables the SW SMI Timer.
+ ACPI events are disabled and ACPI event status is cleared.
+
+ Disable port 60/64 SMI trap if they are enabled
+
+ Disable PM sources except power button Clear status bits
+
+ Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+
+ Enable SCI
+**/
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+
+ UINT32 SmiEn;
+ UINT32 SmiSts;
+ UINT32 ULKMC;
+ UINTN LpcBaseAddress;
+ UINT16 AcpiBaseAddr;
+ UINT32 Pm1Cnt;
+
+ LpcBaseAddress = LpcPciCfgBase ();
+
+ //
+ // Get the ACPI Base Address
+ //
+ AcpiBaseAddr = PmcGetAcpiBase();
+
+ //
+ // Clear Port 80h
+ //
+ IoWrite8 (0x80, 0);
+
+ //
+ // Disable SW SMI Timer and clean the status // SmiEn = IoRead32
+ (AcpiBaseAddr + R_ACPI_IO_SMI_EN); SmiEn &=
+ ~(B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR |
+ B_ACPI_IO_SMI_EN_LEGACY_USB);
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN, SmiEn);
+
+ SmiSts = IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS); SmiSts |=
+ B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR |
+ B_ACPI_IO_SMI_EN_LEGACY_USB;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS, SmiSts);
+
+ //
+ // Disable port 60/64 SMI trap if they are enabled // ULKMC =
+ MmioRead32 (LpcBaseAddress + R_LPC_CFG_ULKMC) &
+ ~(B_LPC_CFG_ULKMC_60REN | B_LPC_CFG_ULKMC_60WEN |
+ B_LPC_CFG_ULKMC_64REN | B_LPC_CFG_ULKMC_64WEN |
+ B_LPC_CFG_ULKMC_A20PASSEN);
+ MmioWrite32 (LpcBaseAddress + R_LPC_CFG_ULKMC, ULKMC);
+
+ //
+ // Disable PM sources except power button //
+ IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_EN, B_ACPI_IO_PM1_EN_PWRBTN);
+
+ //
+ // Clear PM status except Power Button status for RapidStart Resume
+ //
+ IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_STS, 0xFEFF);
+
+ //
+ // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+ //
+ IoWrite8 (R_RTC_IO_INDEX_ALT, R_RTC_IO_REGD);
+ IoWrite8 (R_RTC_IO_TARGET_ALT, 0x0);
+
+ //
+ // Enable SCI
+ //
+ if (EnableSci) {
+ Pm1Cnt = IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);
+ Pm1Cnt |= B_ACPI_IO_PM1_CNT_SCI_EN;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt); }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+
+ UINT16 AcpiBaseAddr;
+ UINT32 Pm1Cnt;
+
+ //
+ // Get the ACPI Base Address
+ //
+ AcpiBaseAddr = PmcGetAcpiBase();
+ //
+ // Disable SCI
+ //
+ if (DisableSci) {
+ Pm1Cnt = IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);
+ Pm1Cnt &= ~B_ACPI_IO_PM1_CNT_SCI_EN;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt); }
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardPchInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardPchInitPreMemLib.c
new file mode 100644
index 0000000000..13ad444f8b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/BoardPchInitPreMemLib.c
@@ -0,0 +1,104 @@
+/** @file
+ Source code for the board PCH configuration Pcd init functions for Pre-Memory Init phase.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h> #include <Library/DebugLib.h>
+#include <Library/BoardConfigLib.h> #include
+<Include/PlatformBoardId.h> #include <PlatformBoardConfig.h> #include
+<Library/PcdLib.h> #include <PlatformBoardId.h> #include
+<Library/PchInfoLib.h>
+/**
+ Board Root Port Clock Info configuration init function for PEI pre-memory phase.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+AdlPRootPortClkInfoInit (
+ VOID
+ )
+{
+ PCD64_BLOB Clock[PCH_MAX_PCIE_CLOCKS];
+ UINT32 Index;
+ PCIE_CLOCKS_USAGE *PcieClocks;
+
+ PcieClocks = NULL;
+
+ //
+ //The default clock assignment will be NOT_USED, which corresponds to PchClockUsageNotUsed. This will prevent clocks drawing Power by default.
+ //If Platform code doesn't contain port-clock map for a given board, the clocks will be NOT_USED, preventing PCIe devices not to operate.
+ //To prevent this, remember to provide port-clock map for every board.
+ //
+ for (Index = 0; Index < PCH_MAX_PCIE_CLOCKS; Index++) {
+ Clock[Index].PcieClock.ClkReqSupported = TRUE;
+ Clock[Index].PcieClock.ClockUsage = NOT_USED; }
+
+ ///
+ /// Assign ClkReq signal to root port. (Base 0) /// For LP, Set 0 -
+ 5 /// For H, Set 0 - 15 /// Note that if GbE is enabled, ClkReq
+ assigned to GbE will not be available for Root Port.
+ ///
+
+ PcieClocks = PcdGetPtr(VpdPcdPcieClkUsageMap); if (PcieClocks ==
+ NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Clock[0].PcieClock.ClockUsage = PcieClocks->ClockUsage[0];
+ Clock[1].PcieClock.ClockUsage = PcieClocks->ClockUsage[1];
+ Clock[2].PcieClock.ClockUsage = PcieClocks->ClockUsage[2];
+ Clock[3].PcieClock.ClockUsage = PcieClocks->ClockUsage[3];
+ Clock[4].PcieClock.ClockUsage = PcieClocks->ClockUsage[4];
+ Clock[5].PcieClock.ClockUsage = PcieClocks->ClockUsage[5];
+ Clock[6].PcieClock.ClockUsage = PcieClocks->ClockUsage[6];
+ Clock[7].PcieClock.ClockUsage = PcieClocks->ClockUsage[7];
+ Clock[8].PcieClock.ClockUsage = PcieClocks->ClockUsage[8];
+ Clock[9].PcieClock.ClockUsage = PcieClocks->ClockUsage[9];
+
+ PcdSet64S (PcdPcieClock0, Clock[ 0].Blob);
+ PcdSet64S (PcdPcieClock1, Clock[ 1].Blob);
+ PcdSet64S (PcdPcieClock2, Clock[ 2].Blob);
+ PcdSet64S (PcdPcieClock3, Clock[ 3].Blob);
+ PcdSet64S (PcdPcieClock4, Clock[ 4].Blob);
+ PcdSet64S (PcdPcieClock5, Clock[ 5].Blob);
+ PcdSet64S (PcdPcieClock6, Clock[ 6].Blob);
+ PcdSet64S (PcdPcieClock7, Clock[ 7].Blob);
+ PcdSet64S (PcdPcieClock8, Clock[ 8].Blob);
+ PcdSet64S (PcdPcieClock9, Clock[ 9].Blob);
+ PcdSet64S (PcdPcieClock10, Clock[10].Blob);
+ PcdSet64S (PcdPcieClock11, Clock[11].Blob);
+ PcdSet64S (PcdPcieClock12, Clock[12].Blob);
+ PcdSet64S (PcdPcieClock13, Clock[13].Blob);
+ PcdSet64S (PcdPcieClock14, Clock[14].Blob);
+ PcdSet64S (PcdPcieClock15, Clock[15].Blob);
+ return EFI_SUCCESS;
+}
+
+/**
+ Board GPIO Group Tier configuration init function for PEI pre-memory phase.
+**/
+VOID
+AdlPGpioGroupTierInit (
+ VOID
+ )
+{
+ //
+ // GPIO Group Tier
+ //
+ PcdSet32S (PcdGpioGroupToGpeDw0, 0);
+ PcdSet32S (PcdGpioGroupToGpeDw1, 0);
+ PcdSet32S (PcdGpioGroupToGpeDw2, 0);
+
+ return;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaConfigPreMem.h b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaConfigPreMem.h
new file mode 100644
index 0000000000..c79555cde8
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/BoardSaConfigPreMem.h
@@ -0,0 +1,73 @@
+/** @file
+ PEI Boards Configurations for PreMem phase.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _BOARD_SA_CONFIG_PRE_MEM_H_
+#define _BOARD_SA_CONFIG_PRE_MEM_H_
+
+#include <Ppi/SiPolicy.h>
+#include <Library/BoardConfigLib.h>
+
+#define SA_MRC_MAX_RCOMP_TARGETS (5)
+
+//
+// Reference RCOMP resistors on motherboard - MRC will set
+automatically // GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
+AdlPRcompResistorZero = 0;
+
+//
+// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - MRC
+will set automatically // GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
+RcompTargetAdlP[SA_MRC_MAX_RCOMP_TARGETS] = { 0, 0, 0, 0, 0 };
+
+//
+// DQ byte mapping to CMD/CTL/CLK, from the CPU side //
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 DqByteMapAdlP[2][6][2] = {
+ // Channel 0:
+ {
+ { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+ { 0x0F, 0xF0 }, // Cmd CAA goes to Bytes[3:0], Cmd CAB goes to Byte[7:4]
+ { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ },
+ // Channel 1:
+ {
+ { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+ { 0x0F, 0xF0 }, // Cmd CAA goes to Bytes[3:0], Cmd CAB goes to Byte[7:4]
+ { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ }
+};
+
+//
+// Display DDI settings for Adl-P Ddr5 Rvp Edp + DP //
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mAdlPDdr5RvpDisplayDdiConfig[16] = {
+ DdiPortEdp, // DDI Port A Config : DdiPortDisabled = No LFP is Connected, DdiPortEdp = eDP, DdiPortMipiDsi = MIPI DSI
+ DdiPortDisabled, // DDI Port B Config : DdiPortDisabled = No LFP is Connected, DdiPortEdp = eDP, DdiPortMipiDsi = MIPI DSI
+ DdiHpdDisable, // DDI Port A HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdEnable, // DDI Port B HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port C HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port 1 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port 2 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port 3 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port 4 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiDisable, // DDI Port A DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port B DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port C DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port 1 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port 2 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port 3 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable // DDI Port 4 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+};
+
+#endif // _BOARD_SA_CONFIG_PRE_MEM_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaInitPreMemLib.c
new file mode 100644
index 0000000000..e42c8fb5f8
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/BoardSaInitPreMemLib.c
@@ -0,0 +1,160 @@
+/** @file
+ Source code for the board SA configuration Pcd init functions in Pre-Memory init phase.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BoardSaConfigPreMem.h"
+#include <Library/CpuPlatformLib.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+/**
+ MRC configuration init function for PEI pre-memory phase.
+
+ @param[in] VOID
+
+ @retval VOID
+**/
+VOID
+AdlPSaMiscConfigInit (
+ VOID
+ )
+{
+ PcdSet8S (PcdSaMiscUserBd, 6);
+ return;
+}
+
+/**
+ Board Memory Init related configuration init function for PEI pre-memory phase.
+
+ @param[in] VOID
+
+ @retval VOID
+**/
+VOID
+AdlPMrcConfigInit (
+ VOID
+ )
+{
+ UINT16 BoardId;
+ BOOLEAN ExternalSpdPresent;
+ MRC_DQS *MrcDqs;
+ MRC_DQ *MrcDq;
+ SPD_DATA *SpdData;
+
+ BoardId = PcdGet16(PcdBoardId);
+
+ // SPD is the same size for all boards PcdSet16S (PcdMrcSpdDataSize,
+ 512);
+
+ ExternalSpdPresent = PcdGetBool (PcdSpdPresent);
+
+ // Assume internal SPD is used
+ PcdSet8S (PcdMrcSpdAddressTable0, 0); PcdSet8S
+ (PcdMrcSpdAddressTable1, 0); PcdSet8S (PcdMrcSpdAddressTable2, 0);
+ PcdSet8S (PcdMrcSpdAddressTable3, 0); PcdSet8S
+ (PcdMrcSpdAddressTable4, 0); PcdSet8S (PcdMrcSpdAddressTable5, 0);
+ PcdSet8S (PcdMrcSpdAddressTable6, 0); PcdSet8S
+ (PcdMrcSpdAddressTable7, 0); PcdSet8S (PcdMrcSpdAddressTable8, 0);
+ PcdSet8S (PcdMrcSpdAddressTable9, 0); PcdSet8S
+ (PcdMrcSpdAddressTable10, 0); PcdSet8S (PcdMrcSpdAddressTable11, 0);
+ PcdSet8S (PcdMrcSpdAddressTable12, 0); PcdSet8S
+ (PcdMrcSpdAddressTable13, 0); PcdSet8S (PcdMrcSpdAddressTable14, 0);
+ PcdSet8S (PcdMrcSpdAddressTable15, 0);
+
+ // Check for external SPD presence
+ if (ExternalSpdPresent) {
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ PcdSet8S (PcdMrcSpdAddressTable0, 0xA0);
+ PcdSet8S (PcdMrcSpdAddressTable1, 0xA2);
+ PcdSet8S (PcdMrcSpdAddressTable8, 0xA4);
+ PcdSet8S (PcdMrcSpdAddressTable9, 0xA6);
+ break;
+ default:
+ break;
+ }
+ }
+
+ // Setting the default DQ Byte Map. It may be overriden to board specific settings below.
+ PcdSet32S (PcdMrcDqByteMap, (UINTN) DqByteMapAdlP); PcdSet16S
+ (PcdMrcDqByteMapSize, sizeof (DqByteMapAdlP));
+
+ // ADL uses the same RCOMP resistors for all DDR types PcdSet32S
+ (PcdMrcRcompResistor, (UINTN) AdlPRcompResistorZero);
+
+ // Use default RCOMP target values for all boards PcdSet32S
+ (PcdMrcRcompTarget, (UINTN) RcompTargetAdlP);
+
+ // Default is NIL
+ PcdSetBoolS (PcdMrcDqPinsInterleavedControl, TRUE); PcdSetBoolS
+ (PcdMrcDqPinsInterleaved, FALSE);
+
+ // DqsMapCpu2Dram is the same size for all boards PcdSet16S
+ (PcdMrcDqsMapCpu2DramSize, sizeof (MRC_DQS)); // DqMapCpu2Dram is the
+ same size for all boards PcdSet16S (PcdMrcDqMapCpu2DramSize, sizeof
+ (MRC_DQ));
+ PcdSet8S (PcdMrcLp5CccConfig, 0x0);
+
+ // CPU-DRAM DQ mapping
+ MrcDq = PcdGetPtr (VpdPcdMrcDqMapCpu2Dram); if (MrcDq != NULL) {
+ PcdSet32S (PcdMrcDqMapCpu2Dram, (UINTN)MrcDq->DqMapCpu2Dram); }
+
+ // CPU-DRAM DQS mapping
+ MrcDqs = PcdGetPtr (VpdPcdMrcDqsMapCpu2Dram); if (MrcDqs != NULL) {
+ PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN)MrcDqs->DqsMapCpu2Dram); }
+
+ // DRAM SPD Data
+ SpdData = PcdGetPtr (VpdPcdMrcSpdData); if (SpdData != NULL) {
+ if (SpdData->OverrideSpd == TRUE) {
+ PcdSet32S (PcdMrcSpdData, (UINTN)SpdData->SpdData);
+ }
+ }
+
+ return;
+}
+
+/**
+ SA Display DDI configuration init function for PEI pre-memory phase.
+
+ @param[in] VOID
+
+ @retval VOID
+**/
+VOID
+AdlPSaDisplayConfigInit (
+ VOID
+ )
+{
+ UINT16 BoardId;
+
+ BoardId = PcdGet16 (PcdBoardId);
+
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ DEBUG ((DEBUG_INFO, "DDI Configuration ADLP Edp DP\n"));
+ PcdSet32S (PcdSaDisplayConfigTable, (UINTN) mAdlPDdr5RvpDisplayDdiConfig);
+ PcdSet16S (PcdSaDisplayConfigTableSize, sizeof (mAdlPDdr5RvpDisplayDdiConfig));
+ break;
+ default:
+ break;
+ }
+
+ return;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiDetect.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiDetect.c
new file mode 100644
index 0000000000..5ad8e56f4d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiDetect.c
@@ -0,0 +1,62 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <Library/BoardConfigLib.h>
+
+BOOLEAN
+IsAdlP (
+ VOID
+ )
+{
+ UINT16 BoardId;
+ BoardId = PcdGet16 (PcdBoardId);
+ if (BoardId == 0) {
+ DEBUG ((DEBUG_INFO, "Let's get Board information first ...\n"));
+ GetBoardConfig ();
+ BoardId = PcdGet16 (PcdBoardId);
+ }
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ DEBUG ((DEBUG_INFO, "AlderLake P Board detected\n"));
+
+ // set sku type to ADL P
+ PcdSet8S (PcdSkuType, AdlPSkuType);
+ return TRUE;
+ break;
+ default:
+ return FALSE;
+ }
+}
+
+EFI_STATUS
+EFIAPI
+AdlPBoardDetect (
+ VOID
+ )
+{
+ UINTN SkuId;
+ SkuId = 0;
+
+ if (LibPcdGetSku () != 0) {
+ return EFI_SUCCESS;
+ }
+
+ DEBUG ((DEBUG_INFO, "AlderLakeP Board Detection Callback\n"));
+
+ if (IsAdlP ()) {
+ SkuId = (UINTN) (PcdGet16 (PcdBoardBomId) << 16) | (PcdGet16 (PcdBoardRev) << 8) | (PcdGet16 (PcdBoardId));
+ LibPcdSetSku (SkuId);
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ }
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPostMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPostMemLib.c
new file mode 100644
index 0000000000..51201bb300
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiInitPostMemLib.c
@@ -0,0 +1,100 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <Library/BoardConfigLib.h>
+#include <Library/GpioLib.h>
+#include <Library/IoLib.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PchInfoLib.h>
+#include <Library/HobLib.h>
+
+
+
+/**
+ Alderlake P boards configuration init function for PEI post memory phase.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlPInit (
+ VOID
+ )
+{
+ UINT16 GpioCount;
+ UINTN Size;
+ EFI_STATUS Status;
+ GPIO_INIT_CONFIG *GpioTable;
+ //
+ // GPIO Table Init
+ //
+ Status = EFI_SUCCESS;
+ GpioCount = 0;
+ Size = 0;
+ GpioTable = NULL;
+ //
+ // GPIO Table Init
+ //
+ //
+ // GPIO Table Init, Update PostMem GPIO table to PcdBoardGpioTable
+ //
+ GpioTable = (GPIO_INIT_CONFIG *)PcdGetPtr(VpdPcdBoardGpioTable);
+
+ GetGpioTableSize (GpioTable, &GpioCount); // // Increase GpioCount
+ for the zero terminator.
+ //
+ GpioCount ++;
+ Size = (UINTN) (GpioCount * sizeof (GPIO_INIT_CONFIG)); Status =
+ PcdSetPtrS (PcdBoardGpioTable, &Size, GpioTable); ASSERT_EFI_ERROR
+ (Status);
+
+ return Status;
+}
+
+/**
+ Configures GPIO
+
+ @param[in] GpioTable Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+
+**/
+VOID
+ConfigureGpio (
+ IN GPIO_INIT_CONFIG *GpioDefinition,
+ IN UINT16 GpioTableCount
+ )
+{
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
+
+ GpioConfigurePads (GpioTableCount, GpioDefinition);
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); }
+
+/**
+ Configure GPIO, TouchPanel, HDA, PMC, TBT etc.
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeSiliconInit (
+ VOID
+ )
+{
+ AdlPInit ();
+ GpioInit (PcdGetPtr (PcdBoardGpioTable));
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPreMemLib.c
new file mode 100644
index 0000000000..0b7db476a1
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiInitPreMemLib.c
@@ -0,0 +1,202 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/BiosIdLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PciLib.h>
+#include <Library/MemoryAllocationLib.h> #include <Library/PeiLib.h>
+#include <Guid/MemoryOverwriteControl.h> #include
+<PlatformBoardConfig.h> #include <Library/PchCycleDecodingLib.h>
+#include <Register/PmcRegs.h> #include <Library/PmcLib.h> #include
+<Ppi/ReadOnlyVariable2.h> #include <Library/PeiServicesLib.h> #include
+<Library/GpioLib.h> #include <Library/BoardConfigLib.h> #include
+<Library/TimerLib.h> #include <PlatformBoardId.h> #include
+<Library/IoLib.h> #include <Pins/GpioPinsVer2Lp.h> #include
+<Library/PchInfoLib.h>
+
+/**
+ Get Vpd binary address
+
+ Parse through each FV for VPD FFS file and return the address
+
+ @retval Address on VPD FFS detection else returns 0
+
+**/
+UINTN
+EFIAPI
+GetVpdFfsAddress (
+ )
+{
+ EFI_STATUS Status;
+ VOID *Address;
+ UINTN Instance;
+ EFI_PEI_FV_HANDLE VolumeHandle;
+ EFI_PEI_FILE_HANDLE FileHandle;
+
+ Address = NULL;
+
+ VolumeHandle = NULL;
+ Instance = 0;
+ while (TRUE) {
+ //
+ // Traverse all firmware volume instances.
+ //
+ Status = PeiServicesFfsFindNextVolume (Instance, &VolumeHandle);
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+
+ FileHandle = NULL;
+ Status = PeiServicesFfsFindFileByName (&gVpdFfsGuid, VolumeHandle, &FileHandle);
+ if (!EFI_ERROR (Status)) {
+ //
+ // Search RAW section.
+ //
+ Status = PeiServicesFfsFindSectionData (EFI_SECTION_RAW, FileHandle, &Address);
+ if (!EFI_ERROR (Status)) {
+ return (UINTN)Address;
+ }
+ }
+
+ //
+ // Search the next volume.
+ //
+ Instance++;
+ }
+
+ DEBUG ((DEBUG_ERROR, " PEI get VPD address: %r\n", EFI_NOT_FOUND));
+ return 0;
+}
+
+/**
+ Alderlake P boards configuration init function for PEI pre-memory phase.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlPInitPreMem (
+ VOID
+ )
+{
+ UINTN VpdBaseAddress;
+
+ VpdBaseAddress = (UINTN) PcdGet64 (PcdVpdBaseAddress64); DEBUG
+ ((DEBUG_INFO, "VpdFfsAddress: %x\n", VpdBaseAddress)); if
+ (VpdBaseAddress == 0) {
+ VpdBaseAddress= (UINTN) GetVpdFfsAddress();
+ PcdSet64S (PcdVpdBaseAddress64,VpdBaseAddress);
+ DEBUG ((DEBUG_INFO, "VpdFfsAddress updated: %x\n",
+ VpdBaseAddress)); } PcdSet32S (PcdStackBase, PcdGet32
+ (PcdTemporaryRamBase) + PcdGet32 (PcdTemporaryRamSize) - (PcdGet32
+ (PcdFspTemporaryRamSize) + PcdGet32 (PcdFspReservedBufferSize)));
+ PcdSet32S (PcdStackSize, PcdGet32 (PcdFspTemporaryRamSize));
+
+ return EFI_SUCCESS;
+}
+
+
+VOID
+AdlPMrcConfigInit (
+ VOID
+ );
+
+VOID
+AdlPSaMiscConfigInit (
+ VOID
+ );
+
+VOID
+AdlPSaDisplayConfigInit (
+ VOID
+ );
+
+EFI_STATUS
+AdlPRootPortClkInfoInit (
+ VOID
+ );
+
+VOID
+AdlPGpioGroupTierInit (
+ VOID
+ );
+
+
+/**
+ A hook for board-specific initialization prior to memory initialization.
+
+ @retval EFI_SUCCESS The board initialization was successful.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeMemoryInit (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "AdlPBoardInitBeforeMemoryInit\n"));
+
+ AdlPInitPreMem ();
+
+ AdlPGpioGroupTierInit ();
+
+ AdlPMrcConfigInit ();
+ AdlPSaMiscConfigInit ();
+ Status = AdlPRootPortClkInfoInit ();
+ AdlPSaDisplayConfigInit ();
+ if (PcdGetPtr (PcdBoardGpioTableEarlyPreMem) != 0) {
+ GpioInit (PcdGetPtr (PcdBoardGpioTableEarlyPreMem));
+
+ MicroSecondDelay (15 * 1000); // 15 ms Delay } // Configure GPIO
+ Before Memory GpioInit (PcdGetPtr (PcdBoardGpioTablePreMem));
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This board service initializes board-specific debug devices.
+
+ @retval EFI_SUCCESS Board-specific debug initialization was successful.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardDebugInit (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "AdlPBoardDebugInit\n"));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This board service detects the boot mode.
+
+ @retval EFI_BOOT_MODE The boot mode.
+**/
+EFI_BOOT_MODE
+EFIAPI
+AdlPBoardBootModeDetect (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "AdlPBoardBootModeDetect\n"));
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c
new file mode 100644
index 0000000000..aa9809d126
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiMultiBoardInitPostMemLib.c
@@ -0,0 +1,45 @@
+/** @file
+ PEI Multi-Board Initialization in Post-Memory PEI Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeSiliconInit (
+ VOID
+ );
+
+
+BOARD_POST_MEM_INIT_FUNC mAdlPBoardInitFunc = {
+ AdlPBoardInitBeforeSiliconInit,
+ NULL,
+};
+
+EFI_STATUS
+EFIAPI
+PeiAdlPMultiBoardInitLibConstructor (
+ VOID
+ )
+{
+ UINT8 SkuType;
+ SkuType = PcdGet8 (PcdSkuType);
+
+ if (SkuType==AdlPSkuType) {
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ return RegisterBoardPostMemInit (&mAdlPBoardInitFunc);
+ }
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf
new file mode 100644
index 0000000000..a4dbc9294d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiMultiBoardInitPostMemLib.inf
@@ -0,0 +1,53 @@
+## @file
+# Component information file for Alderlake Multi-Board Initialization in PEI post memory phase.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiAdlPMultiBoardInitLib
+ FILE_GUID = C7D39F17-E5BA-41D9-8DFE-FF9017499280
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = PeiAdlPMultiBoardInitLibConstructor
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PcdLib
+ MultiBoardInitSupportLib
+ PciSegmentLib
+ GpioLib
+ HobLib
+ BoardConfigLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ SecurityPkg/SecurityPkg.dec
+
+[Sources]
+ PeiInitPostMemLib.c
+ PeiMultiBoardInitPostMemLib.c
+
+[Pcd]
+ # Board GPIO Table
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
+
+ # TPM interrupt
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable ## CONSUMES
+ #Misc Config
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId
+
+ gBoardModuleTokenSpaceGuid.PcdBoardId
+ gBoardModuleTokenSpaceGuid.PcdSkuType
+ gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c
new file mode 100644
index 0000000000..fa45e86ac2
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiMultiBoardInitPreMemLib.c
@@ -0,0 +1,89 @@
+/** @file
+ PEI Multi-Board Initialization in Pre-Memory PEI Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BoardConfigLib.h>
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+AdlPBoardDetect (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+AdlPMultiBoardDetect (
+ VOID
+ );
+
+EFI_BOOT_MODE
+EFIAPI
+AdlPBoardBootModeDetect (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+AdlPBoardDebugInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeMemoryInit (
+ VOID
+ );
+
+BOARD_DETECT_FUNC mAdlPBoardDetectFunc = {
+ AdlPMultiBoardDetect
+};
+
+BOARD_PRE_MEM_INIT_FUNC mAdlPBoardPreMemInitFunc = {
+ AdlPBoardDebugInit,
+ AdlPBoardBootModeDetect,
+ AdlPBoardInitBeforeMemoryInit,
+ NULL, // BoardInitAfterMemoryInit
+ NULL, // BoardInitBeforeTempRamExit
+ NULL, // BoardInitAfterTempRamExit
+};
+
+EFI_STATUS
+EFIAPI
+AdlPMultiBoardDetect (
+ VOID
+ )
+{
+ UINT8 SkuType;
+ DEBUG ((DEBUG_INFO, " In AdlPMultiBoardDetect \n"));
+
+ AdlPBoardDetect ();
+
+ SkuType = PcdGet8 (PcdSkuType);
+ if (SkuType==AdlPSkuType) {
+ RegisterBoardPreMemInit (&mAdlPBoardPreMemInitFunc);
+ } else {
+ DEBUG ((DEBUG_WARN,"Not a Valid Alderlake P Board\n"));
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+PeiAdlPMultiBoardInitPreMemLibConstructor (
+ VOID
+ )
+{
+ return RegisterBoardDetect (&mAdlPBoardDetectFunc); }
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf
new file mode 100644
index 0000000000..ea2b64050d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiMultiBoardInitPreMemLib.inf
@@ -0,0 +1,149 @@
+## @file
+# Component information file for PEI Alderlake P Board Init Pre-Mem
+Library #
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiAdlPMultiBoardInitPreMemLib
+ FILE_GUID = EA05BD43-136F-45EE-BBBA-27D75817574F
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = PeiAdlPMultiBoardInitPreMemLibConstructor
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PcdLib
+ MultiBoardInitSupportLib
+ PeiLib
+ BoardConfigLib
+ PchInfoLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+
+[Sources]
+ PeiInitPreMemLib.c
+ PeiMultiBoardInitPreMemLib.c
+ PeiDetect.c
+ BoardSaInitPreMemLib.c
+ BoardPchInitPreMemLib.c
+
+[Pcd]
+ # SA Misc Config
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
+
+ # SPD Address Table
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable4
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable5
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable6
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable7
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable8
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable9
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable10
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable11
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable12
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable13
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable14
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable15
+
+ #MRC Config
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2DramSize
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2Dram
+ gBoardModuleTokenSpaceGuid.PcdMrcLp5CccConfig
+ gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd
+
+ #Board Information
+ gBoardModuleTokenSpaceGuid.PcdSpdPresent
+ gBoardModuleTokenSpaceGuid.PcdBoardRev
+ gBoardModuleTokenSpaceGuid.PcdBoardId
+ gBoardModuleTokenSpaceGuid.PcdSkuType
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
+ gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem
+ gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcDqsMapCpu2Dram
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcDqMapCpu2Dram
+
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES
+
+ gBoardModuleTokenSpaceGuid.PcdStackBase
+ gBoardModuleTokenSpaceGuid.PcdStackSize
+
+ #SA GPIO Config
+ gBoardModuleTokenSpaceGuid.PcdRootPortIndex
+
+ # PCIe Clock Info
+ gBoardModuleTokenSpaceGuid.PcdPcieClock0
+ gBoardModuleTokenSpaceGuid.PcdPcieClock1
+ gBoardModuleTokenSpaceGuid.PcdPcieClock2
+ gBoardModuleTokenSpaceGuid.PcdPcieClock3
+ gBoardModuleTokenSpaceGuid.PcdPcieClock4
+ gBoardModuleTokenSpaceGuid.PcdPcieClock5
+ gBoardModuleTokenSpaceGuid.PcdPcieClock6
+ gBoardModuleTokenSpaceGuid.PcdPcieClock7
+ gBoardModuleTokenSpaceGuid.PcdPcieClock8
+ gBoardModuleTokenSpaceGuid.PcdPcieClock9
+ gBoardModuleTokenSpaceGuid.PcdPcieClock10
+ gBoardModuleTokenSpaceGuid.PcdPcieClock11
+ gBoardModuleTokenSpaceGuid.PcdPcieClock12
+ gBoardModuleTokenSpaceGuid.PcdPcieClock13
+ gBoardModuleTokenSpaceGuid.PcdPcieClock14
+ gBoardModuleTokenSpaceGuid.PcdPcieClock15
+
+
+ # GPIO Group Tier
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2
+
+
+
+ # WWAN Full Card Power Off and reset pins
+ gBoardModuleTokenSpaceGuid.PcdDisableVpdGpioTable
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem ## PRODUCES
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem ## PRODUCES
+
+
+ # Display DDI
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## PRODUCES
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress64 ## CONSUMES
+
+[Guids]
+ gFspNonVolatileStorageHobGuid
+ gEfiMemoryOverwriteControlDataGuid
+ gVpdFfsGuid
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
--
2.36.1.windows.1
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [edk2-devel] [PATCH v2 4/6] AlderlakeOpenBoardPkg: Add ACPI module
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 4/6] AlderlakeOpenBoardPkg: Add ACPI module Saloni Kasbekar
@ 2023-08-02 20:25 ` Chaganty, Rangasai V
2023-08-04 0:48 ` Chuang, Rosen
1 sibling, 0 replies; 18+ messages in thread
From: Chaganty, Rangasai V @ 2023-08-02 20:25 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Oram, Isaac W, Chuang, Rosen
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Tuesday, August 01, 2023 3:18 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 4/6] AlderlakeOpenBoardPkg: Add ACPI module
Adds the MinDsdt driver
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Acpi/MinDsdt/MinDsdt.asl | 68 +++++
.../Acpi/MinDsdt/MinDsdt.c | 232 ++++++++++++++++++
.../Acpi/MinDsdt/MinDsdt.inf | 48 ++++
3 files changed, 348 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl
new file mode 100644
index 0000000000..be110145bc
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl
@@ -0,0 +1,68 @@
+/** @file
+ ACPI minimum DSDT table
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+DefinitionBlock (
+ "DSDT.aml",
+ "DSDT",
+ 0x01, // DSDT revision.
+ // A Revision field value greater than or equal to 2 signifies that integers
+ // declared within the Definition Block are to be evaluated as 64-bit values
+ "INTEL ", // OEM ID (6 byte string)
+ "MIN ",// OEM table ID (8 byte string)
+ 0x00 // OEM version of DSDT table (4 byte Integer)
+)
+
+// BEGIN OF ASL SCOPE
+{
+ Scope(\_SB) {
+
+//---------------------------------------------------------------------
+------
+ // Begin PCI tree object scope
+ //---------------------------------------------------------------------------
+ Device(PCI0) { // PCI Bridge "Host Bridge"
+ Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy
+ Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't understand the new HID
+ Name(_SEG, 0)
+ Method(^BN00, 0){ return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope
+ Method(_BBN, 0){ return(BN00()) } // Bus number, optional for the Root PCI Bus
+ Name(_UID, 0x0000) // Unique Bus ID, optional
+ Name(BUF0,ResourceTemplate()
+ {
+ //
+ // PCI Configuration Registers ( 0x0CF8 - 0x0CFF )
+ //
+ Io(Decode16,0x0CF8,0x0CF8,1,0x08)
+ //
+ // PCI MMIO space
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
+ ReadWrite,0x00,0x00,0x00,0x00,0x00,,,PM01)
+ })
+ Method(_CRS,0,Serialized)
+ {
+ //
+ // Create pointers to Memory Sizing values.
+ //
+ CreateDwordField(BUF0, ^PM01._MIN,M1MN)
+ CreateDwordField(BUF0, ^PM01._MAX,M1MX)
+ CreateDwordField(BUF0, ^PM01._LEN,M1LN)
+
+ //
+ // Set Memory Size Values. TLUD represents bits 31:20 of phyical
+ // TOM, so shift these bits into the correct position and fix up
+ // the Memory Region available to PCI.
+ //
+ Subtract (FixedPcdGet32(PcdPciReservedMemLimit),FixedPcdGet32(PcdPciReservedMemBase),M1LN)
+ Store (FixedPcdGet32(PcdPciReservedMemBase), M1MN)
+ Subtract (FixedPcdGet32(PcdPciReservedMemLimit), 1, M1MX)
+
+ Return(BUF0)
+ }
+ }
+ }
+}// End of ASL File
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c
new file mode 100644
index 0000000000..08709a43cd
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c
@@ -0,0 +1,232 @@
+/** @file
+ Min DSDT Driver
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <IndustryStandard/Acpi.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include <Protocol/FirmwareVolume2.h>
+#include <Protocol/AcpiTable.h>
+
+//
+// Function implementations
+//
+
+/**
+ Locate the first instance of a protocol. If the protocol requested
+is an
+ FV protocol, then it will return the first FV that contains the ACPI
+table
+ storage file.
+
+ @param[in] Protocol The protocol to find.
+ @param[in] FfsGuid The FFS that contains the ACPI table.
+ @param[out] Instance Return pointer to the first instance of the protocol.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NOT_FOUND The protocol could not be located.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.
+**/
+EFI_STATUS
+LocateSupportProtocol (
+ IN EFI_GUID *Protocol,
+ IN EFI_GUID *FfsGuid,
+ OUT VOID **Instance
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN NumberOfHandles;
+ EFI_FV_FILETYPE FileType;
+ UINT32 FvStatus;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINTN Size;
+ UINTN Index;
+
+ //
+ // Locate protocol.
+ //
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ Protocol,
+ NULL,
+ &NumberOfHandles,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // Defined errors at this time are not found and out of resources.
+ //
+ return Status;
+ }
+
+ //
+ // Looking for FV with ACPI storage file // for (Index = 0; Index <
+ NumberOfHandles; Index++) {
+
+ //
+ // Get the protocol on this handle
+ // This should not fail because of LocateHandleBuffer
+ //
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ Protocol,
+ Instance
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // See if it has the ACPI storage file
+ //
+ Size = 0;
+ FvStatus = 0;
+ Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile (
+ *Instance,
+ FfsGuid,
+ NULL,
+ &Size,
+ &FileType,
+ &Attributes,
+ &FvStatus
+ );
+
+ //
+ // If we found it, then we are done
+ //
+ if (Status == EFI_SUCCESS) {
+ break;
+ }
+ }
+
+ //
+ // Our exit status is determined by the success of the previous
+ operations // If the protocol was found, Instance already points to it.
+ //
+ //
+ // Free any allocated buffers
+ //
+ FreePool (HandleBuffer);
+
+ return Status;
+}
+
+/**
+ Publish ACPI table from FV.
+
+ @param[in] FfsGuid The FFS that contains the ACPI table.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+PublishAcpiTablesFromFv (
+ IN EFI_GUID *FfsGuid
+ )
+{
+ EFI_STATUS Status;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+ EFI_ACPI_COMMON_HEADER *CurrentTable;
+ UINT32 FvStatus;
+ UINTN Size;
+ UINTN TableHandle;
+ INTN Instance;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+
+ Instance = 0;
+ TableHandle = 0;
+ CurrentTable = NULL;
+ FwVol = NULL;
+
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID
+ **)&AcpiTable); ASSERT_EFI_ERROR (Status);
+
+ //
+ // Locate the firmware volume protocol // Status =
+ LocateSupportProtocol (
+ &gEfiFirmwareVolume2ProtocolGuid,
+ FfsGuid,
+ (VOID **) &FwVol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Read tables from the storage file.
+ //
+
+ while (Status == EFI_SUCCESS) {
+ Status = FwVol->ReadSection (
+ FwVol,
+ FfsGuid,
+ EFI_SECTION_RAW,
+ Instance,
+ (VOID **) &CurrentTable,
+ &Size,
+ &FvStatus
+ );
+
+ if (!EFI_ERROR (Status)) {
+
+ //
+ // Add the table
+ //
+ TableHandle = 0;
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ CurrentTable,
+ CurrentTable->Length,
+ &TableHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Increment the instance
+ //
+ Instance++;
+ CurrentTable = NULL;
+ }
+ }
+
+ //
+ // Finished
+ //
+ return EFI_SUCCESS;
+}
+
+/**
+ ACPI Platform driver installation function.
+
+ @param[in] ImageHandle Handle for this drivers loaded image protocol.
+ @param[in] SystemTable EFI system table.
+
+ @retval EFI_SUCCESS The driver installed without error.
+ @retval EFI_ABORTED The driver encountered an error and could not complete installation of
+ the ACPI tables.
+
+**/
+EFI_STATUS
+EFIAPI
+InstallMinDsdt (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = PublishAcpiTablesFromFv (&gEfiCallerIdGuid);
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf
new file mode 100644
index 0000000000..f257140754
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf
@@ -0,0 +1,48 @@
+### @file
+# Component information file for Minimal DSDT module #
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+# @par Glossary:
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = MinDsdt
+ FILE_GUID = 8EB04370-482C-4505-AA27-7EB226A5729F
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InstallMinDsdt
+
+[Sources.common]
+ MinDsdt.c
+ MinDsdt.asl
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ DebugLib
+ PcdLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ BaseMemoryLib
+ MemoryAllocationLib
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid ## CONSUMES
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+
+[Pcd]
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit
+
+[Depex]
+ gEfiAcpiTableProtocolGuid AND
+ gEfiFirmwareVolume2ProtocolGuid
+
--
2.36.1.windows.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [edk2-devel] [PATCH v2 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module Saloni Kasbekar
@ 2023-08-02 20:35 ` Chaganty, Rangasai V
2023-08-04 0:48 ` Chuang, Rosen
1 sibling, 0 replies; 18+ messages in thread
From: Chaganty, Rangasai V @ 2023-08-02 20:35 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Oram, Isaac W, Chuang, Rosen
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Tuesday, August 01, 2023 3:18 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module
Adds the following libraries within the Policy module
- DxeSiliconPolicyUpdateLib
- PeiPolicyUpdateLib
- PeiSiliconPolicyUpdateLib
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../DxeSaPolicyInit.c | 64 +++
.../DxeSiliconPolicyUpdateLate.c | 78 ++++
.../DxeSiliconPolicyUpdateLib.inf | 53 +++
.../PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c | 114 +++++
.../PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h | 31 ++
.../PeiCpuPolicyUpdatePreMem.c | 93 +++++
.../PeiPolicyUpdateLib/PeiPchPolicyUpdate.c | 210 ++++++++++
.../PeiPolicyUpdateLib/PeiPchPolicyUpdate.h | 24 ++
.../PeiPchPolicyUpdatePreMem.c | 124 ++++++
.../PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf | 208 ++++++++++
.../PeiPolicyUpdateLib/PeiSaPolicyUpdate.c | 214 ++++++++++
.../PeiPolicyUpdateLib/PeiSaPolicyUpdate.h | 27 ++
.../PeiSaPolicyUpdatePreMem.c | 389 ++++++++++++++++++
.../PeiSiliconPolicyUpdateLib.inf | 65 +++
.../PeiSiliconPolicyUpdatePostMem.c | 39 ++
.../PeiSiliconPolicyUpdatePreMem.c | 37 ++
16 files changed, 1770 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
new file mode 100644
index 0000000000..da2f568e07
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
@@ -0,0 +1,64 @@
+/** @file
+ This file initialises and Installs GopPolicy Protocol.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/GraphicsInfoLib.h>
+#include <Protocol/SaPolicy.h>
+
+EFI_STATUS
+EFIAPI
+CreateSaDxeConfigBlocks (
+ IN OUT VOID **SaPolicy
+ );
+
+EFI_STATUS
+EFIAPI
+SaInstallPolicyProtocol (
+ IN EFI_HANDLE ImageHandle,
+ IN VOID *SaPolicy
+ );
+
+/**
+ Initialize SA DXE Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SaPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+ SA_POLICY_PROTOCOL *SaPolicy;
+
+ //
+ // Call CreateSaDxeConfigBlocks to create & initialize platform policy structure
+ // and get all Intel default policy settings.
+ //
+ Status = CreateSaDxeConfigBlocks (&SaPolicy);
+ DEBUG ((DEBUG_INFO, "SaPolicy->TableHeader.NumberOfBlocks = 0x%x\n ", SaPolicy->TableHeader.NumberOfBlocks));
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Install SaInstallPolicyProtocol.
+ // While installed, RC assumes the Policy is ready and finalized. So please
+ // update and override any setting before calling this function.
+ //
+ Status = SaInstallPolicyProtocol (ImageHandle, SaPolicy);
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
new file mode 100644
index 0000000000..11a9950124
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
@@ -0,0 +1,78 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+/**
+ Initialize SA DXE Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SaPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ );
+
+/**
+ Initilize Intel Silicon DXE Platform Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SiliconPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ );
+
+/**
+ Performs silicon late policy update.
+
+ The meaning of Policy is defined by silicon code.
+ It could be the raw data, a handle, a Protocol, etc.
+
+ The input Policy must be returned by SiliconPolicyDoneLate().
+
+ In FSP or non-FSP path, the board may use additional way to get
+ the silicon policy data field based upon the input Policy.
+
+ @param[in, out] Policy Pointer to policy.
+
+ @return the updated policy.
+**/
+VOID *
+EFIAPI
+SiliconPolicyUpdateLate (
+ IN OUT VOID *Policy
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+
+ //
+ // SystemAgent Dxe Platform Policy Initialization
+ //
+ Status = SaPolicyInitDxe (gImageHandle);
+ DEBUG ((DEBUG_INFO, "SystemAgent Dxe Platform Policy Initialization status: %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
new file mode 100644
index 0000000000..54b4d7b17d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
@@ -0,0 +1,53 @@
+## @file
+# Component information file for Silicon Policy Update Library
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = DxeSiliconUpdateLib
+ FILE_GUID = C523609D-E354-416B-B24F-33468D4BD21D
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconPolicyUpdateLib
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ PcdLib
+ DebugLib
+ UefiBootServicesTableLib
+ MemoryAllocationLib
+ DxeSaPolicyLib
+ UefiLib
+ ConfigBlockLib
+ GraphicsInfoLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ DxeSiliconPolicyUpdateLate.c
+ DxeSaPolicyInit.c
+
+[Pcd]
+ gBoardModuleTokenSpaceGuid.PcdIntelGopEnable
+ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid
+ gPlatformModuleTokenSpaceGuid.PcdSmbiosOemTypeFirmwareVersionInfo ## CONSUMES
+
+[Protocols]
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+ gSaPolicyProtocolGuid ## CONSUMES
+ gDxeSiPolicyProtocolGuid ## PRODUCES
+ gGopPolicyProtocolGuid ## PRODUCES
+
+[Depex]
+ gEfiVariableArchProtocolGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c
new file mode 100644
index 0000000000..1ee4bdd038
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c
@@ -0,0 +1,114 @@
+/** @file
+ CPU PEI Policy Update & initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+#include "PeiCpuPolicyUpdate.h"
+#include <Library/ConfigBlockLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/HobLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Library/Tpm12CommandLib.h>
+#include <Library/Tpm2CommandLib.h>
+#include <PolicyUpdateMacro.h>
+
+/*
+ Get the uCode region from PCD settings, and copy the patches to memory.
+ This function is used to replace CpuLocateMicrocodePatch due to that function can not works
+ with uCode update new design.
+ In current uCode update solution, there are some padding data between uCode patches,
+ the algorithm in CpuLocateMicrocodePatch can not handle this.
+ Besides that, in CpuLocateMicrocodePatch function, the scan algorithm just find the first
+ correct uCode patch which is not the highest version uCode.
+ This function just copy the uCode region to memory, and in later, the CpuMpInit driver
+ will load the correct patch for CPU.
+
+ @param[out] RegionAddress Pointer to the uCode array.
+ @param[out] RegionSize Size of the microcode FV.
+
+ @retval EFI_SUCCESS Find uCode patch region and success copy the data to memory.
+ @retval EFI_NOT_FOUND Something wrong with uCode region.
+ @retval EFI_OUT_OF_RESOUCES Memory allocation fail.
+ @retval EFI_INVALID_PARAMETER RegionAddres or RegionSize is NULL.
+
+*/
+EFI_STATUS
+SearchMicrocodeRegion (
+ OUT UINTN *RegionAddress,
+ OUT UINTN *RegionSize
+ )
+{
+ UINTN MicrocodeStart;
+ UINTN MicrocodeEnd;
+ UINT8 *MemoryBuffer;
+
+ if (RegionAddress == NULL || RegionSize == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *RegionAddress = 0;
+ *RegionSize = 0;
+
+ if ((FixedPcdGet32 (PcdFlashFvMicrocodeBase) == 0) || (FixedPcdGet32 (PcdFlashFvMicrocodeSize) == 0)) {
+ return EFI_NOT_FOUND;
+ }
+
+ MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeBase) + (UINTN) FixedPcdGet32 (PcdMicrocodeOffsetInFv);
+ MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeBase) + (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeSize);
+ *RegionSize = MicrocodeEnd - MicrocodeStart;
+
+ DEBUG ((DEBUG_INFO, "[SearchMicrocodeRegion]: Microcode Region Address = %x, Size = %d\n", MicrocodeStart, *RegionSize));
+
+ MemoryBuffer = AllocatePages (EFI_SIZE_TO_PAGES (*RegionSize));
+ ASSERT (MemoryBuffer != NULL);
+ if (MemoryBuffer == NULL) {
+ DEBUG ((DEBUG_ERROR, "Failed to allocate enough memory for Microcode Patch.\n"));
+ return EFI_OUT_OF_RESOURCES;
+ } else {
+ CopyMem (MemoryBuffer, (UINT8 *)MicrocodeStart, *RegionSize);
+ *RegionAddress = (UINTN)MemoryBuffer;
+ DEBUG ((DEBUG_INFO, "Copy whole uCode region to memory, address = %x, size = %d\n", RegionAddress, *RegionSize));
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function performs CPU PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicy (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ SI_POLICY_PPI *SiPolicyPpi;
+ CPU_CONFIG *CpuConfig;
+
+ DEBUG ((DEBUG_INFO, "Update PeiCpuPolicyUpdate Pos-Mem Start\n"));
+
+ SiPolicyPpi = NULL;
+ CpuConfig = NULL;
+
+ Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID *) &CpuConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = SearchMicrocodeRegion (
+ (UINTN *)&CpuConfig->MicrocodePatchAddress,
+ (UINTN *)&CpuConfig->MicrocodePatchRegionSize
+ );
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h
new file mode 100644
index 0000000000..b003481db0
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h
@@ -0,0 +1,31 @@
+/** @file
+ Header file for PEI CpuPolicyUpdate.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_CPU_POLICY_UPDATE_H_
+#define _PEI_CPU_POLICY_UPDATE_H_
+
+#include <PiPei.h>
+#include <Ppi/SiPolicy.h>
+#include <Ppi/Wdt.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <PlatformBoardId.h>
+#include <Library/BaseCryptLib.h>
+#include <Register/Cpuid.h>
+#include <Register/Msr.h>
+#include <Ppi/MasterBootMode.h>
+#include <Library/PeiServicesLib.h>
+#include "PeiPchPolicyUpdate.h"
+#include <Library/CpuPlatformLib.h>
+
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..b23e2ceceb
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c
@@ -0,0 +1,93 @@
+/** @file
+ This file is SampleCode of the library for Intel CPU PEI Policy initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "PeiCpuPolicyUpdate.h"
+#include <Library/ConfigBlockLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/FirmwareBootMediaLib.h>
+#include <Library/HobLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/PmcLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Library/SpiLib.h>
+#include <Ppi/Spi.h>
+#include <Register/CommonMsr.h>
+#include <Register/PchRegs.h>
+#include <PlatformBoardConfig.h>
+#include <PolicyUpdateMacro.h>
+
+#define GET_OCCUPIED_SIZE(ActualSize, Alignment) \
+ ((ActualSize) + (((Alignment) - ((ActualSize) & ((Alignment) - 1))) & ((Alignment) - 1)))
+
+
+/**
+ This function performs CPU PEI Policy initialization in Pre-memory.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ CPU_SECURITY_PREMEM_CONFIG *CpuSecurityPreMemConfig;
+ CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ UINT32 MaxLogicProcessors;
+ UINT16 BiosSize;
+ UINT16 BiosMemSizeInMb;
+ FW_BOOT_MEDIA_TYPE FwBootMediaType;
+ MSR_CORE_THREAD_COUNT_REGISTER MsrCoreThreadCount;
+ UINT8 AllCoreCount;
+ UINT8 AllSmallCoreCount;
+ UINT32 DisablePerCoreMask;
+
+ DEBUG ((DEBUG_INFO, "Update PeiCpuPolicyUpdate Pre-Mem Start\n"));
+
+ SiPreMemPolicyPpi = NULL;
+ CpuSecurityPreMemConfig = NULL;
+ CpuConfigLibPreMemConfig = NULL;
+ BiosSize = 0;
+ BiosMemSizeInMb = 0;
+ FwBootMediaType = FwBootMediaMax;
+ AllCoreCount = 0;
+ AllSmallCoreCount = 0;
+ DisablePerCoreMask = 0;
+
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuSecurityPreMemConfigGuid, (VOID *) &CpuSecurityPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPreMemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SkipStopPbet, CpuSecurityPreMemConfig->SkipStopPbet, FALSE);
+
+ SpiServiceInit ();
+ DEBUG ((DEBUG_INFO, "BIOS Guard PCD and Policy are disabled\n"));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.BiosGuard, CpuSecurityPreMemConfig->BiosGuard, CPU_FEATURE_DISABLE);
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.CpuRatio, CpuConfigLibPreMemConfig->CpuRatio, 0);
+
+ ///
+ /// Set PcdCpuMaxLogicalProcessorNumber to max number of logical processors enabled
+ /// Read MSR_CORE_THREAD_COUNT (0x35) to check the total active Threads
+ ///
+ MsrCoreThreadCount.Uint64 = AsmReadMsr64 (MSR_CORE_THREAD_COUNT);
+ MaxLogicProcessors = MsrCoreThreadCount.Bits.Threadcount;
+ DEBUG ((DEBUG_INFO, "MaxLogicProcessors = %d\n", MaxLogicProcessors));
+
+ PcdSetEx32S (&gUefiCpuPkgTokenSpaceGuid, PcdCpuMaxLogicalProcessorNumber, MaxLogicProcessors);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
new file mode 100644
index 0000000000..1c0cf6bee0
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
@@ -0,0 +1,210 @@
+/** @file
+ This file is SampleCode of the library for Intel PCH PEI Policy initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Guid/FmpCapsule.h>
+#include <Guid/GlobalVariable.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioConfig.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <ConfigBlock.h>
+#include <Ppi/Spi.h>
+#include <PlatformBoardConfig.h>
+#include <PolicyUpdateMacro.h>
+#include <SerialIoDevices.h>
+#include <Pins/GpioPinsVer2Lp.h>
+
+/**
+ This is helper function for getting I2C Pads Internal Termination settings from Pcd
+
+ @param[in] Index I2C Controller Index
+**/
+UINT8
+STATIC
+GetSerialIoI2cPadsTerminationFromPcd (
+ IN UINT8 Index
+ )
+{
+ switch (Index) {
+ case 0:
+ return PcdGet8 (PcdPchSerialIoI2c0PadInternalTerm);
+ case 1:
+ return PcdGet8 (PcdPchSerialIoI2c1PadInternalTerm);
+ case 2:
+ return PcdGet8 (PcdPchSerialIoI2c2PadInternalTerm);
+ case 3:
+ return PcdGet8 (PcdPchSerialIoI2c3PadInternalTerm);
+ case 4:
+ return PcdGet8 (PcdPchSerialIoI2c4PadInternalTerm);
+ case 5:
+ return PcdGet8 (PcdPchSerialIoI2c5PadInternalTerm);
+ case 6:
+ return PcdGet8 (PcdPchSerialIoI2c6PadInternalTerm);
+ case 7:
+ return PcdGet8 (PcdPchSerialIoI2c7PadInternalTerm);
+ default:
+ ASSERT (FALSE); // Invalid I2C Controller Index
+ }
+ return 0;
+}
+
+/**
+ This function performs PCH Serial IO Platform Policy initialization
+
+ @param[in] SiPolicy Pointer to SI_POLICY_PPI
+ @param[in] FspsUpd A VOID pointer
+**/
+VOID
+UpdateSerialIoConfig (
+ IN SI_POLICY_PPI *SiPolicy,
+ IN VOID *FspsUpd
+ )
+{
+ UINT8 Index;
+ SERIAL_IO_CONFIG *SerialIoConfig;
+ EFI_STATUS Status;
+
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOID *) &SerialIoConfig);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ //
+ // I2C
+ //
+ for (Index = 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PchSerialIoI2cPadsTermination[Index], SerialIoConfig->I2cDeviceConfig[Index].PadTermination, GetSerialIoI2cPadsTerminationFromPcd (Index));
+ }
+
+ if (IsPchP ()) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[0], SerialIoConfig->I2cDeviceConfig[0].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[1], SerialIoConfig->I2cDeviceConfig[1].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[2], SerialIoConfig->I2cDeviceConfig[2].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[3], SerialIoConfig->I2cDeviceConfig[3].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[4], SerialIoConfig->I2cDeviceConfig[4].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[5], SerialIoConfig->I2cDeviceConfig[5].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[6], SerialIoConfig->I2cDeviceConfig[6].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[7], SerialIoConfig->I2cDeviceConfig[7].Mode, 0);
+ }
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[0], SerialIoConfig->UartDeviceConfig[0].Mode, 2);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[1], SerialIoConfig->UartDeviceConfig[1].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[2], SerialIoConfig->UartDeviceConfig[2].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[3], SerialIoConfig->UartDeviceConfig[3].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[4], SerialIoConfig->UartDeviceConfig[4].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[5], SerialIoConfig->UartDeviceConfig[5].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[6], SerialIoConfig->UartDeviceConfig[6].Mode, 0);
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[0], SerialIoConfig->UartDeviceConfig[0].Attributes.AutoFlow, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[1], SerialIoConfig->UartDeviceConfig[1].Attributes.AutoFlow, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[2], SerialIoConfig->UartDeviceConfig[2].Attributes.AutoFlow, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[3], SerialIoConfig->UartDeviceConfig[3].Attributes.AutoFlow, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[4], SerialIoConfig->UartDeviceConfig[4].Attributes.AutoFlow, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[5], SerialIoConfig->UartDeviceConfig[5].Attributes.AutoFlow, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[6], SerialIoConfig->UartDeviceConfig[6].Attributes.AutoFlow, 0);
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[0], SerialIoConfig->UartDeviceConfig[0].PowerGating, 2);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[1], SerialIoConfig->UartDeviceConfig[1].PowerGating, 2);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[2], SerialIoConfig->UartDeviceConfig[2].PowerGating, 2);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[3], SerialIoConfig->UartDeviceConfig[3].PowerGating, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[4], SerialIoConfig->UartDeviceConfig[4].PowerGating, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[5], SerialIoConfig->UartDeviceConfig[5].PowerGating, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[6], SerialIoConfig->UartDeviceConfig[6].PowerGating, 0);
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[0], SerialIoConfig->UartDeviceConfig[0].DmaEnable, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[1], SerialIoConfig->UartDeviceConfig[1].DmaEnable, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[2], SerialIoConfig->UartDeviceConfig[2].DmaEnable, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[3], SerialIoConfig->UartDeviceConfig[3].DmaEnable, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[4], SerialIoConfig->UartDeviceConfig[4].DmaEnable, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[5], SerialIoConfig->UartDeviceConfig[5].DmaEnable, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[6], SerialIoConfig->UartDeviceConfig[6].DmaEnable, 0);
+
+}
+
+
+/**
+ Update PCIe Root Port Configuration
+
+ @param[in] SiPolicy Pointer to SI_POLICY_PPI
+ @param[in] FspsUpd Pointer to FspsUpd structure
+ // @param[in] PchSetup Pointer to PCH_SETUP buffer
+ // @param[in] SetupVariables Pointer to SETUP_DATA buffer
+**/
+VOID
+UpdatePcieRpConfig (
+ IN SI_POLICY_PPI *SiPolicy,
+ IN VOID *FspsUpd
+ )
+{
+ UINT8 Index;
+ EFI_STATUS Status;
+ PCH_PCIE_CONFIG *PchPcieConfig;
+ UINTN MaxPciePorts;
+
+ MaxPciePorts = GetPchMaxPciePortNum ();
+
+ PchPcieConfig = NULL;
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gPchPcieConfigGuid, (VOID *) &PchPcieConfig);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ //
+ // PCI express config
+ //
+ for (Index = 0; Index < MaxPciePorts; Index++) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpMaxPayload[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.MaxPayload, PchPcieMaxPayload256);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpPhysicalSlotNumber[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PhysicalSlotNumber, (UINT8) Index);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpClkReqDetect[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.ClkReqDetect, TRUE);
+ }
+}
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicy (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ VOID *FspsUpd;
+ SI_POLICY_PPI *SiPolicy;
+ VOID *FspmUpd;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ CPU_SECURITY_PREMEM_CONFIG *CpuSecurityPreMemConfig;
+
+ DEBUG ((DEBUG_INFO, "Update PeiPchPolicyUpdate Pos-Mem Start\n"));
+
+ FspsUpd = NULL;
+ FspmUpd = NULL;
+ SiPolicy = NULL;
+ CpuSecurityPreMemConfig = NULL;
+ SiPreMemPolicyPpi = NULL;
+
+ Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicy);
+ ASSERT_EFI_ERROR (Status);
+
+ UpdatePcieRpConfig (SiPolicy, FspsUpd);
+ UpdateSerialIoConfig (SiPolicy, FspsUpd);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h
new file mode 100644
index 0000000000..133660c59e
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h
@@ -0,0 +1,24 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_PCH_POLICY_UPDATE_H_
+#define _PEI_PCH_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <PiPei.h>
+#include <PlatformBoardId.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/ConfigBlockLib.h>
+#include <PlatformBoardConfig.h>
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..47ecd41b39
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
@@ -0,0 +1,124 @@
+/** @file
+ This file is SampleCode of the library for Intel PCH PEI Policy initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Guid/GlobalVariable.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <PolicyUpdateMacro.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <PchDmiConfig.h>
+
+VOID
+UpdatePcieClockInfo (
+ PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig,
+ IN VOID *FspmUpd,
+ UINTN Index,
+ UINT64 Data
+ )
+{
+ PCD64_BLOB Pcd64;
+
+ Pcd64.Blob = Data;
+ DEBUG ((DEBUG_INFO, "UpdatePcieClockInfo ClkIndex %x ClkUsage %x, Supported %x\n", Index, Pcd64.PcieClock.ClockUsage, Pcd64.PcieClock.ClkReqSupported));
+
+ UPDATE_POLICY (((FSPM_UPD *)FspmUpd)->FspmConfig.PcieClkSrcUsage[Index], PcieRpPreMemConfig->PcieClock[Index].Usage, (UINT8)Pcd64.PcieClock.ClockUsage);
+ UPDATE_POLICY (((FSPM_UPD *)FspmUpd)->FspmConfig.PcieClkSrcClkReq[Index], PcieRpPreMemConfig->PcieClock[Index].ClkReq, Pcd64.PcieClock.ClkReqSupported ? (UINT8)Index : 0xFF);
+}
+
+/**
+ Update PcieRp pre mem policies.
+
+ @param[in] SiPreMemPolicy Pointer to SI_PREMEM_POLICY_PPI
+ @param[in] FspsUpm Pointer to FSPM_UPD
+ @param[in] PchSetup Pointer to PCH_SETUP
+**/
+STATIC
+VOID
+UpdatePcieRpPreMemPolicy (
+ IN SI_PREMEM_POLICY_PPI *SiPreMemPolicy,
+ IN VOID *FspmUpd
+ )
+{
+ UINT32 RpIndex;
+ UINT32 RpEnabledMask;
+ PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig;
+ EFI_STATUS Status;
+
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfigGuid, (VOID *) &PcieRpPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ GET_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PcieRpEnableMask, PcieRpPreMemConfig->RpEnabledMask, RpEnabledMask);
+
+ for (RpIndex = 0; RpIndex < GetPchMaxPciePortNum (); RpIndex ++) {
+ RpEnabledMask |= (UINT32) (1 << RpIndex);
+ }
+ // RpEnabledMask value is related with Setup value, Need to check Policy Default
+ COMPARE_AND_UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PcieRpEnableMask, PcieRpPreMemConfig->RpEnabledMask, RpEnabledMask);
+
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 0, PcdGet64(PcdPcieClock0));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 1, PcdGet64(PcdPcieClock1));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 2, PcdGet64(PcdPcieClock2));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 3, PcdGet64(PcdPcieClock3));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 4, PcdGet64(PcdPcieClock4));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 5, PcdGet64(PcdPcieClock5));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 6, PcdGet64(PcdPcieClock6));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 7, PcdGet64(PcdPcieClock7));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 8, PcdGet64(PcdPcieClock8));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 9, PcdGet64(PcdPcieClock9));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 10, PcdGet64(PcdPcieClock10));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 11, PcdGet64(PcdPcieClock11));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 12, PcdGet64(PcdPcieClock12));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 13, PcdGet64(PcdPcieClock13));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 14, PcdGet64(PcdPcieClock14));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 15, PcdGet64(PcdPcieClock15));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 16, PcdGet64(PcdPcieClock16));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 17, PcdGet64(PcdPcieClock17));
+
+}
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ VOID *FspmUpd;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicy;
+
+ DEBUG ((DEBUG_INFO, "Update PeiPchPolicyUpdate Pre-Mem Start\n"));
+
+ FspmUpd = NULL;
+ SiPreMemPolicy = NULL;
+
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicy);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ UpdatePcieRpPreMemPolicy (SiPreMemPolicy, FspmUpd);
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
new file mode 100644
index 0000000000..844e4c9967
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
@@ -0,0 +1,208 @@
+### @file
+# Module Information file for PEI PolicyUpdateLib Library
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiPolicyUpdateLib
+ FILE_GUID = D42F5BB8-E0CE-47BD-8C52-476C79055FC6
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = PeiPolicyUpdateLib|PEIM PEI_CORE SEC
+
+[LibraryClasses]
+ HobLib
+ BaseCryptLib
+ CpuPlatformLib
+ IoLib
+ ConfigBlockLib
+ MemoryAllocationLib
+ PeiServicesTablePointerLib
+ PcdLib
+ Tpm2CommandLib
+ Tpm12CommandLib
+ Tpm2DeviceLib
+ Tpm12DeviceLib
+ BoardConfigLib
+ PciSegmentLib
+ SiPolicyLib
+ PeiServicesLib
+ FirmwareBootMediaLib
+ SpiLib
+ BmpSupportLib
+ PeiGetFvInfoLib
+ TimerLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ CryptoPkg/CryptoPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+
+[FixedPcd]
+ gBoardModuleTokenSpaceGuid.PcdDefaultBoardId ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdMchBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdGttMmAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress ## CONSUMES
+
+ gBoardModuleTokenSpaceGuid.PcdBoardId ## CONSUMES
+
+ # SA Misc Config
+ gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2Dram ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2DramSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcLp5CccConfig ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcCmdMirror ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMask ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMaskEcc ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaMiscDisableMrcRetrainingOnRtcPowerLoss ## CONSUMES
+
+ # Display DDI
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## CONSUMES
+
+ # PCIE RTD3 GPIO
+ gBoardModuleTokenSpaceGuid.PcdRootPortIndex ## CONSUMES
+
+ # SPD Address Table
+ gBoardModuleTokenSpaceGuid.PcdSpdPresent ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable4 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable5 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable6 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable7 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable8 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable9 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable10 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable11 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable12 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable13 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable14 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable15 ## CONSUMES
+
+
+ # PCIe Clock Info
+ gBoardModuleTokenSpaceGuid.PcdPcieClock0 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock1 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock2 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock3 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock4 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock5 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock6 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock7 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock8 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock9 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock10 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock11 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock12 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock13 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock14 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock15 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock16 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock17 ## CONSUMES
+
+
+ # Pch SerialIo I2c Pads Termination
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c6PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c7PadInternalTerm ## CONSUMES
+
+ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem ## CONSUMES
+
+[Sources]
+ PeiPchPolicyUpdatePreMem.c
+ PeiPchPolicyUpdate.c
+ PeiCpuPolicyUpdatePreMem.c
+ PeiCpuPolicyUpdate.c
+ PeiSaPolicyUpdate.c
+ PeiSaPolicyUpdatePreMem.c
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+ gWdtPpiGuid ## CONSUMES
+ gPchSpiPpiGuid ## CONSUMES
+ gSiPolicyPpiGuid ## CONSUMES
+ gSiPreMemPolicyPpiGuid ## CONSUMES
+ gFspmArchConfigPpiGuid ## PRODUCES
+ gReadyForGopConfigPpiGuid ## PRODUCES
+ gPeiGraphicsPlatformPpiGuid ## CONSUMES
+ gPeiGraphicsFramebufferReadyPpiGuid ## CONSUMES
+
+[Guids]
+ gEfiGlobalVariableGuid ## CONSUMES
+ gMemoryConfigVariableGuid ## CONSUMES
+ gEfiCapsuleVendorGuid ## CONSUMES
+ gEfiMemoryTypeInformationGuid ## CONSUMES
+ gEfiMemoryOverwriteControlDataGuid ## CONSUMES
+ gSiPreMemConfigGuid ## CONSUMES
+ gSiConfigGuid ## CONSUMES
+ gCpuSecurityPreMemConfigGuid ## CONSUMES
+ gCpuConfigLibPreMemConfigGuid ## CONSUMES
+ gCpuConfigGuid ## CONSUMES
+ gVmdPeiConfigGuid ## CONSUMES
+ gCpuPcieRpPrememConfigGuid ## CONSUMES
+ gVmdInfoHobGuid ## CONSUMES
+ gPciePreMemConfigGuid ## CONSUMES
+ gPlatformInitFvLocationGuid ## CONSUMES
+ gHostBridgePeiPreMemConfigGuid ## CONSUMES
+ gEfiGraphicsInfoHobGuid ## CONSUMES
+ gPchDmiPreMemConfigGuid ## CONSUMES
+ gGraphicsPeiConfigGuid ## CONSUMES
+ gMemoryConfigGuid ## CONSUMES
+ gMemoryConfigNoCrcGuid ## CONSUMES
+ gPchPcieConfigGuid ## CONSUMES
+ gSerialIoConfigGuid ## CONSUMES
+ gPcieRpPreMemConfigGuid ## CONSUMES
+ gSaMiscPeiPreMemConfigGuid ## CONSUMES
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c
new file mode 100644
index 0000000000..c62b0a14ef
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c
@@ -0,0 +1,214 @@
+/** @file
+Do Platform Stage System Agent initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/BmpSupportLib.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiGetFvInfoLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Protocol/GraphicsOutput.h>
+
+#include <CpuPcieConfig.h>
+#include <CpuPcieHob.h>
+#include <IndustryStandard/Bmp.h>
+#include <PolicyUpdateMacro.h>
+#include <Guid/GraphicsInfoHob.h>
+
+#include <VmdPeiConfig.h>
+#include <Ppi/GraphicsPlatformPolicyPpi.h>
+
+
+EFI_STATUS
+EFIAPI
+PeiGraphicsPolicyUpdateCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_GRAPHICS_INFO_HOB *PlatformGraphicsOutput;
+ EFI_PEI_HOB_POINTERS Hob;
+ UINT8 *HobStart;
+ GRAPHICS_PEI_CONFIG *GtConfig;
+ SI_POLICY_PPI *SiPolicyPpi;
+
+ PlatformGraphicsOutput = NULL;
+ HobStart = NULL;
+
+ GtConfig = NULL;
+ SiPolicyPpi = NULL;
+ Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *) &GtConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
+ HobStart = Hob.Raw;
+
+ if (!EFI_ERROR (Status)) {
+ if (HobStart != NULL) {
+ if ((Hob.Raw = GetNextGuidHob (&gEfiGraphicsInfoHobGuid, HobStart)) != NULL) {
+ DEBUG ((DEBUG_INFO, "Found EFI_PEI_GRAPHICS_INFO_HOB\n"));
+ PlatformGraphicsOutput = GET_GUID_HOB_DATA (Hob.Guid);
+ }
+ }
+ }
+
+ if (PlatformGraphicsOutput != NULL) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.HorizontalResolution, GtConfig->HorizontalResolution, PlatformGraphicsOutput->GraphicsMode.HorizontalResolution);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.VerticalResolution, GtConfig->VerticalResolution, PlatformGraphicsOutput->GraphicsMode.VerticalResolution);
+ } else {
+ DEBUG ((DEBUG_INFO, "Not able to find EFI_PEI_GRAPHICS_INFO_HOB\n"));
+ }
+
+ return Status;
+}
+
+STATIC
+EFI_PEI_NOTIFY_DESCRIPTOR mPeiGfxPolicyUpdateNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gPeiGraphicsFramebufferReadyPpiGuid,
+ PeiGraphicsPolicyUpdateCallback
+};
+
+/**
+ UpdatePeiSaPolicy performs SA PEI Policy initialization
+
+ @retval EFI_SUCCESS The policy is installed and initialized.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicy (
+ VOID
+ )
+{
+ EFI_GUID BmpImageGuid;
+ EFI_STATUS Status;
+ EFI_GUID FileGuid;
+ VOID *Buffer;
+ UINT32 Size;
+ VOID *VmdVariablePtr;
+ GRAPHICS_PEI_CONFIG *GtConfig;
+ SI_POLICY_PPI *SiPolicyPpi;
+ CPU_PCIE_CONFIG *CpuPcieRpConfig;
+ VMD_PEI_CONFIG *VmdPeiConfig;
+ EFI_PEI_PPI_DESCRIPTOR *ReadyForGopConfigPpiDesc;
+ VOID *VbtPtr;
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Blt;
+ UINTN BltSize;
+ UINTN Height;
+ UINTN Width;
+
+ DEBUG ((DEBUG_INFO, "Update PeiSaPolicyUpdate Pos-Mem Start\n"));
+
+ Size = 0;
+ Blt = NULL;
+ BltSize = 0;
+
+ GtConfig = NULL;
+ SiPolicyPpi = NULL;
+ CpuPcieRpConfig = NULL;
+ VmdVariablePtr = NULL;
+ Buffer = NULL;
+
+ Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *) &GtConfig);
+ ASSERT_EFI_ERROR(Status);
+
+
+
+ VmdPeiConfig = NULL;
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gVmdPeiConfigGuid, (VOID *) &VmdPeiConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ CopyMem(&BmpImageGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid), sizeof(BmpImageGuid));
+
+ if (!EFI_ERROR (Status)) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SkipFspGop, GtConfig->SkipFspGop, 0x0);
+ Buffer = NULL;
+
+ CopyMem(&FileGuid, &BmpImageGuid, sizeof(FileGuid));
+ PeiGetSectionFromFv(FileGuid, &Buffer, &Size);
+ if (Buffer == NULL) {
+ DEBUG((DEBUG_ERROR, "Could not locate VBT\n"));
+ }
+
+ GtConfig->GraphicsConfigPtr = Buffer;
+ DEBUG ((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", GtConfig->GraphicsConfigPtr));
+ DEBUG ((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size));
+ GET_POLICY ((VOID *) ((FSPS_UPD *) FspsUpd)->FspsConfig.GraphicsConfigPtr, GtConfig->GraphicsConfigPtr, VbtPtr);
+
+ //
+ // Install ReadyForGopConfig PPI to trigger PEI phase GopConfig callback.
+ //
+ ReadyForGopConfigPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+ if (ReadyForGopConfigPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+ ReadyForGopConfigPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ ReadyForGopConfigPpiDesc->Guid = &gReadyForGopConfigPpiGuid;
+ ReadyForGopConfigPpiDesc->Ppi = VbtPtr;
+ Status = PeiServicesInstallPpi (ReadyForGopConfigPpiDesc);
+
+ Status = TranslateBmpToGopBlt (
+ Buffer,
+ Size,
+ &Blt,
+ &BltSize,
+ &Height,
+ &Width
+ );
+
+ if (Status == EFI_BUFFER_TOO_SMALL) {
+ Blt = NULL;
+ Status = TranslateBmpToGopBlt (
+ Buffer,
+ Size,
+ &Blt,
+ &BltSize,
+ &Height,
+ &Width
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "TranslateBmpToGopBlt, Status = %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+ }
+
+ //
+ // Initialize Blt, BltSize
+ //
+ GtConfig->BltBufferAddress = Blt;
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.BltBufferSize, GtConfig->BltBufferSize, BltSize);
+
+ DEBUG ((DEBUG_INFO, "Calling mPeiGfxPolicyUpdateNotifyList\n"));
+ Status = PeiServicesNotifyPpi (&mPeiGfxPolicyUpdateNotifyList);
+
+ }
+
+ //
+ // VMD related settings from setup variable
+ //
+ COMPARE_AND_UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.VmdEnable, VmdPeiConfig->VmdEnable, 0);
+ VmdPeiConfig->VmdVariablePtr = VmdVariablePtr;
+ DEBUG ((DEBUG_INFO, "VmdVariablePtr from PeiGetSectionFromFv is 0x%x\n", VmdVariablePtr));
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h
new file mode 100644
index 0000000000..64f97b672b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h
@@ -0,0 +1,27 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_SA_POLICY_UPDATE_H_
+#define _PEI_SA_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <Ppi/SiPolicy.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <Ppi/Wdt.h>
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+#include "PeiPchPolicyUpdate.h"
+#include <Library/PcdLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/SiPolicyLib.h>
+
+#define WDT_TIMEOUT 60
+
+#endif
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..a4ceda76c3
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
@@ -0,0 +1,389 @@
+/** @file
+Do Platform Stage System Agent initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include "MemoryConfig.h"
+#include <Guid/MemoryOverwriteControl.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/GpioLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Register/CommonMsr.h>
+#include <Register/Cpuid.h>
+#include <Register/Msr.h>
+#include <CpuRegs.h>
+#include <HostBridgeConfig.h>
+#include <PlatformBoardConfig.h>
+#include <PolicyUpdateMacro.h>
+#include <SaDataHob.h>
+#include <Ppi/FspmArchConfigPpi.h>
+
+///
+/// Memory Reserved should be between 125% to 150% of the Current required memory
+/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resume issues.
+///
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
+ { EfiACPIReclaimMemory, FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemorySize) }, // ASL
+ { EfiACPIMemoryNVS, FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize) }, // ACPI NVS (including S3 related)
+ { EfiReservedMemoryType, FixedPcdGet32 (PcdPlatformEfiReservedMemorySize) }, // BIOS Reserved (including S3 related)
+ { EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize) }, // Runtime Service Data
+ { EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize) }, // Runtime Service Code
+ { EfiMaxMemoryType, 0 }
+};
+
+#define PEI_MIN_MEMORY_SIZE (10 * 0x800000) // 80MB
+
+/**
+ UpdatePeiSaPolicyPreMem performs SA PEI Policy initialization
+
+ @retval EFI_SUCCESS The policy is installed and initialized.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
+ UINTN VariableSize;
+ SA_MEMORY_RCOMP *RcompData;
+ WDT_PPI *gWdtPei;
+ UINT8 WdtTimeout;
+
+ UINT8 Index;
+ UINTN DataSize;
+ EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1];
+ EFI_BOOT_MODE BootMode;
+ UINT8 MorControl;
+ UINT64 PlatformMemorySize;
+ VOID *MemorySavedData;
+ VOID *NullSpdPtr;
+ UINT32 RpEnabledMask;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ MEMORY_CONFIGURATION *MemConfig;
+ SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
+ MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;
+ EFI_PEI_PPI_DESCRIPTOR *FspmArchConfigPpiDesc;
+ FSPM_ARCH_CONFIG_PPI *FspmArchConfigPpi;
+ HOST_BRIDGE_PREMEM_CONFIG *HostBridgePreMemConfig;
+ UINT16 AdjustedMmioSize;
+ UINT8 SaDisplayConfigTable[16];
+ EFI_BOOT_MODE SysBootMode;
+ UINT32 ProcessorTraceTotalMemSize;
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
+ UINT32 CapsuleSupportMemSize;
+
+ DEBUG ((DEBUG_INFO, "Update PeiSaPolicyUpdate Pre-Mem Start\n"));
+ ZeroMem ((VOID*) SaDisplayConfigTable, sizeof (SaDisplayConfigTable));
+ WdtTimeout = 0;
+ SysBootMode = 0;
+ RcompData = NULL;
+ PlatformMemorySize = 0;
+ RpEnabledMask = 0;
+ SiPreMemPolicyPpi = NULL;
+ MemConfig = NULL;
+ MemConfigNoCrc = NULL;
+
+
+ MiscPeiPreMemConfig = NULL;
+ HostBridgePreMemConfig = NULL;
+ FspmArchConfigPpi = NULL;
+
+ ProcessorTraceTotalMemSize = 0;
+ CapsuleSupportMemSize = 0;
+
+ AdjustedMmioSize = PcdGet16 (PcdSaMiscMmioSizeAdjustment);
+
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gHostBridgePeiPreMemConfigGuid, (VOID *) &HostBridgePreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigGuid, (VOID *) &MemConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);
+ ASSERT_EFI_ERROR(Status);
+
+ RcompData = MemConfigNoCrc->RcompData;
+
+ //
+ // Locate system configuration variable
+ //
+ Status = PeiServicesLocatePpi(
+ &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
+ 0, // INSTANCE
+ NULL, // EFI_PEI_PPI_DESCRIPTOR
+ (VOID **) &VariableServices // PPI
+ );
+ ASSERT_EFI_ERROR(Status);
+
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Initialize S3 Data variable (S3DataPtr)
+ //
+ VariableSize = 0;
+ MemorySavedData = NULL;
+ Status = VariableServices->GetVariable (
+ VariableServices,
+ L"MemoryConfig",
+ &gMemoryConfigVariableGuid,
+ NULL,
+ &VariableSize,
+ MemorySavedData
+ );
+ if (Status == EFI_BUFFER_TOO_SMALL) {
+ MemorySavedData = AllocateZeroPool (VariableSize);
+ ASSERT (MemorySavedData != NULL);
+
+ Status = VariableServices->GetVariable (
+ VariableServices,
+ L"MemoryConfig",
+ &gMemoryConfigVariableGuid,
+ NULL,
+ &VariableSize,
+ MemorySavedData
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Fail to retrieve Variable: MemoryConfig, Status = %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+ FspmArchConfigPpi = (FSPM_ARCH_CONFIG_PPI *) AllocateZeroPool (sizeof (FSPM_ARCH_CONFIG_PPI));
+ if (FspmArchConfigPpi == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+ FspmArchConfigPpi->Revision = 1;
+ FspmArchConfigPpi->NvsBufferPtr = MemorySavedData;
+ MiscPeiPreMemConfig->S3DataPtr = MemorySavedData;
+
+ FspmArchConfigPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+ if (FspmArchConfigPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+ FspmArchConfigPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ FspmArchConfigPpiDesc->Guid = &gFspmArchConfigPpiGuid;
+ FspmArchConfigPpiDesc->Ppi = FspmArchConfigPpi;
+
+ //
+ // Install FSP-M Arch Config PPI
+ //
+ Status = PeiServicesInstallPpi (FspmArchConfigPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+
+ VariableSize = sizeof (MorControl);
+ Status = VariableServices->GetVariable(
+ VariableServices,
+ MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME,
+ &gEfiMemoryOverwriteControlDataGuid,
+ NULL,
+ &VariableSize,
+ &MorControl
+ );
+ if (EFI_ERROR (Status)) {
+ MorControl = 0;
+ }
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.UserBd, MiscPeiPreMemConfig->UserBd, 0); // It's a CRB mobile board by default (btCRBMB)
+
+ MiscPeiPreMemConfig->TxtImplemented = 0;
+
+ if (PcdGet32 (PcdMrcRcompTarget)) {
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.RcompTarget, (VOID *)RcompData->RcompTarget, (VOID *)(UINTN)PcdGet32 (PcdMrcRcompTarget), sizeof (UINT16) * MRC_MAX_RCOMP_TARGETS);
+ }
+
+ if (PcdGetBool (PcdMrcDqPinsInterleavedControl)) {
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.DqPinsInterleaved, MemConfig->DqPinsInterleaved, PcdGetBool (PcdMrcDqPinsInterleaved));
+ }
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[0], MiscPeiPreMemConfig->SpdAddressTable[0], PcdGet8 (PcdMrcSpdAddressTable0));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[1], MiscPeiPreMemConfig->SpdAddressTable[1], PcdGet8 (PcdMrcSpdAddressTable1));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[2], MiscPeiPreMemConfig->SpdAddressTable[2], PcdGet8 (PcdMrcSpdAddressTable2));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[3], MiscPeiPreMemConfig->SpdAddressTable[3], PcdGet8 (PcdMrcSpdAddressTable3));
+ if (PcdGet8 (PcdMrcLp5CccConfig)) {
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.Lp5CccConfig, MemConfig->Lp5CccConfig, PcdGet8 (PcdMrcLp5CccConfig));
+ }
+
+
+ NullSpdPtr = AllocateZeroPool (SPD_DATA_SIZE);
+ ASSERT (NullSpdPtr != NULL);
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[4], MiscPeiPreMemConfig->SpdAddressTable[4], PcdGet8 (PcdMrcSpdAddressTable4));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[5], MiscPeiPreMemConfig->SpdAddressTable[5], PcdGet8 (PcdMrcSpdAddressTable5));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[6], MiscPeiPreMemConfig->SpdAddressTable[6], PcdGet8 (PcdMrcSpdAddressTable6));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[7], MiscPeiPreMemConfig->SpdAddressTable[7], PcdGet8 (PcdMrcSpdAddressTable7));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[8], MiscPeiPreMemConfig->SpdAddressTable[8], PcdGet8 (PcdMrcSpdAddressTable8));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[9], MiscPeiPreMemConfig->SpdAddressTable[9], PcdGet8 (PcdMrcSpdAddressTable9));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[10], MiscPeiPreMemConfig->SpdAddressTable[10], PcdGet8 (PcdMrcSpdAddressTable10));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[11], MiscPeiPreMemConfig->SpdAddressTable[11], PcdGet8 (PcdMrcSpdAddressTable11));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[12], MiscPeiPreMemConfig->SpdAddressTable[12], PcdGet8 (PcdMrcSpdAddressTable12));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[13], MiscPeiPreMemConfig->SpdAddressTable[13], PcdGet8 (PcdMrcSpdAddressTable13));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[14], MiscPeiPreMemConfig->SpdAddressTable[14], PcdGet8 (PcdMrcSpdAddressTable14));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[15], MiscPeiPreMemConfig->SpdAddressTable[15], PcdGet8 (PcdMrcSpdAddressTable15));
+ if (PcdGet32 (PcdMrcRcompResistor)) {
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.RcompResistor, RcompData->RcompResistor, (UINT8) PcdGet32 (PcdMrcRcompResistor));
+ }
+ if (PcdGet32 (PcdMrcDqsMapCpu2Dram)) {
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.DqsMapCpu2DramMc0Ch0, (VOID *)MemConfigNoCrc->DqDqsMap->DqsMapCpu2Dram, (VOID *)(UINTN)PcdGet32 (PcdMrcDqsMapCpu2Dram), sizeof (UINT8) * MEM_CFG_MAX_CONTROLLERS * MEM_CFG_MAX_CHANNELS * MEM_CFG_NUM_BYTES_MAPPED);
+ }
+ if (PcdGet32 (PcdMrcDqMapCpu2Dram)) {
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.DqMapCpu2DramMc0Ch0, (VOID *)MemConfigNoCrc->DqDqsMap->DqMapCpu2Dram, (VOID *)(UINTN)PcdGet32 (PcdMrcDqMapCpu2Dram), sizeof (UINT8) * MEM_CFG_MAX_CONTROLLERS * MEM_CFG_MAX_CHANNELS * MEM_CFG_NUM_BYTES_MAPPED * 8);
+ }
+ if (PcdGetBool (PcdSpdPresent)) {
+ // Clear SPD data so it can be filled in by the MRC init code
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr000, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][0][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr010, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][1][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr020, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][2][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr030, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][3][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr100, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][0][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr110, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][1][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr120, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][2][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr130, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][3][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ } else {
+ if (PcdGet32 (PcdMrcSpdData)) {
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr000, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr010, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr020, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][2][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr030, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][3][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr100, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr110, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr120, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][2][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr130, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][3][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ }
+ }
+
+ HostBridgePreMemConfig->MchBar = (UINTN) PcdGet64 (PcdMchBaseAddress);
+ HostBridgePreMemConfig->DmiBar = (UINTN) PcdGet64 (PcdDmiBaseAddress);
+ HostBridgePreMemConfig->EpBar = (UINTN) PcdGet64 (PcdEpBaseAddress);
+ HostBridgePreMemConfig->EdramBar = (UINTN) PcdGet64 (PcdEdramBaseAddress);
+ MiscPeiPreMemConfig->SmbusBar = (UINTN) PcdGet16 (PcdSmbusBaseAddress);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.TsegSize, MiscPeiPreMemConfig->TsegSize, PcdGet32 (PcdTsegSize));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.UserBd, MiscPeiPreMemConfig->UserBd, PcdGet8 (PcdSaMiscUserBd));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.DisableMrcRetrainingOnRtcPowerLoss,MiscPeiPreMemConfig->DisableMrcRetrainingOnRtcPowerLoss, PcdGet8(PcdSaMiscDisableMrcRetrainingOnRtcPowerLoss));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.MmioSizeAdjustment, HostBridgePreMemConfig->MmioSizeAdjustment, PcdGet16 (PcdSaMiscMmioSizeAdjustment));
+ //
+ // Display DDI Initialization ( default Native GPIO as per board during AUTO case)
+ //
+ CopyMem (SaDisplayConfigTable, (VOID *) (UINTN) PcdGet32 (PcdSaDisplayConfigTable), (UINTN)PcdGet16 (PcdSaDisplayConfigTableSize));
+
+ gWdtPei = NULL;
+ Status = PeiServicesLocatePpi(
+ &gWdtPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &gWdtPei
+ );
+ if (gWdtPei != NULL) {
+ WdtTimeout = gWdtPei->CheckStatus();
+ } else {
+ WdtTimeout = FALSE;
+ }
+
+ if ((WdtTimeout == FALSE)) {
+ //
+ // If USER custom profile is selected, we will start the WDT.
+ //
+ if (gWdtPei != NULL) {
+ Status = gWdtPei->ReloadAndStart(WDT_TIMEOUT);
+ }
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.VddVoltage, MemConfig->VddVoltage, 0); // Use platform default as the safe value.
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.VddqVoltage, MemConfig->VddqVoltage, 0); // Use platform default as the safe value.
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.VppVoltage, MemConfig->VppVoltage, 0); // Use platform default as the safe value.
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.Ratio, MemConfig->Ratio, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tCL, MemConfig->tCL, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tCWL, MemConfig->tCWL, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tFAW, MemConfig->tFAW, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRAS, MemConfig->tRAS, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRCDtRP, MemConfig->tRCDtRP, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tREFI, MemConfig->tREFI, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRFC, MemConfig->tRFC, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRRD, MemConfig->tRRD, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRTP, MemConfig->tRTP, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tWR, MemConfig->tWR, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tWTR, MemConfig->tWTR, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.NModeSupport, MemConfig->NModeSupport, 0);
+ }
+
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.CmdMirror, MemConfig->CmdMirror, PcdGet8 (PcdMrcCmdMirror)); // BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
+
+ // FirstDimmBitMask defines which DIMM should be populated first on a 2DPC board
+
+ COMPARE_AND_UPDATE_POLICY(((FSPM_UPD *)FspmUpd)->FspmConfig.FirstDimmBitMask, MemConfig->FirstDimmBitMask, PcdGet8(PcdSaMiscFirstDimmBitMask));
+ COMPARE_AND_UPDATE_POLICY(((FSPM_UPD *)FspmUpd)->FspmConfig.FirstDimmBitMaskEcc, MemConfig->FirstDimmBitMaskEcc, PcdGet8(PcdSaMiscFirstDimmBitMaskEcc));
+
+ //
+ // Update CleanMemory variable from Memory overwrite request value. Ignore if we are performing capsule update.
+ //
+ if ((BootMode != BOOT_ON_FLASH_UPDATE) && (BootMode != BOOT_ON_S3_RESUME)) {
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.CleanMemory, MemConfigNoCrc->CleanMemory, (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK));
+ }
+
+ DataSize = sizeof (MemoryData);
+ Status = VariableServices->GetVariable (
+ VariableServices,
+ EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
+ &gEfiMemoryTypeInformationGuid,
+ NULL,
+ &DataSize,
+ &MemoryData
+ );
+ ///
+ /// Accumulate maximum amount of memory needed
+ ///
+ PlatformMemorySize = MemConfigNoCrc->PlatformMemorySize;
+ AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, &Ebx.Uint32, NULL, NULL);
+
+ if (EFI_ERROR (Status)) {
+ ///
+ /// Use default value to avoid memory fragment.
+ /// OS boot/installation fails if there is not enough continuous memory available
+ ///
+ PlatformMemorySize = PEI_MIN_MEMORY_SIZE + ProcessorTraceTotalMemSize + CapsuleSupportMemSize;
+ DataSize = sizeof (mDefaultMemoryTypeInformation);
+ CopyMem (MemoryData, mDefaultMemoryTypeInformation, DataSize);
+ } else {
+ ///
+ /// Start with at least PEI_MIN_MEMORY_SIZE of memory for the DXE Core and the DXE Stack
+ ///
+ PlatformMemorySize = PEI_MIN_MEMORY_SIZE + ProcessorTraceTotalMemSize + CapsuleSupportMemSize;
+ }
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PlatformMemorySize, MemConfigNoCrc->PlatformMemorySize, PlatformMemorySize);
+
+ if (BootMode != BOOT_IN_RECOVERY_MODE) {
+ for (Index = 0; Index < DataSize / sizeof (EFI_MEMORY_TYPE_INFORMATION); Index++) {
+ PlatformMemorySize += MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE;
+ }
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PlatformMemorySize, MemConfigNoCrc->PlatformMemorySize, PlatformMemorySize);
+
+ ///
+ /// Build the GUID'd HOB for DXE
+ ///
+ BuildGuidDataHob (
+ &gEfiMemoryTypeInformationGuid,
+ MemoryData,
+ DataSize
+ );
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
new file mode 100644
index 0000000000..c2bdd599a8
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
@@ -0,0 +1,65 @@
+## @file
+# Provide Silicon policy update functionality.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SiliconPolicyUpdateLib
+ FILE_GUID = 34435831-33D7-4742-992F-3A3C7B860BC5
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconPolicyUpdateLib
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+################################################################################
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
+################################################################################
+
+[Sources]
+ PeiSiliconPolicyUpdatePreMem.c
+ PeiSiliconPolicyUpdatePostMem.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[LibraryClasses.IA32]
+ BaseMemoryLib
+ BaseLib
+ DebugLib
+ PeiServicesTablePointerLib
+ PeiServicesLib
+ PcdLib
+ PeiPolicyUpdateLib
+
+[FixedPcd]
+
+[Ppis]
+
+[Guids]
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c
new file mode 100644
index 0000000000..181b491c4c
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c
@@ -0,0 +1,39 @@
+/** @file
+ This file is SampleCode for Intel PEI Platform Policy initialization in post-memory.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+
+VOID
+EFIAPI
+SiliconPolicyUpdatePostMemFirmwareConfig (
+ VOID
+ )
+{
+ //
+ // Update and override all platform related and customized settings below.
+ //
+ UpdatePeiPchPolicy ();
+ UpdatePeiSaPolicy ();
+ UpdatePeiCpuPolicy ();
+}
+
+VOID *
+EFIAPI
+SiliconPolicyUpdatePostMem (
+ IN OUT VOID *Policy
+ )
+{
+ Policy = NULL;
+
+ SiliconPolicyUpdatePostMemFirmwareConfig ();
+
+ return Policy;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..42e6ac34c2
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c
@@ -0,0 +1,37 @@
+/** @file
+ This file is SampleCode for Intel PEI Platform Policy initialization in pre-memory.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+
+VOID
+EFIAPI
+SiliconPolicyUpdatePreMemFirmwareConfig (
+ VOID
+ )
+{
+ UpdatePeiPchPolicyPreMem ();
+ UpdatePeiSaPolicyPreMem ();
+ UpdatePeiCpuPolicyPreMem ();
+}
+
+
+VOID *
+EFIAPI
+SiliconPolicyUpdatePreMem (
+ IN OUT VOID *Policy
+ )
+{
+ Policy = NULL;
+
+ SiliconPolicyUpdatePreMemFirmwareConfig ();
+
+ return Policy;
+}
--
2.36.1.windows.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [edk2-devel] [PATCH v2 6/6] AlderlakeOpenBoardPkg: Add Library Instances
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 6/6] AlderlakeOpenBoardPkg: Add Library Instances Saloni Kasbekar
@ 2023-08-02 20:44 ` Chaganty, Rangasai V
2023-08-04 0:48 ` Chuang, Rosen
1 sibling, 0 replies; 18+ messages in thread
From: Chaganty, Rangasai V @ 2023-08-02 20:44 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Oram, Isaac W, Chuang, Rosen
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Tuesday, August 01, 2023 3:18 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 6/6] AlderlakeOpenBoardPkg: Add Library Instances
Adds the following libraries
- BasePlatformHookLib
- PeiBoardConfigLib
- PeiGetFvInfoLib
- SmmSpiFlashCommonLib
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../BasePlatformHookLib/BasePlatformHookLib.c | 38 ++++
.../BasePlatformHookLib.inf | 44 ++++
.../PeiBoardConfigLib/PeiBoardConfigLib.c | 136 +++++++++++
.../PeiBoardConfigLib/PeiBoardConfigLib.inf | 56 +++++
.../Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c | 89 ++++++++
.../PeiGetFvInfoLib/PeiGetFvInfoLib.inf | 34 +++
.../SmmSpiFlashCommonLib.inf | 49 ++++
.../SmmSpiFlashCommonLib/SpiFlashCommon.c | 215 ++++++++++++++++++
.../SpiFlashCommonSmmLib.c | 60 +++++
9 files changed, 721 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
new file mode 100644
index 0000000000..cccb1e18cc
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/B
+++ asePlatformHookLib.c
@@ -0,0 +1,38 @@
+/** @file
+ Platform Hook Library instances
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi/UefiBaseType.h>
+#include <Library/PchCycleDecodingLib.h>
+
+
+/**
+ Performs platform specific initialization required for the CPU to
+access
+ the hardware associated with a SerialPortLib instance. This function
+does
+ not initialize the serial port hardware itself. Instead, it
+initializes
+ hardware devices that are required for the CPU to access the serial
+port
+ hardware. This function may be called more than once.
+
+ @retval RETURN_SUCCESS The platform specific initialization succeeded.
+ @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.
+
+**/
+RETURN_STATUS
+EFIAPI
+PlatformHookSerialPortInitialize (
+ VOID
+ )
+{
+
+ //
+ // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h.
+ //
+ PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));
+ PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));
+
+ return RETURN_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf
new file mode 100644
index 0000000000..b77724d5ab
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/B
+++ asePlatformHookLib.inf
@@ -0,0 +1,44 @@
+### @file
+# Platform Hook Library instance for Alderlake Mobile/Desktop CRB.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BasePlatformHookLib
+ FILE_GUID = E22ADCC6-ED90-4A90-9837-C8E7FF9E963D
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = PlatformHookLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC #
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciSegmentLib
+ PciLib
+ PchCycleDecodingLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+
+[FixedPcd]
+ gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES
+
+[Sources]
+ BasePlatformHookLib.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c
new file mode 100644
index 0000000000..a9674bdd22
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/Pei
+++ BoardConfigLib.c
@@ -0,0 +1,136 @@
+/** @file
+ Implementation of PeiBoardConfigLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PostCodeLib.h>
+#include <Library/TimerLib.h>
+#include <Library/GpioLib.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PmcLib.h>
+#include <Library/BoardConfigLib.h>
+
+
+
+VOID
+EFIAPI
+InternalUpdateRvpBoardConfig (
+ IN OUT UINT16 BoardId
+ )
+{
+ //
+ // Update Board Type/Platform Type/Platform Flavor
+ //
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ if(PcdSet64S (PcdAcpiDefaultOemTableId, ACPI_OEM_TABLE_ID_ADL_P_M) != EFI_SUCCESS)
+ {
+ DEBUG ((DEBUG_INFO, "Set PcdAcpiDefaultOemTableId error!!!\n"));
+ }
+ break;
+ }
+ DEBUG ((DEBUG_INFO, "PcdAcpiDefaultOemTableId is 0x%llX\n", PcdGet64
+(PcdAcpiDefaultOemTableId))); }
+
+/**
+ Procedure to detect current board HW configuration.
+
+**/
+VOID
+GetBoardConfig (
+ VOID
+ )
+{
+ UINT16 BoardId;
+
+ //
+ // Get Platform Info and fill the PCD //
+ BoardId = BoardIdAdlPDdr5Rvp;
+ PcdSet16S (PcdBoardId, BoardId);
+ //
+ // update RVP board config
+ //
+ InternalUpdateRvpBoardConfig (BoardId);
+
+ DEBUG ((DEBUG_INFO, "Platform Information:\n")); DEBUG ((DEBUG_INFO,
+ "BoardID: 0x%x\n", BoardId));
+
+}
+
+/**
+ Count the number of GPIO settings in the Table.
+
+ @param[in] GpioTable The pointer of GPIO config table
+ @param[out] GpioCount The number of GPIO config entries
+**/
+VOID
+GetGpioTableSize (
+ GPIO_INIT_CONFIG *GpioTable,
+ OUT UINT16 *GpioCount
+ )
+{
+ *GpioCount = 0;
+ if(GpioTable != NULL) {
+ while (GpioTable[*GpioCount].GpioPad != 0 && *GpioCount < MAX_GPIO_PINS) {
+ DEBUG ((DEBUG_INFO, "GpioTable[%d]->GpioPad = %x \n", *GpioCount, GpioTable[*GpioCount].GpioPad));
+ (*GpioCount) ++;
+ }
+ } else {
+ DEBUG ((DEBUG_INFO, "GpioTable is NULL\n"));
+ }
+ DEBUG ((DEBUG_INFO, "GetGpioTableSize() GpioCount = %d\n",
+*GpioCount)); }
+
+/**
+ Configures GPIO
+
+ @param[in] GpioTable Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries **/ STATIC
+VOID ConfigureGpio (
+ IN GPIO_INIT_CONFIG *GpioTable,
+ IN UINT16 GpioTableCount
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
+
+ Status = GpioConfigurePads (GpioTableCount, GpioTable);
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); }
+
+/**
+ Configure GPIO Before Memory is initialized.
+
+ @param[in] GpioTable Pointer to Gpio table **/ VOID GpioInit (
+ IN GPIO_INIT_CONFIG *GpioTable
+ )
+{
+ UINT16 GpioCount;
+
+ if (GpioTable != 0) {
+ GpioCount = 0;
+ GetGpioTableSize (GpioTable, &GpioCount);
+ if (GpioCount != 0) {
+ ConfigureGpio ((VOID *) GpioTable, (UINTN) GpioCount);
+ }
+ }
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf
new file mode 100644
index 0000000000..1f78e9a0ba
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/Pei
+++ BoardConfigLib.inf
@@ -0,0 +1,56 @@
+### @file
+# Component information file for BaseBoardConfigLib.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiBoardConfigLib
+ FILE_GUID = AA9812A8-1BA6-40AD-A846-50D0BC29C38C
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BoardConfigLib|PEIM
+
+[LibraryClasses]
+ DebugLib
+ PcdLib
+ PostCodeLib
+ TimerLib
+ PeiServicesLib
+ PmcLib
+ GpioLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ PeiBoardConfigLib.c
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardId ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardRev ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSpdPresent ## PRODUCES ## CONSUMES
+
+ # GPIO Group Tier
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2
+
+ gBoardModuleTokenSpaceGuid.PcdDisableVpdGpioTable
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem
+
+[Depex]
+ gEfiPeiReadOnlyVariable2PpiGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c
new file mode 100644
index 0000000000..d9ed1c5064
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGe
+++ tFvInfoLib.c
@@ -0,0 +1,89 @@
+/** @file
+ Helper Library for PEI Graphics PEIM
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/PeiGetFvInfoLib.h>
+#include <Ppi/FirmwareVolume.h>
+#include <Pi/PiPeiCis.h>
+#include <Core/Pei/PeiMain.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/HobLib.h>
+
+/**
+ PeiGetSectionFromFv finds the file in FV and gets file Address and
+Size
+
+ @param[in] NameGuid - File GUID
+ @param[out] Address - Pointer to the File Address
+ @param[out] Size - Pointer to File Size
+
+ @retval EFI_SUCCESS Successfull in reading the section from FV
+ @retval EFI_NOT_FOUND File not found
+**/
+EFI_STATUS
+EFIAPI
+PeiGetSectionFromFv (
+ IN CONST EFI_GUID NameGuid,
+ OUT VOID **Address,
+ OUT UINT32 *Size
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_FIRMWARE_VOLUME_PPI *FvPpi;
+ EFI_FV_FILE_INFO FvFileInfo;
+ PEI_CORE_FV_HANDLE *CoreFvHandle;
+ EFI_PEI_FILE_HANDLE FileHandle;
+ EFI_GUID *FileGuid;
+ EFI_COMMON_SECTION_HEADER *Section;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ VOID *HobData;
+
+ Status = PeiServicesLocatePpi(
+ &gEfiFirmwareFileSystem2Guid,
+ 0,
+ NULL,
+ (VOID **)&FvPpi
+ );
+ ASSERT_EFI_ERROR(Status);
+
+ GuidHob = GetFirstGuidHob (&gPlatformInitFvLocationGuid); if
+ (GuidHob != NULL) {
+ HobData = *(VOID **)GET_GUID_HOB_DATA(GuidHob);
+ CoreFvHandle = (PEI_CORE_FV_HANDLE *) HobData;
+
+ //
+ // File typically resides in current FV or previous FV, so searching both of them.
+ //
+ Status = FvPpi->FindFileByName (FvPpi, &NameGuid,
+ &CoreFvHandle->FvHandle, &FileHandle);
+
+ if (!EFI_ERROR(Status) && FileHandle != NULL) {
+
+ DEBUG((DEBUG_INFO, "Find SectionByType \n"));
+
+ Status = FvPpi->FindSectionByType(FvPpi, EFI_SECTION_RAW, FileHandle, (VOID **)&FileGuid);
+ if (!EFI_ERROR(Status)) {
+
+ DEBUG((DEBUG_INFO, "GetFileInfo \n"));
+
+ Status = FvPpi->GetFileInfo(FvPpi, FileHandle, &FvFileInfo);
+ Section = (EFI_COMMON_SECTION_HEADER *)FvFileInfo.Buffer;
+
+ if (IS_SECTION2(Section)) {
+ ASSERT(SECTION2_SIZE(Section) > 0x00FFFFFF);
+ *Size = SECTION2_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEADER2);
+ *Address = ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER2));
+ } else {
+ *Size = SECTION_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEADER);
+ *Address = ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER));
+ }
+ return EFI_SUCCESS;
+ }
+ }
+ } else {
+ DEBUG ((DEBUG_INFO, "Hob not found\n"));
+ }
+ return EFI_NOT_FOUND;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf
new file mode 100644
index 0000000000..1701fb15fe
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGe
+++ tFvInfoLib.inf
@@ -0,0 +1,34 @@
+### @file
+# Component description file for PeiGetFvInfo library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiGetFvInfoLib
+ FILE_GUID = C2584BE4-2CCD-418C-9205-A2031CE75861
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = PeiGetFvInfoLib
+
+[LibraryClasses]
+ BaseMemoryLib
+ BaseLib
+ DebugLib
+ DebugPrintErrorLevelLib
+ HobLib
+ PeiServicesLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ PeiGetFvInfoLib.c
+
+[Guids]
+ gPlatformInitFvLocationGuid ## CONSUMES
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
new file mode 100644
index 0000000000..cf6ca0d0ab
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/
+++ SmmSpiFlashCommonLib.inf
@@ -0,0 +1,49 @@
+### @file
+# SMM Library instance of Spi Flash Common Library Class #
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SmmSpiFlashCommonLib
+ FILE_GUID = 9632D96E-E849-4217-9217-DC500B8AAE47
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_SMM_DRIVER
+ LIBRARY_CLASS = SpiFlashCommonLib|DXE_SMM_DRIVER
+ CONSTRUCTOR = SmmSpiFlashCommonLibConstructor
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[LibraryClasses]
+ IoLib
+ MemoryAllocationLib
+ BaseLib
+ UefiLib
+ SmmServicesTableLib
+ BaseMemoryLib
+ DebugLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+
+[Sources]
+ SpiFlashCommonSmmLib.c
+ SpiFlashCommon.c
+
+[Protocols]
+ gPchSmmSpiProtocolGuid ## CONSUMES
+
+[Depex.X64.DXE_SMM_DRIVER]
+ gPchSmmSpiProtocolGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
new file mode 100644
index 0000000000..3f7c52ac73
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/
+++ SpiFlashCommon.c
@@ -0,0 +1,215 @@
+/** @file
+ Wrap EFI_SPI_PROTOCOL to provide some library level interfaces
+ for module use.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+
+#include <Library/SpiFlashCommon.h>
+#include <Library/IoLib.h>
+
+PCH_SPI_PROTOCOL *mSpiProtocol;
+
+//
+// Variables for boottime and runtime usage.
+//
+UINTN mBiosAreaBaseAddress = 0;
+UINTN mBiosSize = 0;
+UINTN mBiosOffset = 0;
+
+/**
+ Enable block protection on the Serial Flash device.
+
+ @retval EFI_SUCCESS Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashLock (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+
+ return Status;
+}
+
+/**
+ Read NumBytes bytes of data from the address specified by
+ PAddress into Buffer.
+
+ @param[in] Address The starting physical address of the read.
+ @param[in,out] NumBytes On input, the number of bytes to read. On output, the number
+ of bytes actually read.
+ @param[out] Buffer The destination data buffer for the read.
+
+ @retval EFI_SUCCESS Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashRead (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ OUT UINT8 *Buffer
+ )
+{
+ ASSERT ((NumBytes != NULL) && (Buffer != NULL));
+ if ((NumBytes == NULL) || (Buffer == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // This function is implemented specifically for those platforms //
+ at which the SPI device is memory mapped for read. So this //
+ function just do a memory copy for Spi Flash Read.
+ //
+ CopyMem (Buffer, (VOID *) Address, *NumBytes);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Write NumBytes bytes of data from Buffer to the address specified by
+ PAddresss.
+
+ @param[in] Address The starting physical address of the write.
+ @param[in,out] NumBytes On input, the number of bytes to write. On output,
+ the actual number of bytes written.
+ @param[in] Buffer The source data buffer for the write.
+
+ @retval EFI_SUCCESS Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_BAD_BUFFER_SIZE DataSectionSize in BGUP header exceeds the
+ size ofBIOS Guard script
+ buffer
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashWrite (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINTN Offset;
+ UINT32 Length;
+ UINT32 RemainingBytes;
+
+ ASSERT ((NumBytes != NULL) && (Buffer != NULL)); if ((NumBytes ==
+ NULL) || (Buffer == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ASSERT (Address >= mBiosAreaBaseAddress); if (Address <
+ mBiosAreaBaseAddress) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Offset = Address - mBiosAreaBaseAddress;
+
+ ASSERT ((*NumBytes + Offset) <= mBiosSize); if ((*NumBytes + Offset)
+ > mBiosSize) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = EFI_SUCCESS;
+ RemainingBytes = *NumBytes;
+
+ while (RemainingBytes > 0) {
+ if (RemainingBytes > SECTOR_SIZE_4KB) {
+ Length = SECTOR_SIZE_4KB;
+ } else {
+ Length = RemainingBytes;
+ }
+ Status = mSpiProtocol->FlashWrite (
+ mSpiProtocol,
+ FlashRegionBios,
+ (UINT32) Offset,
+ Length,
+ Buffer
+ );
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+ RemainingBytes -= Length;
+ Offset += Length;
+ Buffer += Length;
+ }
+
+ //
+ // Actual number of bytes written
+ //
+ *NumBytes -= RemainingBytes;
+
+ return Status;
+}
+
+/**
+ Erase the block starting at Address.
+
+ @param[in] Address The starting physical address of the block to be erased.
+ This library assume that caller garantee that the PAddress
+ is at the starting address of this block.
+ @param[in] NumBytes On input, the number of bytes of the logical block to be erased.
+ On output, the actual number of bytes erased.
+
+ @retval EFI_SUCCESS. Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashBlockErase (
+ IN UINTN Address,
+ IN UINTN *NumBytes
+ )
+{
+ EFI_STATUS Status;
+ UINTN Offset;
+ UINTN RemainingBytes;
+
+ ASSERT (NumBytes != NULL);
+ if (NumBytes == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ASSERT (Address >= mBiosAreaBaseAddress); if (Address <
+ mBiosAreaBaseAddress) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Offset = Address - mBiosAreaBaseAddress;
+
+ ASSERT ((*NumBytes % SECTOR_SIZE_4KB) == 0); if ((*NumBytes %
+ SECTOR_SIZE_4KB) != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ASSERT ((*NumBytes + Offset) <= mBiosSize); if ((*NumBytes + Offset)
+ > mBiosSize) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = EFI_SUCCESS;
+ RemainingBytes = *NumBytes;
+
+ Status = mSpiProtocol->FlashErase (
+ mSpiProtocol,
+ FlashRegionBios,
+ (UINT32) Offset,
+ (UINT32) RemainingBytes
+ );
+ return Status;
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
new file mode 100644
index 0000000000..897d85743a
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/
+++ SpiFlashCommonSmmLib.c
@@ -0,0 +1,60 @@
+/** @file
+ SMM Library instance of SPI Flash Common Library Class
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+
+#include <Library/SpiFlashCommon.h>
+#include <Library/SmmServicesTableLib.h>
+
+extern PCH_SPI_PROTOCOL *mSpiProtocol;
+
+extern UINTN mBiosAreaBaseAddress;
+extern UINTN mBiosSize;
+extern UINTN mBiosOffset;
+
+/**
+ The library constructuor.
+
+ The function does the necessary initialization work for this library
+ instance.
+
+ @param[in] ImageHandle The firmware allocated handle for the UEFI image.
+ @param[in] SystemTable A pointer to the EFI system table.
+
+ @retval EFI_SUCCESS The function always return EFI_SUCCESS for now.
+ It will ASSERT on error for debug version.
+ @retval EFI_ERROR Please reference LocateProtocol for error code details.
+**/
+EFI_STATUS
+EFIAPI
+SmmSpiFlashCommonLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINT32 BaseAddr;
+ UINT32 RegionSize;
+
+ mBiosAreaBaseAddress = (UINTN) PcdGet32 (PcdBiosAreaBaseAddress);
+ mBiosSize = (UINTN) PcdGet32 (PcdBiosSize);
+
+ //
+ // Locate the SMM SPI protocol.
+ //
+ Status = gSmst->SmmLocateProtocol (
+ &gPchSmmSpiProtocolGuid,
+ NULL,
+ (VOID **) &mSpiProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ mSpiProtocol->GetRegionAddress (mSpiProtocol, FlashRegionBios,
+ &BaseAddr, &RegionSize); mBiosOffset = BaseAddr;
+
+ return Status;
+}
--
2.36.1.windows.1
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^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [edk2-devel] [PATCH v2 1/6] AlderlakeOpenBoardPkg: Add package and headers
2023-08-01 22:17 [edk2-devel] [PATCH v2 1/6] AlderlakeOpenBoardPkg: Add package and headers Saloni Kasbekar
` (5 preceding siblings ...)
2023-08-02 17:25 ` [edk2-devel] [PATCH v2 1/6] AlderlakeOpenBoardPkg: Add package and headers Chaganty, Rangasai V
@ 2023-08-04 0:40 ` Chuang, Rosen
6 siblings, 0 replies; 18+ messages in thread
From: Chuang, Rosen @ 2023-08-04 0:40 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Desimone, Nathaniel L, Oram, Isaac W
Reviewed-by: Rosen Chuang < rosen.chuang@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Wednesday, August 2, 2023 6:18 AM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 1/6] AlderlakeOpenBoardPkg: Add package and headers
Create the AlderlakeOpenBoardPkg to provide board support code. The package supports Alderlake Mobile board with LPDDR4. The package serves as a support package in the EDK II Minimum Platform design.
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Include/Library/BoardConfigLib.h | 59 ++++
.../Include/Library/PeiGetFvInfoLib.h | 29 ++
.../Include/Library/SpiFlashCommon.h | 99 ++++++
.../Include/PlatformBoardConfig.h | 93 ++++++
.../Include/PlatformBoardId.h | 21 ++
.../Include/PlatformGpioConfig.h | 18 +
.../Include/PlatformPostCode.h | 39 +++
.../Include/PolicyUpdateMacro.h | 48 +++
.../AlderlakeOpenBoardPkg/OpenBoardPkg.dec | 307 ++++++++++++++++++
9 files changed, 713 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h
new file mode 100644
index 0000000000..3a07563c5d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLi
+++ b.h
@@ -0,0 +1,59 @@
+/** @file
+ Function prototype of BoardConfigLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _BOARD_CONFIG_LIB_H_
+#define _BOARD_CONFIG_LIB_H_
+
+#include <Library/GpioLib.h>
+#include <PlatformBoardConfig.h>
+
+#define SIZE_OF_FIELD(TYPE, Field) (sizeof (((TYPE *)0)->Field))
+
+#define SIZE_OF_TABLE(TABLE, TYPE) (sizeof (TABLE) / sizeof (TYPE))
+
+#define BOARD_CONFIG PLATFORM_INFO
+
+#define PRE_MEM 0
+#define POST_MEM 1
+#define EARLY_PRE_MEM 2
+
+/**
+ Procedure to detect current board HW configuration.
+
+**/
+VOID
+EFIAPI
+GetBoardConfig (
+ VOID
+ );
+
+
+/**
+ Count the number of GPIO settings in the Table.
+
+ @param[in] GpioTable The pointer of GPIO config table
+ @param[out] GpioCount The number of GPIO config entries
+**/
+VOID
+GetGpioTableSize (
+ GPIO_INIT_CONFIG *GpioTable,
+ OUT UINT16 *GpioCount
+ );
+
+
+/**
+ Configure GPIO pads in PEI phase.
+
+ @param[in] GpioTable Pointer to Gpio table **/ VOID GpioInit (
+ IN GPIO_INIT_CONFIG *GpioTable
+ );
+
+#endif // _BOARD_CONFIG_LIB_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h
new file mode 100644
index 0000000000..f2e5a77787
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoL
+++ ib.h
@@ -0,0 +1,29 @@
+/** @file
+ Header file for PeiGetFvInfoLib..
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PEI_GET_FV_INFO_LIB_H_
+#define _PEI_GET_FV_INFO_LIB_H_
+
+/**
+ PeiGetSectionFromFv finds the file in FV and gets file Address and
+Size
+
+ @param[in] NameGuid - File GUID
+ @param[out] Address - Pointer to the File Address
+ @param[out] Size - Pointer to File Size
+
+ @retval EFI_SUCCESS Successfull in reading the section from FV
+**/
+EFI_STATUS
+EFIAPI
+PeiGetSectionFromFv (
+ IN CONST EFI_GUID NameGuid,
+ OUT VOID **Address,
+ OUT UINT32 *Size
+ );
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h
new file mode 100644
index 0000000000..76ba3a8094
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommo
+++ n.h
@@ -0,0 +1,99 @@
+/** @file
+ The header file includes the common header files, defines
+ internal structure and functions used by SpiFlashCommonLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SPI_FLASH_COMMON_H__
+#define __SPI_FLASH_COMMON_H__
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h> #include
+<Library/UefiDriverEntryPoint.h> #include
+<Library/UefiBootServicesTableLib.h>
+#include <Protocol/Spi.h>
+
+#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size
+/**
+ Enable block protection on the Serial Flash device.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashLock (
+ VOID
+ );
+
+/**
+ Read NumBytes bytes of data from the address specified by
+ PAddress into Buffer.
+
+ @param[in] Address The starting physical address of the read.
+ @param[in,out] NumBytes On input, the number of bytes to read. On output, the number
+ of bytes actually read.
+ @param[out] Buffer The destination data buffer for the read.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashRead (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Write NumBytes bytes of data from Buffer to the address specified by
+ PAddresss.
+
+ @param[in] Address The starting physical address of the write.
+ @param[in,out] NumBytes On input, the number of bytes to write. On output,
+ the actual number of bytes written.
+ @param[in] Buffer The source data buffer for the write.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashWrite (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Erase the block starting at Address.
+
+ @param[in] Address The starting physical address of the block to be erased.
+ This library assume that caller garantee that the PAddress
+ is at the starting address of this block.
+ @param[in] NumBytes On input, the number of bytes of the logical block to be erased.
+ On output, the actual number of bytes erased.
+
+ @retval EFI_SUCCESS. Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashBlockErase (
+ IN UINTN Address,
+ IN UINTN *NumBytes
+ );
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h
new file mode 100644
index 0000000000..f9ac991eb4
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h
@@ -0,0 +1,93 @@
+/** @file
+ Header file for Platform Boards Configurations.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PLATFORM_BOARD_CONFIG_H
+#define _PLATFORM_BOARD_CONFIG_H
+
+#include <ConfigBlock.h>
+#include <PchPolicyCommon.h>
+#include <MemoryConfig.h>
+#include <Library/GpioConfig.h>
+
+#define MAX_GPIO_PINS 130
+
+//
+// ACPI table information used to update tables thru PCD //
+#define ACPI_OEM_TABLE_ID_ADL_P_M 0x4D2D502D4C4441 //ADL-P-M
+
+#pragma pack(1)
+
+typedef struct {
+ UINT8 ClkReqNumber : 4;
+ UINT8 ClkReqSupported : 1;
+ UINT8 DeviceResetPadActiveHigh : 1;
+ UINT32 DeviceResetPad;
+} ROOT_PORT_CLK_INFO;
+
+typedef struct {
+ UINT8 Section;
+ UINT8 Pin;
+} EXPANDER_GPIO_CONFIG;
+
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved[3]; // alignment for COMMON_GPIO_CONFIG
+ union {
+ UINT32 Pin;
+ EXPANDER_GPIO_CONFIG Expander;
+ } u;
+} BOARD_GPIO_CONFIG;
+
+// Do not change the encoding. It must correspond with PCH_PCIE_CLOCK_USAGE from PCH RC.
+#define NOT_USED 0xFF
+#define LAN_CLOCK 0x70
+#define PCIE_PEG 0x40
+#define PCIE_PCH 0x00
+
+typedef struct {
+ UINT32 ClockUsage;
+ UINT32 ClkReqSupported;
+} PCIE_CLOCK_CONFIG;
+
+typedef union {
+ UINT64 Blob;
+ BOARD_GPIO_CONFIG BoardGpioConfig;
+ ROOT_PORT_CLK_INFO Info;
+ PCIE_CLOCK_CONFIG PcieClock;
+} PCD64_BLOB;
+
+// Having Max CLK config to support both ADL P and ALD S #define
+PCH_MAX_PCIE_CLOCKS_SBC 18
+
+//seamless board configurations
+typedef struct {
+ UINT32 ClockUsage[PCH_MAX_PCIE_CLOCKS_SBC];
+} PCIE_CLOCKS_USAGE;
+
+#define SPD_DATA_SIZE 1024
+
+//SBC MRC DQS
+typedef struct {
+ UINT8 DqsMapCpu2Dram[8][2];
+} MRC_DQS;
+
+//SBC MRC DQ
+typedef struct {
+ UINT8 DqMapCpu2Dram[8][2][8];
+} MRC_DQ;
+
+//SBC SPD DATA
+typedef struct {
+ BOOLEAN OverrideSpd;
+ UINT8 SpdData[SPD_DATA_SIZE];
+} SPD_DATA;
+
+#pragma pack()
+
+#endif // _PLATFORM_BOARD_CONFIG_H
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h
new file mode 100644
index 0000000000..51b317ffec
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h
@@ -0,0 +1,21 @@
+/** @file
+Defines Platform BoardIds
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PLATFORM_BOARD_ID_H_
+#define _PLATFORM_BOARD_ID_H_
+
+//
+// Alderlake Sku IDs
+//
+#define SkuIdAdlPDdr5Rvp 0x000012
+#define AdlPSkuType 2
+
+// Alderlake P Board IDs
+#define BoardIdAdlPDdr5Rvp 0x12
+
+#endif // _PLATFORM_BOARD_ID_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h
new file mode 100644
index 0000000000..d8a4c2ab77
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h
@@ -0,0 +1,18 @@
+/** @file
+Defines Platform GPIO Configuration Arrary
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/GpioLib.h>
+
+#ifndef _PLATFORM_GPIO_CONFIG_H_
+#define _PLATFORM_GPIO_CONFIG_H_
+
+typedef struct {
+ GPIO_INIT_CONFIG GpioConfig[0];
+} GPIO_INIT_CONFIG_ARRAY;
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h
new file mode 100644
index 0000000000..4dbdd8e391
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h
@@ -0,0 +1,39 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PLATFORMPOSTCODE_H_
+#define _PLATFORMPOSTCODE_H_
+
+//
+// GENERAL USAGE GUIDELINES
+//
+
+/**
+[definition]
+PostCode = XYZZ
+X - "D"=premem, "9"=postmem, "8"=SMM, "7"=DXE Y - "6"=platform driver,
+"5"=board driver ZZ - "00"=entry, "7F"=exit
+ - 1 - board init premem: entry/exit (0xD500/0xD57F)
+ - 2 - platform init premem: entry/exit (0xD600/0xD67F)
+ - 3 - board init postmem: entry/exit (0x9500/0x957F)
+ - 4 - platform init postmem: entry/exit (0x9600/0x967F)
+ - 5 - board init DXE: entry/exit (0x7500/0x757F)
+ - 6 - platform init DXE: entry/exit (0x7600/0x767F)
+ - 7 - platform SMM init: entry/exit (0x8600/0x867F)
+ - 8 - BIOS S3 entry (0xB503) means BioS PC 03, to differentiate with
+ACPI _PTS PC
+ - 9 - BIOS S4 entry (0xB504) means BioS PC 04, to differentiate with
+ACPI _PTS PC
+ - 10 - BIOS S5 entry (0B505) means BioS PC 05, to differentiate with
+ACPI _PTS PC */
+
+#define PLATFORM_INIT_PREMEM_ENTRY 0xD600
+#define PLATFORM_INIT_PREMEM_EXIT 0xD67F
+#define PLATFORM_INIT_POSTMEM_ENTRY 0x9600 #define
+PLATFORM_INIT_POSTMEM_EXIT 0x967F
+#define PLATFORM_SMM_INIT_ENTRY 0x8600
+#define PLATFORM_SMM_INIT_EXIT 0x867F
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h
new file mode 100644
index 0000000000..c9ace9d910
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h
@@ -0,0 +1,48 @@
+/** @file
+ Macros for platform to update different types of policy.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _POLICY_UPDATE_MACRO_H_
+#define _POLICY_UPDATE_MACRO_H_
+
+#ifdef UPDATE_POLICY
+#undef UPDATE_POLICY
+#endif
+
+#ifdef COPY_POLICY
+#undef COPY_POLICY
+#endif
+
+#ifdef GET_POLICY
+#undef GET_POLICY
+#endif
+
+#ifdef AND_POLICY
+#undef AND_POLICY
+#endif
+
+#ifdef OR_POLICY
+#undef OR_POLICY
+#endif
+
+#define UPDATE_POLICY(UpdField, ConfigField, Value) ConfigField =
+Value; #define COPY_POLICY(UpdField, ConfigField, Value, Size) CopyMem
+(ConfigField, Value, Size); #define GET_POLICY(UpdField, ConfigField,
+Value) Value = ConfigField; #define AND_POLICY(UpdField, ConfigField,
+Value) ConfigField &= Value; #define OR_POLICY(UpdField, ConfigField,
+Value) ConfigField |= Value; // // Compare Policy Default and Setup
+Default when FirstBoot and RvpSupport //
+
+#define COMPARE_AND_UPDATE_POLICY(UpdField, ConfigField, Value) {\
+ UPDATE_POLICY(UpdField, ConfigField, Value);\ } #define
+COMPARE_UPDATE_POLICY_ARRAY(UpdField, ConfigField, Value, ArrayIndex)
+{\
+ UPDATE_POLICY(UpdField, ConfigField, Value);\ }
+
+#endif //_POLICY_UPDATE_MACRO_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec
new file mode 100644
index 0000000000..0f0ed386f6
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec
@@ -0,0 +1,307 @@
+## @file
+#
+# The DEC files are used by the utilities that parse DSC and # INF
+files to generate AutoGen.c and AutoGen.h files # for the build
+infrastructure.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+DEC_SPECIFICATION = 0x00010017
+PACKAGE_NAME = OpenBoardPkg
+PACKAGE_VERSION = 0.1
+PACKAGE_GUID = A840FA72-FBF7-4357-B301-DAE2233F14AB
+
+[Includes]
+Include
+
+[Guids]
+ gBoardModuleTokenSpaceGuid = {0x72d1fff7, 0xa42a, 0x4219, {0xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}}
+ gPlatformModuleTokenSpaceGuid = {0x69d13bf0, 0xaf91, 0x4d96, {0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}}
+ gPlatformInitFvLocationGuid = {0xa564010a, 0x1d90, 0x4b1c, {0x8d, 0x10, 0xcb, 0xba, 0xff, 0xb2, 0x55, 0x42}}
+ gVpdFfsGuid = {0x338FA35A, 0xCA4A, 0x4DBC, {0xA6, 0xF4, 0x9B, 0xD1, 0x59, 0x3B, 0x61, 0xBC}}
+ gMemoryConfigVariableGuid = {0xc94f8c4d, 0x9b9a, 0x45fe, {0x8a, 0x55, 0x23, 0x8b, 0x67, 0x30, 0x26, 0x43}}
+
+#
+# FvImage File
+#
+ gFvAdvancedFileGuid = {0xAD198BA5, 0xC330, 0x41CD, {0xB0, 0x97, 0x16, 0x48, 0x83, 0x28, 0xB7, 0x98}}
+ gFvOsBootFileGuid = {0xB9020753, 0x84A8, 0x4BB6, {0x94, 0x7C, 0xCE, 0x7D, 0x41, 0xF5, 0xCE, 0x39}}
+ gFvUefiBootFileGuid = {0x9E21FD93, 0x9C72, 0x4c15, {0x8C, 0x4B, 0xE7, 0x7F, 0x1D, 0xB2, 0xD7, 0x92}}
+ gTianoLogoGuid = {0x7BB28B99, 0x61BB, 0x11D5, {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}}
+
+ # gUefiShellFileGuid is FILE GUID for MinUefiShell.inf/UefiShell.inf/Shell.inf.
+ gUefiShellFileGuid = {0x7c04a583, 0x9e3e, 0x4f1c, {0xad, 0x65, 0xe0, 0x52, 0x68, 0xd0, 0xb4, 0xd1}}
+
+[Ppis]
+ gReadyForGopConfigPpiGuid = {0x5f252c18, 0x1781, 0x4290, {0xa7, 0xb6, 0xfd, 0x99, 0x63, 0x4c, 0x6a, 0x8a}}
+
+[PcdsFixedAtBuild, PcdsPatchableInModule] ## ##
+PcdSmbiosOemTypeFirmwareVersionInfo determines the SMBIOS OEM type
+(0x80 to 0xFF) defined in SMBIOS, ## values 0-0x7F will be treated as disable FVI reporting.
+## FVI structure uses it as SMBIOS OEM type to provide version information.
+##
+gPlatformModuleTokenSpaceGuid.PcdSmbiosOemTypeFirmwareVersionInfo|0xDD|
+UINT8|0x20000001
+
+[PcdsFixedAtBuild]
+ gBoardModuleTokenSpaceGuid.PcdDefaultBoardId|0|UINT16|0x10101009
+
+
+ gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x1000101
+ 0
+
+ gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|0x1000
+ 1011
+
+ ##
+ ## The Flash PCDs will be patched based on FDF definitions during build.
+ ## Set them to 0 here to prevent confusion.
+ ##
+
+
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase|0x00000000|U
+ INT32|0x20000040
+
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize|0x00000000|U
+ INT32|0x20000041
+
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset|0x00000000
+ |UINT32|0x20000042
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase|0x00000000|UINT32|0x
+ 2000004C
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize|0x00000000|UINT32|0x
+ 2000004D
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalOffset|0x00000000|UINT32|
+ 0x2000004E
+
+
+ gBoardModuleTokenSpaceGuid.PcdFlashObbSize|0x00000000|UINT32|0xF0000A5
+ 3
+
+ gBoardModuleTokenSpaceGuid.PcdFlashIbbOffset|0x00000000|UINT32|0xF0000
+ A58
+
+ gBoardModuleTokenSpaceGuid.PcdFlashIbbSize|0x00000000|UINT32|0xF0000A5
+ 9
+ gBoardModuleTokenSpaceGuid.PcdFlashFvRsvdOffset|0x00000000|UINT32|0x20
+ 000A5E
+ gBoardModuleTokenSpaceGuid.PcdFlashFvRsvdSize|0x00000000|UINT32|0x2000
+ 0A5F
+
+ gBoardModuleTokenSpaceGuid.PcdFlashIbbROffset|0x00000000|UINT32|0x2000
+ 0A61
+
+#(ACPI.inf)
+
+gPlatformModuleTokenSpaceGuid.PcdApicLocalAddress|0xFEE00000|UINT64|0x9
+000000B
+gPlatformModuleTokenSpaceGuid.PcdApicIoAddress|0xFEC00000|UINT64|0x9000
+000D
+ gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012
+
+gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013
+ gPlatformModuleTokenSpaceGuid.PcdApicIoIdPch|0x02|UINT8|0x9000001E
+
+#(BaseMmioInitLib.inf)
+gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress|0xFEDA0000|UINT64|0x900
+00003
+gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress|0xFEDA1000|UINT64|0x9000
+0005
+
+## This PCD specifies whether StatusCode is reported via SerialIoUart
+gPlatformModuleTokenSpaceGuid.PcdStatusCodeUseSerialIoUart|FALSE|BOOLEA
+N|0xFF000002
+
+## This flag is used to initialize debug output interface.
+# BIT0 - RAM debug interface.
+# BIT1 - UART debug interface.
+# BIT2 - USB debug interface.
+# BIT3 - USB3 debug interface.
+# BIT4 - Serial IO debug interface.
+# BIT5 - TraceHub debug interface.
+# BIT6 - Reserved.
+# BIT7 - CMOS control.
+gPlatformModuleTokenSpaceGuid.PcdStatusCodeFlags|0x82|UINT8|0xF0000111
+
+gPlatformModuleTokenSpaceGuid.PcdGttMmAddress|0xAF000000|UINT64|0x90000
+00F
+gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress|0xB0000000|UINT64|0x90000
+010
+
+gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress|0xFED80000|UINT64|0x9
+0000009
+
+gPlatformModuleTokenSpaceGuid.PcdLzmaEnable |FALSE|BOOLEAN|0xF000002B
+
+[PcdsDynamic]
+ # DRAM Configuration
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000174
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000175
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2Dram|0|UINT32|0x00000072
+
+gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2DramSize|0|UINT16|0x00000073
+
+ # SPD Address Table
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000199
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x0000019A
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x0000019B
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x0000019C
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable4|0|UINT8|0x0000019D
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable5|0|UINT8|0x0000019E
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable6|0|UINT8|0x0000019F
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable7|0|UINT8|0x000001A0
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable8|0|UINT8|0x000001A1
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable9|0|UINT8|0x000001A2
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable10|0|UINT8|0x000001A3
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable11|0|UINT8|0x000001A4
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable12|0|UINT8|0x000001A5
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable13|0|UINT8|0x000001A6
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable14|0|UINT8|0x000001A7
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable15|0|UINT8|0x000001A8
+
+ # Root Port Clock Info
+ gBoardModuleTokenSpaceGuid.PcdPcieClock0|0|UINT64|0x0000009E
+ gBoardModuleTokenSpaceGuid.PcdPcieClock1|0|UINT64|0x0000009F
+ gBoardModuleTokenSpaceGuid.PcdPcieClock2|0|UINT64|0x000000A0
+ gBoardModuleTokenSpaceGuid.PcdPcieClock3|0|UINT64|0x000000A1
+ gBoardModuleTokenSpaceGuid.PcdPcieClock4|0|UINT64|0x000000A2
+ gBoardModuleTokenSpaceGuid.PcdPcieClock5|0|UINT64|0x000000A3
+ gBoardModuleTokenSpaceGuid.PcdPcieClock6|0|UINT64|0x000000A4
+ gBoardModuleTokenSpaceGuid.PcdPcieClock7|0|UINT64|0x000000A5
+ gBoardModuleTokenSpaceGuid.PcdPcieClock8|0|UINT64|0x000000A6
+ gBoardModuleTokenSpaceGuid.PcdPcieClock9|0|UINT64|0x000000A7
+ gBoardModuleTokenSpaceGuid.PcdPcieClock10|0|UINT64|0x000000A8
+ gBoardModuleTokenSpaceGuid.PcdPcieClock11|0|UINT64|0x000000A9
+ gBoardModuleTokenSpaceGuid.PcdPcieClock12|0|UINT64|0x000000AA
+ gBoardModuleTokenSpaceGuid.PcdPcieClock13|0|UINT64|0x000000AB
+ gBoardModuleTokenSpaceGuid.PcdPcieClock14|0|UINT64|0x000000AC
+ gBoardModuleTokenSpaceGuid.PcdPcieClock15|0|UINT64|0x000000AD
+ gBoardModuleTokenSpaceGuid.PcdPcieClock16|0|UINT64|0x000000AE
+ gBoardModuleTokenSpaceGuid.PcdPcieClock17|0|UINT64|0x000000AF
+
+
+ # GPIO Group Tier
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0|0|UINT32|0x000000E9
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1|0|UINT32|0x000000EA
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2|0|UINT32|0x000000EB
+
+ # Display DDI
+
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable|0|UINT32|0x00100033
+
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize|0|UINT16|0x0010
+ 0034
+
+ # MISC
+ gBoardModuleTokenSpaceGuid.PcdStackBase|0x0|UINT32|0x40000A10
+ gBoardModuleTokenSpaceGuid.PcdStackSize|0x0|UINT32|0x40000A11
+
+ # SA Misc Configuration
+ gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066
+
+ gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|0x0000
+ 0067
+
+ gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMask|0|UINT8|0x0000A10
+ 3
+
+ gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMaskEcc|0|UINT8|0x0000
+ A104
+
+ gBoardModuleTokenSpaceGuid.PcdSaMiscDisableMrcRetrainingOnRtcPowerLoss
+ |0|UINT8|0x0000A105
+
+ # Board Information
+ gBoardModuleTokenSpaceGuid.PcdSpdPresent|FALSE|BOOLEAN|0x00101012
+ gBoardModuleTokenSpaceGuid.PcdBoardRev|0x0|UINT16|0x00101016
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId|0x0|UINT16|0x00101017
+ gBoardModuleTokenSpaceGuid.PcdBoardId|0|UINT16|0x00101018
+ gBoardModuleTokenSpaceGuid.PcdSkuType|0x0|UINT8|0x0010101F
+
+ # MRC Config
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x00000A68
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x00000A69
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x00000A6A
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x00000A6B
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x00000A6C
+
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0x00000A6
+ D
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALSE|BOOLEA
+ N|0x00000A6E
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLEAN|0x000
+ 00A6F
+ gBoardModuleTokenSpaceGuid.PcdMrcLp5CccConfig|0|UINT8|0x00000A73
+ gBoardModuleTokenSpaceGuid.PcdMrcCmdMirror|0|UINT8|0x00000A74
+ gBoardModuleTokenSpaceGuid.PcdRootPortIndex|0xFF|UINT8|0x00000A78
+
+ # Pch SerialIo I2c Pads Termination
+
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm|0x1|UINT8
+ |0x00000020
+
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm|0x1|UINT8
+ |0x00000021
+
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm|0x1|UINT8
+ |0x00000022
+
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm|0x1|UINT8
+ |0x00000023
+
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm|0x1|UINT8
+ |0x00000030
+
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm|0x1|UINT8
+ |0x00000031
+
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c6PadInternalTerm|0x1|UINT8
+ |0x00000032
+
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c7PadInternalTerm|0x1|UINT8
+ |0x00000033
+
+[PcdsDynamicEx]
+# Flag to Disable Vpd Gpio
+gBoardModuleTokenSpaceGuid.PcdDisableVpdGpioTable|FALSE|BOOLEAN|0x50000
+015
+# Pre-Mem GPIO table
+
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem|{0}|GPIO_INIT_CONFIG
+_ARRAY|0x50000017 {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioLib.h
+ PlatformGpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+
+gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|{0}|GPIO_INIT_CON
+FIG[]|0x50000018 {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioLib.h
+ Library/GpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# GPIO table
+
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTable|{0}|GPIO_INIT_CONFIG_ARRAY
+|0x50000019 {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioLib.h
+ PlatformGpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable|{0}|GPIO_INIT_CONFIG[]|
+0x5000001C {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# PCIE CLOCKS USAGE
+
+gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|{0}|PCIE_CLOCKS_USAGE|
+0x50000022 {
+ <HeaderFiles>
+ PlatformBoardConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+#SBC SPD DATA
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData|{0}|SPD_DATA|0x50000025 {
+ <HeaderFiles>
+ PlatformBoardConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# SBC MRC DQS MAPPING
+
+gBoardModuleTokenSpaceGuid.VpdPcdMrcDqsMapCpu2Dram|{0}|MRC_DQS|0x500000
+26 {
+ <HeaderFiles>
+ PlatformBoardConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# SBC MRC DQ MAPPING
+
+gBoardModuleTokenSpaceGuid.VpdPcdMrcDqMapCpu2Dram|{0}|MRC_DQ|0x50000027
+{
+ <HeaderFiles>
+ PlatformBoardConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# ACPI data
+ gBoardModuleTokenSpaceGuid.PcdBoardAcpiData|{0}|VOID*|0x5000001A
+
+# Early Pre-Mem GPIO table
+
+gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem|{0}|GPIO_INIT_C
+ONFIG_ARRAY|0x5000001B {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioLib.h
+ PlatformGpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderLakeOpenBoardPkg/OpenBoardPkg.dec
+}
+[PcdsDynamic, PcdsDynamicEx]
+
+[PcdsPatchableInModule]
+
+[PcdsFeatureFlag]
+ gBoardModuleTokenSpaceGuid.PcdIntelGopEnable |FALSE|BOOLEAN|0xF0000B54
--
2.36.1.windows.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [edk2-devel] [PATCH v2 2/6] AlderlakeOpenBoardPkg: Add modules
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 2/6] AlderlakeOpenBoardPkg: Add modules Saloni Kasbekar
2023-08-02 17:46 ` Chaganty, Rangasai V
@ 2023-08-04 0:42 ` Chuang, Rosen
1 sibling, 0 replies; 18+ messages in thread
From: Chuang, Rosen @ 2023-08-04 0:42 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Desimone, Nathaniel L, Oram, Isaac W
Reviewed-by: Rosen Chuang < rosen.chuang@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Wednesday, August 2, 2023 6:18 AM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 2/6] AlderlakeOpenBoardPkg: Add modules
Adds the following modules:
-BiosInfo
-OpenBoardPlatformInit
-SBCVpdStructurePcd
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c | 196 +++++++++++++++
.../BiosInfo/BiosInfo.inf | 84 +++++++
.../OpenBoardPlatformInitPostMem.c | 233 ++++++++++++++++++
.../OpenBoardPlatformInitPostMem.inf | 75 ++++++
.../SBCVpdStructurePcd/AllStructPCD.dsc | 19 ++
.../GpioTableAdlPPostMem.dsc | 40 +++
.../GpioTableAdlPPreMem.dsc | 29 +++
.../MrcDqDqsSPD/AdlPSpdMap.dsc | 138 +++++++++++
.../PcieClocks/AdlPPcieClocks.dsc | 31 +++
9 files changed, 845 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
new file mode 100644
index 0000000000..64462900de
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
@@ -0,0 +1,196 @@
+/** @file
+ PEIM to provide BiosInfo structure listing up all firmware volume's
+base addresses, sizes,
+ attributes, and information associated to the firmware volume.
+ Primarily the structure is used on FIT table creation and Bpm.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Guid/BiosInfo.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/FirmwareInterfaceTable.h>
+#include <Ppi/FirmwareVolumeInfoMeasurementExcluded.h>
+#include <Library/MemoryAllocationLib.h>
+
+#define BASE_FV_SIZE 10
+
+#define FSP_WRAPPER_FV_SIZE 3
+
+#define TSN_MAC_ADDRESS_FV_SIZE 0
+
+#define BIOS_INFO_STRUCT_SIZE (BASE_FV_SIZE + FSP_WRAPPER_FV_SIZE +
+TSN_MAC_ADDRESS_FV_SIZE)
+
+
+/*
+ BIOS_INFO structure is the base of the firmware volume layout for
+Intel platform BIOS implementation
+ so security checker module can run based on the structure and throw
+warnings, error or deadloop
+ when any unexpected firmware volumes are detected.
+
+ BIOS_INFO is recommended to support full entries of firmware volumes
+present in a flash
+ with right type, attribute, version, flash map base address and size,
+ all associated information which is defined by BIOS_INFO_STRUCT structure.
+ - IBB firmware volumes, which are expected to be measured or/and verified
+ by hardware base security solution to meet SecureBoot chain of trust
+ (Intel BootGuard for example), have attribute 0x0.
+ - Post IBB firmware volumes, which are expected to be measured or/and verified
+ by BIOS (TCG code for measurement, RSA2048SHA256Sign algorithm for verification for example),
+ have attribute BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB.
+ - Else, follows Firmware Interface Table specification.
+*/
+#pragma pack (1)
+typedef struct {
+ BIOS_INFO_HEADER Header;
+ BIOS_INFO_STRUCT Entry[BIOS_INFO_STRUCT_SIZE]; } BIOS_INFO; #pragma
+pack ()
+
+GLOBAL_REMOVE_IF_UNREFERENCED BIOS_INFO mBiosInfo = {
+ {
+ BIOS_INFO_SIGNATURE,
+ BIOS_INFO_STRUCT_SIZE,
+ 0,
+ },
+ {
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashNvStorageVariableSize) + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize),
+ FixedPcdGet32 (PcdFlashNvStorageVariableBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvAdvancedSize),
+ FixedPcdGet32 (PcdFlashFvAdvancedBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvOptionalSize),
+ FixedPcdGet32 (PcdFlashFvOptionalBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvSecuritySize),
+ FixedPcdGet32 (PcdFlashFvSecurityBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvOsBootSize),
+ FixedPcdGet32 (PcdFlashFvOsBootBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvUefiBootSize),
+ FixedPcdGet32 (PcdFlashFvUefiBootBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvPostMemorySize),
+ FixedPcdGet32 (PcdFlashFvPostMemoryBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFirmwareBinariesSize),
+ FixedPcdGet32 (PcdFlashFvFirmwareBinariesBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspSSize),
+ FixedPcdGet32 (PcdFlashFvFspSBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspMSize),
+ FixedPcdGet32 (PcdFlashFvFspMBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspTSize),
+ FixedPcdGet32 (PcdFlashFvFspTBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvPreMemorySize),
+ FixedPcdGet32 (PcdFlashFvPreMemoryBase)
+ },
+ {
+ FIT_TYPE_01_MICROCODE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_MICROCODE_WHOLE_REGION,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashMicrocodeFvSize),
+ FixedPcdGet32 (PcdFlashMicrocodeFvBase)
+ },
+ }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mBiosInfoPpiList
+= {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gBiosInfoGuid,
+ &mBiosInfo
+};
+
+/**
+ Installs BiosInfo Ppi.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS Install the BiosInfo Ppi successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+BiosInfoEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ VOID *HobData;
+
+ //
+ // Install PPI, so that other PEI module can add dependency.
+ //
+ Status = PeiServicesInstallPpi (&mBiosInfoPpiList);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Build hob, so that DXE module can also get the data.
+ //
+ HobData = BuildGuidHob (&gBiosInfoGuid, sizeof (mBiosInfo));
+ ASSERT (HobData != NULL);
+ if (HobData == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ CopyMem (HobData, &mBiosInfo, sizeof (mBiosInfo));
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
new file mode 100644
index 0000000000..b11451807a
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
@@ -0,0 +1,84 @@
+### @file
+# Module Information description file for BIOS Info PEIM.
+# The module provides BiosInfo structure listing up all firmware
+volume's base addresses, # sizes, attributes, those information associated to each firmware volume.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BiosInfo
+ FILE_GUID = 4A4CA1C6-871C-45BB-8801-6910A7AA5807
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = BiosInfoEntryPoint
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES IA32 X64
+#
+
+[LibraryClasses]
+ PeimEntryPoint
+ PeiServicesLib
+ PeiServicesTablePointerLib
+ HobLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+
+[Pcd]
+ gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase ##
+CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize ## CONSUMES
+
+[Sources]
+ BiosInfo.c
+
+[Guids]
+ gBiosInfoGuid ## PRODUCES
+
+[Depex]
+ gEfiPeiMasterBootModePpiGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c
new file mode 100644
index 0000000000..4fab4ad8e6
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoa
+++ rdPlatformInitPei/OpenBoardPlatformInitPostMem.c
@@ -0,0 +1,233 @@
+/** @file
+ Source code file for OpenBoard Platform Init PEI module
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Register/Msr.h>
+#include <CpuRegs.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/EndOfPeiPhase.h>
+#include <Library/MtrrLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Guid/SmramMemoryReserve.h>
+#include <Library/ConfigBlockLib.h>
+#include <Ppi/SiPolicy.h>
+#include <PchPolicyCommon.h>
+#include <Library/SiPolicyLib.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <Protocol/FirmwareVolumeBlock.h> #include
+<Library/PostCodeLib.h> #include <PlatformPostCode.h> #include
+<Ppi/Spi.h> #include <Library/MtrrLib.h> #include
+<Library/PciSegmentLib.h> #include <Register/PchRegs.h> #include
+<PlatformBoardId.h> #include <Core/Pei/PeiMain.h> #include
+<Library/PchPciBdfLib.h> #include <Ppi/GraphicsPlatformPolicyPpi.h>
+#include <Library/PeiGetFvInfoLib.h>
+
+
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitEndOfPei (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK |
+EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiEndOfPeiSignalPpiGuid,
+ (EFI_PEIM_NOTIFY_ENTRY_POINT) OpenBoardPlatformInitEndOfPei };
+
+EFI_STATUS
+EFIAPI
+GetPeiPlatformLidStatus (
+ OUT LID_STATUS *CurrentLidStatus
+ );
+
+EFI_STATUS
+EFIAPI
+GetVbtData (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ );
+
+PEI_GRAPHICS_PLATFORM_POLICY_PPI PeiGraphicsPlatform = {
+ PEI_GRAPHICS_PLATFORM_POLICY_REVISION,
+ GetPeiPlatformLidStatus,
+ GetVbtData
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPeiGraphicsPlatformPpi = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gPeiGraphicsPlatformPpiGuid,
+ &PeiGraphicsPlatform
+};
+
+EFI_STATUS
+EFIAPI
+GetVbtData (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ )
+{
+ EFI_GUID FileGuid;
+ EFI_GUID BmpImageGuid;
+ VOID *Buffer;
+ UINT32 Size;
+
+ Size = 0;
+ Buffer = NULL;
+
+
+ DEBUG((DEBUG_INFO, "GetVbtData Entry\n"));
+
+ CopyMem (&BmpImageGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid),
+ sizeof(BmpImageGuid));
+
+ CopyMem(&FileGuid, &BmpImageGuid, sizeof(FileGuid));
+ PeiGetSectionFromFv(FileGuid, &Buffer, &Size); if (Buffer == NULL) {
+ DEBUG((DEBUG_ERROR, "Could not locate VBT\n")); } else {
+ DEBUG ((DEBUG_INFO, "GetVbtData Buffer is 0x%x\n", Buffer));
+ DEBUG ((DEBUG_INFO, "GetVbtData Size is 0x%x\n", Size));
+ *VbtAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer;
+ *VbtSize = Size;
+ }
+ DEBUG((DEBUG_INFO, "GetVbtData exit\n"));
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function will return Lid Status in PEI phase.
+
+ @param[out] CurrentLidStatus
+
+ @retval EFI_SUCCESS
+ @retval EFI_UNSUPPORTED
+**/
+
+EFI_STATUS
+EFIAPI
+GetPeiPlatformLidStatus (
+ OUT LID_STATUS *CurrentLidStatus
+ )
+{
+ DEBUG ((DEBUG_INFO, "LidStatus Unsupported\n"));
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Configure PciHostBridge related PCDs
+**/
+VOID
+ConfigurePciHostBridgePcds (
+ VOID
+ )
+{
+ //
+ // Provide 256GB available above 4GB MMIO resource
+ // limited to use single variable MTRR to cover this above 4GB MMIO region.
+ //
+ PcdSet64S (PcdPciReservedMemAbove4GBBase, BASE_256GB);
+ PcdSet64S (PcdPciReservedMemAbove4GBLimit, BASE_256GB + SIZE_256GB -
+1);
+ if (PcdGet64 (PcdPciReservedMemAbove4GBBase) < PcdGet64 (PcdPciReservedMemAbove4GBLimit)) {
+ DEBUG ((DEBUG_INFO, " PCI space that above 4GB MMIO is from 0x%lX", PcdGet64 (PcdPciReservedMemAbove4GBBase)));
+ DEBUG ((DEBUG_INFO, " to 0x%lX\n", PcdGet64
+(PcdPciReservedMemAbove4GBLimit)));
+ }
+}
+
+/**
+ This function handles PlatformInit task at the end of PEI
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this function.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval others
+**/
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitEndOfPei (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ //
+ // Configure PciHostBridge related PCDs before DXE phase
+ //
+ ConfigurePciHostBridgePcds ();
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Platform Init PEI module entry point
+
+ @param[in] FileHandle Not used.
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
+**/
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitPostMemEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ PEI_CORE_INSTANCE *PrivateData;
+ UINTN CurrentFv;
+ PEI_CORE_FV_HANDLE *CoreFvHandle;
+ VOID *HobData;
+
+ PostCode (PLATFORM_INIT_POSTMEM_ENTRY);
+
+ //
+ // Build a HOB to show current FV location for SA policy update code to consume.
+ //
+ PrivateData = PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices);
+ CurrentFv = PrivateData->CurrentPeimFvCount; CoreFvHandle =
+ &(PrivateData->Fv[CurrentFv]);
+
+ HobData = BuildGuidHob (
+ &gPlatformInitFvLocationGuid,
+ sizeof (VOID *)
+ );
+ ASSERT (HobData != NULL);
+ CopyMem (HobData, (VOID *) &CoreFvHandle, sizeof (VOID *));
+
+ //
+ // Install mPeiGraphicsPlatformPpi
+ //
+ DEBUG ((DEBUG_INFO, "Install mPeiGraphicsPlatformPpi \n")); Status =
+ PeiServicesInstallPpi (&mPeiGraphicsPlatformPpi);
+
+ //
+ // Performing PlatformInitEndOfPei after EndOfPei PPI produced //
+ Status = PeiServicesNotifyPpi (&mEndOfPeiNotifyList); PostCode
+ (PLATFORM_INIT_POSTMEM_EXIT);
+
+ return Status;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
new file mode 100644
index 0000000000..b2bfd97f8a
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoa
+++ rdPlatformInitPei/OpenBoardPlatformInitPostMem.inf
@@ -0,0 +1,75 @@
+### @file
+# Component information file for the OpenBoard Platform Init PEI module.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = OpenBoardPlatformInitPostMem
+ FILE_GUID = 314EE04C-1106-4DC6-ACBC-CF19C0DBC5CC
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = OpenBoardPlatformInitPostMemEntryPoint
+
+[LibraryClasses]
+ PeimEntryPoint
+ DebugLib
+ IoLib
+ MemoryAllocationLib
+ BaseMemoryLib
+ HobLib
+ PeiServicesLib
+ PciSegmentLib
+ MtrrLib
+ PchInfoLib
+ PostCodeLib
+ SiPolicyLib
+ FspCommonLib
+ PcdLib
+ PchPciBdfLib
+ GpioLib
+ PeiGetFvInfoLib
+
+[Packages]
+ AlderlakeSiliconPkg/SiPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ AlderLakeFspBinPkg/Client/AlderLakeP/AlderLakeFspBinPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+ OpenBoardPlatformInitPostMem.c
+
+[Ppis]
+ gEfiEndOfPeiSignalPpiGuid ## CONSUMES
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+ gPeiGraphicsPlatformPpiGuid ## PRODUCES
+ gFspSiliconInitDonePpiGuid ## CONSUMES
+
+[Protocols]
+
+[Guids]
+ gEfiSmmSmramMemoryGuid ## CONSUMES
+ gPlatformInitFvLocationGuid ## PRODUCES
+
+[Depex]
+ gEfiPeiMemoryDiscoveredPpiGuid
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIobase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIoLimit ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciSegmentCount ## CONSUMES
+
+ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUMES
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc
new file mode 100644
index 0000000000..9215a026ae
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructP
+++ CD.dsc
@@ -0,0 +1,19 @@
+## @file
+# Include All Board Gpio configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+!include
+$(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
+!include
+$(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
+
+
+# PCIe clock mapping
+!include
+$(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.
+dsc
+
+# MRC DQS DQ and SPD mapping
+!include
+$(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
+
+
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
new file mode 100644
index 0000000000..3eb8c276b5
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableA
+++ dlPPostMem.dsc
@@ -0,0 +1,40 @@
+## @file
+# GPIO definition table for Alderlake P #
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+###
+### !!! GPIOs designated to Native Functions shall not be configured by Platform Code.
+### Native Pins shall be configured by Silicon Code (based on BIOS policies setting) or soft straps(set by CSME in FITc).
+###
+###
+
+
+#mGpioTableAdlPDdr5Rvp
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable|*|{CODE({
+ // CPU M.2 SSD1
+ {GPIO_VER2_LP_GPP_F20, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD1 RESET
+
+ // CPU M.2 SSD2
+ {GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 PWREN
+ {GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, // CPU SSD2 RESET
+
+ // X4 Pcie Slot for Gen3 and Gen 4
+ {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}},//ONBOARD_X4_PCIE_SLOT1_RESET_N
+
+ // PCH M.2 SSD
+ {GPIO_VER2_LP_GPP_D16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_PCH_SSD_PWREN
+ {GPIO_VER2_LP_GPP_H0, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_SSD_RST_N
+
+ // EC
+ {GPIO_VER2_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSmi,GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //EC_SMI_N
+ {GPIO_VER2_LP_GPP_F9, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //EC_SLP_S0_CS_N
+
+ {0x0} // terminator
+})}
+
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
new file mode 100644
index 0000000000..7bf8571c27
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableA
+++ dlPPreMem.dsc
@@ -0,0 +1,29 @@
+## @file
+# Alderlake P RVP GPIO definition table for Pre-Memory Initialization
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+###
+### !!! GPIOs designated to Native Functions shall not be configured by Platform Code.
+### Native Pins shall be configured by Silicon Code (based on BIOS policies setting) or soft straps(set by CSME in FITc).
+###
+###
+
+# mGpioTablePreMemAdlPDdr5Rvp
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
+ // CPU M.2 SSD
+ { GPIO_VER2_LP_GPP_F20, { GpioPadModeGpio, GpioHostOwnAcpi,
+GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }
+}, //CPU SSD RESET
+
+ // CPU M.2 SSD2
+ {GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 PWREN
+ {GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 RESET
+
+ // X4 Pcie Slot for Gen3 and Gen 4
+ {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}},//ONBOARD_X4_PCIE_SLOT1_RESET_N
+
+ {0x0} // terminator
+})}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
new file mode 100644
index 0000000000..096cc380cd
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSP
+++ D/AdlPSpdMap.dsc
@@ -0,0 +1,138 @@
+## @file
+# ADL P SPD DATA configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData|*|{CODE(
+{
+// DDR5 1Rx16 - 4800 MHz
+ 1,
+ {0x30, ///< 0 1024 SPD bytes total
+ 0x08, ///< 1 SPD Revision 0.8
+ 0x12, ///< 2 DRAM Type: DDR5 SDRAM
+ 0x03, ///< 3 Module Type: Not Hybrid (DRAM only) / SO-DIMM Solution
+ 0x04, ///< 4 Monolithic SDRAM, 16 Gb SDRAM density
+ 0x00, ///< 5 16 Rows, 10 Columns
+ 0x40, ///< 6 x16 SDRAM I/O Width
+ 0x42, ///< 7 4 Bank Groups, 4 Banks per Bank Group
+ 0x00, ///< 8 Secondary SDRAM Density and Package
+ 0x00, ///< 9 Secondary SDRAM Addressing
+ 0x00, ///< 10 Secondary SDRAM I/O Width
+ 0x00, ///< 11 Secondary BankGroups and Banks per Bank Group
+ 0x60, ///< 12 PPR Supported, One row per bank group, Soft PPR Supported
+ 0x00, ///< 13 Commercial Temperature Grade, 0 to 85 C
+ 0x00, ///< 14 Reserved
+ 0x00, ///< 15 Reserved
+ 0x00, ///< 16 SDRAM Nominal Voltage VDD: 1.1V
+ 0x00, ///< 17 SDRAM Nominal Voltage VDDQ: 1.1V
+ 0x00, ///< 18 SDRAM Nominal Voltage VPP: 1.8V
+ 0x00, ///< 19 Reserved
+ 0xA1, ///< 20 tCKAVGmin LSB
+ 0x01, ///< 21 tCKAVGmin MSB
+ 0xE8, ///< 22 tCKAVGmax LSB
+ 0x03, ///< 23 tCKAVGmax MSB
+ 0x72, ///< 24 CAS Latencies supported (First Byte) : 32, 30, 28, 22
+ 0x15, ///< 25 CAS Latencies supported (Second Byte): 44, 40, 36
+ 0x00, ///< 26 CAS Latencies supported (Third Byte) :
+ 0x00, ///< 27 CAS Latencies supported (Fourth Byte):
+ 0x00, ///< 28 CAS Latencies supported (Fifth Byte) :
+ 0x00, ///< 29 Reserved
+ 0x1E, ///< 30 Minimum CAS Latency (tAAmin) LSB
+ 0x41, ///< 31 Minimum CAS Latency (tAAmin) MSB
+ 0x1E, ///< 32 Minimum RAS-to-CAS delay (tRCDmin) LSB
+ 0x41, ///< 33 Minimum RAS-to-CAS delay (tRCDmin) MSB
+ 0x1E, ///< 34 Minimum Row Precharge delay (tRPmin) LSB
+ 0x41, ///< 35 Minimum Row Precharge delay (tRPmin) MSB
+ 0x00, ///< 36 Minimum Active to Precharge delay (tRASmin) LSB
+ 0x7D, ///< 37 Minimum Active to Precharge delay (tRASmin) MSB
+ 0x1E, ///< 38 Minimum Active to Active/Refresh delay (tRCmin) LSB
+ 0xBE, ///< 39 Minimum Active to Active/Refresh delay (tRCmin) MSB
+ 0x30, ///< 40 Minimum Write Recovery time (tWRmin) LSB
+ 0x75, ///< 41 Minimum Write Recovery time (tWRmin) MSB
+ 0x27, ///< 42 Refresh Recovery Delay (tRFC1min) LSB
+ 0x01, ///< 43 Refresh Recovery Delay (tRFC1min) MSB
+ 0xA0, ///< 44 Refresh Recovery Delay (tRFC2min) MSB
+ 0x00, ///< 45 Refresh Recovery Delay (tRFC2min) MSB
+ 0x82, ///< 46 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0x00, ///< 47 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0, 0, ///< 48 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0, 0, 0, 0, 0, 0, ///< 120 - 125
+ 0x47, ///< 126 CRC Bytes 0 - 127 LSB
+ 0xAE, ///< 127 CRC Bytes 0 - 127 MSB
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, ///< 190 - 191
+ 0x08, ///< 192 SPD Revision for Module Information: 0.8
+ 0x00, ///< 193 Reserved
+ 0xC2, ///< 194 SPD Manufacturer ID First Byte
+ 0xC4, ///< 195 SPD Manufacturer ID Second Byte
+ 0x80, ///< 196 SPD Device Type
+ 0x00, ///< 197 SPD Device Revision
+ 0x80, ///< 198 PMIC0 Manufacturer ID First Byte
+ 0xB3, ///< 199 PMIC0 Manufacturer ID Second Byte
+ 0x80, ///< 200 PMIC0 Device Type
+ 0x11, ///< 201 PMIC0 Device Revision
+ 0, 0, 0, 0, ///< 202 - 205 PMIC1
+ 0, 0, 0, 0, ///< 206 - 209 PMIC2
+ 0x80, ///< 210 Thermal Sensors Manufacturer ID First Byte
+ 0xB3, ///< 211 Thermal Sensors Manufacturer ID First Byte
+ 0x80, ///< 212 Thermal Sensors Device Type
+ 0x11, ///< 213 Thermal Sensors Device Revision
+ 0, 0, 0, 0, 0, 0, ///< 214 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0x0F, ///< 230 Module Nominal Height
+ 0x10, ///< 231 Module Nominal Thickness
+ 0x00, ///< 232 Reference Raw Card Used
+ 0x01, ///< 233 1 Row of DRAM on Module
+ 0x01, ///< 234 1 Rank, 8 bits SDRAM data width per channel
+ 0x22, ///< 235 2 Channels per DIMM, 32 bits per Channel
+ 0, 0, 0, 0, ///< 236 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 320 - 329
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 330 - 339
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 340 - 349
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 350 - 359
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ///< 440 - 445
+ 0x9C, ///< 446 CRC for Bytes 128 - 253 LSB
+ 0xAD, ///< 447 CRC for Bytes 128 - 253 MSB
+ 0, 0, ///< 448 - 449
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
+ 0, 0 ///< 510 - 511
+ ///< Ignore bytes 512-1023, @todo_adl: support 1024 bytes SPD
+array }})}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
new file mode 100644
index 0000000000..57106e92c4
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks
+++ /AdlPPcieClocks.dsc
@@ -0,0 +1,31 @@
+## @file
+# Alderlake P Pcie Clock configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
+{{
+ PCIE_PEG, // CPU M.2 SSD 1
+ PCIE_PCH + 8, // PCH M.2 SSD
+ PCIE_PCH + 4,
+ PCIE_PEG + 1, // X8 DG/DG2
+ PCIE_PEG + 2, // CPU M.2 SSD 2
+ PCIE_PCH + 5, // M.2 KEY B WWAN - PCIe P6
+ LAN_CLOCK,
+ // Default Case:
+ // - PCIe P7 mapped to GBELAN
+ // - PCIe P8 mapped to x4 PCIe DT Slot (Pair 1)
+ PCIE_PCH + 7, // x4 PCIe DT Slot (x1)
+ // Reworked Case: with rework and soft strap changes
+ // - PCIe P7 mapped to x4 PCIe DT Slot (Pair 2)
+ // - PCIe P8 mapped to x4 PCIe DT Slot (Pair 1)
+ // PCIE_PCH + 6, // x4 PCIe DT Slot (x2)
+ NOT_USED,
+ NOT_USED
+}}
+)}
--
2.36.1.windows.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [edk2-devel] [PATCH v2 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add libraries
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add libraries Saloni Kasbekar
2023-08-02 18:10 ` Chaganty, Rangasai V
@ 2023-08-04 0:48 ` Chuang, Rosen
1 sibling, 0 replies; 18+ messages in thread
From: Chuang, Rosen @ 2023-08-04 0:48 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Desimone, Nathaniel L, Oram, Isaac W
Reviewed-by: Rosen Chuang < rosen.chuang@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Wednesday, August 2, 2023 6:18 AM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add libraries
Adds the following library instances:
- BoardAcpiLib
- BoardInitLib
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../SmmAlderlakePRvpAcpiEnableLib.c | 50 +++++
.../SmmMultiBoardAcpiSupportLib.c | 88 ++++++++
.../SmmMultiBoardAcpiSupportLib.inf | 41 ++++
.../BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 134 ++++++++++++
.../BoardInitLib/Pei/BoardPchInitPreMemLib.c | 104 +++++++++
.../BoardInitLib/Pei/BoardSaConfigPreMem.h | 73 +++++++
.../BoardInitLib/Pei/BoardSaInitPreMemLib.c | 160 ++++++++++++++
.../Library/BoardInitLib/Pei/PeiDetect.c | 62 ++++++
.../BoardInitLib/Pei/PeiInitPostMemLib.c | 100 +++++++++
.../BoardInitLib/Pei/PeiInitPreMemLib.c | 202 ++++++++++++++++++
.../Pei/PeiMultiBoardInitPostMemLib.c | 45 ++++
.../Pei/PeiMultiBoardInitPostMemLib.inf | 53 +++++
.../Pei/PeiMultiBoardInitPreMemLib.c | 89 ++++++++
.../Pei/PeiMultiBoardInitPreMemLib.inf | 149 +++++++++++++
14 files changed, 1350 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmAlderlakePRvpAcpiEnableLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardPchInitPreMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaConfigPreMem.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaInitPreMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiDetect.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPostMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPreMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmAlderlakePRvpAcpiEnableLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmAlderlakePRvpAcpiEnableLib.c
new file mode 100644
index 0000000000..8dfc04c5f5
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAc
+++ piLib/SmmAlderlakePRvpAcpiEnableLib.c
@@ -0,0 +1,50 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardId.h>
+
+/**
+ Enable Board Acpi
+
+ @param[in] EnableSci Enable SCI if EnableSci parameters is True.
+
+ @retval EFI_SUCCESS The function always return successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ // enable additional board register
+ return EFI_SUCCESS;
+}
+
+/**
+ Disable Board Acpi
+
+ @param[in] DisableSci Disable SCI if DisableSci parameters is True.
+
+ @retval EFI_SUCCESS The function always return successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ // enable additional board register
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
new file mode 100644
index 0000000000..ea0f7c966b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAc
+++ piLib/SmmMultiBoardAcpiSupportLib.c
@@ -0,0 +1,88 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h> #include
+<Library/MultiBoardAcpiSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+AdlBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+AdlBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+MultiBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ SiliconEnableAcpi (EnableSci);
+ return AdlBoardEnableAcpi (EnableSci); }
+
+EFI_STATUS
+EFIAPI
+MultiBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ SiliconDisableAcpi (DisableSci);
+ return AdlBoardDisableAcpi (DisableSci); }
+
+BOARD_ACPI_ENABLE_FUNC mBoardAcpiEnableFunc = {
+ MultiBoardEnableAcpi,
+ MultiBoardDisableAcpi,
+};
+
+/**
+ The constructor function to register mBoardAcpiEnableFunc function.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS This constructor always return EFI_SUCCESS.
+ It will ASSERT on errors.
+**/
+EFI_STATUS
+EFIAPI
+SmmMultiBoardAcpiSupportLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ return RegisterBoardAcpiEnableFunc (&mBoardAcpiEnableFunc); }
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
new file mode 100644
index 0000000000..8a418bc8da
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAc
+++ piLib/SmmMultiBoardAcpiSupportLib.inf
@@ -0,0 +1,41 @@
+## @file
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> #
+SPDX-License-Identifier: BSD-2-Clause-Patent # ##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SmmMultiBoardAcpiSupportLib
+ FILE_GUID = 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_SMM_DRIVER
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = SmmMultiBoardAcpiSupportLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC #
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciLib
+ PchCycleDecodingLib
+ PchPciBdfLib
+ PmcLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ SmmAlderlakePRvpAcpiEnableLib.c
+ SmmSiliconAcpiEnableLib.c
+ SmmMultiBoardAcpiSupportLib.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
new file mode 100644
index 0000000000..fbe745ad36
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAc
+++ piLib/SmmSiliconAcpiEnableLib.c
@@ -0,0 +1,134 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/BoardAcpiEnableLib.h> #include <Library/PcdLib.h>
+#include <Library/DebugLib.h> #include <Library/PmcLib.h> #include
+<Library/PchPciBdfLib.h> #include <Register/PchRegs.h> #include
+<Register/PchRegsLpc.h> #include <Register/PmcRegs.h> #include
+<Register/RtcRegs.h>
+
+/**
+ Clear Port 80h
+
+ Disables the SW SMI Timer.
+ ACPI events are disabled and ACPI event status is cleared.
+
+ Disable port 60/64 SMI trap if they are enabled
+
+ Disable PM sources except power button Clear status bits
+
+ Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+
+ Enable SCI
+**/
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+
+ UINT32 SmiEn;
+ UINT32 SmiSts;
+ UINT32 ULKMC;
+ UINTN LpcBaseAddress;
+ UINT16 AcpiBaseAddr;
+ UINT32 Pm1Cnt;
+
+ LpcBaseAddress = LpcPciCfgBase ();
+
+ //
+ // Get the ACPI Base Address
+ //
+ AcpiBaseAddr = PmcGetAcpiBase();
+
+ //
+ // Clear Port 80h
+ //
+ IoWrite8 (0x80, 0);
+
+ //
+ // Disable SW SMI Timer and clean the status // SmiEn = IoRead32
+ (AcpiBaseAddr + R_ACPI_IO_SMI_EN); SmiEn &=
+ ~(B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR |
+ B_ACPI_IO_SMI_EN_LEGACY_USB);
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN, SmiEn);
+
+ SmiSts = IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS); SmiSts |=
+ B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR |
+ B_ACPI_IO_SMI_EN_LEGACY_USB;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS, SmiSts);
+
+ //
+ // Disable port 60/64 SMI trap if they are enabled // ULKMC =
+ MmioRead32 (LpcBaseAddress + R_LPC_CFG_ULKMC) &
+ ~(B_LPC_CFG_ULKMC_60REN | B_LPC_CFG_ULKMC_60WEN |
+ B_LPC_CFG_ULKMC_64REN | B_LPC_CFG_ULKMC_64WEN |
+ B_LPC_CFG_ULKMC_A20PASSEN);
+ MmioWrite32 (LpcBaseAddress + R_LPC_CFG_ULKMC, ULKMC);
+
+ //
+ // Disable PM sources except power button //
+ IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_EN, B_ACPI_IO_PM1_EN_PWRBTN);
+
+ //
+ // Clear PM status except Power Button status for RapidStart Resume
+ //
+ IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_STS, 0xFEFF);
+
+ //
+ // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+ //
+ IoWrite8 (R_RTC_IO_INDEX_ALT, R_RTC_IO_REGD);
+ IoWrite8 (R_RTC_IO_TARGET_ALT, 0x0);
+
+ //
+ // Enable SCI
+ //
+ if (EnableSci) {
+ Pm1Cnt = IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);
+ Pm1Cnt |= B_ACPI_IO_PM1_CNT_SCI_EN;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt); }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+
+ UINT16 AcpiBaseAddr;
+ UINT32 Pm1Cnt;
+
+ //
+ // Get the ACPI Base Address
+ //
+ AcpiBaseAddr = PmcGetAcpiBase();
+ //
+ // Disable SCI
+ //
+ if (DisableSci) {
+ Pm1Cnt = IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);
+ Pm1Cnt &= ~B_ACPI_IO_PM1_CNT_SCI_EN;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt); }
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardPchInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardPchInitPreMemLib.c
new file mode 100644
index 0000000000..13ad444f8b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/BoardPchInitPreMemLib.c
@@ -0,0 +1,104 @@
+/** @file
+ Source code for the board PCH configuration Pcd init functions for Pre-Memory Init phase.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h> #include <Library/DebugLib.h>
+#include <Library/BoardConfigLib.h> #include
+<Include/PlatformBoardId.h> #include <PlatformBoardConfig.h> #include
+<Library/PcdLib.h> #include <PlatformBoardId.h> #include
+<Library/PchInfoLib.h>
+/**
+ Board Root Port Clock Info configuration init function for PEI pre-memory phase.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+AdlPRootPortClkInfoInit (
+ VOID
+ )
+{
+ PCD64_BLOB Clock[PCH_MAX_PCIE_CLOCKS];
+ UINT32 Index;
+ PCIE_CLOCKS_USAGE *PcieClocks;
+
+ PcieClocks = NULL;
+
+ //
+ //The default clock assignment will be NOT_USED, which corresponds to PchClockUsageNotUsed. This will prevent clocks drawing Power by default.
+ //If Platform code doesn't contain port-clock map for a given board, the clocks will be NOT_USED, preventing PCIe devices not to operate.
+ //To prevent this, remember to provide port-clock map for every board.
+ //
+ for (Index = 0; Index < PCH_MAX_PCIE_CLOCKS; Index++) {
+ Clock[Index].PcieClock.ClkReqSupported = TRUE;
+ Clock[Index].PcieClock.ClockUsage = NOT_USED; }
+
+ ///
+ /// Assign ClkReq signal to root port. (Base 0) /// For LP, Set 0 -
+ 5 /// For H, Set 0 - 15 /// Note that if GbE is enabled, ClkReq
+ assigned to GbE will not be available for Root Port.
+ ///
+
+ PcieClocks = PcdGetPtr(VpdPcdPcieClkUsageMap); if (PcieClocks ==
+ NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Clock[0].PcieClock.ClockUsage = PcieClocks->ClockUsage[0];
+ Clock[1].PcieClock.ClockUsage = PcieClocks->ClockUsage[1];
+ Clock[2].PcieClock.ClockUsage = PcieClocks->ClockUsage[2];
+ Clock[3].PcieClock.ClockUsage = PcieClocks->ClockUsage[3];
+ Clock[4].PcieClock.ClockUsage = PcieClocks->ClockUsage[4];
+ Clock[5].PcieClock.ClockUsage = PcieClocks->ClockUsage[5];
+ Clock[6].PcieClock.ClockUsage = PcieClocks->ClockUsage[6];
+ Clock[7].PcieClock.ClockUsage = PcieClocks->ClockUsage[7];
+ Clock[8].PcieClock.ClockUsage = PcieClocks->ClockUsage[8];
+ Clock[9].PcieClock.ClockUsage = PcieClocks->ClockUsage[9];
+
+ PcdSet64S (PcdPcieClock0, Clock[ 0].Blob);
+ PcdSet64S (PcdPcieClock1, Clock[ 1].Blob);
+ PcdSet64S (PcdPcieClock2, Clock[ 2].Blob);
+ PcdSet64S (PcdPcieClock3, Clock[ 3].Blob);
+ PcdSet64S (PcdPcieClock4, Clock[ 4].Blob);
+ PcdSet64S (PcdPcieClock5, Clock[ 5].Blob);
+ PcdSet64S (PcdPcieClock6, Clock[ 6].Blob);
+ PcdSet64S (PcdPcieClock7, Clock[ 7].Blob);
+ PcdSet64S (PcdPcieClock8, Clock[ 8].Blob);
+ PcdSet64S (PcdPcieClock9, Clock[ 9].Blob);
+ PcdSet64S (PcdPcieClock10, Clock[10].Blob);
+ PcdSet64S (PcdPcieClock11, Clock[11].Blob);
+ PcdSet64S (PcdPcieClock12, Clock[12].Blob);
+ PcdSet64S (PcdPcieClock13, Clock[13].Blob);
+ PcdSet64S (PcdPcieClock14, Clock[14].Blob);
+ PcdSet64S (PcdPcieClock15, Clock[15].Blob);
+ return EFI_SUCCESS;
+}
+
+/**
+ Board GPIO Group Tier configuration init function for PEI pre-memory phase.
+**/
+VOID
+AdlPGpioGroupTierInit (
+ VOID
+ )
+{
+ //
+ // GPIO Group Tier
+ //
+ PcdSet32S (PcdGpioGroupToGpeDw0, 0);
+ PcdSet32S (PcdGpioGroupToGpeDw1, 0);
+ PcdSet32S (PcdGpioGroupToGpeDw2, 0);
+
+ return;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaConfigPreMem.h b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaConfigPreMem.h
new file mode 100644
index 0000000000..c79555cde8
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/BoardSaConfigPreMem.h
@@ -0,0 +1,73 @@
+/** @file
+ PEI Boards Configurations for PreMem phase.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _BOARD_SA_CONFIG_PRE_MEM_H_
+#define _BOARD_SA_CONFIG_PRE_MEM_H_
+
+#include <Ppi/SiPolicy.h>
+#include <Library/BoardConfigLib.h>
+
+#define SA_MRC_MAX_RCOMP_TARGETS (5)
+
+//
+// Reference RCOMP resistors on motherboard - MRC will set
+automatically // GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
+AdlPRcompResistorZero = 0;
+
+//
+// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - MRC
+will set automatically // GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
+RcompTargetAdlP[SA_MRC_MAX_RCOMP_TARGETS] = { 0, 0, 0, 0, 0 };
+
+//
+// DQ byte mapping to CMD/CTL/CLK, from the CPU side //
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 DqByteMapAdlP[2][6][2] = {
+ // Channel 0:
+ {
+ { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+ { 0x0F, 0xF0 }, // Cmd CAA goes to Bytes[3:0], Cmd CAB goes to Byte[7:4]
+ { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ },
+ // Channel 1:
+ {
+ { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+ { 0x0F, 0xF0 }, // Cmd CAA goes to Bytes[3:0], Cmd CAB goes to Byte[7:4]
+ { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ }
+};
+
+//
+// Display DDI settings for Adl-P Ddr5 Rvp Edp + DP //
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mAdlPDdr5RvpDisplayDdiConfig[16] = {
+ DdiPortEdp, // DDI Port A Config : DdiPortDisabled = No LFP is Connected, DdiPortEdp = eDP, DdiPortMipiDsi = MIPI DSI
+ DdiPortDisabled, // DDI Port B Config : DdiPortDisabled = No LFP is Connected, DdiPortEdp = eDP, DdiPortMipiDsi = MIPI DSI
+ DdiHpdDisable, // DDI Port A HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdEnable, // DDI Port B HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port C HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port 1 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port 2 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port 3 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port 4 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiDisable, // DDI Port A DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port B DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port C DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port 1 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port 2 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port 3 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable // DDI Port 4 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+};
+
+#endif // _BOARD_SA_CONFIG_PRE_MEM_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaInitPreMemLib.c
new file mode 100644
index 0000000000..e42c8fb5f8
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/BoardSaInitPreMemLib.c
@@ -0,0 +1,160 @@
+/** @file
+ Source code for the board SA configuration Pcd init functions in Pre-Memory init phase.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BoardSaConfigPreMem.h"
+#include <Library/CpuPlatformLib.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+/**
+ MRC configuration init function for PEI pre-memory phase.
+
+ @param[in] VOID
+
+ @retval VOID
+**/
+VOID
+AdlPSaMiscConfigInit (
+ VOID
+ )
+{
+ PcdSet8S (PcdSaMiscUserBd, 6);
+ return;
+}
+
+/**
+ Board Memory Init related configuration init function for PEI pre-memory phase.
+
+ @param[in] VOID
+
+ @retval VOID
+**/
+VOID
+AdlPMrcConfigInit (
+ VOID
+ )
+{
+ UINT16 BoardId;
+ BOOLEAN ExternalSpdPresent;
+ MRC_DQS *MrcDqs;
+ MRC_DQ *MrcDq;
+ SPD_DATA *SpdData;
+
+ BoardId = PcdGet16(PcdBoardId);
+
+ // SPD is the same size for all boards PcdSet16S (PcdMrcSpdDataSize,
+ 512);
+
+ ExternalSpdPresent = PcdGetBool (PcdSpdPresent);
+
+ // Assume internal SPD is used
+ PcdSet8S (PcdMrcSpdAddressTable0, 0); PcdSet8S
+ (PcdMrcSpdAddressTable1, 0); PcdSet8S (PcdMrcSpdAddressTable2, 0);
+ PcdSet8S (PcdMrcSpdAddressTable3, 0); PcdSet8S
+ (PcdMrcSpdAddressTable4, 0); PcdSet8S (PcdMrcSpdAddressTable5, 0);
+ PcdSet8S (PcdMrcSpdAddressTable6, 0); PcdSet8S
+ (PcdMrcSpdAddressTable7, 0); PcdSet8S (PcdMrcSpdAddressTable8, 0);
+ PcdSet8S (PcdMrcSpdAddressTable9, 0); PcdSet8S
+ (PcdMrcSpdAddressTable10, 0); PcdSet8S (PcdMrcSpdAddressTable11, 0);
+ PcdSet8S (PcdMrcSpdAddressTable12, 0); PcdSet8S
+ (PcdMrcSpdAddressTable13, 0); PcdSet8S (PcdMrcSpdAddressTable14, 0);
+ PcdSet8S (PcdMrcSpdAddressTable15, 0);
+
+ // Check for external SPD presence
+ if (ExternalSpdPresent) {
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ PcdSet8S (PcdMrcSpdAddressTable0, 0xA0);
+ PcdSet8S (PcdMrcSpdAddressTable1, 0xA2);
+ PcdSet8S (PcdMrcSpdAddressTable8, 0xA4);
+ PcdSet8S (PcdMrcSpdAddressTable9, 0xA6);
+ break;
+ default:
+ break;
+ }
+ }
+
+ // Setting the default DQ Byte Map. It may be overriden to board specific settings below.
+ PcdSet32S (PcdMrcDqByteMap, (UINTN) DqByteMapAdlP); PcdSet16S
+ (PcdMrcDqByteMapSize, sizeof (DqByteMapAdlP));
+
+ // ADL uses the same RCOMP resistors for all DDR types PcdSet32S
+ (PcdMrcRcompResistor, (UINTN) AdlPRcompResistorZero);
+
+ // Use default RCOMP target values for all boards PcdSet32S
+ (PcdMrcRcompTarget, (UINTN) RcompTargetAdlP);
+
+ // Default is NIL
+ PcdSetBoolS (PcdMrcDqPinsInterleavedControl, TRUE); PcdSetBoolS
+ (PcdMrcDqPinsInterleaved, FALSE);
+
+ // DqsMapCpu2Dram is the same size for all boards PcdSet16S
+ (PcdMrcDqsMapCpu2DramSize, sizeof (MRC_DQS)); // DqMapCpu2Dram is the
+ same size for all boards PcdSet16S (PcdMrcDqMapCpu2DramSize, sizeof
+ (MRC_DQ));
+ PcdSet8S (PcdMrcLp5CccConfig, 0x0);
+
+ // CPU-DRAM DQ mapping
+ MrcDq = PcdGetPtr (VpdPcdMrcDqMapCpu2Dram); if (MrcDq != NULL) {
+ PcdSet32S (PcdMrcDqMapCpu2Dram, (UINTN)MrcDq->DqMapCpu2Dram); }
+
+ // CPU-DRAM DQS mapping
+ MrcDqs = PcdGetPtr (VpdPcdMrcDqsMapCpu2Dram); if (MrcDqs != NULL) {
+ PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN)MrcDqs->DqsMapCpu2Dram); }
+
+ // DRAM SPD Data
+ SpdData = PcdGetPtr (VpdPcdMrcSpdData); if (SpdData != NULL) {
+ if (SpdData->OverrideSpd == TRUE) {
+ PcdSet32S (PcdMrcSpdData, (UINTN)SpdData->SpdData);
+ }
+ }
+
+ return;
+}
+
+/**
+ SA Display DDI configuration init function for PEI pre-memory phase.
+
+ @param[in] VOID
+
+ @retval VOID
+**/
+VOID
+AdlPSaDisplayConfigInit (
+ VOID
+ )
+{
+ UINT16 BoardId;
+
+ BoardId = PcdGet16 (PcdBoardId);
+
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ DEBUG ((DEBUG_INFO, "DDI Configuration ADLP Edp DP\n"));
+ PcdSet32S (PcdSaDisplayConfigTable, (UINTN) mAdlPDdr5RvpDisplayDdiConfig);
+ PcdSet16S (PcdSaDisplayConfigTableSize, sizeof (mAdlPDdr5RvpDisplayDdiConfig));
+ break;
+ default:
+ break;
+ }
+
+ return;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiDetect.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiDetect.c
new file mode 100644
index 0000000000..5ad8e56f4d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiDetect.c
@@ -0,0 +1,62 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <Library/BoardConfigLib.h>
+
+BOOLEAN
+IsAdlP (
+ VOID
+ )
+{
+ UINT16 BoardId;
+ BoardId = PcdGet16 (PcdBoardId);
+ if (BoardId == 0) {
+ DEBUG ((DEBUG_INFO, "Let's get Board information first ...\n"));
+ GetBoardConfig ();
+ BoardId = PcdGet16 (PcdBoardId);
+ }
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ DEBUG ((DEBUG_INFO, "AlderLake P Board detected\n"));
+
+ // set sku type to ADL P
+ PcdSet8S (PcdSkuType, AdlPSkuType);
+ return TRUE;
+ break;
+ default:
+ return FALSE;
+ }
+}
+
+EFI_STATUS
+EFIAPI
+AdlPBoardDetect (
+ VOID
+ )
+{
+ UINTN SkuId;
+ SkuId = 0;
+
+ if (LibPcdGetSku () != 0) {
+ return EFI_SUCCESS;
+ }
+
+ DEBUG ((DEBUG_INFO, "AlderLakeP Board Detection Callback\n"));
+
+ if (IsAdlP ()) {
+ SkuId = (UINTN) (PcdGet16 (PcdBoardBomId) << 16) | (PcdGet16 (PcdBoardRev) << 8) | (PcdGet16 (PcdBoardId));
+ LibPcdSetSku (SkuId);
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ }
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPostMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPostMemLib.c
new file mode 100644
index 0000000000..51201bb300
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiInitPostMemLib.c
@@ -0,0 +1,100 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <Library/BoardConfigLib.h>
+#include <Library/GpioLib.h>
+#include <Library/IoLib.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PchInfoLib.h>
+#include <Library/HobLib.h>
+
+
+
+/**
+ Alderlake P boards configuration init function for PEI post memory phase.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlPInit (
+ VOID
+ )
+{
+ UINT16 GpioCount;
+ UINTN Size;
+ EFI_STATUS Status;
+ GPIO_INIT_CONFIG *GpioTable;
+ //
+ // GPIO Table Init
+ //
+ Status = EFI_SUCCESS;
+ GpioCount = 0;
+ Size = 0;
+ GpioTable = NULL;
+ //
+ // GPIO Table Init
+ //
+ //
+ // GPIO Table Init, Update PostMem GPIO table to PcdBoardGpioTable
+ //
+ GpioTable = (GPIO_INIT_CONFIG *)PcdGetPtr(VpdPcdBoardGpioTable);
+
+ GetGpioTableSize (GpioTable, &GpioCount); // // Increase GpioCount
+ for the zero terminator.
+ //
+ GpioCount ++;
+ Size = (UINTN) (GpioCount * sizeof (GPIO_INIT_CONFIG)); Status =
+ PcdSetPtrS (PcdBoardGpioTable, &Size, GpioTable); ASSERT_EFI_ERROR
+ (Status);
+
+ return Status;
+}
+
+/**
+ Configures GPIO
+
+ @param[in] GpioTable Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+
+**/
+VOID
+ConfigureGpio (
+ IN GPIO_INIT_CONFIG *GpioDefinition,
+ IN UINT16 GpioTableCount
+ )
+{
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
+
+ GpioConfigurePads (GpioTableCount, GpioDefinition);
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); }
+
+/**
+ Configure GPIO, TouchPanel, HDA, PMC, TBT etc.
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeSiliconInit (
+ VOID
+ )
+{
+ AdlPInit ();
+ GpioInit (PcdGetPtr (PcdBoardGpioTable));
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPreMemLib.c
new file mode 100644
index 0000000000..0b7db476a1
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiInitPreMemLib.c
@@ -0,0 +1,202 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/BiosIdLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PciLib.h>
+#include <Library/MemoryAllocationLib.h> #include <Library/PeiLib.h>
+#include <Guid/MemoryOverwriteControl.h> #include
+<PlatformBoardConfig.h> #include <Library/PchCycleDecodingLib.h>
+#include <Register/PmcRegs.h> #include <Library/PmcLib.h> #include
+<Ppi/ReadOnlyVariable2.h> #include <Library/PeiServicesLib.h> #include
+<Library/GpioLib.h> #include <Library/BoardConfigLib.h> #include
+<Library/TimerLib.h> #include <PlatformBoardId.h> #include
+<Library/IoLib.h> #include <Pins/GpioPinsVer2Lp.h> #include
+<Library/PchInfoLib.h>
+
+/**
+ Get Vpd binary address
+
+ Parse through each FV for VPD FFS file and return the address
+
+ @retval Address on VPD FFS detection else returns 0
+
+**/
+UINTN
+EFIAPI
+GetVpdFfsAddress (
+ )
+{
+ EFI_STATUS Status;
+ VOID *Address;
+ UINTN Instance;
+ EFI_PEI_FV_HANDLE VolumeHandle;
+ EFI_PEI_FILE_HANDLE FileHandle;
+
+ Address = NULL;
+
+ VolumeHandle = NULL;
+ Instance = 0;
+ while (TRUE) {
+ //
+ // Traverse all firmware volume instances.
+ //
+ Status = PeiServicesFfsFindNextVolume (Instance, &VolumeHandle);
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+
+ FileHandle = NULL;
+ Status = PeiServicesFfsFindFileByName (&gVpdFfsGuid, VolumeHandle, &FileHandle);
+ if (!EFI_ERROR (Status)) {
+ //
+ // Search RAW section.
+ //
+ Status = PeiServicesFfsFindSectionData (EFI_SECTION_RAW, FileHandle, &Address);
+ if (!EFI_ERROR (Status)) {
+ return (UINTN)Address;
+ }
+ }
+
+ //
+ // Search the next volume.
+ //
+ Instance++;
+ }
+
+ DEBUG ((DEBUG_ERROR, " PEI get VPD address: %r\n", EFI_NOT_FOUND));
+ return 0;
+}
+
+/**
+ Alderlake P boards configuration init function for PEI pre-memory phase.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlPInitPreMem (
+ VOID
+ )
+{
+ UINTN VpdBaseAddress;
+
+ VpdBaseAddress = (UINTN) PcdGet64 (PcdVpdBaseAddress64); DEBUG
+ ((DEBUG_INFO, "VpdFfsAddress: %x\n", VpdBaseAddress)); if
+ (VpdBaseAddress == 0) {
+ VpdBaseAddress= (UINTN) GetVpdFfsAddress();
+ PcdSet64S (PcdVpdBaseAddress64,VpdBaseAddress);
+ DEBUG ((DEBUG_INFO, "VpdFfsAddress updated: %x\n",
+ VpdBaseAddress)); } PcdSet32S (PcdStackBase, PcdGet32
+ (PcdTemporaryRamBase) + PcdGet32 (PcdTemporaryRamSize) - (PcdGet32
+ (PcdFspTemporaryRamSize) + PcdGet32 (PcdFspReservedBufferSize)));
+ PcdSet32S (PcdStackSize, PcdGet32 (PcdFspTemporaryRamSize));
+
+ return EFI_SUCCESS;
+}
+
+
+VOID
+AdlPMrcConfigInit (
+ VOID
+ );
+
+VOID
+AdlPSaMiscConfigInit (
+ VOID
+ );
+
+VOID
+AdlPSaDisplayConfigInit (
+ VOID
+ );
+
+EFI_STATUS
+AdlPRootPortClkInfoInit (
+ VOID
+ );
+
+VOID
+AdlPGpioGroupTierInit (
+ VOID
+ );
+
+
+/**
+ A hook for board-specific initialization prior to memory initialization.
+
+ @retval EFI_SUCCESS The board initialization was successful.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeMemoryInit (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "AdlPBoardInitBeforeMemoryInit\n"));
+
+ AdlPInitPreMem ();
+
+ AdlPGpioGroupTierInit ();
+
+ AdlPMrcConfigInit ();
+ AdlPSaMiscConfigInit ();
+ Status = AdlPRootPortClkInfoInit ();
+ AdlPSaDisplayConfigInit ();
+ if (PcdGetPtr (PcdBoardGpioTableEarlyPreMem) != 0) {
+ GpioInit (PcdGetPtr (PcdBoardGpioTableEarlyPreMem));
+
+ MicroSecondDelay (15 * 1000); // 15 ms Delay } // Configure GPIO
+ Before Memory GpioInit (PcdGetPtr (PcdBoardGpioTablePreMem));
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This board service initializes board-specific debug devices.
+
+ @retval EFI_SUCCESS Board-specific debug initialization was successful.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardDebugInit (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "AdlPBoardDebugInit\n"));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This board service detects the boot mode.
+
+ @retval EFI_BOOT_MODE The boot mode.
+**/
+EFI_BOOT_MODE
+EFIAPI
+AdlPBoardBootModeDetect (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "AdlPBoardBootModeDetect\n"));
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c
new file mode 100644
index 0000000000..aa9809d126
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiMultiBoardInitPostMemLib.c
@@ -0,0 +1,45 @@
+/** @file
+ PEI Multi-Board Initialization in Post-Memory PEI Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeSiliconInit (
+ VOID
+ );
+
+
+BOARD_POST_MEM_INIT_FUNC mAdlPBoardInitFunc = {
+ AdlPBoardInitBeforeSiliconInit,
+ NULL,
+};
+
+EFI_STATUS
+EFIAPI
+PeiAdlPMultiBoardInitLibConstructor (
+ VOID
+ )
+{
+ UINT8 SkuType;
+ SkuType = PcdGet8 (PcdSkuType);
+
+ if (SkuType==AdlPSkuType) {
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ return RegisterBoardPostMemInit (&mAdlPBoardInitFunc);
+ }
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf
new file mode 100644
index 0000000000..a4dbc9294d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiMultiBoardInitPostMemLib.inf
@@ -0,0 +1,53 @@
+## @file
+# Component information file for Alderlake Multi-Board Initialization in PEI post memory phase.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiAdlPMultiBoardInitLib
+ FILE_GUID = C7D39F17-E5BA-41D9-8DFE-FF9017499280
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = PeiAdlPMultiBoardInitLibConstructor
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PcdLib
+ MultiBoardInitSupportLib
+ PciSegmentLib
+ GpioLib
+ HobLib
+ BoardConfigLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ SecurityPkg/SecurityPkg.dec
+
+[Sources]
+ PeiInitPostMemLib.c
+ PeiMultiBoardInitPostMemLib.c
+
+[Pcd]
+ # Board GPIO Table
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
+
+ # TPM interrupt
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable ## CONSUMES
+ #Misc Config
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId
+
+ gBoardModuleTokenSpaceGuid.PcdBoardId
+ gBoardModuleTokenSpaceGuid.PcdSkuType
+ gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c
new file mode 100644
index 0000000000..fa45e86ac2
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiMultiBoardInitPreMemLib.c
@@ -0,0 +1,89 @@
+/** @file
+ PEI Multi-Board Initialization in Pre-Memory PEI Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BoardConfigLib.h>
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+AdlPBoardDetect (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+AdlPMultiBoardDetect (
+ VOID
+ );
+
+EFI_BOOT_MODE
+EFIAPI
+AdlPBoardBootModeDetect (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+AdlPBoardDebugInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeMemoryInit (
+ VOID
+ );
+
+BOARD_DETECT_FUNC mAdlPBoardDetectFunc = {
+ AdlPMultiBoardDetect
+};
+
+BOARD_PRE_MEM_INIT_FUNC mAdlPBoardPreMemInitFunc = {
+ AdlPBoardDebugInit,
+ AdlPBoardBootModeDetect,
+ AdlPBoardInitBeforeMemoryInit,
+ NULL, // BoardInitAfterMemoryInit
+ NULL, // BoardInitBeforeTempRamExit
+ NULL, // BoardInitAfterTempRamExit
+};
+
+EFI_STATUS
+EFIAPI
+AdlPMultiBoardDetect (
+ VOID
+ )
+{
+ UINT8 SkuType;
+ DEBUG ((DEBUG_INFO, " In AdlPMultiBoardDetect \n"));
+
+ AdlPBoardDetect ();
+
+ SkuType = PcdGet8 (PcdSkuType);
+ if (SkuType==AdlPSkuType) {
+ RegisterBoardPreMemInit (&mAdlPBoardPreMemInitFunc);
+ } else {
+ DEBUG ((DEBUG_WARN,"Not a Valid Alderlake P Board\n"));
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+PeiAdlPMultiBoardInitPreMemLibConstructor (
+ VOID
+ )
+{
+ return RegisterBoardDetect (&mAdlPBoardDetectFunc); }
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf
new file mode 100644
index 0000000000..ea2b64050d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardIn
+++ itLib/Pei/PeiMultiBoardInitPreMemLib.inf
@@ -0,0 +1,149 @@
+## @file
+# Component information file for PEI Alderlake P Board Init Pre-Mem
+Library #
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiAdlPMultiBoardInitPreMemLib
+ FILE_GUID = EA05BD43-136F-45EE-BBBA-27D75817574F
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = PeiAdlPMultiBoardInitPreMemLibConstructor
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PcdLib
+ MultiBoardInitSupportLib
+ PeiLib
+ BoardConfigLib
+ PchInfoLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+
+[Sources]
+ PeiInitPreMemLib.c
+ PeiMultiBoardInitPreMemLib.c
+ PeiDetect.c
+ BoardSaInitPreMemLib.c
+ BoardPchInitPreMemLib.c
+
+[Pcd]
+ # SA Misc Config
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
+
+ # SPD Address Table
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable4
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable5
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable6
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable7
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable8
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable9
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable10
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable11
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable12
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable13
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable14
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable15
+
+ #MRC Config
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2DramSize
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2Dram
+ gBoardModuleTokenSpaceGuid.PcdMrcLp5CccConfig
+ gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd
+
+ #Board Information
+ gBoardModuleTokenSpaceGuid.PcdSpdPresent
+ gBoardModuleTokenSpaceGuid.PcdBoardRev
+ gBoardModuleTokenSpaceGuid.PcdBoardId
+ gBoardModuleTokenSpaceGuid.PcdSkuType
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
+ gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem
+ gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcDqsMapCpu2Dram
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcDqMapCpu2Dram
+
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES
+
+ gBoardModuleTokenSpaceGuid.PcdStackBase
+ gBoardModuleTokenSpaceGuid.PcdStackSize
+
+ #SA GPIO Config
+ gBoardModuleTokenSpaceGuid.PcdRootPortIndex
+
+ # PCIe Clock Info
+ gBoardModuleTokenSpaceGuid.PcdPcieClock0
+ gBoardModuleTokenSpaceGuid.PcdPcieClock1
+ gBoardModuleTokenSpaceGuid.PcdPcieClock2
+ gBoardModuleTokenSpaceGuid.PcdPcieClock3
+ gBoardModuleTokenSpaceGuid.PcdPcieClock4
+ gBoardModuleTokenSpaceGuid.PcdPcieClock5
+ gBoardModuleTokenSpaceGuid.PcdPcieClock6
+ gBoardModuleTokenSpaceGuid.PcdPcieClock7
+ gBoardModuleTokenSpaceGuid.PcdPcieClock8
+ gBoardModuleTokenSpaceGuid.PcdPcieClock9
+ gBoardModuleTokenSpaceGuid.PcdPcieClock10
+ gBoardModuleTokenSpaceGuid.PcdPcieClock11
+ gBoardModuleTokenSpaceGuid.PcdPcieClock12
+ gBoardModuleTokenSpaceGuid.PcdPcieClock13
+ gBoardModuleTokenSpaceGuid.PcdPcieClock14
+ gBoardModuleTokenSpaceGuid.PcdPcieClock15
+
+
+ # GPIO Group Tier
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2
+
+
+
+ # WWAN Full Card Power Off and reset pins
+ gBoardModuleTokenSpaceGuid.PcdDisableVpdGpioTable
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem ## PRODUCES
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem ## PRODUCES
+
+
+ # Display DDI
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## PRODUCES
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress64 ## CONSUMES
+
+[Guids]
+ gFspNonVolatileStorageHobGuid
+ gEfiMemoryOverwriteControlDataGuid
+ gVpdFfsGuid
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
--
2.36.1.windows.1
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* Re: [edk2-devel] [PATCH v2 4/6] AlderlakeOpenBoardPkg: Add ACPI module
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 4/6] AlderlakeOpenBoardPkg: Add ACPI module Saloni Kasbekar
2023-08-02 20:25 ` Chaganty, Rangasai V
@ 2023-08-04 0:48 ` Chuang, Rosen
1 sibling, 0 replies; 18+ messages in thread
From: Chuang, Rosen @ 2023-08-04 0:48 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Desimone, Nathaniel L, Oram, Isaac W
Reviewed-by: Rosen Chuang < rosen.chuang@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Wednesday, August 2, 2023 6:18 AM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 4/6] AlderlakeOpenBoardPkg: Add ACPI module
Adds the MinDsdt driver
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Acpi/MinDsdt/MinDsdt.asl | 68 +++++
.../Acpi/MinDsdt/MinDsdt.c | 232 ++++++++++++++++++
.../Acpi/MinDsdt/MinDsdt.inf | 48 ++++
3 files changed, 348 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl
new file mode 100644
index 0000000000..be110145bc
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl
@@ -0,0 +1,68 @@
+/** @file
+ ACPI minimum DSDT table
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+DefinitionBlock (
+ "DSDT.aml",
+ "DSDT",
+ 0x01, // DSDT revision.
+ // A Revision field value greater than or equal to 2 signifies that integers
+ // declared within the Definition Block are to be evaluated as 64-bit values
+ "INTEL ", // OEM ID (6 byte string)
+ "MIN ",// OEM table ID (8 byte string)
+ 0x00 // OEM version of DSDT table (4 byte Integer)
+)
+
+// BEGIN OF ASL SCOPE
+{
+ Scope(\_SB) {
+
+//---------------------------------------------------------------------
+------
+ // Begin PCI tree object scope
+ //---------------------------------------------------------------------------
+ Device(PCI0) { // PCI Bridge "Host Bridge"
+ Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy
+ Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't understand the new HID
+ Name(_SEG, 0)
+ Method(^BN00, 0){ return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope
+ Method(_BBN, 0){ return(BN00()) } // Bus number, optional for the Root PCI Bus
+ Name(_UID, 0x0000) // Unique Bus ID, optional
+ Name(BUF0,ResourceTemplate()
+ {
+ //
+ // PCI Configuration Registers ( 0x0CF8 - 0x0CFF )
+ //
+ Io(Decode16,0x0CF8,0x0CF8,1,0x08)
+ //
+ // PCI MMIO space
+ //
+ DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
+ ReadWrite,0x00,0x00,0x00,0x00,0x00,,,PM01)
+ })
+ Method(_CRS,0,Serialized)
+ {
+ //
+ // Create pointers to Memory Sizing values.
+ //
+ CreateDwordField(BUF0, ^PM01._MIN,M1MN)
+ CreateDwordField(BUF0, ^PM01._MAX,M1MX)
+ CreateDwordField(BUF0, ^PM01._LEN,M1LN)
+
+ //
+ // Set Memory Size Values. TLUD represents bits 31:20 of phyical
+ // TOM, so shift these bits into the correct position and fix up
+ // the Memory Region available to PCI.
+ //
+ Subtract (FixedPcdGet32(PcdPciReservedMemLimit),FixedPcdGet32(PcdPciReservedMemBase),M1LN)
+ Store (FixedPcdGet32(PcdPciReservedMemBase), M1MN)
+ Subtract (FixedPcdGet32(PcdPciReservedMemLimit), 1, M1MX)
+
+ Return(BUF0)
+ }
+ }
+ }
+}// End of ASL File
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c
new file mode 100644
index 0000000000..08709a43cd
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c
@@ -0,0 +1,232 @@
+/** @file
+ Min DSDT Driver
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <IndustryStandard/Acpi.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include <Protocol/FirmwareVolume2.h>
+#include <Protocol/AcpiTable.h>
+
+//
+// Function implementations
+//
+
+/**
+ Locate the first instance of a protocol. If the protocol requested
+is an
+ FV protocol, then it will return the first FV that contains the ACPI
+table
+ storage file.
+
+ @param[in] Protocol The protocol to find.
+ @param[in] FfsGuid The FFS that contains the ACPI table.
+ @param[out] Instance Return pointer to the first instance of the protocol.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NOT_FOUND The protocol could not be located.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.
+**/
+EFI_STATUS
+LocateSupportProtocol (
+ IN EFI_GUID *Protocol,
+ IN EFI_GUID *FfsGuid,
+ OUT VOID **Instance
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN NumberOfHandles;
+ EFI_FV_FILETYPE FileType;
+ UINT32 FvStatus;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINTN Size;
+ UINTN Index;
+
+ //
+ // Locate protocol.
+ //
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ Protocol,
+ NULL,
+ &NumberOfHandles,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // Defined errors at this time are not found and out of resources.
+ //
+ return Status;
+ }
+
+ //
+ // Looking for FV with ACPI storage file // for (Index = 0; Index <
+ NumberOfHandles; Index++) {
+
+ //
+ // Get the protocol on this handle
+ // This should not fail because of LocateHandleBuffer
+ //
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ Protocol,
+ Instance
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // See if it has the ACPI storage file
+ //
+ Size = 0;
+ FvStatus = 0;
+ Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile (
+ *Instance,
+ FfsGuid,
+ NULL,
+ &Size,
+ &FileType,
+ &Attributes,
+ &FvStatus
+ );
+
+ //
+ // If we found it, then we are done
+ //
+ if (Status == EFI_SUCCESS) {
+ break;
+ }
+ }
+
+ //
+ // Our exit status is determined by the success of the previous
+ operations // If the protocol was found, Instance already points to it.
+ //
+ //
+ // Free any allocated buffers
+ //
+ FreePool (HandleBuffer);
+
+ return Status;
+}
+
+/**
+ Publish ACPI table from FV.
+
+ @param[in] FfsGuid The FFS that contains the ACPI table.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+PublishAcpiTablesFromFv (
+ IN EFI_GUID *FfsGuid
+ )
+{
+ EFI_STATUS Status;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+ EFI_ACPI_COMMON_HEADER *CurrentTable;
+ UINT32 FvStatus;
+ UINTN Size;
+ UINTN TableHandle;
+ INTN Instance;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+
+ Instance = 0;
+ TableHandle = 0;
+ CurrentTable = NULL;
+ FwVol = NULL;
+
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID
+ **)&AcpiTable); ASSERT_EFI_ERROR (Status);
+
+ //
+ // Locate the firmware volume protocol // Status =
+ LocateSupportProtocol (
+ &gEfiFirmwareVolume2ProtocolGuid,
+ FfsGuid,
+ (VOID **) &FwVol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Read tables from the storage file.
+ //
+
+ while (Status == EFI_SUCCESS) {
+ Status = FwVol->ReadSection (
+ FwVol,
+ FfsGuid,
+ EFI_SECTION_RAW,
+ Instance,
+ (VOID **) &CurrentTable,
+ &Size,
+ &FvStatus
+ );
+
+ if (!EFI_ERROR (Status)) {
+
+ //
+ // Add the table
+ //
+ TableHandle = 0;
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ CurrentTable,
+ CurrentTable->Length,
+ &TableHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Increment the instance
+ //
+ Instance++;
+ CurrentTable = NULL;
+ }
+ }
+
+ //
+ // Finished
+ //
+ return EFI_SUCCESS;
+}
+
+/**
+ ACPI Platform driver installation function.
+
+ @param[in] ImageHandle Handle for this drivers loaded image protocol.
+ @param[in] SystemTable EFI system table.
+
+ @retval EFI_SUCCESS The driver installed without error.
+ @retval EFI_ABORTED The driver encountered an error and could not complete installation of
+ the ACPI tables.
+
+**/
+EFI_STATUS
+EFIAPI
+InstallMinDsdt (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = PublishAcpiTablesFromFv (&gEfiCallerIdGuid);
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf
new file mode 100644
index 0000000000..f257140754
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf
@@ -0,0 +1,48 @@
+### @file
+# Component information file for Minimal DSDT module #
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+# @par Glossary:
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = MinDsdt
+ FILE_GUID = 8EB04370-482C-4505-AA27-7EB226A5729F
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InstallMinDsdt
+
+[Sources.common]
+ MinDsdt.c
+ MinDsdt.asl
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ DebugLib
+ PcdLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ BaseMemoryLib
+ MemoryAllocationLib
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid ## CONSUMES
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+
+[Pcd]
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit
+
+[Depex]
+ gEfiAcpiTableProtocolGuid AND
+ gEfiFirmwareVolume2ProtocolGuid
+
--
2.36.1.windows.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [edk2-devel] [PATCH v2 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module Saloni Kasbekar
2023-08-02 20:35 ` Chaganty, Rangasai V
@ 2023-08-04 0:48 ` Chuang, Rosen
1 sibling, 0 replies; 18+ messages in thread
From: Chuang, Rosen @ 2023-08-04 0:48 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Desimone, Nathaniel L, Oram, Isaac W
Reviewed-by: Rosen Chuang < rosen.chuang@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Wednesday, August 2, 2023 6:18 AM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module
Adds the following libraries within the Policy module
- DxeSiliconPolicyUpdateLib
- PeiPolicyUpdateLib
- PeiSiliconPolicyUpdateLib
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../DxeSaPolicyInit.c | 64 +++
.../DxeSiliconPolicyUpdateLate.c | 78 ++++
.../DxeSiliconPolicyUpdateLib.inf | 53 +++
.../PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c | 114 +++++
.../PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h | 31 ++
.../PeiCpuPolicyUpdatePreMem.c | 93 +++++
.../PeiPolicyUpdateLib/PeiPchPolicyUpdate.c | 210 ++++++++++
.../PeiPolicyUpdateLib/PeiPchPolicyUpdate.h | 24 ++
.../PeiPchPolicyUpdatePreMem.c | 124 ++++++
.../PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf | 208 ++++++++++
.../PeiPolicyUpdateLib/PeiSaPolicyUpdate.c | 214 ++++++++++
.../PeiPolicyUpdateLib/PeiSaPolicyUpdate.h | 27 ++
.../PeiSaPolicyUpdatePreMem.c | 389 ++++++++++++++++++
.../PeiSiliconPolicyUpdateLib.inf | 65 +++
.../PeiSiliconPolicyUpdatePostMem.c | 39 ++
.../PeiSiliconPolicyUpdatePreMem.c | 37 ++
16 files changed, 1770 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
new file mode 100644
index 0000000000..da2f568e07
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
@@ -0,0 +1,64 @@
+/** @file
+ This file initialises and Installs GopPolicy Protocol.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/GraphicsInfoLib.h>
+#include <Protocol/SaPolicy.h>
+
+EFI_STATUS
+EFIAPI
+CreateSaDxeConfigBlocks (
+ IN OUT VOID **SaPolicy
+ );
+
+EFI_STATUS
+EFIAPI
+SaInstallPolicyProtocol (
+ IN EFI_HANDLE ImageHandle,
+ IN VOID *SaPolicy
+ );
+
+/**
+ Initialize SA DXE Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SaPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+ SA_POLICY_PROTOCOL *SaPolicy;
+
+ //
+ // Call CreateSaDxeConfigBlocks to create & initialize platform policy structure
+ // and get all Intel default policy settings.
+ //
+ Status = CreateSaDxeConfigBlocks (&SaPolicy);
+ DEBUG ((DEBUG_INFO, "SaPolicy->TableHeader.NumberOfBlocks = 0x%x\n ", SaPolicy->TableHeader.NumberOfBlocks));
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Install SaInstallPolicyProtocol.
+ // While installed, RC assumes the Policy is ready and finalized. So please
+ // update and override any setting before calling this function.
+ //
+ Status = SaInstallPolicyProtocol (ImageHandle, SaPolicy);
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
new file mode 100644
index 0000000000..11a9950124
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
@@ -0,0 +1,78 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+/**
+ Initialize SA DXE Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SaPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ );
+
+/**
+ Initilize Intel Silicon DXE Platform Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SiliconPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ );
+
+/**
+ Performs silicon late policy update.
+
+ The meaning of Policy is defined by silicon code.
+ It could be the raw data, a handle, a Protocol, etc.
+
+ The input Policy must be returned by SiliconPolicyDoneLate().
+
+ In FSP or non-FSP path, the board may use additional way to get
+ the silicon policy data field based upon the input Policy.
+
+ @param[in, out] Policy Pointer to policy.
+
+ @return the updated policy.
+**/
+VOID *
+EFIAPI
+SiliconPolicyUpdateLate (
+ IN OUT VOID *Policy
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+
+ //
+ // SystemAgent Dxe Platform Policy Initialization
+ //
+ Status = SaPolicyInitDxe (gImageHandle);
+ DEBUG ((DEBUG_INFO, "SystemAgent Dxe Platform Policy Initialization status: %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
new file mode 100644
index 0000000000..54b4d7b17d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
@@ -0,0 +1,53 @@
+## @file
+# Component information file for Silicon Policy Update Library
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = DxeSiliconUpdateLib
+ FILE_GUID = C523609D-E354-416B-B24F-33468D4BD21D
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconPolicyUpdateLib
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ PcdLib
+ DebugLib
+ UefiBootServicesTableLib
+ MemoryAllocationLib
+ DxeSaPolicyLib
+ UefiLib
+ ConfigBlockLib
+ GraphicsInfoLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ DxeSiliconPolicyUpdateLate.c
+ DxeSaPolicyInit.c
+
+[Pcd]
+ gBoardModuleTokenSpaceGuid.PcdIntelGopEnable
+ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid
+ gPlatformModuleTokenSpaceGuid.PcdSmbiosOemTypeFirmwareVersionInfo ## CONSUMES
+
+[Protocols]
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+ gSaPolicyProtocolGuid ## CONSUMES
+ gDxeSiPolicyProtocolGuid ## PRODUCES
+ gGopPolicyProtocolGuid ## PRODUCES
+
+[Depex]
+ gEfiVariableArchProtocolGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c
new file mode 100644
index 0000000000..1ee4bdd038
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c
@@ -0,0 +1,114 @@
+/** @file
+ CPU PEI Policy Update & initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+#include "PeiCpuPolicyUpdate.h"
+#include <Library/ConfigBlockLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/HobLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Library/Tpm12CommandLib.h>
+#include <Library/Tpm2CommandLib.h>
+#include <PolicyUpdateMacro.h>
+
+/*
+ Get the uCode region from PCD settings, and copy the patches to memory.
+ This function is used to replace CpuLocateMicrocodePatch due to that function can not works
+ with uCode update new design.
+ In current uCode update solution, there are some padding data between uCode patches,
+ the algorithm in CpuLocateMicrocodePatch can not handle this.
+ Besides that, in CpuLocateMicrocodePatch function, the scan algorithm just find the first
+ correct uCode patch which is not the highest version uCode.
+ This function just copy the uCode region to memory, and in later, the CpuMpInit driver
+ will load the correct patch for CPU.
+
+ @param[out] RegionAddress Pointer to the uCode array.
+ @param[out] RegionSize Size of the microcode FV.
+
+ @retval EFI_SUCCESS Find uCode patch region and success copy the data to memory.
+ @retval EFI_NOT_FOUND Something wrong with uCode region.
+ @retval EFI_OUT_OF_RESOUCES Memory allocation fail.
+ @retval EFI_INVALID_PARAMETER RegionAddres or RegionSize is NULL.
+
+*/
+EFI_STATUS
+SearchMicrocodeRegion (
+ OUT UINTN *RegionAddress,
+ OUT UINTN *RegionSize
+ )
+{
+ UINTN MicrocodeStart;
+ UINTN MicrocodeEnd;
+ UINT8 *MemoryBuffer;
+
+ if (RegionAddress == NULL || RegionSize == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *RegionAddress = 0;
+ *RegionSize = 0;
+
+ if ((FixedPcdGet32 (PcdFlashFvMicrocodeBase) == 0) || (FixedPcdGet32 (PcdFlashFvMicrocodeSize) == 0)) {
+ return EFI_NOT_FOUND;
+ }
+
+ MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeBase) + (UINTN) FixedPcdGet32 (PcdMicrocodeOffsetInFv);
+ MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeBase) + (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeSize);
+ *RegionSize = MicrocodeEnd - MicrocodeStart;
+
+ DEBUG ((DEBUG_INFO, "[SearchMicrocodeRegion]: Microcode Region Address = %x, Size = %d\n", MicrocodeStart, *RegionSize));
+
+ MemoryBuffer = AllocatePages (EFI_SIZE_TO_PAGES (*RegionSize));
+ ASSERT (MemoryBuffer != NULL);
+ if (MemoryBuffer == NULL) {
+ DEBUG ((DEBUG_ERROR, "Failed to allocate enough memory for Microcode Patch.\n"));
+ return EFI_OUT_OF_RESOURCES;
+ } else {
+ CopyMem (MemoryBuffer, (UINT8 *)MicrocodeStart, *RegionSize);
+ *RegionAddress = (UINTN)MemoryBuffer;
+ DEBUG ((DEBUG_INFO, "Copy whole uCode region to memory, address = %x, size = %d\n", RegionAddress, *RegionSize));
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function performs CPU PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicy (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ SI_POLICY_PPI *SiPolicyPpi;
+ CPU_CONFIG *CpuConfig;
+
+ DEBUG ((DEBUG_INFO, "Update PeiCpuPolicyUpdate Pos-Mem Start\n"));
+
+ SiPolicyPpi = NULL;
+ CpuConfig = NULL;
+
+ Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID *) &CpuConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = SearchMicrocodeRegion (
+ (UINTN *)&CpuConfig->MicrocodePatchAddress,
+ (UINTN *)&CpuConfig->MicrocodePatchRegionSize
+ );
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h
new file mode 100644
index 0000000000..b003481db0
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h
@@ -0,0 +1,31 @@
+/** @file
+ Header file for PEI CpuPolicyUpdate.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_CPU_POLICY_UPDATE_H_
+#define _PEI_CPU_POLICY_UPDATE_H_
+
+#include <PiPei.h>
+#include <Ppi/SiPolicy.h>
+#include <Ppi/Wdt.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <PlatformBoardId.h>
+#include <Library/BaseCryptLib.h>
+#include <Register/Cpuid.h>
+#include <Register/Msr.h>
+#include <Ppi/MasterBootMode.h>
+#include <Library/PeiServicesLib.h>
+#include "PeiPchPolicyUpdate.h"
+#include <Library/CpuPlatformLib.h>
+
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..b23e2ceceb
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c
@@ -0,0 +1,93 @@
+/** @file
+ This file is SampleCode of the library for Intel CPU PEI Policy initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "PeiCpuPolicyUpdate.h"
+#include <Library/ConfigBlockLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/FirmwareBootMediaLib.h>
+#include <Library/HobLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/PmcLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Library/SpiLib.h>
+#include <Ppi/Spi.h>
+#include <Register/CommonMsr.h>
+#include <Register/PchRegs.h>
+#include <PlatformBoardConfig.h>
+#include <PolicyUpdateMacro.h>
+
+#define GET_OCCUPIED_SIZE(ActualSize, Alignment) \
+ ((ActualSize) + (((Alignment) - ((ActualSize) & ((Alignment) - 1))) & ((Alignment) - 1)))
+
+
+/**
+ This function performs CPU PEI Policy initialization in Pre-memory.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ CPU_SECURITY_PREMEM_CONFIG *CpuSecurityPreMemConfig;
+ CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ UINT32 MaxLogicProcessors;
+ UINT16 BiosSize;
+ UINT16 BiosMemSizeInMb;
+ FW_BOOT_MEDIA_TYPE FwBootMediaType;
+ MSR_CORE_THREAD_COUNT_REGISTER MsrCoreThreadCount;
+ UINT8 AllCoreCount;
+ UINT8 AllSmallCoreCount;
+ UINT32 DisablePerCoreMask;
+
+ DEBUG ((DEBUG_INFO, "Update PeiCpuPolicyUpdate Pre-Mem Start\n"));
+
+ SiPreMemPolicyPpi = NULL;
+ CpuSecurityPreMemConfig = NULL;
+ CpuConfigLibPreMemConfig = NULL;
+ BiosSize = 0;
+ BiosMemSizeInMb = 0;
+ FwBootMediaType = FwBootMediaMax;
+ AllCoreCount = 0;
+ AllSmallCoreCount = 0;
+ DisablePerCoreMask = 0;
+
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuSecurityPreMemConfigGuid, (VOID *) &CpuSecurityPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPreMemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SkipStopPbet, CpuSecurityPreMemConfig->SkipStopPbet, FALSE);
+
+ SpiServiceInit ();
+ DEBUG ((DEBUG_INFO, "BIOS Guard PCD and Policy are disabled\n"));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.BiosGuard, CpuSecurityPreMemConfig->BiosGuard, CPU_FEATURE_DISABLE);
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.CpuRatio, CpuConfigLibPreMemConfig->CpuRatio, 0);
+
+ ///
+ /// Set PcdCpuMaxLogicalProcessorNumber to max number of logical processors enabled
+ /// Read MSR_CORE_THREAD_COUNT (0x35) to check the total active Threads
+ ///
+ MsrCoreThreadCount.Uint64 = AsmReadMsr64 (MSR_CORE_THREAD_COUNT);
+ MaxLogicProcessors = MsrCoreThreadCount.Bits.Threadcount;
+ DEBUG ((DEBUG_INFO, "MaxLogicProcessors = %d\n", MaxLogicProcessors));
+
+ PcdSetEx32S (&gUefiCpuPkgTokenSpaceGuid, PcdCpuMaxLogicalProcessorNumber, MaxLogicProcessors);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
new file mode 100644
index 0000000000..1c0cf6bee0
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
@@ -0,0 +1,210 @@
+/** @file
+ This file is SampleCode of the library for Intel PCH PEI Policy initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Guid/FmpCapsule.h>
+#include <Guid/GlobalVariable.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioConfig.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <ConfigBlock.h>
+#include <Ppi/Spi.h>
+#include <PlatformBoardConfig.h>
+#include <PolicyUpdateMacro.h>
+#include <SerialIoDevices.h>
+#include <Pins/GpioPinsVer2Lp.h>
+
+/**
+ This is helper function for getting I2C Pads Internal Termination settings from Pcd
+
+ @param[in] Index I2C Controller Index
+**/
+UINT8
+STATIC
+GetSerialIoI2cPadsTerminationFromPcd (
+ IN UINT8 Index
+ )
+{
+ switch (Index) {
+ case 0:
+ return PcdGet8 (PcdPchSerialIoI2c0PadInternalTerm);
+ case 1:
+ return PcdGet8 (PcdPchSerialIoI2c1PadInternalTerm);
+ case 2:
+ return PcdGet8 (PcdPchSerialIoI2c2PadInternalTerm);
+ case 3:
+ return PcdGet8 (PcdPchSerialIoI2c3PadInternalTerm);
+ case 4:
+ return PcdGet8 (PcdPchSerialIoI2c4PadInternalTerm);
+ case 5:
+ return PcdGet8 (PcdPchSerialIoI2c5PadInternalTerm);
+ case 6:
+ return PcdGet8 (PcdPchSerialIoI2c6PadInternalTerm);
+ case 7:
+ return PcdGet8 (PcdPchSerialIoI2c7PadInternalTerm);
+ default:
+ ASSERT (FALSE); // Invalid I2C Controller Index
+ }
+ return 0;
+}
+
+/**
+ This function performs PCH Serial IO Platform Policy initialization
+
+ @param[in] SiPolicy Pointer to SI_POLICY_PPI
+ @param[in] FspsUpd A VOID pointer
+**/
+VOID
+UpdateSerialIoConfig (
+ IN SI_POLICY_PPI *SiPolicy,
+ IN VOID *FspsUpd
+ )
+{
+ UINT8 Index;
+ SERIAL_IO_CONFIG *SerialIoConfig;
+ EFI_STATUS Status;
+
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOID *) &SerialIoConfig);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ //
+ // I2C
+ //
+ for (Index = 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PchSerialIoI2cPadsTermination[Index], SerialIoConfig->I2cDeviceConfig[Index].PadTermination, GetSerialIoI2cPadsTerminationFromPcd (Index));
+ }
+
+ if (IsPchP ()) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[0], SerialIoConfig->I2cDeviceConfig[0].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[1], SerialIoConfig->I2cDeviceConfig[1].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[2], SerialIoConfig->I2cDeviceConfig[2].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[3], SerialIoConfig->I2cDeviceConfig[3].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[4], SerialIoConfig->I2cDeviceConfig[4].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[5], SerialIoConfig->I2cDeviceConfig[5].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[6], SerialIoConfig->I2cDeviceConfig[6].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[7], SerialIoConfig->I2cDeviceConfig[7].Mode, 0);
+ }
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[0], SerialIoConfig->UartDeviceConfig[0].Mode, 2);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[1], SerialIoConfig->UartDeviceConfig[1].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[2], SerialIoConfig->UartDeviceConfig[2].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[3], SerialIoConfig->UartDeviceConfig[3].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[4], SerialIoConfig->UartDeviceConfig[4].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[5], SerialIoConfig->UartDeviceConfig[5].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[6], SerialIoConfig->UartDeviceConfig[6].Mode, 0);
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[0], SerialIoConfig->UartDeviceConfig[0].Attributes.AutoFlow, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[1], SerialIoConfig->UartDeviceConfig[1].Attributes.AutoFlow, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[2], SerialIoConfig->UartDeviceConfig[2].Attributes.AutoFlow, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[3], SerialIoConfig->UartDeviceConfig[3].Attributes.AutoFlow, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[4], SerialIoConfig->UartDeviceConfig[4].Attributes.AutoFlow, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[5], SerialIoConfig->UartDeviceConfig[5].Attributes.AutoFlow, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[6], SerialIoConfig->UartDeviceConfig[6].Attributes.AutoFlow, 0);
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[0], SerialIoConfig->UartDeviceConfig[0].PowerGating, 2);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[1], SerialIoConfig->UartDeviceConfig[1].PowerGating, 2);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[2], SerialIoConfig->UartDeviceConfig[2].PowerGating, 2);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[3], SerialIoConfig->UartDeviceConfig[3].PowerGating, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[4], SerialIoConfig->UartDeviceConfig[4].PowerGating, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[5], SerialIoConfig->UartDeviceConfig[5].PowerGating, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[6], SerialIoConfig->UartDeviceConfig[6].PowerGating, 0);
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[0], SerialIoConfig->UartDeviceConfig[0].DmaEnable, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[1], SerialIoConfig->UartDeviceConfig[1].DmaEnable, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[2], SerialIoConfig->UartDeviceConfig[2].DmaEnable, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[3], SerialIoConfig->UartDeviceConfig[3].DmaEnable, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[4], SerialIoConfig->UartDeviceConfig[4].DmaEnable, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[5], SerialIoConfig->UartDeviceConfig[5].DmaEnable, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[6], SerialIoConfig->UartDeviceConfig[6].DmaEnable, 0);
+
+}
+
+
+/**
+ Update PCIe Root Port Configuration
+
+ @param[in] SiPolicy Pointer to SI_POLICY_PPI
+ @param[in] FspsUpd Pointer to FspsUpd structure
+ // @param[in] PchSetup Pointer to PCH_SETUP buffer
+ // @param[in] SetupVariables Pointer to SETUP_DATA buffer
+**/
+VOID
+UpdatePcieRpConfig (
+ IN SI_POLICY_PPI *SiPolicy,
+ IN VOID *FspsUpd
+ )
+{
+ UINT8 Index;
+ EFI_STATUS Status;
+ PCH_PCIE_CONFIG *PchPcieConfig;
+ UINTN MaxPciePorts;
+
+ MaxPciePorts = GetPchMaxPciePortNum ();
+
+ PchPcieConfig = NULL;
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gPchPcieConfigGuid, (VOID *) &PchPcieConfig);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ //
+ // PCI express config
+ //
+ for (Index = 0; Index < MaxPciePorts; Index++) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpMaxPayload[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.MaxPayload, PchPcieMaxPayload256);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpPhysicalSlotNumber[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PhysicalSlotNumber, (UINT8) Index);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpClkReqDetect[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.ClkReqDetect, TRUE);
+ }
+}
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicy (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ VOID *FspsUpd;
+ SI_POLICY_PPI *SiPolicy;
+ VOID *FspmUpd;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ CPU_SECURITY_PREMEM_CONFIG *CpuSecurityPreMemConfig;
+
+ DEBUG ((DEBUG_INFO, "Update PeiPchPolicyUpdate Pos-Mem Start\n"));
+
+ FspsUpd = NULL;
+ FspmUpd = NULL;
+ SiPolicy = NULL;
+ CpuSecurityPreMemConfig = NULL;
+ SiPreMemPolicyPpi = NULL;
+
+ Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicy);
+ ASSERT_EFI_ERROR (Status);
+
+ UpdatePcieRpConfig (SiPolicy, FspsUpd);
+ UpdateSerialIoConfig (SiPolicy, FspsUpd);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h
new file mode 100644
index 0000000000..133660c59e
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h
@@ -0,0 +1,24 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_PCH_POLICY_UPDATE_H_
+#define _PEI_PCH_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <PiPei.h>
+#include <PlatformBoardId.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/ConfigBlockLib.h>
+#include <PlatformBoardConfig.h>
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..47ecd41b39
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
@@ -0,0 +1,124 @@
+/** @file
+ This file is SampleCode of the library for Intel PCH PEI Policy initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Guid/GlobalVariable.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <PolicyUpdateMacro.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <PchDmiConfig.h>
+
+VOID
+UpdatePcieClockInfo (
+ PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig,
+ IN VOID *FspmUpd,
+ UINTN Index,
+ UINT64 Data
+ )
+{
+ PCD64_BLOB Pcd64;
+
+ Pcd64.Blob = Data;
+ DEBUG ((DEBUG_INFO, "UpdatePcieClockInfo ClkIndex %x ClkUsage %x, Supported %x\n", Index, Pcd64.PcieClock.ClockUsage, Pcd64.PcieClock.ClkReqSupported));
+
+ UPDATE_POLICY (((FSPM_UPD *)FspmUpd)->FspmConfig.PcieClkSrcUsage[Index], PcieRpPreMemConfig->PcieClock[Index].Usage, (UINT8)Pcd64.PcieClock.ClockUsage);
+ UPDATE_POLICY (((FSPM_UPD *)FspmUpd)->FspmConfig.PcieClkSrcClkReq[Index], PcieRpPreMemConfig->PcieClock[Index].ClkReq, Pcd64.PcieClock.ClkReqSupported ? (UINT8)Index : 0xFF);
+}
+
+/**
+ Update PcieRp pre mem policies.
+
+ @param[in] SiPreMemPolicy Pointer to SI_PREMEM_POLICY_PPI
+ @param[in] FspsUpm Pointer to FSPM_UPD
+ @param[in] PchSetup Pointer to PCH_SETUP
+**/
+STATIC
+VOID
+UpdatePcieRpPreMemPolicy (
+ IN SI_PREMEM_POLICY_PPI *SiPreMemPolicy,
+ IN VOID *FspmUpd
+ )
+{
+ UINT32 RpIndex;
+ UINT32 RpEnabledMask;
+ PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig;
+ EFI_STATUS Status;
+
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfigGuid, (VOID *) &PcieRpPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ GET_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PcieRpEnableMask, PcieRpPreMemConfig->RpEnabledMask, RpEnabledMask);
+
+ for (RpIndex = 0; RpIndex < GetPchMaxPciePortNum (); RpIndex ++) {
+ RpEnabledMask |= (UINT32) (1 << RpIndex);
+ }
+ // RpEnabledMask value is related with Setup value, Need to check Policy Default
+ COMPARE_AND_UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PcieRpEnableMask, PcieRpPreMemConfig->RpEnabledMask, RpEnabledMask);
+
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 0, PcdGet64(PcdPcieClock0));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 1, PcdGet64(PcdPcieClock1));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 2, PcdGet64(PcdPcieClock2));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 3, PcdGet64(PcdPcieClock3));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 4, PcdGet64(PcdPcieClock4));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 5, PcdGet64(PcdPcieClock5));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 6, PcdGet64(PcdPcieClock6));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 7, PcdGet64(PcdPcieClock7));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 8, PcdGet64(PcdPcieClock8));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 9, PcdGet64(PcdPcieClock9));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 10, PcdGet64(PcdPcieClock10));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 11, PcdGet64(PcdPcieClock11));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 12, PcdGet64(PcdPcieClock12));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 13, PcdGet64(PcdPcieClock13));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 14, PcdGet64(PcdPcieClock14));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 15, PcdGet64(PcdPcieClock15));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 16, PcdGet64(PcdPcieClock16));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 17, PcdGet64(PcdPcieClock17));
+
+}
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ VOID *FspmUpd;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicy;
+
+ DEBUG ((DEBUG_INFO, "Update PeiPchPolicyUpdate Pre-Mem Start\n"));
+
+ FspmUpd = NULL;
+ SiPreMemPolicy = NULL;
+
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicy);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ UpdatePcieRpPreMemPolicy (SiPreMemPolicy, FspmUpd);
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
new file mode 100644
index 0000000000..844e4c9967
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
@@ -0,0 +1,208 @@
+### @file
+# Module Information file for PEI PolicyUpdateLib Library
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiPolicyUpdateLib
+ FILE_GUID = D42F5BB8-E0CE-47BD-8C52-476C79055FC6
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = PeiPolicyUpdateLib|PEIM PEI_CORE SEC
+
+[LibraryClasses]
+ HobLib
+ BaseCryptLib
+ CpuPlatformLib
+ IoLib
+ ConfigBlockLib
+ MemoryAllocationLib
+ PeiServicesTablePointerLib
+ PcdLib
+ Tpm2CommandLib
+ Tpm12CommandLib
+ Tpm2DeviceLib
+ Tpm12DeviceLib
+ BoardConfigLib
+ PciSegmentLib
+ SiPolicyLib
+ PeiServicesLib
+ FirmwareBootMediaLib
+ SpiLib
+ BmpSupportLib
+ PeiGetFvInfoLib
+ TimerLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ CryptoPkg/CryptoPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+
+[FixedPcd]
+ gBoardModuleTokenSpaceGuid.PcdDefaultBoardId ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdMchBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdGttMmAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress ## CONSUMES
+
+ gBoardModuleTokenSpaceGuid.PcdBoardId ## CONSUMES
+
+ # SA Misc Config
+ gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2Dram ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2DramSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcLp5CccConfig ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcCmdMirror ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMask ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMaskEcc ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaMiscDisableMrcRetrainingOnRtcPowerLoss ## CONSUMES
+
+ # Display DDI
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## CONSUMES
+
+ # PCIE RTD3 GPIO
+ gBoardModuleTokenSpaceGuid.PcdRootPortIndex ## CONSUMES
+
+ # SPD Address Table
+ gBoardModuleTokenSpaceGuid.PcdSpdPresent ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable4 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable5 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable6 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable7 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable8 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable9 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable10 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable11 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable12 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable13 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable14 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable15 ## CONSUMES
+
+
+ # PCIe Clock Info
+ gBoardModuleTokenSpaceGuid.PcdPcieClock0 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock1 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock2 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock3 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock4 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock5 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock6 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock7 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock8 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock9 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock10 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock11 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock12 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock13 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock14 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock15 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock16 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock17 ## CONSUMES
+
+
+ # Pch SerialIo I2c Pads Termination
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c6PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c7PadInternalTerm ## CONSUMES
+
+ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem ## CONSUMES
+
+[Sources]
+ PeiPchPolicyUpdatePreMem.c
+ PeiPchPolicyUpdate.c
+ PeiCpuPolicyUpdatePreMem.c
+ PeiCpuPolicyUpdate.c
+ PeiSaPolicyUpdate.c
+ PeiSaPolicyUpdatePreMem.c
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+ gWdtPpiGuid ## CONSUMES
+ gPchSpiPpiGuid ## CONSUMES
+ gSiPolicyPpiGuid ## CONSUMES
+ gSiPreMemPolicyPpiGuid ## CONSUMES
+ gFspmArchConfigPpiGuid ## PRODUCES
+ gReadyForGopConfigPpiGuid ## PRODUCES
+ gPeiGraphicsPlatformPpiGuid ## CONSUMES
+ gPeiGraphicsFramebufferReadyPpiGuid ## CONSUMES
+
+[Guids]
+ gEfiGlobalVariableGuid ## CONSUMES
+ gMemoryConfigVariableGuid ## CONSUMES
+ gEfiCapsuleVendorGuid ## CONSUMES
+ gEfiMemoryTypeInformationGuid ## CONSUMES
+ gEfiMemoryOverwriteControlDataGuid ## CONSUMES
+ gSiPreMemConfigGuid ## CONSUMES
+ gSiConfigGuid ## CONSUMES
+ gCpuSecurityPreMemConfigGuid ## CONSUMES
+ gCpuConfigLibPreMemConfigGuid ## CONSUMES
+ gCpuConfigGuid ## CONSUMES
+ gVmdPeiConfigGuid ## CONSUMES
+ gCpuPcieRpPrememConfigGuid ## CONSUMES
+ gVmdInfoHobGuid ## CONSUMES
+ gPciePreMemConfigGuid ## CONSUMES
+ gPlatformInitFvLocationGuid ## CONSUMES
+ gHostBridgePeiPreMemConfigGuid ## CONSUMES
+ gEfiGraphicsInfoHobGuid ## CONSUMES
+ gPchDmiPreMemConfigGuid ## CONSUMES
+ gGraphicsPeiConfigGuid ## CONSUMES
+ gMemoryConfigGuid ## CONSUMES
+ gMemoryConfigNoCrcGuid ## CONSUMES
+ gPchPcieConfigGuid ## CONSUMES
+ gSerialIoConfigGuid ## CONSUMES
+ gPcieRpPreMemConfigGuid ## CONSUMES
+ gSaMiscPeiPreMemConfigGuid ## CONSUMES
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c
new file mode 100644
index 0000000000..c62b0a14ef
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c
@@ -0,0 +1,214 @@
+/** @file
+Do Platform Stage System Agent initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/BmpSupportLib.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiGetFvInfoLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Protocol/GraphicsOutput.h>
+
+#include <CpuPcieConfig.h>
+#include <CpuPcieHob.h>
+#include <IndustryStandard/Bmp.h>
+#include <PolicyUpdateMacro.h>
+#include <Guid/GraphicsInfoHob.h>
+
+#include <VmdPeiConfig.h>
+#include <Ppi/GraphicsPlatformPolicyPpi.h>
+
+
+EFI_STATUS
+EFIAPI
+PeiGraphicsPolicyUpdateCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_GRAPHICS_INFO_HOB *PlatformGraphicsOutput;
+ EFI_PEI_HOB_POINTERS Hob;
+ UINT8 *HobStart;
+ GRAPHICS_PEI_CONFIG *GtConfig;
+ SI_POLICY_PPI *SiPolicyPpi;
+
+ PlatformGraphicsOutput = NULL;
+ HobStart = NULL;
+
+ GtConfig = NULL;
+ SiPolicyPpi = NULL;
+ Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *) &GtConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
+ HobStart = Hob.Raw;
+
+ if (!EFI_ERROR (Status)) {
+ if (HobStart != NULL) {
+ if ((Hob.Raw = GetNextGuidHob (&gEfiGraphicsInfoHobGuid, HobStart)) != NULL) {
+ DEBUG ((DEBUG_INFO, "Found EFI_PEI_GRAPHICS_INFO_HOB\n"));
+ PlatformGraphicsOutput = GET_GUID_HOB_DATA (Hob.Guid);
+ }
+ }
+ }
+
+ if (PlatformGraphicsOutput != NULL) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.HorizontalResolution, GtConfig->HorizontalResolution, PlatformGraphicsOutput->GraphicsMode.HorizontalResolution);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.VerticalResolution, GtConfig->VerticalResolution, PlatformGraphicsOutput->GraphicsMode.VerticalResolution);
+ } else {
+ DEBUG ((DEBUG_INFO, "Not able to find EFI_PEI_GRAPHICS_INFO_HOB\n"));
+ }
+
+ return Status;
+}
+
+STATIC
+EFI_PEI_NOTIFY_DESCRIPTOR mPeiGfxPolicyUpdateNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gPeiGraphicsFramebufferReadyPpiGuid,
+ PeiGraphicsPolicyUpdateCallback
+};
+
+/**
+ UpdatePeiSaPolicy performs SA PEI Policy initialization
+
+ @retval EFI_SUCCESS The policy is installed and initialized.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicy (
+ VOID
+ )
+{
+ EFI_GUID BmpImageGuid;
+ EFI_STATUS Status;
+ EFI_GUID FileGuid;
+ VOID *Buffer;
+ UINT32 Size;
+ VOID *VmdVariablePtr;
+ GRAPHICS_PEI_CONFIG *GtConfig;
+ SI_POLICY_PPI *SiPolicyPpi;
+ CPU_PCIE_CONFIG *CpuPcieRpConfig;
+ VMD_PEI_CONFIG *VmdPeiConfig;
+ EFI_PEI_PPI_DESCRIPTOR *ReadyForGopConfigPpiDesc;
+ VOID *VbtPtr;
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Blt;
+ UINTN BltSize;
+ UINTN Height;
+ UINTN Width;
+
+ DEBUG ((DEBUG_INFO, "Update PeiSaPolicyUpdate Pos-Mem Start\n"));
+
+ Size = 0;
+ Blt = NULL;
+ BltSize = 0;
+
+ GtConfig = NULL;
+ SiPolicyPpi = NULL;
+ CpuPcieRpConfig = NULL;
+ VmdVariablePtr = NULL;
+ Buffer = NULL;
+
+ Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *) &GtConfig);
+ ASSERT_EFI_ERROR(Status);
+
+
+
+ VmdPeiConfig = NULL;
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gVmdPeiConfigGuid, (VOID *) &VmdPeiConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ CopyMem(&BmpImageGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid), sizeof(BmpImageGuid));
+
+ if (!EFI_ERROR (Status)) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SkipFspGop, GtConfig->SkipFspGop, 0x0);
+ Buffer = NULL;
+
+ CopyMem(&FileGuid, &BmpImageGuid, sizeof(FileGuid));
+ PeiGetSectionFromFv(FileGuid, &Buffer, &Size);
+ if (Buffer == NULL) {
+ DEBUG((DEBUG_ERROR, "Could not locate VBT\n"));
+ }
+
+ GtConfig->GraphicsConfigPtr = Buffer;
+ DEBUG ((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", GtConfig->GraphicsConfigPtr));
+ DEBUG ((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size));
+ GET_POLICY ((VOID *) ((FSPS_UPD *) FspsUpd)->FspsConfig.GraphicsConfigPtr, GtConfig->GraphicsConfigPtr, VbtPtr);
+
+ //
+ // Install ReadyForGopConfig PPI to trigger PEI phase GopConfig callback.
+ //
+ ReadyForGopConfigPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+ if (ReadyForGopConfigPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+ ReadyForGopConfigPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ ReadyForGopConfigPpiDesc->Guid = &gReadyForGopConfigPpiGuid;
+ ReadyForGopConfigPpiDesc->Ppi = VbtPtr;
+ Status = PeiServicesInstallPpi (ReadyForGopConfigPpiDesc);
+
+ Status = TranslateBmpToGopBlt (
+ Buffer,
+ Size,
+ &Blt,
+ &BltSize,
+ &Height,
+ &Width
+ );
+
+ if (Status == EFI_BUFFER_TOO_SMALL) {
+ Blt = NULL;
+ Status = TranslateBmpToGopBlt (
+ Buffer,
+ Size,
+ &Blt,
+ &BltSize,
+ &Height,
+ &Width
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "TranslateBmpToGopBlt, Status = %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+ }
+
+ //
+ // Initialize Blt, BltSize
+ //
+ GtConfig->BltBufferAddress = Blt;
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.BltBufferSize, GtConfig->BltBufferSize, BltSize);
+
+ DEBUG ((DEBUG_INFO, "Calling mPeiGfxPolicyUpdateNotifyList\n"));
+ Status = PeiServicesNotifyPpi (&mPeiGfxPolicyUpdateNotifyList);
+
+ }
+
+ //
+ // VMD related settings from setup variable
+ //
+ COMPARE_AND_UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.VmdEnable, VmdPeiConfig->VmdEnable, 0);
+ VmdPeiConfig->VmdVariablePtr = VmdVariablePtr;
+ DEBUG ((DEBUG_INFO, "VmdVariablePtr from PeiGetSectionFromFv is 0x%x\n", VmdVariablePtr));
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h
new file mode 100644
index 0000000000..64f97b672b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h
@@ -0,0 +1,27 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_SA_POLICY_UPDATE_H_
+#define _PEI_SA_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <Ppi/SiPolicy.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <Ppi/Wdt.h>
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+#include "PeiPchPolicyUpdate.h"
+#include <Library/PcdLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/SiPolicyLib.h>
+
+#define WDT_TIMEOUT 60
+
+#endif
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..a4ceda76c3
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
@@ -0,0 +1,389 @@
+/** @file
+Do Platform Stage System Agent initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include "MemoryConfig.h"
+#include <Guid/MemoryOverwriteControl.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/GpioLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Register/CommonMsr.h>
+#include <Register/Cpuid.h>
+#include <Register/Msr.h>
+#include <CpuRegs.h>
+#include <HostBridgeConfig.h>
+#include <PlatformBoardConfig.h>
+#include <PolicyUpdateMacro.h>
+#include <SaDataHob.h>
+#include <Ppi/FspmArchConfigPpi.h>
+
+///
+/// Memory Reserved should be between 125% to 150% of the Current required memory
+/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resume issues.
+///
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
+ { EfiACPIReclaimMemory, FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemorySize) }, // ASL
+ { EfiACPIMemoryNVS, FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize) }, // ACPI NVS (including S3 related)
+ { EfiReservedMemoryType, FixedPcdGet32 (PcdPlatformEfiReservedMemorySize) }, // BIOS Reserved (including S3 related)
+ { EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize) }, // Runtime Service Data
+ { EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize) }, // Runtime Service Code
+ { EfiMaxMemoryType, 0 }
+};
+
+#define PEI_MIN_MEMORY_SIZE (10 * 0x800000) // 80MB
+
+/**
+ UpdatePeiSaPolicyPreMem performs SA PEI Policy initialization
+
+ @retval EFI_SUCCESS The policy is installed and initialized.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
+ UINTN VariableSize;
+ SA_MEMORY_RCOMP *RcompData;
+ WDT_PPI *gWdtPei;
+ UINT8 WdtTimeout;
+
+ UINT8 Index;
+ UINTN DataSize;
+ EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1];
+ EFI_BOOT_MODE BootMode;
+ UINT8 MorControl;
+ UINT64 PlatformMemorySize;
+ VOID *MemorySavedData;
+ VOID *NullSpdPtr;
+ UINT32 RpEnabledMask;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ MEMORY_CONFIGURATION *MemConfig;
+ SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
+ MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;
+ EFI_PEI_PPI_DESCRIPTOR *FspmArchConfigPpiDesc;
+ FSPM_ARCH_CONFIG_PPI *FspmArchConfigPpi;
+ HOST_BRIDGE_PREMEM_CONFIG *HostBridgePreMemConfig;
+ UINT16 AdjustedMmioSize;
+ UINT8 SaDisplayConfigTable[16];
+ EFI_BOOT_MODE SysBootMode;
+ UINT32 ProcessorTraceTotalMemSize;
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
+ UINT32 CapsuleSupportMemSize;
+
+ DEBUG ((DEBUG_INFO, "Update PeiSaPolicyUpdate Pre-Mem Start\n"));
+ ZeroMem ((VOID*) SaDisplayConfigTable, sizeof (SaDisplayConfigTable));
+ WdtTimeout = 0;
+ SysBootMode = 0;
+ RcompData = NULL;
+ PlatformMemorySize = 0;
+ RpEnabledMask = 0;
+ SiPreMemPolicyPpi = NULL;
+ MemConfig = NULL;
+ MemConfigNoCrc = NULL;
+
+
+ MiscPeiPreMemConfig = NULL;
+ HostBridgePreMemConfig = NULL;
+ FspmArchConfigPpi = NULL;
+
+ ProcessorTraceTotalMemSize = 0;
+ CapsuleSupportMemSize = 0;
+
+ AdjustedMmioSize = PcdGet16 (PcdSaMiscMmioSizeAdjustment);
+
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gHostBridgePeiPreMemConfigGuid, (VOID *) &HostBridgePreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigGuid, (VOID *) &MemConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);
+ ASSERT_EFI_ERROR(Status);
+
+ RcompData = MemConfigNoCrc->RcompData;
+
+ //
+ // Locate system configuration variable
+ //
+ Status = PeiServicesLocatePpi(
+ &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
+ 0, // INSTANCE
+ NULL, // EFI_PEI_PPI_DESCRIPTOR
+ (VOID **) &VariableServices // PPI
+ );
+ ASSERT_EFI_ERROR(Status);
+
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Initialize S3 Data variable (S3DataPtr)
+ //
+ VariableSize = 0;
+ MemorySavedData = NULL;
+ Status = VariableServices->GetVariable (
+ VariableServices,
+ L"MemoryConfig",
+ &gMemoryConfigVariableGuid,
+ NULL,
+ &VariableSize,
+ MemorySavedData
+ );
+ if (Status == EFI_BUFFER_TOO_SMALL) {
+ MemorySavedData = AllocateZeroPool (VariableSize);
+ ASSERT (MemorySavedData != NULL);
+
+ Status = VariableServices->GetVariable (
+ VariableServices,
+ L"MemoryConfig",
+ &gMemoryConfigVariableGuid,
+ NULL,
+ &VariableSize,
+ MemorySavedData
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Fail to retrieve Variable: MemoryConfig, Status = %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+ FspmArchConfigPpi = (FSPM_ARCH_CONFIG_PPI *) AllocateZeroPool (sizeof (FSPM_ARCH_CONFIG_PPI));
+ if (FspmArchConfigPpi == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+ FspmArchConfigPpi->Revision = 1;
+ FspmArchConfigPpi->NvsBufferPtr = MemorySavedData;
+ MiscPeiPreMemConfig->S3DataPtr = MemorySavedData;
+
+ FspmArchConfigPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+ if (FspmArchConfigPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+ FspmArchConfigPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ FspmArchConfigPpiDesc->Guid = &gFspmArchConfigPpiGuid;
+ FspmArchConfigPpiDesc->Ppi = FspmArchConfigPpi;
+
+ //
+ // Install FSP-M Arch Config PPI
+ //
+ Status = PeiServicesInstallPpi (FspmArchConfigPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+
+ VariableSize = sizeof (MorControl);
+ Status = VariableServices->GetVariable(
+ VariableServices,
+ MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME,
+ &gEfiMemoryOverwriteControlDataGuid,
+ NULL,
+ &VariableSize,
+ &MorControl
+ );
+ if (EFI_ERROR (Status)) {
+ MorControl = 0;
+ }
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.UserBd, MiscPeiPreMemConfig->UserBd, 0); // It's a CRB mobile board by default (btCRBMB)
+
+ MiscPeiPreMemConfig->TxtImplemented = 0;
+
+ if (PcdGet32 (PcdMrcRcompTarget)) {
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.RcompTarget, (VOID *)RcompData->RcompTarget, (VOID *)(UINTN)PcdGet32 (PcdMrcRcompTarget), sizeof (UINT16) * MRC_MAX_RCOMP_TARGETS);
+ }
+
+ if (PcdGetBool (PcdMrcDqPinsInterleavedControl)) {
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.DqPinsInterleaved, MemConfig->DqPinsInterleaved, PcdGetBool (PcdMrcDqPinsInterleaved));
+ }
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[0], MiscPeiPreMemConfig->SpdAddressTable[0], PcdGet8 (PcdMrcSpdAddressTable0));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[1], MiscPeiPreMemConfig->SpdAddressTable[1], PcdGet8 (PcdMrcSpdAddressTable1));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[2], MiscPeiPreMemConfig->SpdAddressTable[2], PcdGet8 (PcdMrcSpdAddressTable2));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[3], MiscPeiPreMemConfig->SpdAddressTable[3], PcdGet8 (PcdMrcSpdAddressTable3));
+ if (PcdGet8 (PcdMrcLp5CccConfig)) {
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.Lp5CccConfig, MemConfig->Lp5CccConfig, PcdGet8 (PcdMrcLp5CccConfig));
+ }
+
+
+ NullSpdPtr = AllocateZeroPool (SPD_DATA_SIZE);
+ ASSERT (NullSpdPtr != NULL);
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[4], MiscPeiPreMemConfig->SpdAddressTable[4], PcdGet8 (PcdMrcSpdAddressTable4));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[5], MiscPeiPreMemConfig->SpdAddressTable[5], PcdGet8 (PcdMrcSpdAddressTable5));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[6], MiscPeiPreMemConfig->SpdAddressTable[6], PcdGet8 (PcdMrcSpdAddressTable6));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[7], MiscPeiPreMemConfig->SpdAddressTable[7], PcdGet8 (PcdMrcSpdAddressTable7));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[8], MiscPeiPreMemConfig->SpdAddressTable[8], PcdGet8 (PcdMrcSpdAddressTable8));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[9], MiscPeiPreMemConfig->SpdAddressTable[9], PcdGet8 (PcdMrcSpdAddressTable9));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[10], MiscPeiPreMemConfig->SpdAddressTable[10], PcdGet8 (PcdMrcSpdAddressTable10));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[11], MiscPeiPreMemConfig->SpdAddressTable[11], PcdGet8 (PcdMrcSpdAddressTable11));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[12], MiscPeiPreMemConfig->SpdAddressTable[12], PcdGet8 (PcdMrcSpdAddressTable12));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[13], MiscPeiPreMemConfig->SpdAddressTable[13], PcdGet8 (PcdMrcSpdAddressTable13));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[14], MiscPeiPreMemConfig->SpdAddressTable[14], PcdGet8 (PcdMrcSpdAddressTable14));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[15], MiscPeiPreMemConfig->SpdAddressTable[15], PcdGet8 (PcdMrcSpdAddressTable15));
+ if (PcdGet32 (PcdMrcRcompResistor)) {
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.RcompResistor, RcompData->RcompResistor, (UINT8) PcdGet32 (PcdMrcRcompResistor));
+ }
+ if (PcdGet32 (PcdMrcDqsMapCpu2Dram)) {
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.DqsMapCpu2DramMc0Ch0, (VOID *)MemConfigNoCrc->DqDqsMap->DqsMapCpu2Dram, (VOID *)(UINTN)PcdGet32 (PcdMrcDqsMapCpu2Dram), sizeof (UINT8) * MEM_CFG_MAX_CONTROLLERS * MEM_CFG_MAX_CHANNELS * MEM_CFG_NUM_BYTES_MAPPED);
+ }
+ if (PcdGet32 (PcdMrcDqMapCpu2Dram)) {
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.DqMapCpu2DramMc0Ch0, (VOID *)MemConfigNoCrc->DqDqsMap->DqMapCpu2Dram, (VOID *)(UINTN)PcdGet32 (PcdMrcDqMapCpu2Dram), sizeof (UINT8) * MEM_CFG_MAX_CONTROLLERS * MEM_CFG_MAX_CHANNELS * MEM_CFG_NUM_BYTES_MAPPED * 8);
+ }
+ if (PcdGetBool (PcdSpdPresent)) {
+ // Clear SPD data so it can be filled in by the MRC init code
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr000, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][0][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr010, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][1][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr020, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][2][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr030, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][3][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr100, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][0][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr110, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][1][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr120, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][2][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr130, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][3][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ } else {
+ if (PcdGet32 (PcdMrcSpdData)) {
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr000, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr010, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr020, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][2][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr030, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][3][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr100, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr110, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr120, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][2][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr130, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][3][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ }
+ }
+
+ HostBridgePreMemConfig->MchBar = (UINTN) PcdGet64 (PcdMchBaseAddress);
+ HostBridgePreMemConfig->DmiBar = (UINTN) PcdGet64 (PcdDmiBaseAddress);
+ HostBridgePreMemConfig->EpBar = (UINTN) PcdGet64 (PcdEpBaseAddress);
+ HostBridgePreMemConfig->EdramBar = (UINTN) PcdGet64 (PcdEdramBaseAddress);
+ MiscPeiPreMemConfig->SmbusBar = (UINTN) PcdGet16 (PcdSmbusBaseAddress);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.TsegSize, MiscPeiPreMemConfig->TsegSize, PcdGet32 (PcdTsegSize));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.UserBd, MiscPeiPreMemConfig->UserBd, PcdGet8 (PcdSaMiscUserBd));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.DisableMrcRetrainingOnRtcPowerLoss,MiscPeiPreMemConfig->DisableMrcRetrainingOnRtcPowerLoss, PcdGet8(PcdSaMiscDisableMrcRetrainingOnRtcPowerLoss));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.MmioSizeAdjustment, HostBridgePreMemConfig->MmioSizeAdjustment, PcdGet16 (PcdSaMiscMmioSizeAdjustment));
+ //
+ // Display DDI Initialization ( default Native GPIO as per board during AUTO case)
+ //
+ CopyMem (SaDisplayConfigTable, (VOID *) (UINTN) PcdGet32 (PcdSaDisplayConfigTable), (UINTN)PcdGet16 (PcdSaDisplayConfigTableSize));
+
+ gWdtPei = NULL;
+ Status = PeiServicesLocatePpi(
+ &gWdtPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &gWdtPei
+ );
+ if (gWdtPei != NULL) {
+ WdtTimeout = gWdtPei->CheckStatus();
+ } else {
+ WdtTimeout = FALSE;
+ }
+
+ if ((WdtTimeout == FALSE)) {
+ //
+ // If USER custom profile is selected, we will start the WDT.
+ //
+ if (gWdtPei != NULL) {
+ Status = gWdtPei->ReloadAndStart(WDT_TIMEOUT);
+ }
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.VddVoltage, MemConfig->VddVoltage, 0); // Use platform default as the safe value.
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.VddqVoltage, MemConfig->VddqVoltage, 0); // Use platform default as the safe value.
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.VppVoltage, MemConfig->VppVoltage, 0); // Use platform default as the safe value.
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.Ratio, MemConfig->Ratio, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tCL, MemConfig->tCL, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tCWL, MemConfig->tCWL, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tFAW, MemConfig->tFAW, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRAS, MemConfig->tRAS, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRCDtRP, MemConfig->tRCDtRP, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tREFI, MemConfig->tREFI, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRFC, MemConfig->tRFC, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRRD, MemConfig->tRRD, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRTP, MemConfig->tRTP, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tWR, MemConfig->tWR, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tWTR, MemConfig->tWTR, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.NModeSupport, MemConfig->NModeSupport, 0);
+ }
+
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.CmdMirror, MemConfig->CmdMirror, PcdGet8 (PcdMrcCmdMirror)); // BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
+
+ // FirstDimmBitMask defines which DIMM should be populated first on a 2DPC board
+
+ COMPARE_AND_UPDATE_POLICY(((FSPM_UPD *)FspmUpd)->FspmConfig.FirstDimmBitMask, MemConfig->FirstDimmBitMask, PcdGet8(PcdSaMiscFirstDimmBitMask));
+ COMPARE_AND_UPDATE_POLICY(((FSPM_UPD *)FspmUpd)->FspmConfig.FirstDimmBitMaskEcc, MemConfig->FirstDimmBitMaskEcc, PcdGet8(PcdSaMiscFirstDimmBitMaskEcc));
+
+ //
+ // Update CleanMemory variable from Memory overwrite request value. Ignore if we are performing capsule update.
+ //
+ if ((BootMode != BOOT_ON_FLASH_UPDATE) && (BootMode != BOOT_ON_S3_RESUME)) {
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.CleanMemory, MemConfigNoCrc->CleanMemory, (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK));
+ }
+
+ DataSize = sizeof (MemoryData);
+ Status = VariableServices->GetVariable (
+ VariableServices,
+ EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
+ &gEfiMemoryTypeInformationGuid,
+ NULL,
+ &DataSize,
+ &MemoryData
+ );
+ ///
+ /// Accumulate maximum amount of memory needed
+ ///
+ PlatformMemorySize = MemConfigNoCrc->PlatformMemorySize;
+ AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, &Ebx.Uint32, NULL, NULL);
+
+ if (EFI_ERROR (Status)) {
+ ///
+ /// Use default value to avoid memory fragment.
+ /// OS boot/installation fails if there is not enough continuous memory available
+ ///
+ PlatformMemorySize = PEI_MIN_MEMORY_SIZE + ProcessorTraceTotalMemSize + CapsuleSupportMemSize;
+ DataSize = sizeof (mDefaultMemoryTypeInformation);
+ CopyMem (MemoryData, mDefaultMemoryTypeInformation, DataSize);
+ } else {
+ ///
+ /// Start with at least PEI_MIN_MEMORY_SIZE of memory for the DXE Core and the DXE Stack
+ ///
+ PlatformMemorySize = PEI_MIN_MEMORY_SIZE + ProcessorTraceTotalMemSize + CapsuleSupportMemSize;
+ }
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PlatformMemorySize, MemConfigNoCrc->PlatformMemorySize, PlatformMemorySize);
+
+ if (BootMode != BOOT_IN_RECOVERY_MODE) {
+ for (Index = 0; Index < DataSize / sizeof (EFI_MEMORY_TYPE_INFORMATION); Index++) {
+ PlatformMemorySize += MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE;
+ }
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PlatformMemorySize, MemConfigNoCrc->PlatformMemorySize, PlatformMemorySize);
+
+ ///
+ /// Build the GUID'd HOB for DXE
+ ///
+ BuildGuidDataHob (
+ &gEfiMemoryTypeInformationGuid,
+ MemoryData,
+ DataSize
+ );
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
new file mode 100644
index 0000000000..c2bdd599a8
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
@@ -0,0 +1,65 @@
+## @file
+# Provide Silicon policy update functionality.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SiliconPolicyUpdateLib
+ FILE_GUID = 34435831-33D7-4742-992F-3A3C7B860BC5
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconPolicyUpdateLib
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+################################################################################
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
+################################################################################
+
+[Sources]
+ PeiSiliconPolicyUpdatePreMem.c
+ PeiSiliconPolicyUpdatePostMem.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[LibraryClasses.IA32]
+ BaseMemoryLib
+ BaseLib
+ DebugLib
+ PeiServicesTablePointerLib
+ PeiServicesLib
+ PcdLib
+ PeiPolicyUpdateLib
+
+[FixedPcd]
+
+[Ppis]
+
+[Guids]
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c
new file mode 100644
index 0000000000..181b491c4c
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c
@@ -0,0 +1,39 @@
+/** @file
+ This file is SampleCode for Intel PEI Platform Policy initialization in post-memory.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+
+VOID
+EFIAPI
+SiliconPolicyUpdatePostMemFirmwareConfig (
+ VOID
+ )
+{
+ //
+ // Update and override all platform related and customized settings below.
+ //
+ UpdatePeiPchPolicy ();
+ UpdatePeiSaPolicy ();
+ UpdatePeiCpuPolicy ();
+}
+
+VOID *
+EFIAPI
+SiliconPolicyUpdatePostMem (
+ IN OUT VOID *Policy
+ )
+{
+ Policy = NULL;
+
+ SiliconPolicyUpdatePostMemFirmwareConfig ();
+
+ return Policy;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..42e6ac34c2
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c
@@ -0,0 +1,37 @@
+/** @file
+ This file is SampleCode for Intel PEI Platform Policy initialization in pre-memory.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+
+VOID
+EFIAPI
+SiliconPolicyUpdatePreMemFirmwareConfig (
+ VOID
+ )
+{
+ UpdatePeiPchPolicyPreMem ();
+ UpdatePeiSaPolicyPreMem ();
+ UpdatePeiCpuPolicyPreMem ();
+}
+
+
+VOID *
+EFIAPI
+SiliconPolicyUpdatePreMem (
+ IN OUT VOID *Policy
+ )
+{
+ Policy = NULL;
+
+ SiliconPolicyUpdatePreMemFirmwareConfig ();
+
+ return Policy;
+}
--
2.36.1.windows.1
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^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [edk2-devel] [PATCH v2 6/6] AlderlakeOpenBoardPkg: Add Library Instances
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 6/6] AlderlakeOpenBoardPkg: Add Library Instances Saloni Kasbekar
2023-08-02 20:44 ` Chaganty, Rangasai V
@ 2023-08-04 0:48 ` Chuang, Rosen
1 sibling, 0 replies; 18+ messages in thread
From: Chuang, Rosen @ 2023-08-04 0:48 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Desimone, Nathaniel L, Oram, Isaac W
Reviewed-by: Rosen Chuang < rosen.chuang@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Wednesday, August 2, 2023 6:18 AM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 6/6] AlderlakeOpenBoardPkg: Add Library Instances
Adds the following libraries
- BasePlatformHookLib
- PeiBoardConfigLib
- PeiGetFvInfoLib
- SmmSpiFlashCommonLib
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../BasePlatformHookLib/BasePlatformHookLib.c | 38 ++++
.../BasePlatformHookLib.inf | 44 ++++
.../PeiBoardConfigLib/PeiBoardConfigLib.c | 136 +++++++++++
.../PeiBoardConfigLib/PeiBoardConfigLib.inf | 56 +++++
.../Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c | 89 ++++++++
.../PeiGetFvInfoLib/PeiGetFvInfoLib.inf | 34 +++
.../SmmSpiFlashCommonLib.inf | 49 ++++
.../SmmSpiFlashCommonLib/SpiFlashCommon.c | 215 ++++++++++++++++++
.../SpiFlashCommonSmmLib.c | 60 +++++
9 files changed, 721 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
new file mode 100644
index 0000000000..cccb1e18cc
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/B
+++ asePlatformHookLib.c
@@ -0,0 +1,38 @@
+/** @file
+ Platform Hook Library instances
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi/UefiBaseType.h>
+#include <Library/PchCycleDecodingLib.h>
+
+
+/**
+ Performs platform specific initialization required for the CPU to
+access
+ the hardware associated with a SerialPortLib instance. This function
+does
+ not initialize the serial port hardware itself. Instead, it
+initializes
+ hardware devices that are required for the CPU to access the serial
+port
+ hardware. This function may be called more than once.
+
+ @retval RETURN_SUCCESS The platform specific initialization succeeded.
+ @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.
+
+**/
+RETURN_STATUS
+EFIAPI
+PlatformHookSerialPortInitialize (
+ VOID
+ )
+{
+
+ //
+ // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h.
+ //
+ PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));
+ PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));
+
+ return RETURN_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf
new file mode 100644
index 0000000000..b77724d5ab
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/B
+++ asePlatformHookLib.inf
@@ -0,0 +1,44 @@
+### @file
+# Platform Hook Library instance for Alderlake Mobile/Desktop CRB.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BasePlatformHookLib
+ FILE_GUID = E22ADCC6-ED90-4A90-9837-C8E7FF9E963D
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = PlatformHookLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC #
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciSegmentLib
+ PciLib
+ PchCycleDecodingLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+
+[FixedPcd]
+ gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES
+
+[Sources]
+ BasePlatformHookLib.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c
new file mode 100644
index 0000000000..a9674bdd22
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/Pei
+++ BoardConfigLib.c
@@ -0,0 +1,136 @@
+/** @file
+ Implementation of PeiBoardConfigLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PostCodeLib.h>
+#include <Library/TimerLib.h>
+#include <Library/GpioLib.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PmcLib.h>
+#include <Library/BoardConfigLib.h>
+
+
+
+VOID
+EFIAPI
+InternalUpdateRvpBoardConfig (
+ IN OUT UINT16 BoardId
+ )
+{
+ //
+ // Update Board Type/Platform Type/Platform Flavor
+ //
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ if(PcdSet64S (PcdAcpiDefaultOemTableId, ACPI_OEM_TABLE_ID_ADL_P_M) != EFI_SUCCESS)
+ {
+ DEBUG ((DEBUG_INFO, "Set PcdAcpiDefaultOemTableId error!!!\n"));
+ }
+ break;
+ }
+ DEBUG ((DEBUG_INFO, "PcdAcpiDefaultOemTableId is 0x%llX\n", PcdGet64
+(PcdAcpiDefaultOemTableId))); }
+
+/**
+ Procedure to detect current board HW configuration.
+
+**/
+VOID
+GetBoardConfig (
+ VOID
+ )
+{
+ UINT16 BoardId;
+
+ //
+ // Get Platform Info and fill the PCD //
+ BoardId = BoardIdAdlPDdr5Rvp;
+ PcdSet16S (PcdBoardId, BoardId);
+ //
+ // update RVP board config
+ //
+ InternalUpdateRvpBoardConfig (BoardId);
+
+ DEBUG ((DEBUG_INFO, "Platform Information:\n")); DEBUG ((DEBUG_INFO,
+ "BoardID: 0x%x\n", BoardId));
+
+}
+
+/**
+ Count the number of GPIO settings in the Table.
+
+ @param[in] GpioTable The pointer of GPIO config table
+ @param[out] GpioCount The number of GPIO config entries
+**/
+VOID
+GetGpioTableSize (
+ GPIO_INIT_CONFIG *GpioTable,
+ OUT UINT16 *GpioCount
+ )
+{
+ *GpioCount = 0;
+ if(GpioTable != NULL) {
+ while (GpioTable[*GpioCount].GpioPad != 0 && *GpioCount < MAX_GPIO_PINS) {
+ DEBUG ((DEBUG_INFO, "GpioTable[%d]->GpioPad = %x \n", *GpioCount, GpioTable[*GpioCount].GpioPad));
+ (*GpioCount) ++;
+ }
+ } else {
+ DEBUG ((DEBUG_INFO, "GpioTable is NULL\n"));
+ }
+ DEBUG ((DEBUG_INFO, "GetGpioTableSize() GpioCount = %d\n",
+*GpioCount)); }
+
+/**
+ Configures GPIO
+
+ @param[in] GpioTable Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries **/ STATIC
+VOID ConfigureGpio (
+ IN GPIO_INIT_CONFIG *GpioTable,
+ IN UINT16 GpioTableCount
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
+
+ Status = GpioConfigurePads (GpioTableCount, GpioTable);
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); }
+
+/**
+ Configure GPIO Before Memory is initialized.
+
+ @param[in] GpioTable Pointer to Gpio table **/ VOID GpioInit (
+ IN GPIO_INIT_CONFIG *GpioTable
+ )
+{
+ UINT16 GpioCount;
+
+ if (GpioTable != 0) {
+ GpioCount = 0;
+ GetGpioTableSize (GpioTable, &GpioCount);
+ if (GpioCount != 0) {
+ ConfigureGpio ((VOID *) GpioTable, (UINTN) GpioCount);
+ }
+ }
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf
new file mode 100644
index 0000000000..1f78e9a0ba
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/Pei
+++ BoardConfigLib.inf
@@ -0,0 +1,56 @@
+### @file
+# Component information file for BaseBoardConfigLib.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiBoardConfigLib
+ FILE_GUID = AA9812A8-1BA6-40AD-A846-50D0BC29C38C
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BoardConfigLib|PEIM
+
+[LibraryClasses]
+ DebugLib
+ PcdLib
+ PostCodeLib
+ TimerLib
+ PeiServicesLib
+ PmcLib
+ GpioLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ PeiBoardConfigLib.c
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardId ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardRev ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSpdPresent ## PRODUCES ## CONSUMES
+
+ # GPIO Group Tier
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2
+
+ gBoardModuleTokenSpaceGuid.PcdDisableVpdGpioTable
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem
+
+[Depex]
+ gEfiPeiReadOnlyVariable2PpiGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c
new file mode 100644
index 0000000000..d9ed1c5064
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGe
+++ tFvInfoLib.c
@@ -0,0 +1,89 @@
+/** @file
+ Helper Library for PEI Graphics PEIM
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/PeiGetFvInfoLib.h>
+#include <Ppi/FirmwareVolume.h>
+#include <Pi/PiPeiCis.h>
+#include <Core/Pei/PeiMain.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/HobLib.h>
+
+/**
+ PeiGetSectionFromFv finds the file in FV and gets file Address and
+Size
+
+ @param[in] NameGuid - File GUID
+ @param[out] Address - Pointer to the File Address
+ @param[out] Size - Pointer to File Size
+
+ @retval EFI_SUCCESS Successfull in reading the section from FV
+ @retval EFI_NOT_FOUND File not found
+**/
+EFI_STATUS
+EFIAPI
+PeiGetSectionFromFv (
+ IN CONST EFI_GUID NameGuid,
+ OUT VOID **Address,
+ OUT UINT32 *Size
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_FIRMWARE_VOLUME_PPI *FvPpi;
+ EFI_FV_FILE_INFO FvFileInfo;
+ PEI_CORE_FV_HANDLE *CoreFvHandle;
+ EFI_PEI_FILE_HANDLE FileHandle;
+ EFI_GUID *FileGuid;
+ EFI_COMMON_SECTION_HEADER *Section;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ VOID *HobData;
+
+ Status = PeiServicesLocatePpi(
+ &gEfiFirmwareFileSystem2Guid,
+ 0,
+ NULL,
+ (VOID **)&FvPpi
+ );
+ ASSERT_EFI_ERROR(Status);
+
+ GuidHob = GetFirstGuidHob (&gPlatformInitFvLocationGuid); if
+ (GuidHob != NULL) {
+ HobData = *(VOID **)GET_GUID_HOB_DATA(GuidHob);
+ CoreFvHandle = (PEI_CORE_FV_HANDLE *) HobData;
+
+ //
+ // File typically resides in current FV or previous FV, so searching both of them.
+ //
+ Status = FvPpi->FindFileByName (FvPpi, &NameGuid,
+ &CoreFvHandle->FvHandle, &FileHandle);
+
+ if (!EFI_ERROR(Status) && FileHandle != NULL) {
+
+ DEBUG((DEBUG_INFO, "Find SectionByType \n"));
+
+ Status = FvPpi->FindSectionByType(FvPpi, EFI_SECTION_RAW, FileHandle, (VOID **)&FileGuid);
+ if (!EFI_ERROR(Status)) {
+
+ DEBUG((DEBUG_INFO, "GetFileInfo \n"));
+
+ Status = FvPpi->GetFileInfo(FvPpi, FileHandle, &FvFileInfo);
+ Section = (EFI_COMMON_SECTION_HEADER *)FvFileInfo.Buffer;
+
+ if (IS_SECTION2(Section)) {
+ ASSERT(SECTION2_SIZE(Section) > 0x00FFFFFF);
+ *Size = SECTION2_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEADER2);
+ *Address = ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER2));
+ } else {
+ *Size = SECTION_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEADER);
+ *Address = ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER));
+ }
+ return EFI_SUCCESS;
+ }
+ }
+ } else {
+ DEBUG ((DEBUG_INFO, "Hob not found\n"));
+ }
+ return EFI_NOT_FOUND;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf
new file mode 100644
index 0000000000..1701fb15fe
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGe
+++ tFvInfoLib.inf
@@ -0,0 +1,34 @@
+### @file
+# Component description file for PeiGetFvInfo library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiGetFvInfoLib
+ FILE_GUID = C2584BE4-2CCD-418C-9205-A2031CE75861
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = PeiGetFvInfoLib
+
+[LibraryClasses]
+ BaseMemoryLib
+ BaseLib
+ DebugLib
+ DebugPrintErrorLevelLib
+ HobLib
+ PeiServicesLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ PeiGetFvInfoLib.c
+
+[Guids]
+ gPlatformInitFvLocationGuid ## CONSUMES
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
new file mode 100644
index 0000000000..cf6ca0d0ab
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/
+++ SmmSpiFlashCommonLib.inf
@@ -0,0 +1,49 @@
+### @file
+# SMM Library instance of Spi Flash Common Library Class #
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SmmSpiFlashCommonLib
+ FILE_GUID = 9632D96E-E849-4217-9217-DC500B8AAE47
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_SMM_DRIVER
+ LIBRARY_CLASS = SpiFlashCommonLib|DXE_SMM_DRIVER
+ CONSTRUCTOR = SmmSpiFlashCommonLibConstructor
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[LibraryClasses]
+ IoLib
+ MemoryAllocationLib
+ BaseLib
+ UefiLib
+ SmmServicesTableLib
+ BaseMemoryLib
+ DebugLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+
+[Sources]
+ SpiFlashCommonSmmLib.c
+ SpiFlashCommon.c
+
+[Protocols]
+ gPchSmmSpiProtocolGuid ## CONSUMES
+
+[Depex.X64.DXE_SMM_DRIVER]
+ gPchSmmSpiProtocolGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
new file mode 100644
index 0000000000..3f7c52ac73
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/
+++ SpiFlashCommon.c
@@ -0,0 +1,215 @@
+/** @file
+ Wrap EFI_SPI_PROTOCOL to provide some library level interfaces
+ for module use.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+
+#include <Library/SpiFlashCommon.h>
+#include <Library/IoLib.h>
+
+PCH_SPI_PROTOCOL *mSpiProtocol;
+
+//
+// Variables for boottime and runtime usage.
+//
+UINTN mBiosAreaBaseAddress = 0;
+UINTN mBiosSize = 0;
+UINTN mBiosOffset = 0;
+
+/**
+ Enable block protection on the Serial Flash device.
+
+ @retval EFI_SUCCESS Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashLock (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+
+ return Status;
+}
+
+/**
+ Read NumBytes bytes of data from the address specified by
+ PAddress into Buffer.
+
+ @param[in] Address The starting physical address of the read.
+ @param[in,out] NumBytes On input, the number of bytes to read. On output, the number
+ of bytes actually read.
+ @param[out] Buffer The destination data buffer for the read.
+
+ @retval EFI_SUCCESS Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashRead (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ OUT UINT8 *Buffer
+ )
+{
+ ASSERT ((NumBytes != NULL) && (Buffer != NULL));
+ if ((NumBytes == NULL) || (Buffer == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // This function is implemented specifically for those platforms //
+ at which the SPI device is memory mapped for read. So this //
+ function just do a memory copy for Spi Flash Read.
+ //
+ CopyMem (Buffer, (VOID *) Address, *NumBytes);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Write NumBytes bytes of data from Buffer to the address specified by
+ PAddresss.
+
+ @param[in] Address The starting physical address of the write.
+ @param[in,out] NumBytes On input, the number of bytes to write. On output,
+ the actual number of bytes written.
+ @param[in] Buffer The source data buffer for the write.
+
+ @retval EFI_SUCCESS Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_BAD_BUFFER_SIZE DataSectionSize in BGUP header exceeds the
+ size ofBIOS Guard script
+ buffer
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashWrite (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINTN Offset;
+ UINT32 Length;
+ UINT32 RemainingBytes;
+
+ ASSERT ((NumBytes != NULL) && (Buffer != NULL)); if ((NumBytes ==
+ NULL) || (Buffer == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ASSERT (Address >= mBiosAreaBaseAddress); if (Address <
+ mBiosAreaBaseAddress) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Offset = Address - mBiosAreaBaseAddress;
+
+ ASSERT ((*NumBytes + Offset) <= mBiosSize); if ((*NumBytes + Offset)
+ > mBiosSize) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = EFI_SUCCESS;
+ RemainingBytes = *NumBytes;
+
+ while (RemainingBytes > 0) {
+ if (RemainingBytes > SECTOR_SIZE_4KB) {
+ Length = SECTOR_SIZE_4KB;
+ } else {
+ Length = RemainingBytes;
+ }
+ Status = mSpiProtocol->FlashWrite (
+ mSpiProtocol,
+ FlashRegionBios,
+ (UINT32) Offset,
+ Length,
+ Buffer
+ );
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+ RemainingBytes -= Length;
+ Offset += Length;
+ Buffer += Length;
+ }
+
+ //
+ // Actual number of bytes written
+ //
+ *NumBytes -= RemainingBytes;
+
+ return Status;
+}
+
+/**
+ Erase the block starting at Address.
+
+ @param[in] Address The starting physical address of the block to be erased.
+ This library assume that caller garantee that the PAddress
+ is at the starting address of this block.
+ @param[in] NumBytes On input, the number of bytes of the logical block to be erased.
+ On output, the actual number of bytes erased.
+
+ @retval EFI_SUCCESS. Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashBlockErase (
+ IN UINTN Address,
+ IN UINTN *NumBytes
+ )
+{
+ EFI_STATUS Status;
+ UINTN Offset;
+ UINTN RemainingBytes;
+
+ ASSERT (NumBytes != NULL);
+ if (NumBytes == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ASSERT (Address >= mBiosAreaBaseAddress); if (Address <
+ mBiosAreaBaseAddress) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Offset = Address - mBiosAreaBaseAddress;
+
+ ASSERT ((*NumBytes % SECTOR_SIZE_4KB) == 0); if ((*NumBytes %
+ SECTOR_SIZE_4KB) != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ASSERT ((*NumBytes + Offset) <= mBiosSize); if ((*NumBytes + Offset)
+ > mBiosSize) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = EFI_SUCCESS;
+ RemainingBytes = *NumBytes;
+
+ Status = mSpiProtocol->FlashErase (
+ mSpiProtocol,
+ FlashRegionBios,
+ (UINT32) Offset,
+ (UINT32) RemainingBytes
+ );
+ return Status;
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
new file mode 100644
index 0000000000..897d85743a
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/
+++ SpiFlashCommonSmmLib.c
@@ -0,0 +1,60 @@
+/** @file
+ SMM Library instance of SPI Flash Common Library Class
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+
+#include <Library/SpiFlashCommon.h>
+#include <Library/SmmServicesTableLib.h>
+
+extern PCH_SPI_PROTOCOL *mSpiProtocol;
+
+extern UINTN mBiosAreaBaseAddress;
+extern UINTN mBiosSize;
+extern UINTN mBiosOffset;
+
+/**
+ The library constructuor.
+
+ The function does the necessary initialization work for this library
+ instance.
+
+ @param[in] ImageHandle The firmware allocated handle for the UEFI image.
+ @param[in] SystemTable A pointer to the EFI system table.
+
+ @retval EFI_SUCCESS The function always return EFI_SUCCESS for now.
+ It will ASSERT on error for debug version.
+ @retval EFI_ERROR Please reference LocateProtocol for error code details.
+**/
+EFI_STATUS
+EFIAPI
+SmmSpiFlashCommonLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINT32 BaseAddr;
+ UINT32 RegionSize;
+
+ mBiosAreaBaseAddress = (UINTN) PcdGet32 (PcdBiosAreaBaseAddress);
+ mBiosSize = (UINTN) PcdGet32 (PcdBiosSize);
+
+ //
+ // Locate the SMM SPI protocol.
+ //
+ Status = gSmst->SmmLocateProtocol (
+ &gPchSmmSpiProtocolGuid,
+ NULL,
+ (VOID **) &mSpiProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ mSpiProtocol->GetRegionAddress (mSpiProtocol, FlashRegionBios,
+ &BaseAddr, &RegionSize); mBiosOffset = BaseAddr;
+
+ return Status;
+}
--
2.36.1.windows.1
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^ permalink raw reply [flat|nested] 18+ messages in thread
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Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
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2023-08-01 22:17 [edk2-devel] [PATCH v2 1/6] AlderlakeOpenBoardPkg: Add package and headers Saloni Kasbekar
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 2/6] AlderlakeOpenBoardPkg: Add modules Saloni Kasbekar
2023-08-02 17:46 ` Chaganty, Rangasai V
2023-08-04 0:42 ` Chuang, Rosen
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add libraries Saloni Kasbekar
2023-08-02 18:10 ` Chaganty, Rangasai V
2023-08-04 0:48 ` Chuang, Rosen
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 4/6] AlderlakeOpenBoardPkg: Add ACPI module Saloni Kasbekar
2023-08-02 20:25 ` Chaganty, Rangasai V
2023-08-04 0:48 ` Chuang, Rosen
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module Saloni Kasbekar
2023-08-02 20:35 ` Chaganty, Rangasai V
2023-08-04 0:48 ` Chuang, Rosen
2023-08-01 22:17 ` [edk2-devel] [PATCH v2 6/6] AlderlakeOpenBoardPkg: Add Library Instances Saloni Kasbekar
2023-08-02 20:44 ` Chaganty, Rangasai V
2023-08-04 0:48 ` Chuang, Rosen
2023-08-02 17:25 ` [edk2-devel] [PATCH v2 1/6] AlderlakeOpenBoardPkg: Add package and headers Chaganty, Rangasai V
2023-08-04 0:40 ` Chuang, Rosen
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