From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 26AFB941BC4 for ; Fri, 4 Aug 2023 18:08:14 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=+swmuodbk6ZKRxDm/p7El9e2f//dEK0JkPNP6wFBtr8=; c=relaxed/simple; d=groups.io; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:From:To:CC:Subject:Thread-Topic:Thread-Index:Date:Message-ID:References:In-Reply-To:Accept-Language:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1691172492; v=1; b=jFrVNlzy3v0/96fl4PRpFcqIT3HwVdpqNrdga7HgRtwfZEiRKptncSNO/vMgRcqsHM6oYZta L3GpQEwxgwXzdDx+7xqDKyFS35HbXLc5o3wPLSzOxMcp0cHCzWQn0qQfrpJhCUJ/+E8kae9wEb2 1ukyhhIFYfwYCvjIYaWQRNhw= X-Received: by 127.0.0.2 with SMTP id 8IDaYY7687511xnLM8SUtCaw; Fri, 04 Aug 2023 11:08:12 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web10.1670.1691109775869162211 for ; Thu, 03 Aug 2023 17:42:56 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10791"; a="354967467" X-IronPort-AV: E=Sophos;i="6.01,253,1684825200"; d="scan'208";a="354967467" X-Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Aug 2023 17:42:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10791"; a="843822781" X-IronPort-AV: E=Sophos;i="6.01,253,1684825200"; d="scan'208";a="843822781" X-Received: from fmsmsx602.amr.corp.intel.com ([10.18.126.82]) by fmsmga002.fm.intel.com with ESMTP; 03 Aug 2023 17:42:53 -0700 X-Received: from fmsmsx611.amr.corp.intel.com (10.18.126.91) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 3 Aug 2023 17:42:52 -0700 X-Received: from fmsmsx610.amr.corp.intel.com (10.18.126.90) by fmsmsx611.amr.corp.intel.com (10.18.126.91) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 3 Aug 2023 17:42:52 -0700 X-Received: from fmsedg601.ED.cps.intel.com (10.1.192.135) by fmsmsx610.amr.corp.intel.com (10.18.126.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27 via Frontend Transport; Thu, 3 Aug 2023 17:42:52 -0700 X-Received: from NAM11-BN8-obe.outbound.protection.outlook.com (104.47.58.168) by edgegateway.intel.com (192.55.55.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.27; Thu, 3 Aug 2023 17:42:51 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WXKGwY4c0/wHK3SjIHv0FBtl0I0BSJneH1l3UZUrnRU1X9RSCV4AaVuPYtFfSPWJNRPzCB2BF7BiMMm3iS6p3EXL1MwICJTIAWdxG3K7sA0P/hOm25BL0fVjRrvSTXPcxqIB6+e7ejh+zFhAjVEPQG39Hiza/TeXS5Flbsmy4sAkl2dq2yhgaiXumXOn2VDhz2ehM1WaMkHn0OTWDwWCGRnpd629a6o56Qnh7269j90fYBlBxnGP0zV0lnw21XzZ3lOY4rbByNUVJ1qGrQ3YkSZpqhnoRCWIME1l/86uoOTPC/08LuvX4O4TI19qsgOwoRnmgzvPxzXxGDciYMjjcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=m6vL7+tCaJX8iH0lwFuM0K+5zYFZ0j3cvUp8bUoYl7k=; b=VWJIiCvdq8o4mzHtJVRzUtVktgBis3Z/budGThXBRpGyllBXr/j2Lm8dbWvR9Zmfe4obrNc1zqBslPix6ku4VNT2lWJ7ESzTXsI27szHaxt63nXfj3pQr/N1JNfZ3YNn/NsnUpjujaDhV222+d2RcMQ2ZbQtkzvKFIEAXagZujTRELh2t6hjl7olJn6oXyBEQtjebYKSgjoQu1+qiGpTl0mhzx525NTLWEHuFAuSq1LQeThTLoH2KtGrN2nPA/jq7NeSXerXbL/IKwtbKIG7DCR2UYCJ2I/GPVYVp5GGuiREQEM/Quys6n1eK5H3KJ7iwu2/8m8lEZf43+Pd9CrwzQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none X-Received: from PH0PR11MB5626.namprd11.prod.outlook.com (2603:10b6:510:ee::15) by MW3PR11MB4537.namprd11.prod.outlook.com (2603:10b6:303:5d::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6652.20; Fri, 4 Aug 2023 00:42:43 +0000 X-Received: from PH0PR11MB5626.namprd11.prod.outlook.com ([fe80::68a8:9cc5:ec4d:ca44]) by PH0PR11MB5626.namprd11.prod.outlook.com ([fe80::68a8:9cc5:ec4d:ca44%7]) with mapi id 15.20.6631.046; Fri, 4 Aug 2023 00:42:43 +0000 From: "Chuang, Rosen" To: "Kasbekar, Saloni" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Desimone, Nathaniel L" , "Oram, Isaac W" Subject: Re: [edk2-devel] [PATCH v2 2/6] AlderlakeOpenBoardPkg: Add modules Thread-Topic: [PATCH v2 2/6] AlderlakeOpenBoardPkg: Add modules Thread-Index: AQHZxMYI0ed7lUTszkSc07uIJHNmaK/ZT4xw Date: Fri, 4 Aug 2023 00:42:43 +0000 Message-ID: References: <6d497bd984f8a16be98d96042f3efea130be8a9c.1690391944.git.saloni.kasbekar@intel.com> In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PH0PR11MB5626:EE_|MW3PR11MB4537:EE_ x-ms-office365-filtering-correlation-id: 8cf0d48b-2246-4e76-ea35-08db9483b72b x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam-message-info: 7LaM2oTJ6SKLcLhU5lvx4QJr5ofe7Q1Gl5GCBeLO7e1lxHGVyg1DAddFSFlWx5Ojc+aODgSI4lQ3MYMNX/3hbgs0NCeujXLqzrIHywop5oNC+uhCR0tHtcsrBPMvcuMUmAbdwrD7sev/aYjGl1cvjjaZcs3hRfWvE7+WqiZHTq23YMtZjPgRUFy5zXecsfFyBk2cZ+ESDxXgGornkplkAgg2ONQsZQ7ebLE8Gl5c7mgxIucVrlREy7qsCzAsMkz3xdhrTi85UQtUCcX9td70XOpVKENamCop2qXn8WspuVS7Y/DHqZ/r7RvXAFmcqRWMFo+d2wzff5lyh/6k7hZWFBfr6Xtt8brfZxk3uhqLukCWpAN6Sf4oXBuNeSsF6+AD9SvLEKjbPpFM2HtthOyPotQh9R+i+Vh4CbaGwj7s7IPZNyfycickEq2WMAVvLYoSH+dQ17ik4Tv7UIDAZCYTbuFxtBoxq1mXqaSeK2PyBw/XLc7IzulRFJXePFSwLlrYy0/N21i9kneRG1JXkhh5MutHSbdnbSzjF4Sw2zyqlHXK7A7P4KVDr3eqEA7a5u/Zazl8REawGy63VOM3kZXEi9/TjtOUte29OoUp2hI2skzXmqW3Ufq3lfCf34pSERvL x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?7grCQrlo8PldgWl+U9/pW4xa2vPGeM3p+9bVDSkgxNsAnC3llUsp0NGJMGLG?= =?us-ascii?Q?NHmNuAjArQ2KYbVPwr8ysVk6o6BcNGFtf3YlCX+FSlt1zFZxOoGdHTcaM+Vc?= =?us-ascii?Q?POKAoWSGi9Ksx9+hl3GQMlnU21WW8hoTzrf4WRSrpRnw0sEBvGB2LvVCFP6A?= =?us-ascii?Q?oIrrYO9JBufy9zpBSmx9TeBEZN3fWzypwoex6qwrZ/ERtSl2cvbHVj6pxNCV?= =?us-ascii?Q?lk4058EmkcgtJ14ku05hVR0H4yGsXHPRypsmPuqaexrd4ei1p+uCqLzikyGW?= =?us-ascii?Q?un8VKyjlLnr4r8ZyGGTt0Oq1Zv3lDfItWMYRaw0gymWPVAPYdN+TQ0TWReOm?= =?us-ascii?Q?Pn+bk38+u24skixO7HaDDZh+Bri+52avdaU+nKL8kCeqM6eJIZ3jLP3p0cn8?= =?us-ascii?Q?QHPY+hx1dEEnH4M5i4wDp7WLye0rkzzNMstt7n1VUKGzfwUoq2lkum/xwrG/?= =?us-ascii?Q?2gIO+gB9qOmLtbPKZdUiP5W+zsHoDQKR9QEL6VvuWolfc63zPTNdcSx2oWBi?= =?us-ascii?Q?azJVo4451zsygGC/eF8VQ5LDt0NNmamgPtQwrViuSkoxq0jGGRU0rCCN0wJT?= =?us-ascii?Q?Luy4bieflEKDzk75b8j6wBD9CNzx2RU2vJl6eVLSm0iflxXS6SxV/3gnjd9H?= =?us-ascii?Q?9FbfAN4njN5EkMr8OM0jkj9W+8T6WozWlIpSMcI/QEpQgA+wvrzJGwTv4KCR?= =?us-ascii?Q?GIDw2HSsyvg0CsITQIML2p2RjPzULFos1nwUzXgeXEyO4Ub6WO86PQPHtF5m?= =?us-ascii?Q?kAdoGvrtePKwAF702iZ7ln6S2hq5A+I2GCPOT9AMxkBcRXnPyWWfA0Ysds1L?= =?us-ascii?Q?KitMdcxBrDnLdzb28XR4zsyw8TVG1m51dwmie4tFNAupnc38le5pUfycnigF?= =?us-ascii?Q?/lnr1/u/OYLr0lkOoc/kmrQ+aEabAT4b29ahqTPe0xInfL2h8CH3CqrbrwDT?= =?us-ascii?Q?qlNm1n3VudbFX3leLWq1EbG6m1ZGCE253k6PI+ZZpj7SXMa20i00xpHvEV4l?= =?us-ascii?Q?GVq+PPujYXwTeuo8yknVG3Z39uO/Fr0MYtNCXODrfAxqXYU3jVC+vnI9BB+a?= =?us-ascii?Q?/mxNBWsfx4H+lkJWTU4ZpLMAYz3iDkWUiJ0AEGCSVOF7IxYxQPdz11m9zKWw?= =?us-ascii?Q?/eBzUbKU4P9Cvux7tgVW+/uPOd1+4AjzKXadpu8bMy06m2X4WulgLVJLUy6V?= =?us-ascii?Q?jW6b5H1W0uQgQ7yHHoS0l7RozwI5H1qCEdvn4mugbhF2d4b4/Y2CnbpBws1a?= =?us-ascii?Q?8zSZ5c/lkRniJribLvHTAhwFxs/xu8UBOO4u5++03wrbgA+2/MMdmLJHPiDd?= =?us-ascii?Q?TO210kYZhnBmcJwpkca6ARba1r1DdkM5VpWdXD0ui48/mrZysb2T40MSOEB2?= =?us-ascii?Q?TzxXrVVN/9t2U/hLYp2MJczFZE9laEexJT3RVKkHOJlnkGCJLfJa8xi1Ox2n?= =?us-ascii?Q?ff9sf4GKxMyfHCTUQHKXh6ylFzApucHXQhkkAkeSMWzGUjK0FwGlG3AfDTat?= =?us-ascii?Q?zwIQqxEswqRRQX8PJWD3WPUX8YBnKSX5DTwa2AkaZTn1GWr4GTtHPlj6nje6?= =?us-ascii?Q?sbsRcbgZTGOkHFziYo4R2reczgXoVwSNiJahfEYH?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB5626.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8cf0d48b-2246-4e76-ea35-08db9483b72b X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Aug 2023 00:42:43.7618 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: fnDRb9cgguS3hcucHO7LRUl56Hdksu+uveEkKmV541n1TNmPpZT+g/Fa3wMhVAviLksYUwZdTyB5VswH+sDlKg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR11MB4537 X-OriginatorOrg: intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rosen.chuang@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: DuuIMwUSgxcaBUytiyCZyC39x7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=jFrVNlzy; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Reviewed-by: Rosen Chuang < rosen.chuang@intel.com> -----Original Message----- From: Kasbekar, Saloni =20 Sent: Wednesday, August 2, 2023 6:18 AM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Oram, Isaac W ; Chuang, Rosen Subject: [PATCH v2 2/6] AlderlakeOpenBoardPkg: Add modules Adds the following modules: -BiosInfo -OpenBoardPlatformInit -SBCVpdStructurePcd Cc: Sai Chaganty Cc: Nate DeSimone Cc: Isaac Oram Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c | 196 +++++++++++++++ .../BiosInfo/BiosInfo.inf | 84 +++++++ .../OpenBoardPlatformInitPostMem.c | 233 ++++++++++++++++++ .../OpenBoardPlatformInitPostMem.inf | 75 ++++++ .../SBCVpdStructurePcd/AllStructPCD.dsc | 19 ++ .../GpioTableAdlPPostMem.dsc | 40 +++ .../GpioTableAdlPPreMem.dsc | 29 +++ .../MrcDqDqsSPD/AdlPSpdMap.dsc | 138 +++++++++++ .../PcieClocks/AdlPPcieClocks.dsc | 31 +++ 9 files changed, 845 insertions(+) create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.= c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.= inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformI= nit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformI= nit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd= /AllStructPCD.dsc create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd= /GpioTableAdlPPostMem.dsc create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd= /GpioTableAdlPPreMem.dsc create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd= /MrcDqDqsSPD/AdlPSpdMap.dsc create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd= /PcieClocks/AdlPPcieClocks.dsc diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c b/Pla= tform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c new file mode 100644 index 0000000000..64462900de --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c @@ -0,0 +1,196 @@ +/** @file + PEIM to provide BiosInfo structure listing up all firmware volume's=20 +base addresses, sizes, + attributes, and information associated to the firmware volume. + Primarily the structure is used on FIT table creation and Bpm. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BASE_FV_SIZE 10 + +#define FSP_WRAPPER_FV_SIZE 3 + +#define TSN_MAC_ADDRESS_FV_SIZE 0 + +#define BIOS_INFO_STRUCT_SIZE (BASE_FV_SIZE + FSP_WRAPPER_FV_SIZE +=20 +TSN_MAC_ADDRESS_FV_SIZE) + + +/* + BIOS_INFO structure is the base of the firmware volume layout for=20 +Intel platform BIOS implementation + so security checker module can run based on the structure and throw=20 +warnings, error or deadloop + when any unexpected firmware volumes are detected. + + BIOS_INFO is recommended to support full entries of firmware volumes=20 +present in a flash + with right type, attribute, version, flash map base address and size, + all associated information which is defined by BIOS_INFO_STRUCT structur= e. + - IBB firmware volumes, which are expected to be measured or/and verifie= d + by hardware base security solution to meet SecureBoot chain of trust + (Intel BootGuard for example), have attribute 0x0. + - Post IBB firmware volumes, which are expected to be measured or/and ve= rified + by BIOS (TCG code for measurement, RSA2048SHA256Sign algorithm for ver= ification for example), + have attribute BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB. + - Else, follows Firmware Interface Table specification. +*/ +#pragma pack (1) +typedef struct { + BIOS_INFO_HEADER Header; + BIOS_INFO_STRUCT Entry[BIOS_INFO_STRUCT_SIZE]; } BIOS_INFO; #pragma=20 +pack () + +GLOBAL_REMOVE_IF_UNREFERENCED BIOS_INFO mBiosInfo =3D { + { + BIOS_INFO_SIGNATURE, + BIOS_INFO_STRUCT_SIZE, + 0, + }, + { + { + FIT_TYPE_07_BIOS_STARTUP_MODULE, + BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT, + 0x0100, + FixedPcdGet32 (PcdFlashNvStorageVariableSize) + FixedPcdGet32 (PcdFl= ashNvStorageFtwWorkingSize) + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize)= , + FixedPcdGet32 (PcdFlashNvStorageVariableBase) + }, + { + FIT_TYPE_07_BIOS_STARTUP_MODULE, + BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB, + 0x0100, + FixedPcdGet32 (PcdFlashFvAdvancedSize), + FixedPcdGet32 (PcdFlashFvAdvancedBase) + }, + { + FIT_TYPE_07_BIOS_STARTUP_MODULE, + BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB, + 0x0100, + FixedPcdGet32 (PcdFlashFvOptionalSize), + FixedPcdGet32 (PcdFlashFvOptionalBase) + }, + { + FIT_TYPE_07_BIOS_STARTUP_MODULE, + BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB, + 0x0100, + FixedPcdGet32 (PcdFlashFvSecuritySize), + FixedPcdGet32 (PcdFlashFvSecurityBase) + }, + { + FIT_TYPE_07_BIOS_STARTUP_MODULE, + BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB, + 0x0100, + FixedPcdGet32 (PcdFlashFvOsBootSize), + FixedPcdGet32 (PcdFlashFvOsBootBase) + }, + { + FIT_TYPE_07_BIOS_STARTUP_MODULE, + BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB, + 0x0100, + FixedPcdGet32 (PcdFlashFvUefiBootSize), + FixedPcdGet32 (PcdFlashFvUefiBootBase) + }, + { + FIT_TYPE_07_BIOS_STARTUP_MODULE, + BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB, + 0x0100, + FixedPcdGet32 (PcdFlashFvPostMemorySize), + FixedPcdGet32 (PcdFlashFvPostMemoryBase) + }, + { + FIT_TYPE_07_BIOS_STARTUP_MODULE, + BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT, + 0x0100, + FixedPcdGet32 (PcdFlashFvFirmwareBinariesSize), + FixedPcdGet32 (PcdFlashFvFirmwareBinariesBase) + }, + { + FIT_TYPE_07_BIOS_STARTUP_MODULE, + BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB, + 0x0100, + FixedPcdGet32 (PcdFlashFvFspSSize), + FixedPcdGet32 (PcdFlashFvFspSBase) + }, + { + FIT_TYPE_07_BIOS_STARTUP_MODULE, + 0x00, // IBB FV + 0x0100, + FixedPcdGet32 (PcdFlashFvFspMSize), + FixedPcdGet32 (PcdFlashFvFspMBase) + }, + { + FIT_TYPE_07_BIOS_STARTUP_MODULE, + 0x00, // IBB FV + 0x0100, + FixedPcdGet32 (PcdFlashFvFspTSize), + FixedPcdGet32 (PcdFlashFvFspTBase) + }, + { + FIT_TYPE_07_BIOS_STARTUP_MODULE, + 0x00, // IBB FV + 0x0100, + FixedPcdGet32 (PcdFlashFvPreMemorySize), + FixedPcdGet32 (PcdFlashFvPreMemoryBase) + }, + { + FIT_TYPE_01_MICROCODE, + BIOS_INFO_STRUCT_ATTRIBUTE_MICROCODE_WHOLE_REGION, + 0x0100, + FixedPcdGet32 (PcdFlashMicrocodeFvSize), + FixedPcdGet32 (PcdFlashMicrocodeFvBase) + }, + } +}; + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mBiosInfoPpiList=20 +=3D { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gBiosInfoGuid, + &mBiosInfo +}; + +/** + Installs BiosInfo Ppi. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS Install the BiosInfo Ppi successfully. + +**/ +EFI_STATUS +EFIAPI +BiosInfoEntryPoint ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + VOID *HobData; + + // + // Install PPI, so that other PEI module can add dependency. + // + Status =3D PeiServicesInstallPpi (&mBiosInfoPpiList); + ASSERT_EFI_ERROR (Status); + + // + // Build hob, so that DXE module can also get the data. + // + HobData =3D BuildGuidHob (&gBiosInfoGuid, sizeof (mBiosInfo)); + ASSERT (HobData !=3D NULL); + if (HobData =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + CopyMem (HobData, &mBiosInfo, sizeof (mBiosInfo)); + return EFI_SUCCESS; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf b/P= latform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf new file mode 100644 index 0000000000..b11451807a --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf @@ -0,0 +1,84 @@ +### @file +# Module Information description file for BIOS Info PEIM. +# The module provides BiosInfo structure listing up all firmware=20 +volume's base addresses, # sizes, attributes, those information associated= to each firmware volume. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D BiosInfo + FILE_GUID =3D 4A4CA1C6-871C-45BB-8801-6910A7AA5807 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + ENTRY_POINT =3D BiosInfoEntryPoint +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES IA32 X64 +# + +[LibraryClasses] + PeimEntryPoint + PeiServicesLib + PeiServicesTablePointerLib + HobLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec + SecurityPkg/SecurityPkg.dec + BoardModulePkg/BoardModulePkg.dec + +[Pcd] + gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSU= MES + gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase ##=20 +CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase ## CONSU= MES + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize ## CONSU= MES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSU= MES + gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize ## CONSU= MES + +[Sources] + BiosInfo.c + +[Guids] + gBiosInfoGuid ## PRODUCES + +[Depex] + gEfiPeiMasterBootModePpiGuid diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/Ope= nBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c b/Platform/Intel/Alder= lakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPl= atformInitPostMem.c new file mode 100644 index 0000000000..4fab4ad8e6 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoa +++ rdPlatformInitPei/OpenBoardPlatformInitPostMem.c @@ -0,0 +1,233 @@ +/** @file + Source code file for OpenBoard Platform Init PEI module + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include=20 + #include #include=20 + #include #include=20 + #include #include=20 + #include #include=20 + #include =20 +#include + + +EFI_STATUS +EFIAPI +OpenBoardPlatformInitEndOfPei ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + +static EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK |=20 +EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiEndOfPeiSignalPpiGuid, + (EFI_PEIM_NOTIFY_ENTRY_POINT) OpenBoardPlatformInitEndOfPei }; + +EFI_STATUS +EFIAPI +GetPeiPlatformLidStatus ( + OUT LID_STATUS *CurrentLidStatus + ); + +EFI_STATUS +EFIAPI +GetVbtData ( + OUT EFI_PHYSICAL_ADDRESS *VbtAddress, + OUT UINT32 *VbtSize + ); + +PEI_GRAPHICS_PLATFORM_POLICY_PPI PeiGraphicsPlatform =3D { + PEI_GRAPHICS_PLATFORM_POLICY_REVISION, + GetPeiPlatformLidStatus, + GetVbtData +}; + +EFI_PEI_PPI_DESCRIPTOR mPeiGraphicsPlatformPpi =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gPeiGraphicsPlatformPpiGuid, + &PeiGraphicsPlatform +}; + +EFI_STATUS +EFIAPI +GetVbtData ( + OUT EFI_PHYSICAL_ADDRESS *VbtAddress, + OUT UINT32 *VbtSize + ) +{ + EFI_GUID FileGuid; + EFI_GUID BmpImageGuid; + VOID *Buffer; + UINT32 Size; + + Size =3D 0; + Buffer =3D NULL; + + + DEBUG((DEBUG_INFO, "GetVbtData Entry\n")); + + CopyMem (&BmpImageGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid),=20 + sizeof(BmpImageGuid)); + + CopyMem(&FileGuid, &BmpImageGuid, sizeof(FileGuid)); =20 + PeiGetSectionFromFv(FileGuid, &Buffer, &Size); if (Buffer =3D=3D NULL) { + DEBUG((DEBUG_ERROR, "Could not locate VBT\n")); } else { + DEBUG ((DEBUG_INFO, "GetVbtData Buffer is 0x%x\n", Buffer)); + DEBUG ((DEBUG_INFO, "GetVbtData Size is 0x%x\n", Size)); + *VbtAddress =3D (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer; + *VbtSize =3D Size; + } + DEBUG((DEBUG_INFO, "GetVbtData exit\n")); + + return EFI_SUCCESS; +} + + +/** + This function will return Lid Status in PEI phase. + + @param[out] CurrentLidStatus + + @retval EFI_SUCCESS + @retval EFI_UNSUPPORTED +**/ + +EFI_STATUS +EFIAPI +GetPeiPlatformLidStatus ( + OUT LID_STATUS *CurrentLidStatus + ) +{ + DEBUG ((DEBUG_INFO, "LidStatus Unsupported\n")); + return EFI_UNSUPPORTED; +} + +/** + Configure PciHostBridge related PCDs +**/ +VOID +ConfigurePciHostBridgePcds ( + VOID + ) +{ + // + // Provide 256GB available above 4GB MMIO resource + // limited to use single variable MTRR to cover this above 4GB MMIO regi= on. + // + PcdSet64S (PcdPciReservedMemAbove4GBBase, BASE_256GB); + PcdSet64S (PcdPciReservedMemAbove4GBLimit, BASE_256GB + SIZE_256GB -=20 +1); + if (PcdGet64 (PcdPciReservedMemAbove4GBBase) < PcdGet64 (PcdPciReservedM= emAbove4GBLimit)) { + DEBUG ((DEBUG_INFO, " PCI space that above 4GB MMIO is from 0x%lX", Pc= dGet64 (PcdPciReservedMemAbove4GBBase))); + DEBUG ((DEBUG_INFO, " to 0x%lX\n", PcdGet64=20 +(PcdPciReservedMemAbove4GBLimit))); + } +} + +/** + This function handles PlatformInit task at the end of PEI + + @param[in] PeiServices Pointer to PEI Services Table. + @param[in] NotifyDesc Pointer to the descriptor for the Notification = event that + caused this function to execute. + @param[in] Ppi Pointer to the PPI data associated with this fu= nction. + + @retval EFI_SUCCESS The function completes successfully + @retval others +**/ +EFI_STATUS +EFIAPI +OpenBoardPlatformInitEndOfPei ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + // + // Configure PciHostBridge related PCDs before DXE phase + // + ConfigurePciHostBridgePcds (); + + return EFI_SUCCESS; +} + + +/** + Platform Init PEI module entry point + + @param[in] FileHandle Not used. + @param[in] PeiServices General purpose services available to e= very PEIM. + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create databa= se +**/ +EFI_STATUS +EFIAPI +OpenBoardPlatformInitPostMemEntryPoint ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + PEI_CORE_INSTANCE *PrivateData; + UINTN CurrentFv; + PEI_CORE_FV_HANDLE *CoreFvHandle; + VOID *HobData; + + PostCode (PLATFORM_INIT_POSTMEM_ENTRY); + + // + // Build a HOB to show current FV location for SA policy update code to = consume. + // + PrivateData =3D PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices); + CurrentFv =3D PrivateData->CurrentPeimFvCount; CoreFvHandle =3D=20 + &(PrivateData->Fv[CurrentFv]); + + HobData =3D BuildGuidHob ( + &gPlatformInitFvLocationGuid, + sizeof (VOID *) + ); + ASSERT (HobData !=3D NULL); + CopyMem (HobData, (VOID *) &CoreFvHandle, sizeof (VOID *)); + + // + // Install mPeiGraphicsPlatformPpi + // + DEBUG ((DEBUG_INFO, "Install mPeiGraphicsPlatformPpi \n")); Status =3D= =20 + PeiServicesInstallPpi (&mPeiGraphicsPlatformPpi); + + // + // Performing PlatformInitEndOfPei after EndOfPei PPI produced // =20 + Status =3D PeiServicesNotifyPpi (&mEndOfPeiNotifyList); PostCode=20 + (PLATFORM_INIT_POSTMEM_EXIT); + + return Status; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/Ope= nBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf b/Platform/Intel/Ald= erlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoard= PlatformInitPostMem.inf new file mode 100644 index 0000000000..b2bfd97f8a --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoa +++ rdPlatformInitPei/OpenBoardPlatformInitPostMem.inf @@ -0,0 +1,75 @@ +### @file +# Component information file for the OpenBoard Platform Init PEI module. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D OpenBoardPlatformInitPostMem + FILE_GUID =3D 314EE04C-1106-4DC6-ACBC-CF19C0DBC5CC + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + ENTRY_POINT =3D OpenBoardPlatformInitPostMemEntryPoin= t + +[LibraryClasses] + PeimEntryPoint + DebugLib + IoLib + MemoryAllocationLib + BaseMemoryLib + HobLib + PeiServicesLib + PciSegmentLib + MtrrLib + PchInfoLib + PostCodeLib + SiPolicyLib + FspCommonLib + PcdLib + PchPciBdfLib + GpioLib + PeiGetFvInfoLib + +[Packages] + AlderlakeSiliconPkg/SiPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + AlderLakeFspBinPkg/Client/AlderLakeP/AlderLakeFspBinPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Sources] + OpenBoardPlatformInitPostMem.c + +[Ppis] + gEfiEndOfPeiSignalPpiGuid ## CONSUMES + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES + gPeiGraphicsPlatformPpiGuid ## PRODUCES + gFspSiliconInitDonePpiGuid ## CONSUMES + +[Protocols] + +[Guids] + gEfiSmmSmramMemoryGuid ## CONSUMES + gPlatformInitFvLocationGuid ## PRODUCES + +[Depex] + gEfiPeiMemoryDiscoveredPpiGuid + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIobase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIoLimit ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdPciSegmentCount ## CONSU= MES + + gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSU= MES + diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStr= uctPCD.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStr= uctPCD.dsc new file mode 100644 index 0000000000..9215a026ae --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructP +++ CD.dsc @@ -0,0 +1,19 @@ +## @file +# Include All Board Gpio configuration file. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +!include=20 +$(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc +!include=20 +$(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc + + +# PCIe clock mapping +!include=20 +$(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks. +dsc + +# MRC DQS DQ and SPD mapping +!include=20 +$(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc + + + diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTa= bleAdlPPostMem.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePc= d/GpioTableAdlPPostMem.dsc new file mode 100644 index 0000000000..3eb8c276b5 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableA +++ dlPPostMem.dsc @@ -0,0 +1,40 @@ +## @file +# GPIO definition table for Alderlake P # +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +### +### !!! GPIOs designated to Native Functions shall not be configured by Pl= atform Code. +### Native Pins shall be configured by Silicon Code (based on BIOS policie= s setting) or soft straps(set by CSME in FITc). +### +### + + +#mGpioTableAdlPDdr5Rvp +[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp] +gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable|*|{CODE({ + // CPU M.2 SSD1 + {GPIO_VER2_LP_GPP_F20, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD1 RE= SET + + // CPU M.2 SSD2 + {GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 PWR= EN + {GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, // CPU SSD2 RE= SET + + // X4 Pcie Slot for Gen3 and Gen 4 + {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}},//ONBOARD_X4_PC= IE_SLOT1_RESET_N + + // PCH M.2 SSD + {GPIO_VER2_LP_GPP_D16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_PCH_SSD_= PWREN + {GPIO_VER2_LP_GPP_H0, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_SSD_RST_= N + + // EC + {GPIO_VER2_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, = GpioOutDefault,GpioIntLevel|GpioIntSmi,GpioPlatformReset, GpioTermNone, = GpioPadConfigUnlock }}, //EC_SMI_N + {GPIO_VER2_LP_GPP_F9, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //EC_SLP_S0_C= S_N + + {0x0} // terminator +})} + + diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTa= bleAdlPPreMem.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd= /GpioTableAdlPPreMem.dsc new file mode 100644 index 0000000000..7bf8571c27 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableA +++ dlPPreMem.dsc @@ -0,0 +1,29 @@ +## @file +# Alderlake P RVP GPIO definition table for Pre-Memory Initialization=20 +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +### +### !!! GPIOs designated to Native Functions shall not be configured by Pl= atform Code. +### Native Pins shall be configured by Silicon Code (based on BIOS policie= s setting) or soft straps(set by CSME in FITc). +### +### + +# mGpioTablePreMemAdlPDdr5Rvp +[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp] +gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({ + // CPU M.2 SSD + { GPIO_VER2_LP_GPP_F20, { GpioPadModeGpio, GpioHostOwnAcpi,=20 +GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }=20 +}, //CPU SSD RESET + + // CPU M.2 SSD2 + {GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 PWR= EN + {GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, Gp= ioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 RES= ET + + // X4 Pcie Slot for Gen3 and Gen 4 + {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}},//ONBOARD_X4_PC= IE_SLOT1_RESET_N + + {0x0} // terminator +})} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqD= qsSPD/AdlPSpdMap.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructure= Pcd/MrcDqDqsSPD/AdlPSpdMap.dsc new file mode 100644 index 0000000000..096cc380cd --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSP +++ D/AdlPSpdMap.dsc @@ -0,0 +1,138 @@ +## @file +# ADL P SPD DATA configuration file. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# + +[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp] +gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData|*|{CODE( +{ +// DDR5 1Rx16 - 4800 MHz + 1, + {0x30, ///< 0 1024 SPD bytes total + 0x08, ///< 1 SPD Revision 0.8 + 0x12, ///< 2 DRAM Type: DDR5 SDRA= M + 0x03, ///< 3 Module Type: Not Hyb= rid (DRAM only) / SO-DIMM Solution + 0x04, ///< 4 Monolithic SDRAM, 16= Gb SDRAM density + 0x00, ///< 5 16 Rows, 10 Columns + 0x40, ///< 6 x16 SDRAM I/O Width + 0x42, ///< 7 4 Bank Groups, 4 Ban= ks per Bank Group + 0x00, ///< 8 Secondary SDRAM Dens= ity and Package + 0x00, ///< 9 Secondary SDRAM Addr= essing + 0x00, ///< 10 Secondary SDRAM I/O = Width + 0x00, ///< 11 Secondary BankGroups= and Banks per Bank Group + 0x60, ///< 12 PPR Supported, One r= ow per bank group, Soft PPR Supported + 0x00, ///< 13 Commercial Temperatu= re Grade, 0 to 85 C + 0x00, ///< 14 Reserved + 0x00, ///< 15 Reserved + 0x00, ///< 16 SDRAM Nominal Voltag= e VDD: 1.1V + 0x00, ///< 17 SDRAM Nominal Voltag= e VDDQ: 1.1V + 0x00, ///< 18 SDRAM Nominal Voltag= e VPP: 1.8V + 0x00, ///< 19 Reserved + 0xA1, ///< 20 tCKAVGmin LSB + 0x01, ///< 21 tCKAVGmin MSB + 0xE8, ///< 22 tCKAVGmax LSB + 0x03, ///< 23 tCKAVGmax MSB + 0x72, ///< 24 CAS Latencies suppor= ted (First Byte) : 32, 30, 28, 22 + 0x15, ///< 25 CAS Latencies suppor= ted (Second Byte): 44, 40, 36 + 0x00, ///< 26 CAS Latencies suppor= ted (Third Byte) : + 0x00, ///< 27 CAS Latencies suppor= ted (Fourth Byte): + 0x00, ///< 28 CAS Latencies suppor= ted (Fifth Byte) : + 0x00, ///< 29 Reserved + 0x1E, ///< 30 Minimum CAS Latency = (tAAmin) LSB + 0x41, ///< 31 Minimum CAS Latency = (tAAmin) MSB + 0x1E, ///< 32 Minimum RAS-to-CAS d= elay (tRCDmin) LSB + 0x41, ///< 33 Minimum RAS-to-CAS d= elay (tRCDmin) MSB + 0x1E, ///< 34 Minimum Row Precharg= e delay (tRPmin) LSB + 0x41, ///< 35 Minimum Row Precharg= e delay (tRPmin) MSB + 0x00, ///< 36 Minimum Active to Pr= echarge delay (tRASmin) LSB + 0x7D, ///< 37 Minimum Active to Pr= echarge delay (tRASmin) MSB + 0x1E, ///< 38 Minimum Active to Ac= tive/Refresh delay (tRCmin) LSB + 0xBE, ///< 39 Minimum Active to Ac= tive/Refresh delay (tRCmin) MSB + 0x30, ///< 40 Minimum Write Recove= ry time (tWRmin) LSB + 0x75, ///< 41 Minimum Write Recove= ry time (tWRmin) MSB + 0x27, ///< 42 Refresh Recovery Del= ay (tRFC1min) LSB + 0x01, ///< 43 Refresh Recovery Del= ay (tRFC1min) MSB + 0xA0, ///< 44 Refresh Recovery Del= ay (tRFC2min) MSB + 0x00, ///< 45 Refresh Recovery Del= ay (tRFC2min) MSB + 0x82, ///< 46 Refresh Recovery Del= ay (tRFCsbmin) MSB + 0x00, ///< 47 Refresh Recovery Del= ay (tRFCsbmin) MSB + 0, 0, ///< 48 - 49 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 + 0, 0, 0, 0, 0, 0, ///< 120 - 125 + 0x47, ///< 126 CRC Bytes 0 - 127 LS= B + 0xAE, ///< 127 CRC Bytes 0 - 127 MS= B + 0, 0, ///< 128 - 129 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 + 0, 0, ///< 190 - 191 + 0x08, ///< 192 SPD Revision for Mod= ule Information: 0.8 + 0x00, ///< 193 Reserved + 0xC2, ///< 194 SPD Manufacturer ID = First Byte + 0xC4, ///< 195 SPD Manufacturer ID = Second Byte + 0x80, ///< 196 SPD Device Type + 0x00, ///< 197 SPD Device Revision + 0x80, ///< 198 PMIC0 Manufacturer I= D First Byte + 0xB3, ///< 199 PMIC0 Manufacturer I= D Second Byte + 0x80, ///< 200 PMIC0 Device Type + 0x11, ///< 201 PMIC0 Device Revisio= n + 0, 0, 0, 0, ///< 202 - 205 PMIC1 + 0, 0, 0, 0, ///< 206 - 209 PMIC2 + 0x80, ///< 210 Thermal Sensors Manu= facturer ID First Byte + 0xB3, ///< 211 Thermal Sensors Manu= facturer ID First Byte + 0x80, ///< 212 Thermal Sensors Devi= ce Type + 0x11, ///< 213 Thermal Sensors Devi= ce Revision + 0, 0, 0, 0, 0, 0, ///< 214 - 219 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 + 0x0F, ///< 230 Module Nominal Heigh= t + 0x10, ///< 231 Module Nominal Thick= ness + 0x00, ///< 232 Reference Raw Card U= sed + 0x01, ///< 233 1 Row of DRAM on Mod= ule + 0x01, ///< 234 1 Rank, 8 bits SDRAM= data width per channel + 0x22, ///< 235 2 Channels per DIMM,= 32 bits per Channel + 0, 0, 0, 0, ///< 236 - 239 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 320 - 329 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 330 - 339 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 340 - 349 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 350 - 359 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ///< 440 - 445 + 0x9C, ///< 446 CRC for Bytes 128 - = 253 LSB + 0xAD, ///< 447 CRC for Bytes 128 - = 253 MSB + 0, 0, ///< 448 - 449 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509 + 0, 0 ///< 510 - 511 + ///< Ignore bytes 512-1023, @todo_adl: support 1024 bytes SPD=20 +array }})} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieCl= ocks/AdlPPcieClocks.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStruct= urePcd/PcieClocks/AdlPPcieClocks.dsc new file mode 100644 index 0000000000..57106e92c4 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks +++ /AdlPPcieClocks.dsc @@ -0,0 +1,31 @@ +## @file +# Alderlake P Pcie Clock configuration file. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp] +gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE( +{{ + PCIE_PEG, // CPU M.2 SSD 1 + PCIE_PCH + 8, // PCH M.2 SSD + PCIE_PCH + 4, + PCIE_PEG + 1, // X8 DG/DG2 + PCIE_PEG + 2, // CPU M.2 SSD 2 + PCIE_PCH + 5, // M.2 KEY B WWAN - PCIe P6 + LAN_CLOCK, + // Default Case: + // - PCIe P7 mapped to GBELAN + // - PCIe P8 mapped to x4 PCIe DT Slot (Pair 1) + PCIE_PCH + 7, // x4 PCIe DT Slot (x1) + // Reworked Case: with rework and soft strap changes + // - PCIe P7 mapped to x4 PCIe DT Slot (Pair 2) + // - PCIe P8 mapped to x4 PCIe DT Slot (Pair 1) + // PCIE_PCH + 6, // x4 PCIe DT Slot (x2) + NOT_USED, + NOT_USED +}} +)} -- 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#107580): https://edk2.groups.io/g/devel/message/107580 Mute This Topic: https://groups.io/mt/100494310/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-