From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 528A3AC09D5 for ; Wed, 16 Aug 2023 02:45:50 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=hHXRtZ/LWAskv3czB5slVmITC64V+7q+bHejJKBl9cA=; c=relaxed/simple; d=groups.io; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:From:To:CC:Subject:Thread-Topic:Thread-Index:Date:Message-ID:References:In-Reply-To:Accept-Language:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1692153949; v=1; b=ebNAx1acPRjI/WZx0aMc4Gg2M89p/rEhsESrUdOb5t5/yBXy+FDaubv0nYbhVR9o872hGyKC wvosbpsFgnRJS+7Vj0YJl/qP1YFpe+CRxO2aVZ3YcuQ4K+ZPzyxoCimZ2lJ8982VmcWhRIasDF5 sjTxkmFzu3U4RByY5cJ/4N1s= X-Received: by 127.0.0.2 with SMTP id vhMfYY7687511xaVcOVN75rB; Tue, 15 Aug 2023 19:45:49 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.152789.1692153948407379657 for ; Tue, 15 Aug 2023 19:45:48 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="438770142" X-IronPort-AV: E=Sophos;i="6.01,175,1684825200"; d="scan'208";a="438770142" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Aug 2023 19:45:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10803"; a="907839669" X-IronPort-AV: E=Sophos;i="6.01,175,1684825200"; d="scan'208";a="907839669" X-Received: from fmsmsx601.amr.corp.intel.com ([10.18.126.81]) by orsmga005.jf.intel.com with ESMTP; 15 Aug 2023 19:45:47 -0700 X-Received: from fmsmsx612.amr.corp.intel.com (10.18.126.92) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 15 Aug 2023 19:45:47 -0700 X-Received: from fmsmsx610.amr.corp.intel.com (10.18.126.90) by fmsmsx612.amr.corp.intel.com (10.18.126.92) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 15 Aug 2023 19:45:47 -0700 X-Received: from fmsedg601.ED.cps.intel.com (10.1.192.135) by fmsmsx610.amr.corp.intel.com (10.18.126.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27 via Frontend Transport; Tue, 15 Aug 2023 19:45:47 -0700 X-Received: from NAM12-MW2-obe.outbound.protection.outlook.com (104.47.66.44) by edgegateway.intel.com (192.55.55.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.27; Tue, 15 Aug 2023 19:45:47 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=G1OAos6IBay25YTD+5i693MfzpYK6AYwZ8ePNwUdJIe8KpNM3R3AkXrpCFDI2NC5Eo3/J30oYNAzXJi/TKWNuHGHpk19E/FjDydMVVVvZ+wfdD05foh/Z/c/4IPxuE866EZ7AGKaVrnl86W7qwdK1SpnSogbcn+9ICGg4UtTirdqZnPfRM7zJ/fWEci1r6+yYx+S3LULV/5osH1JFufjAFhexRxHBJfD0gowdl9rmfamRY11gA+Yh3/tQ4cvIuRdLNpgX4qJ7KCDmcT0u0W8YtrR/7RHMSpiYDvRQG9+EEOKkT1W+zhEx1x5tYJUT/f/Fq8mPoymV6wJBfzeu6tXLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Xz7XunwthdNzeImcteVLv/Mth4Q6+28HZr+VCIN1h5g=; b=nhGFEpBBCo8ocVTNxV+CiIXSjaShRRakC7doku/ll5A3ZnXodpRF79emYBopIFOsNK6Y0spGsFPjSL9dezePYw7V5uOsApOHo0OfhT9Ld70E4J4GXVNEFbUZd8UDSuHX10tNG4JO7SBJdM8OLXr/7f7CRI6rWDkHbc0+An9zYSpyyBFlr9yvrA5FK9bj5fpj0vuZDI2D8i7l6slQLjsXldYSWGfoHwMEq6t+CxnB1iMAP2WsLdNc6ZzppBHhJWZ77OxirOaEMEB1o/6VZRspFGwCbbJogJwEYJLnNomLr8HQ+RQPSu3u4Fx79sPgs1vK9fIr55vqAZiEdGtH2yBBIQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none X-Received: from PH0PR11MB5626.namprd11.prod.outlook.com (2603:10b6:510:ee::15) by SA1PR11MB8447.namprd11.prod.outlook.com (2603:10b6:806:3ac::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6678.26; Wed, 16 Aug 2023 02:45:44 +0000 X-Received: from PH0PR11MB5626.namprd11.prod.outlook.com ([fe80::68a8:9cc5:ec4d:ca44]) by PH0PR11MB5626.namprd11.prod.outlook.com ([fe80::68a8:9cc5:ec4d:ca44%7]) with mapi id 15.20.6678.025; Wed, 16 Aug 2023 02:45:44 +0000 From: "Chuang, Rosen" To: "Kasbekar, Saloni" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Desimone, Nathaniel L" , "Oram, Isaac W" Subject: Re: [edk2-devel] [PATCH v2 7/7] AlderlakeSiliconPkg/SystemAgent: Add library and driver modules Thread-Topic: [PATCH v2 7/7] AlderlakeSiliconPkg/SystemAgent: Add library and driver modules Thread-Index: AQHZxvpqTCq/vBdTN0CwC89w1vr87a/sSXzA Date: Wed, 16 Aug 2023 02:45:44 +0000 Message-ID: References: <620a6c3d1e80809cbdfc35000efbbe54294661b0.1691170619.git.saloni.kasbekar@intel.com> In-Reply-To: <620a6c3d1e80809cbdfc35000efbbe54294661b0.1691170619.git.saloni.kasbekar@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PH0PR11MB5626:EE_|SA1PR11MB8447:EE_ x-ms-office365-filtering-correlation-id: 2ba3a4b8-8c4d-4874-488c-08db9e02e38c x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam-message-info: VCJjLPQlo9JSNvYzXkUBLXcMf1QwNhwT1c2FbTVjyG35QVFoPYgNaB8QFPzrH8PLeIX5cQniso0vCm2/V51XDi6AOz5OWC6YfQ42m87KqWA2/UexSYdrNpZ+waqN89fRIPU8gdImkJu70e7E8UNsaUw/rPxtd3BqggtcQNpCTSDDSqxzjWfrVTXxcRDiLQt2oe6xX8ANG/e5R+69eGMCxADRSr02blaY8ggSJ1Daw6svTi5yxmniaYStJlT7itJBHEeq9hkyCnXhdAf5EqM0eqZ+09V6ol1ZV/unasjexqrnGprQ7k+Yis4gIvZrDXJLIRZhyOtW6/BqrkXn/6hJXmExWXRXvjfwO+YyV+AIzejxJ6jOi8MldsrpRihRZFffT/y0teh0l8KX4ybIzwoiBfy/mWPCEWKyNXo1E/+jDS2voh2cjWQwKWhV1ygxIJHHwDM0Rje9BoKYxCh/2hL8aV0AA10KK+37P23/2peez6nzcSE45IjYL3Hs7my6xhyClT/YwtLClInvJRV0/LOknlj0YBbcv5BQ5Ny2xyYO0Su/6UphjtQMz/aAR2S0dfCsdwiknq7iwLDzgfVaa5qgRapupNg2HD+Aj6E6LjBl7BPv3sr8/gWnm7hQMnwIDZ/nxVtAyg9ICv9dgeKftWaPiiGBQYbxYbZYLAebvMpboPy9Ob7Ly65XCanAvuS1YufbjNADa74GkAdHf4MSgNf0k9U98FJF2vERECPEGNDq58A= x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?FNIyA6BnpfOVPB/TPjuyJtMVnqmeGTF3f77PC/zdirLIFuqPSSJnXaKCjo6d?= =?us-ascii?Q?BKQTtLsxCWjfd6c+M8FHiroUIYF76eQLCvtERozkeIdWHOZs0hW8+NdKjKjf?= =?us-ascii?Q?Ngr050DUliCnDd7AR1MqUPvPk63JBzcR8+zCyJ1Y91Moo0vNVQmO/kd+poJk?= =?us-ascii?Q?IeKB4Bk1QWE3BMR3TAYsZIKvSvMR0W7HaQ1H0dJo5hUwRvHyMuIAIov4RF5Y?= =?us-ascii?Q?F/sRZhuXVvmcFLF33SfnyPGM8174cKha1mUs3JTFPDwOQrluFgiPpueClZxU?= =?us-ascii?Q?KeSJKQGh/6bCbsjUptp0pCZNikJes2E37t3jZLqKZ4mrsETbfDYrcoa2Deyl?= =?us-ascii?Q?gsdGGVvZpQ+9aW+cpA70Ae3jgo94xTnalSealdN2zG8vrQYoo2S26ATGyU8L?= =?us-ascii?Q?DPGryDTm2nJIhDGQPVDF21aWSDdXVrvvoYHdb+xvjH8Wy7N3L2l9s7jq2AQ4?= =?us-ascii?Q?ovwLZT4Ca3B0n5KXi2xmgw8FehgJw48OTmv6IHTnVVNz+MUUlagL6SRovDGy?= =?us-ascii?Q?X/sJvIA1CsbUGYIzqaR2MeihrmJZcqgmbt0qDrk/kIx9NREAVDDR6qeG1rrq?= =?us-ascii?Q?Sd6LSnNi5riHQLnP7rDWXMM46CIwMqgRQwk+Ed+UKBgM/uINIWnt1OohqEtU?= =?us-ascii?Q?xcr41jRL7b6ULGYIy6QutYNMrERVSg5eGolefuvwHkI9FiCK5Quh/O9fCzI1?= =?us-ascii?Q?oX8yzF0oaSBW6+BPA/3iI7qeCZZ0/POTz19l6urh+nDDu+TWRES3ShiFxkAL?= =?us-ascii?Q?veW8xUauuf1uNVXxDImp/N0aHhImvvIGNWXUufqM9FEI6o8W903dMH/1p0lY?= =?us-ascii?Q?q/fxiJ91BtGxjyw1nlN97cEGgrQZJznauv6ehzCK3LLu2vq13/27M4LxOGRL?= =?us-ascii?Q?m4aXRKjTLRhvCKKRtAmaLIEWDLQlwZLI+Jfwj85Y6REXfYRfUcR+zEcoShr5?= =?us-ascii?Q?xWXaIyuKDT8hUnb5jveEkASVdyA5CrKULzZE/dct5iWVTRgYkpOoIIBT6ifw?= =?us-ascii?Q?az5vERPnAGOuT0lfQAEaTaGzWnRg+fPI38Kn7w+1cBluhsP2QsyteawX24k3?= =?us-ascii?Q?TLGFG7/IzYDOUyL1CNS90xgo9nX965HTeUJqG30MAxNoaEOBzmJNMVJl+20n?= =?us-ascii?Q?YC/nZQaiJSXdLSuXXMwKS/hJQYoKGqGf0aTojVDeFMIIyRMgd8zo7d1Lm7Hy?= =?us-ascii?Q?DVGABnGLW2GF0UwiffLVWPK49FyAOFaAtHOGWHxHSymNnzmCUDAlMhSjRPqB?= =?us-ascii?Q?fCIgWJlZgT+SguNNTYABkmOQ+aLZvI1dTUeBwJfZ8dgSp7stR9IaEwxsch5e?= =?us-ascii?Q?N0j12k0q4G+RzNAU/tHqIz0FFXtahfFnUKT0RPZt4YkIE9mYCqrqdChj4Mr0?= =?us-ascii?Q?4vu9RLEeRc8EtTyXpKQxcFcTNCwVSngGY6tmjv65eT3LYGSQMAF/3s9S5Prc?= =?us-ascii?Q?mAwmTcRUdaeuMxW3Ln1hVp71IvtwjSVtYgdwWeva++VubqDvi0/nwSKsmtpF?= =?us-ascii?Q?v5GcSHCC9LZnKGZHa83uDbuxmScJolIbdundMzHZcEIgumjUcv/a6rHnL3rt?= =?us-ascii?Q?dXCy/mhcO1cyNJbnWjqLzuGIBGwLyRmKuRrAj/Oh?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB5626.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2ba3a4b8-8c4d-4874-488c-08db9e02e38c X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Aug 2023 02:45:44.7237 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: QQvsfkGWQuKiLowPFjtdg8yGQrYj8cgBnqxpTpyqx6ax4SpBT9txxfuwkIXmGufQ78fARfuTKviiaAqOL1q+eQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR11MB8447 X-OriginatorOrg: intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rosen.chuang@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 7x0SV5nFVLFTYlLWBSVdVRrbx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=ebNAx1ac; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Reviewed-by: Rosen Chuang < rosen.chuang@intel.com> -----Original Message----- From: Kasbekar, Saloni =20 Sent: Saturday, August 5, 2023 1:38 AM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Oram, Isaac W ; Chuang, Rosen Subject: [PATCH v2 7/7] AlderlakeSiliconPkg/SystemAgent: Add library and dr= iver modules Adds the following modules: - Library/DxeSaPolicyLib - SaInit Cc: Sai Chaganty Cc: Nate DeSimone Cc: Isaac Oram Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../Library/DxeSaPolicyLib/DxeSaPolicyLib.c | 225 ++++++++++++++++++ .../Library/DxeSaPolicyLib/DxeSaPolicyLib.inf | 46 ++++ .../DxeSaPolicyLib/DxeSaPolicyLibrary.h | 30 +++ .../SystemAgent/SaInit/Dxe/SaInit.c | 97 ++++++++ .../SystemAgent/SaInit/Dxe/SaInit.h | 42 ++++ .../SystemAgent/SaInit/Dxe/SaInitDxe.c | 87 +++++++ .../SystemAgent/SaInit/Dxe/SaInitDxe.h | 97 ++++++++ .../SystemAgent/SaInit/Dxe/SaInitDxe.inf | 90 +++++++ 8 files changed, 714 insertions(+) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/D= xeSaPolicyLib/DxeSaPolicyLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/D= xeSaPolicyLib/DxeSaPolicyLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/D= xeSaPolicyLib/DxeSaPolicyLibrary.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dx= e/SaInit.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dx= e/SaInit.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dx= e/SaInitDxe.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dx= e/SaInitDxe.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dx= e/SaInitDxe.inf diff --git a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPol= icyLib/DxeSaPolicyLib.c b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Lib= rary/DxeSaPolicyLib/DxeSaPolicyLib.c new file mode 100644 index 0000000000..d812f300c1 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyL +++ ib/DxeSaPolicyLib.c @@ -0,0 +1,225 @@ +/** @file + This file provide services for DXE phase policy default=20 +initialization + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#include "DxeSaPolicyLibrary.h" +#include #include=20 + #include "MemoryConfig.h" + +extern EFI_GUID gMemoryDxeConfigGuid; + +/** + This function prints the SA DXE phase policy. + + @param[in] SaPolicy - SA DXE Policy protocol **/ VOID=20 +SaPrintPolicyProtocol ( + IN SA_POLICY_PROTOCOL *SaPolicy + ) +{ + UINT8 ControllerIndex; + UINT8 ChannelIndex; + EFI_STATUS Status; + MEMORY_DXE_CONFIG *MemoryDxeConfig; + + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gMemoryDxeConfigGuid,=20 + (VOID *)&MemoryDxeConfig); ASSERT_EFI_ERROR (Status); + + + DEBUG_CODE_BEGIN (); + INTN i; + + DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print=20 + BEGIN -----------------\n")); DEBUG ((DEBUG_INFO, "Revision : %x\n",=20 + SaPolicy->TableHeader.Header.Revision)); + ASSERT (SaPolicy->TableHeader.Header.Revision =3D=3D=20 + SA_POLICY_PROTOCOL_REVISION); + + DEBUG ((DEBUG_INFO, "------------------------ SA_MEMORY_CONFIGURATION=20 + -----------------\n")); + + DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :", 4)); for (i =3D 0; i <=20 + 4; i++) { + DEBUG ((DEBUG_INFO, " %x", MemoryDxeConfig->SpdAddressTable[i])); + } + DEBUG ((DEBUG_INFO, "\n")); + + for (ControllerIndex =3D 0; ControllerIndex < MEM_CFG_MAX_CONTROLLERS; C= ontrollerIndex++) { + for (ChannelIndex =3D 0; ChannelIndex < MEM_CFG_MAX_CHANNELS; ChannelI= ndex++) { + DEBUG ((DEBUG_INFO, " SlotMap[%d][%d] : 0x%x\n", ControllerIndex, Ch= annelIndex, MemoryDxeConfig->SlotMap[ControllerIndex][ChannelIndex])); + } + } + DEBUG ((DEBUG_INFO, " MrcTimeMeasure : %x\n", MemoryDxeConfig->MrcTimeM= easure)); + DEBUG ((DEBUG_INFO, " MrcFastBoot : %x\n", MemoryDxeConfig->MrcFastB= oot)); + + DEBUG ((DEBUG_INFO, "------------------------ CPU_PCIE_CONFIGURATION=20 + -----------------\n")); DEBUG ((DEBUG_INFO, " PegAspm[%d] :",=20 + SA_PEG_MAX_FUN)); DEBUG ((DEBUG_INFO, " PegRootPortHPE[%d] :",=20 + SA_PEG_MAX_FUN)); DEBUG ((DEBUG_INFO, "\n")); + + + DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print=20 + END -----------------\n")); DEBUG_CODE_END (); + + return; +} + +/** + Load DXE Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadMemoryDxeDefault ( + IN VOID *ConfigBlockPointer + ) +{ + UINT8 ControllerIndex; + UINT8 ChannelIndex; + MEMORY_DXE_CONFIG *MemoryDxeConfig; + + MemoryDxeConfig =3D ConfigBlockPointer; + /// + /// Initialize the Memory Configuration + /// + /// + /// DIMM SMBus addresses info + /// Refer to the SpdAddressTable[] mapping rule in=20 +DxeSaPolicyLibrary.h + /// + MemoryDxeConfig->SpdAddressTable =3D AllocateZeroPool (sizeof (UINT8) *= =20 +4); + ASSERT (MemoryDxeConfig->SpdAddressTable !=3D NULL); + if (MemoryDxeConfig->SpdAddressTable !=3D NULL) { + MemoryDxeConfig->SpdAddressTable[0] =3D DIMM_SMB_SPD_P0C0D0; + MemoryDxeConfig->SpdAddressTable[1] =3D DIMM_SMB_SPD_P0C0D1; + MemoryDxeConfig->SpdAddressTable[2] =3D DIMM_SMB_SPD_P0C1D0; + MemoryDxeConfig->SpdAddressTable[3] =3D DIMM_SMB_SPD_P0C1D1; + } + MemoryDxeConfig->SlotMap =3D (UINT8**)AllocateZeroPool (sizeof (UINT8*)= =20 +* MEM_CFG_MAX_CONTROLLERS); + ASSERT (MemoryDxeConfig->SlotMap !=3D NULL); + if (MemoryDxeConfig->SlotMap !=3D NULL) { + for (ControllerIndex =3D 0; ControllerIndex < MEM_CFG_MAX_CONTROLLERS;= ControllerIndex++) { + MemoryDxeConfig->SlotMap[ControllerIndex] =3D (UINT8*)AllocateZeroPo= ol (sizeof (UINT8) * MEM_CFG_MAX_CHANNELS); + ASSERT (MemoryDxeConfig->SlotMap[ControllerIndex] !=3D NULL); + if (MemoryDxeConfig->SlotMap[ControllerIndex] !=3D NULL) { + for (ChannelIndex =3D 0; ChannelIndex < MEM_CFG_MAX_CHANNELS; Chan= nelIndex++) { + MemoryDxeConfig->SlotMap[ControllerIndex][ChannelIndex] =3D 0x01= ; + } + } + } + } +} + +/** + LoadSaDxeConfigBlockDefault - Initialize default settings for each SA=20 +Config block + + @param[in] ConfigBlockPointer The buffer pointer that will be in= itialized as specific config block + @param[in] BlockId Request to initialize defaults of = specified config block by given Block ID + + @retval EFI_SUCCESS The given buffer has contained the= defaults of requested config block + @retval EFI_NOT_FOUND Block ID is not defined so no defa= ult Config block will be initialized +**/ + +GLOBAL_REMOVE_IF_UNREFERENCED COMPONENT_BLOCK_ENTRY mSaDxeIpBlocks [] =3D= { + {&gMemoryDxeConfigGuid, sizeof (MEMORY_DXE_CONFIG), MEMORY_DXE_CONFI= G_REVISION, LoadMemoryDxeDefault} +}; + + +/** + CreateSaDxeConfigBlocks generates the config blocksg of SA DXE Policy. + It allocates and zero out buffer, and fills in the Intel default setting= s. + + @param[out] SaPolicy The pointer to get SA DXE Protocol i= nstance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +CreateSaDxeConfigBlocks ( + IN OUT SA_POLICY_PROTOCOL **SaPolicy + ) +{ + UINT16 TotalBlockSize; + EFI_STATUS Status; + SA_POLICY_PROTOCOL *SaInitPolicy; + UINT16 RequiredSize; + + DEBUG ((DEBUG_INFO, "SA Create Dxe Config Blocks\n")); + + SaInitPolicy =3D NULL; + + TotalBlockSize =3D GetComponentConfigBlockTotalSize=20 + (&mSaDxeIpBlocks[0], sizeof (mSaDxeIpBlocks) / sizeof=20 + (COMPONENT_BLOCK_ENTRY)); TotalBlockSize +=3D=20 + GraphicsGetConfigBlockTotalSizeDxe (); DEBUG ((DEBUG_INFO,=20 + "TotalBlockSize =3D 0x%x\n", TotalBlockSize)); + + RequiredSize =3D sizeof (CONFIG_BLOCK_TABLE_HEADER) + TotalBlockSize; + + Status =3D CreateConfigBlockTable (RequiredSize, (VOID *)=20 + &SaInitPolicy); ASSERT_EFI_ERROR (Status); + + // + // Initialize Policy Revision + // + SaInitPolicy->TableHeader.Header.Revision =3D=20 + SA_POLICY_PROTOCOL_REVISION; // // Add config blocks. + // + Status =3D AddComponentConfigBlocks ((VOID *) SaInitPolicy,=20 + &mSaDxeIpBlocks[0], sizeof (mSaDxeIpBlocks) / sizeof=20 + (COMPONENT_BLOCK_ENTRY)); ASSERT_EFI_ERROR (Status); + + + // Gfx + Status =3D GraphicsAddConfigBlocksDxe ((VOID *) SaInitPolicy); =20 + ASSERT_EFI_ERROR (Status); + + // + // Assignment for returning SaInitPolicy config block base address + // + *SaPolicy =3D SaInitPolicy; + return Status; +} + + +/** + SaInstallPolicyProtocol installs SA Policy. + While installed, RC assumes the Policy is ready and finalized. So=20 +please update and override + any setting before calling this function. + + @param[in] ImageHandle Image handle of this driver. + @param[in] SaPolicy The pointer to SA Policy Protocol = instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +SaInstallPolicyProtocol ( + IN EFI_HANDLE ImageHandle, + IN SA_POLICY_PROTOCOL *SaPolicy + ) +{ + EFI_STATUS Status; + + /// + /// Print SA DXE Policy + /// + SaPrintPolicyProtocol (SaPolicy); + GraphicsDxePolicyPrint (SaPolicy); + + /// + /// Install protocol to to allow access to this Policy. + /// + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gSaPolicyProtocolGuid, + SaPolicy, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPol= icyLib/DxeSaPolicyLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/L= ibrary/DxeSaPolicyLib/DxeSaPolicyLib.inf new file mode 100644 index 0000000000..b7e867de59 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyL +++ ib/DxeSaPolicyLib.inf @@ -0,0 +1,46 @@ +## @file +# Component description file for the PeiSaPolicy library. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D DxeSaPolicyLib +FILE_GUID =3D B402A3A4-4B82-410E-B79C-5914880A05E7 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D DXE_DRIVER +LIBRARY_CLASS =3D DxeSaPolicyLib + + +[LibraryClasses] +BaseMemoryLib +UefiRuntimeServicesTableLib +UefiBootServicesTableLib +DebugLib +PostCodeLib +ConfigBlockLib +HobLib +DxeGraphicsPolicyLib +CpuPlatformLib + +[Packages] +MdePkg/MdePkg.dec +AlderlakeSiliconPkg/SiPkg.dec + + +[Sources] +DxeSaPolicyLib.c +DxeSaPolicyLibrary.h + + +[Guids] +gMemoryDxeConfigGuid + + +[Protocols] +gSaPolicyProtocolGuid ## PRODUCES + +[Pcd] diff --git a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPol= icyLib/DxeSaPolicyLibrary.h b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent= /Library/DxeSaPolicyLib/DxeSaPolicyLibrary.h new file mode 100644 index 0000000000..14fc02512e --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyL +++ ib/DxeSaPolicyLibrary.h @@ -0,0 +1,30 @@ +/** @file + Header file for the DxeSaPolicy library. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef=20 +_DXE_SA_POLICY_LIBRARY_H_ #define _DXE_SA_POLICY_LIBRARY_H_ + +#include +#include +#include +#include +#include +#include #include=20 + #include #include=20 + #include + +#define WORD_FIELD_VALID_BIT BIT15 +/// +/// DIMM SMBus addresses +/// +#define DIMM_SMB_SPD_P0C0D0 0xA0 +#define DIMM_SMB_SPD_P0C0D1 0xA2 +#define DIMM_SMB_SPD_P0C1D0 0xA4 +#define DIMM_SMB_SPD_P0C1D1 0xA6 + +#endif // _DXE_SA_POLICY_LIBRARY_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaIni= t.c b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.c new file mode 100644 index 0000000000..5e472b0f60 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.c @@ -0,0 +1,97 @@ +/** @file + This is the Common driver that initializes the Intel System Agent. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include "SaInit.h" +#include +#include +#include +#include +#include + +/// +/// Global Variables +/// +BOOLEAN mSkip= PamLock =3D FALSE; + +/* + Intel(R) Core Processor Skylake BWG version 0.4.0 + + 18.6 System Agent Configuration Locking + For reliable operation and security, System BIOS must set the following= bits: + 1. For all modern Intel processors, Intel strongly recommends that BIOS= should set + the D_LCK bit. Set B0:D0:F0.R088h [4] =3D 1b to lock down SMRAM spa= ce. + BaseAddr values for mSaSecurityRegisters that uses=20 +PciExpressBaseAddress will be initialized at + Runtime inside function CpuPcieInitPolicy(). +*/ +GLOBAL_REMOVE_IF_UNREFERENCED BOOT_SCRIPT_REGISTER_SETTING=20 +mSaSecurityRegisters[] =3D { + {0, R_SA_SMRAMC, 0xFFFFFFFF, BIT4} }; + +/** + SystemAgent Initialization Common Function. + + @retval EFI_SUCCESS - Always. +**/ + +VOID +SaInitEntryPoint ( + VOID + ) +{ + HOST_BRIDGE_DATA_HOB *HostBridgeDataHob; + + /// + /// Get Host Bridge Data HOB + /// + HostBridgeDataHob =3D NULL; + HostBridgeDataHob =3D (HOST_BRIDGE_DATA_HOB *) GetFirstGuidHob=20 +(&gHostBridgeDataHobGuid); + if (HostBridgeDataHob !=3D NULL) { + mSkipPamLock =3D HostBridgeDataHob->SkipPamLock; + } + return; +} + +/** + This function does SA security lock +**/ +VOID +SaSecurityLock ( + VOID + ) +{ + UINT8 Index; + UINT64 BaseAddress; + UINT32 RegOffset; + UINT32 Data32And; + UINT32 Data32Or; + + /// + /// 17.2 System Agent Security Lock configuration /// DEBUG=20 + ((DEBUG_INFO, "DXE SaSecurityLock\n")); for (Index =3D 0; Index <=20 + (sizeof (mSaSecurityRegisters) / sizeof (BOOT_SCRIPT_REGISTER_SETTING)); = Index++) { + BaseAddress =3D mSaSecurityRegisters[Index].BaseAddr; + RegOffset =3D mSaSecurityRegisters[Index].Offset; + Data32And =3D mSaSecurityRegisters[Index].AndMask; + Data32Or =3D mSaSecurityRegisters[Index].OrMask; + + if (RegOffset =3D=3D R_SA_SMRAMC) { + /// + /// SMRAMC LOCK must use CF8/CFC access + /// + PciCf8Or8 (PCI_CF8_LIB_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_S= A_SMRAMC), (UINT8) Data32Or); + BaseAddress =3D S3_BOOT_SCRIPT_LIB_PCI_ADDRESS (SA_MC_BUS, SA_MC_DEV= , SA_MC_FUN, R_SA_SMRAMC); + S3BootScriptSavePciCfgReadWrite ( + S3BootScriptWidthUint8, + (UINTN) BaseAddress, + &Data32Or, + &Data32And + ); + } + } + +} + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaIni= t.h b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.h new file mode 100644 index 0000000000..14e48a3eb4 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.h @@ -0,0 +1,42 @@ +/** @file + Header file for SA Common Initialization Driver. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef=20 +_SA_INITIALIZATION_DRIVER_H_ #define _SA_INITIALIZATION_DRIVER_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include=20 + #include #include=20 + #include #include=20 + + +typedef struct { + UINT64 BaseAddr; + UINT32 Offset; + UINT32 AndMask; + UINT32 OrMask; +} BOOT_SCRIPT_REGISTER_SETTING; + +/** + SystemAgent Initialization Common Function. + + @retval EFI_SUCCESS - Always. +**/ +VOID +SaInitEntryPoint ( + VOID + ); +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaIni= tDxe.c b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe= .c new file mode 100644 index 0000000000..b30d8667c9 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe +++ .c @@ -0,0 +1,87 @@ +/** @file + This is the driver that initializes the Intel System Agent. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include=20 +"SaInitDxe.h" +#include "SaInit.h" +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPcieIoTrapAddress; + +/** + SystemAgent Dxe Initialization. + + @param[in] ImageHandle Handle for the image of this driver + @param[in] SystemTable Pointer to the EFI System Table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_OUT_OF_RESOURCES No enough buffer to allocate +**/ +EFI_STATUS +EFIAPI +SaInitEntryPointDxe ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + VOID *Registration; +#if FixedPcdGetBool(PcdFspWrapperEnable) =3D=3D 0 + EFI_EVENT Event; +#endif + + DEBUG ((DEBUG_INFO, "SaInitDxe Start\n")); + + SaInitEntryPoint (); + + /// + /// Create PCI Enumeration Completed callback for CPU PCIe /// =20 + EfiCreateProtocolNotifyEvent ( + &gEfiPciEnumerationCompleteProtocolGuid, + TPL_CALLBACK, + CpuPciEnumCompleteCallback, + NULL, + &Registration + ); + + DEBUG ((DEBUG_INFO, "SaInitDxe End\n")); + + return EFI_SUCCESS; +} + +/** + This function gets registered as a callback to perform CPU PCIe=20 +initialization before EndOfDxe + + @param[in] Event - A pointer to the Event that triggered the callbac= k. + @param[in] Context - A pointer to private data registered with the cal= lback function. +**/ +VOID +EFIAPI +CpuPciEnumCompleteCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + VOID *ProtocolPointer; + + DEBUG ((DEBUG_INFO, "CpuPciEnumCompleteCallback Start\n")); /// ///=20 + Check if this is first time called by EfiCreateProtocolNotifyEvent()=20 + or not, /// if it is, we will skip it until real event is triggered =20 + /// Status =3D gBS->LocateProtocol=20 + (&gEfiPciEnumerationCompleteProtocolGuid, NULL, (VOID **)=20 + &ProtocolPointer); if (EFI_SUCCESS !=3D Status) { + return; + } + + gBS->CloseEvent (Event); + + DEBUG ((DEBUG_INFO, "CpuPciEnumCompleteCallback End\n")); + return; +} diff --git a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaIni= tDxe.h b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe= .h new file mode 100644 index 0000000000..10d98d43a7 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe +++ .h @@ -0,0 +1,97 @@ +/** @file + Header file for SA Initialization Driver. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef=20 +_SA_INIT_DXE_DRIVER_H_ #define _SA_INIT_DXE_DRIVER_H_ + +#include +#include +#include #include=20 + #include + +/// +/// Driver Consumed Protocol Prototypes /// #include=20 + + +typedef struct { + UINT64 Address; + EFI_BOOT_SCRIPT_WIDTH Width; + UINT32 Value; +} BOOT_SCRIPT_PCI_REGISTER_SAVE; + +/// +/// Function Prototype +/// +/** + This function gets registered as a callback to perform CPU PCIe=20 +initialization before ExitPmAuth + + @param[in] Event - A pointer to the Event that triggered the callbac= k. + @param[in] Context - A pointer to private data registered with the cal= lback function. + +**/ +VOID +EFIAPI +CpuPciEnumCompleteCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +/** + System Agent Initialization DXE Driver Entry Point + - Introduction \n + Based on the information/data in SA_POLICY_PROTOCOL, this module perfo= rms further SA initialization in DXE phase, + e.g. internal devices enable/disable, SSVID/SID programming, graphic p= ower-management, VT-d, IGD OpRegion initialization. + From the perspective of a PCI Express hierarchy, the Broadwell System = Agent and PCH together appear as a Root Complex with root ports the number = of which depends on how the 8 PCH ports and 4 System Agent PCIe ports are c= onfigured [4x1, 2x8, 1x16]. + There is an internal link (DMI or OPI) that connects the System Agent = to the PCH component. This driver includes initialization of SA DMI, PCI Ex= press, SA & PCH Root Complex Topology. + For iGFX, this module implements the initialization of the Graphics Te= chnology Power Management from the Broadwell System Agent BIOS Specificatio= n and the initialization of the IGD OpRegion/Software SCI - BIOS Specificat= ion. + The ASL files that go along with the driver define the IGD OpRegion ma= ilboxes in ACPI space and implement the software SCI interrupt mechanism. + The IGD OpRegion/Software SCI code serves as a communication interface= between system BIOS, ASL, and Intel graphics driver including making a blo= ck of customizable data (VBT) from the Intel video BIOS available. + Reference Code for the SCI service functions "Get BIOS Data" and "Syst= em BIOS Callback" can be found in the ASL files, those functions can be pla= tform specific, the sample provided in the reference code are implemented f= or Intel CRB. + This module implements the VT-d functionality described in the Broadwe= ll System Agent BIOS Specification. + This module publishes the LegacyRegion protocol to control the read an= d write accesses to the Legacy BIOS ranges. + E000 and F000 segments are the legacy BIOS ranges and contain pointers= to the ACPI regions, SMBIOS tables and so on. This is a private protocol u= sed by Intel Framework. + This module registers CallBack function that performs SA security regi= sters lockdown at end of post as required from Broadwell Bios Spec. + In addition, this module publishes the SaInfo Protocol with informatio= n such as current System Agent reference code version#. + + - @pre + - EFI_FIRMWARE_VOLUME_PROTOCOL: Documented in Firmware Volume Specific= ation, available at the URL: http://www.intel.com/technology/framework/spec= .htm + - SA_POLICY_PROTOCOL: A protocol published by a platform DXE module ex= ecuted earlier; this is documented in this document as well. + - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL: Documented in the Unified Extensibl= e Firmware Interface Specification, version 2.0, available at the URL: http= ://www.uefi.org/specs/ + - EFI_BOOT_SCRIPT_SAVE_PROTOCOL: A protocol published by a platform DX= E module executed earlier; refer to the Sample Code section of the Framewor= k PCH Reference Code. + - EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL: Documented in the = Unified Extensible Firmware Interface Specification, version 2.0, available= at the URL: http://www.uefi.org/specs/ + - EFI_ACPI_TABLE_PROTOCOL : Documented in PI Specification 1.2 + - EFI_CPU_IO_PROTOCOL: Documented in CPU I/O Protocol Specification, a= vailable at the URL: http://www.intel.com/technology/framework/spec.htm + - EFI_DATA_HUB_PROTOCOL: Documented in EFI Data Hub Infrastructure Spe= cification, available at the URL: http://www.intel.com/technology/framework= /spec.htm + - EFI_HII_PROTOCOL (or EFI_HII_DATABASE_PROTOCOL for UEFI 2.1): Docume= nted in Human Interface Infrastructure Specification, available at the URL:= http://www.intel.com/technology/framework/spec.htm + (For EFI_HII_DATABASE_PROTOCOL, refer to UEFI Specification Version=20 + 2.1 available at the URL: http://www.uefi.org/) + + - @result + IGD power-management functionality is initialized; VT-d is=20 + initialized (meanwhile, the DMAR table is updated); IGD OpRegion is=20 + initialized - IGD_OPREGION_PROTOCOL installed, IGD OpRegion allocated=20 + and mailboxes initialized, chipset initialized and ready to generate=20 + Software SCI for Internal graphics events. Publishes the=20 + SA_INFO_PROTOCOL with current SA reference code version #. Publishes=20 + the EFI_LEGACY_REGION_PROTOCOL documented in the Compatibility Support=20 + Module Specification, version 0.9, available at the URL:=20 + http://www.intel.com/technology/framework/spec.htm + + - References \n + IGD OpRegion/Software SCI for Broadwell + Advanced Configuration and Power Interface Specification Revision 4.0a= . + + - Porting Recommendations \n + No modification of the DXE driver should be typically necessary. + This driver should be executed after all related devices (audio, video= , ME, etc.) are initialized to ensure correct data in DMAR table and DMA-re= mapping registers. + + @param[in] ImageHandle Handle for the image of this driver + @param[in] SystemTable Pointer to the EFI System Table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_OUT_OF_RESOURCES No enough buffer to allocate +**/ +EFI_STATUS +EFIAPI +SaInitEntryPointDxe ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaIni= tDxe.inf b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitD= xe.inf new file mode 100644 index 0000000000..4551ea389d --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe +++ .inf @@ -0,0 +1,90 @@ +## @file +# Component description file for SystemAgent Initialization driver # +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D SaInitDxe +FILE_GUID =3D DE23ACEE-CF55-4fb6-AA77-984AB53DE811 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D DXE_DRIVER +ENTRY_POINT =3D SaInitEntryPointDxe +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 EBC +# + + + +[LibraryClasses] +UefiDriverEntryPoint +UefiLib +UefiBootServicesTableLib +DxeServicesTableLib +DebugLib +TimerLib +PciCf8Lib +PciSegmentLib +BaseMemoryLib +MemoryAllocationLib +CpuPlatformLib +IoLib +S3BootScriptLib +PmcLib +PchCycleDecodingLib +PchInfoLib +GpioLib +ConfigBlockLib +PchPcieRpLib +DxeIgdOpRegionInitLib +AslUpdateLib +CpuPcieInfoFruLib + +[Packages] +MdePkg/MdePkg.dec +UefiCpuPkg/UefiCpuPkg.dec +IntelSiliconPkg/IntelSiliconPkg.dec +AlderlakeSiliconPkg/SiPkg.dec + +[Pcd] +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress +gSiPkgTokenSpaceGuid.PcdMchBaseAddress +gSiPkgTokenSpaceGuid.PcdSiIoApicBaseAddress +gSiPkgTokenSpaceGuid.PcdFspWrapperEnable +gSiPkgTokenSpaceGuid.PcdCpuPcieEnable ## CONSUMES + +[Sources] +SaInitDxe.h +SaInitDxe.c +SaInit.h +SaInit.c + +[Protocols] +gEfiAcpiTableProtocolGuid ## CONSUMES +gSaPolicyProtocolGuid ## CONSUMES +gEfiCpuArchProtocolGuid ## CONSUMES +gEfiPciEnumerationCompleteProtocolGuid ## CONSUMES +gEfiPciRootBridgeIoProtocolGuid ## CONSUMES +gIgdOpRegionProtocolGuid ## PRODUCES +gEfiFirmwareVolume2ProtocolGuid ## CONSUMES + +[Guids] +gEfiEndOfDxeEventGroupGuid +gSiConfigHobGuid ## CONSUMES +gGraphicsDxeConfigGuid +gMemoryDxeConfigGuid +gSaDataHobGuid +gHostBridgeDataHobGuid + +[Depex] +gEfiAcpiTableProtocolGuid AND +gEfiFirmwareVolume2ProtocolGuid AND +gSaPolicyProtocolGuid AND +gEfiPciRootBridgeIoProtocolGuid AND +gEfiPciHostBridgeResourceAllocationProtocolGuid AND # This is to ensure th= at PCI MMIO resource has been prepared and available for this driver to all= ocate. +gEfiHiiDatabaseProtocolGuid -- 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#107783): https://edk2.groups.io/g/devel/message/107783 Mute This Topic: https://groups.io/mt/100551006/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-