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List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: j9cRtFRkiUwrAhi0TC7QP5qFx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="UEOjJw/W"; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Reviewed-by: Rosen Chuang < rosen.chuang@intel.com> -----Original Message----- From: Kasbekar, Saloni =20 Sent: Wednesday, August 2, 2023 6:18 AM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Oram, Isaac W ; Chuang, Rosen Subject: [PATCH v2 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module Adds the following libraries within the Policy module - DxeSiliconPolicyUpdateLib - PeiPolicyUpdateLib - PeiSiliconPolicyUpdateLib Cc: Sai Chaganty Cc: Nate DeSimone Cc: Isaac Oram Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../DxeSaPolicyInit.c | 64 +++ .../DxeSiliconPolicyUpdateLate.c | 78 ++++ .../DxeSiliconPolicyUpdateLib.inf | 53 +++ .../PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c | 114 +++++ .../PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h | 31 ++ .../PeiCpuPolicyUpdatePreMem.c | 93 +++++ .../PeiPolicyUpdateLib/PeiPchPolicyUpdate.c | 210 ++++++++++ .../PeiPolicyUpdateLib/PeiPchPolicyUpdate.h | 24 ++ .../PeiPchPolicyUpdatePreMem.c | 124 ++++++ .../PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf | 208 ++++++++++ .../PeiPolicyUpdateLib/PeiSaPolicyUpdate.c | 214 ++++++++++ .../PeiPolicyUpdateLib/PeiSaPolicyUpdate.h | 27 ++ .../PeiSaPolicyUpdatePreMem.c | 389 ++++++++++++++++++ .../PeiSiliconPolicyUpdateLib.inf | 65 +++ .../PeiSiliconPolicyUpdatePostMem.c | 39 ++ .../PeiSiliconPolicyUpdatePreMem.c | 37 ++ 16 files changed, 1770 insertions(+) create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/Dxe= SiliconPolicyUpdateLib/DxeSaPolicyInit.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/Dxe= SiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/Dxe= SiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/Pei= PolicyUpdateLib/PeiCpuPolicyUpdate.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/Pei= PolicyUpdateLib/PeiCpuPolicyUpdate.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/Pei= PolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/Pei= PolicyUpdateLib/PeiPchPolicyUpdate.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/Pei= PolicyUpdateLib/PeiPchPolicyUpdate.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/Pei= PolicyUpdateLib/PeiPchPolicyUpdatePreMem.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/Pei= PolicyUpdateLib/PeiPolicyUpdateLib.inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/Pei= PolicyUpdateLib/PeiSaPolicyUpdate.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/Pei= PolicyUpdateLib/PeiSaPolicyUpdate.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/Pei= PolicyUpdateLib/PeiSaPolicyUpdatePreMem.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/Pei= SiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/Pei= SiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/Pei= SiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSilicon= PolicyUpdateLib/DxeSaPolicyInit.c b/Platform/Intel/AlderlakeOpenBoardPkg/Po= licy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c new file mode 100644 index 0000000000..da2f568e07 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyU= pdateLib/DxeSaPolicyInit.c @@ -0,0 +1,64 @@ +/** @file + This file initialises and Installs GopPolicy Protocol. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +CreateSaDxeConfigBlocks ( + IN OUT VOID **SaPolicy + ); + +EFI_STATUS +EFIAPI +SaInstallPolicyProtocol ( + IN EFI_HANDLE ImageHandle, + IN VOID *SaPolicy + ); + +/** + Initialize SA DXE Policy + + @param[in] ImageHandle Image handle of this driver. + + @retval EFI_SUCCESS Initialization complete. + @retval EFI_UNSUPPORTED The chipset is unsupported by this drive= r. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +SaPolicyInitDxe ( + IN EFI_HANDLE ImageHandle + ) +{ + EFI_STATUS Status; + SA_POLICY_PROTOCOL *SaPolicy; + + // + // Call CreateSaDxeConfigBlocks to create & initialize platform policy s= tructure + // and get all Intel default policy settings. + // + Status =3D CreateSaDxeConfigBlocks (&SaPolicy); + DEBUG ((DEBUG_INFO, "SaPolicy->TableHeader.NumberOfBlocks =3D 0x%x\n ", = SaPolicy->TableHeader.NumberOfBlocks)); + ASSERT_EFI_ERROR (Status); + + // + // Install SaInstallPolicyProtocol. + // While installed, RC assumes the Policy is ready and finalized. So ple= ase + // update and override any setting before calling this function. + // + Status =3D SaInstallPolicyProtocol (ImageHandle, SaPolicy); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSilicon= PolicyUpdateLib/DxeSiliconPolicyUpdateLate.c b/Platform/Intel/AlderlakeOpen= BoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLat= e.c new file mode 100644 index 0000000000..11a9950124 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyU= pdateLib/DxeSiliconPolicyUpdateLate.c @@ -0,0 +1,78 @@ +/** @file + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +/** + Initialize SA DXE Policy + + @param[in] ImageHandle Image handle of this driver. + + @retval EFI_SUCCESS Initialization complete. + @retval EFI_UNSUPPORTED The chipset is unsupported by this drive= r. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +SaPolicyInitDxe ( + IN EFI_HANDLE ImageHandle + ); + +/** + Initilize Intel Silicon DXE Platform Policy + + @param[in] ImageHandle Image handle of this driver. + + @retval EFI_SUCCESS Initialization complete. + @exception EFI_UNSUPPORTED The chipset is unsupported by this driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize= the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +SiliconPolicyInitDxe ( + IN EFI_HANDLE ImageHandle + ); + +/** + Performs silicon late policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a Protocol, etc. + + The input Policy must be returned by SiliconPolicyDoneLate(). + + In FSP or non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdateLate ( + IN OUT VOID *Policy + ) +{ + EFI_STATUS Status; + + Status =3D EFI_SUCCESS; + + // + // SystemAgent Dxe Platform Policy Initialization + // + Status =3D SaPolicyInitDxe (gImageHandle); + DEBUG ((DEBUG_INFO, "SystemAgent Dxe Platform Policy Initialization stat= us: %r\n", Status)); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSilicon= PolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf b/Platform/Intel/AlderlakeOpe= nBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLi= b.inf new file mode 100644 index 0000000000..54b4d7b17d --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyU= pdateLib/DxeSiliconPolicyUpdateLib.inf @@ -0,0 +1,53 @@ +## @file +# Component information file for Silicon Policy Update Library +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D DxeSiliconUpdateLib + FILE_GUID =3D C523609D-E354-416B-B24F-33468D4BD21D + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconPolicyUpdateLib + +[LibraryClasses] + BaseLib + BaseMemoryLib + PcdLib + DebugLib + UefiBootServicesTableLib + MemoryAllocationLib + DxeSaPolicyLib + UefiLib + ConfigBlockLib + GraphicsInfoLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec + +[Sources] + DxeSiliconPolicyUpdateLate.c + DxeSaPolicyInit.c + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdIntelGopEnable + gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid + gPlatformModuleTokenSpaceGuid.PcdSmbiosOemTypeFirmwareVersionInfo ##= CONSUMES + +[Protocols] + gEfiFirmwareVolume2ProtocolGuid ## CONSUMES + gSaPolicyProtocolGuid ## CONSUMES + gDxeSiPolicyProtocolGuid ## PRODUCES + gGopPolicyProtocolGuid ## PRODUCES + +[Depex] + gEfiVariableArchProtocolGuid diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyU= pdateLib/PeiCpuPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy= /Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c new file mode 100644 index 0000000000..1ee4bdd038 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi= b/PeiCpuPolicyUpdate.c @@ -0,0 +1,114 @@ +/** @file + CPU PEI Policy Update & initialization. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + +**/ +#include "PeiCpuPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include + +/* + Get the uCode region from PCD settings, and copy the patches to memory. + This function is used to replace CpuLocateMicrocodePatch due to that fun= ction can not works + with uCode update new design. + In current uCode update solution, there are some padding data between uC= ode patches, + the algorithm in CpuLocateMicrocodePatch can not handle this. + Besides that, in CpuLocateMicrocodePatch function, the scan algorithm ju= st find the first + correct uCode patch which is not the highest version uCode. + This function just copy the uCode region to memory, and in later, the Cp= uMpInit driver + will load the correct patch for CPU. + + @param[out] RegionAddress Pointer to the uCode array. + @param[out] RegionSize Size of the microcode FV. + + @retval EFI_SUCCESS Find uCode patch region and success copy t= he data to memory. + @retval EFI_NOT_FOUND Something wrong with uCode region. + @retval EFI_OUT_OF_RESOUCES Memory allocation fail. + @retval EFI_INVALID_PARAMETER RegionAddres or RegionSize is NULL. + +*/ +EFI_STATUS +SearchMicrocodeRegion ( + OUT UINTN *RegionAddress, + OUT UINTN *RegionSize + ) +{ + UINTN MicrocodeStart; + UINTN MicrocodeEnd; + UINT8 *MemoryBuffer; + + if (RegionAddress =3D=3D NULL || RegionSize =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + *RegionAddress =3D 0; + *RegionSize =3D 0; + + if ((FixedPcdGet32 (PcdFlashFvMicrocodeBase) =3D=3D 0) || (FixedPcdGet32= (PcdFlashFvMicrocodeSize) =3D=3D 0)) { + return EFI_NOT_FOUND; + } + + MicrocodeStart =3D (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeBase) + (UI= NTN) FixedPcdGet32 (PcdMicrocodeOffsetInFv); + MicrocodeEnd =3D (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeBase) + (UINT= N) FixedPcdGet32 (PcdFlashFvMicrocodeSize); + *RegionSize =3D MicrocodeEnd - MicrocodeStart; + + DEBUG ((DEBUG_INFO, "[SearchMicrocodeRegion]: Microcode Region Address = =3D %x, Size =3D %d\n", MicrocodeStart, *RegionSize)); + + MemoryBuffer =3D AllocatePages (EFI_SIZE_TO_PAGES (*RegionSize)); + ASSERT (MemoryBuffer !=3D NULL); + if (MemoryBuffer =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Failed to allocate enough memory for Microcode P= atch.\n")); + return EFI_OUT_OF_RESOURCES; + } else { + CopyMem (MemoryBuffer, (UINT8 *)MicrocodeStart, *RegionSize); + *RegionAddress =3D (UINTN)MemoryBuffer; + DEBUG ((DEBUG_INFO, "Copy whole uCode region to memory, address =3D %x= , size =3D %d\n", RegionAddress, *RegionSize)); + } + + return EFI_SUCCESS; +} + +/** + This function performs CPU PEI Policy initialization. + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initial= ize the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicy ( + VOID + ) +{ + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicyPpi; + CPU_CONFIG *CpuConfig; + + DEBUG ((DEBUG_INFO, "Update PeiCpuPolicyUpdate Pos-Mem Start\n")); + + SiPolicyPpi =3D NULL; + CpuConfig =3D NULL; + + Status =3D PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &= SiPolicyPpi); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID = *) &CpuConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D SearchMicrocodeRegion ( + (UINTN *)&CpuConfig->MicrocodePatchAddress, + (UINTN *)&CpuConfig->MicrocodePatchRegionSize + ); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyU= pdateLib/PeiCpuPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy= /Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h new file mode 100644 index 0000000000..b003481db0 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi= b/PeiCpuPolicyUpdate.h @@ -0,0 +1,31 @@ +/** @file + Header file for PEI CpuPolicyUpdate. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _PEI_CPU_POLICY_UPDATE_H_ +#define _PEI_CPU_POLICY_UPDATE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "PeiPchPolicyUpdate.h" +#include + + +#endif diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyU= pdateLib/PeiCpuPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/= Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c new file mode 100644 index 0000000000..b23e2ceceb --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi= b/PeiCpuPolicyUpdatePreMem.c @@ -0,0 +1,93 @@ +/** @file + This file is SampleCode of the library for Intel CPU PEI Policy initiali= zation. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include "PeiCpuPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GET_OCCUPIED_SIZE(ActualSize, Alignment) \ + ((ActualSize) + (((Alignment) - ((ActualSize) & ((Alignment) - 1))) & ((= Alignment) - 1))) + + +/** + This function performs CPU PEI Policy initialization in Pre-memory. + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initial= ize the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicyPreMem ( + VOID + ) +{ + EFI_STATUS Status; + CPU_SECURITY_PREMEM_CONFIG *CpuSecurityPreMemConfig; + CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + UINT32 MaxLogicProcessors; + UINT16 BiosSize; + UINT16 BiosMemSizeInMb; + FW_BOOT_MEDIA_TYPE FwBootMediaType; + MSR_CORE_THREAD_COUNT_REGISTER MsrCoreThreadCount; + UINT8 AllCoreCount; + UINT8 AllSmallCoreCount; + UINT32 DisablePerCoreMask; + + DEBUG ((DEBUG_INFO, "Update PeiCpuPolicyUpdate Pre-Mem Start\n")); + + SiPreMemPolicyPpi =3D NULL; + CpuSecurityPreMemConfig =3D NULL; + CpuConfigLibPreMemConfig =3D NULL; + BiosSize =3D 0; + BiosMemSizeInMb =3D 0; + FwBootMediaType =3D FwBootMediaMax; + AllCoreCount =3D 0; + AllSmallCoreCount =3D 0; + DisablePerCoreMask =3D 0; + + Status =3D PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID= **) &SiPreMemPolicyPpi); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuSecurityPreM= emConfigGuid, (VOID *) &CpuSecurityPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPre= MemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig); + ASSERT_EFI_ERROR (Status); + + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SkipStopPbet, CpuSecur= ityPreMemConfig->SkipStopPbet, FALSE); + + SpiServiceInit (); + DEBUG ((DEBUG_INFO, "BIOS Guard PCD and Policy are disabled\n")); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.BiosGuard, CpuSecurity= PreMemConfig->BiosGuard, CPU_FEATURE_DISABLE); + + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.CpuRatio, CpuConfigLib= PreMemConfig->CpuRatio, 0); + + /// + /// Set PcdCpuMaxLogicalProcessorNumber to max number of logical process= ors enabled + /// Read MSR_CORE_THREAD_COUNT (0x35) to check the total active Threads + /// + MsrCoreThreadCount.Uint64 =3D AsmReadMsr64 (MSR_CORE_THREAD_COUNT); + MaxLogicProcessors =3D MsrCoreThreadCount.Bits.Threadcount; + DEBUG ((DEBUG_INFO, "MaxLogicProcessors =3D %d\n", MaxLogicProcessors)); + + PcdSetEx32S (&gUefiCpuPkgTokenSpaceGuid, PcdCpuMaxLogicalProcessorNumber= , MaxLogicProcessors); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyU= pdateLib/PeiPchPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy= /Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c new file mode 100644 index 0000000000..1c0cf6bee0 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi= b/PeiPchPolicyUpdate.c @@ -0,0 +1,210 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initiali= zation. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PeiPchPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + This is helper function for getting I2C Pads Internal Termination settin= gs from Pcd + + @param[in] Index I2C Controller Index +**/ +UINT8 +STATIC +GetSerialIoI2cPadsTerminationFromPcd ( + IN UINT8 Index + ) +{ + switch (Index) { + case 0: + return PcdGet8 (PcdPchSerialIoI2c0PadInternalTerm); + case 1: + return PcdGet8 (PcdPchSerialIoI2c1PadInternalTerm); + case 2: + return PcdGet8 (PcdPchSerialIoI2c2PadInternalTerm); + case 3: + return PcdGet8 (PcdPchSerialIoI2c3PadInternalTerm); + case 4: + return PcdGet8 (PcdPchSerialIoI2c4PadInternalTerm); + case 5: + return PcdGet8 (PcdPchSerialIoI2c5PadInternalTerm); + case 6: + return PcdGet8 (PcdPchSerialIoI2c6PadInternalTerm); + case 7: + return PcdGet8 (PcdPchSerialIoI2c7PadInternalTerm); + default: + ASSERT (FALSE); // Invalid I2C Controller Index + } + return 0; +} + +/** + This function performs PCH Serial IO Platform Policy initialization + + @param[in] SiPolicy Pointer to SI_POLICY_PPI + @param[in] FspsUpd A VOID pointer +**/ +VOID +UpdateSerialIoConfig ( + IN SI_POLICY_PPI *SiPolicy, + IN VOID *FspsUpd + ) +{ + UINT8 Index; + SERIAL_IO_CONFIG *SerialIoConfig; + EFI_STATUS Status; + + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOI= D *) &SerialIoConfig); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return; + } + + // + // I2C + // + for (Index =3D 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++= ) { + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PchSerialIoI2cPadsTe= rmination[Index], SerialIoConfig->I2cDeviceConfig[Index].PadTermination, Ge= tSerialIoI2cPadsTerminationFromPcd (Index)); + } + + if (IsPchP ()) { + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[0], = SerialIoConfig->I2cDeviceConfig[0].Mode, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[1], = SerialIoConfig->I2cDeviceConfig[1].Mode, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[2], = SerialIoConfig->I2cDeviceConfig[2].Mode, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[3], = SerialIoConfig->I2cDeviceConfig[3].Mode, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[4], = SerialIoConfig->I2cDeviceConfig[4].Mode, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[5], = SerialIoConfig->I2cDeviceConfig[5].Mode, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[6], = SerialIoConfig->I2cDeviceConfig[6].Mode, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[7], = SerialIoConfig->I2cDeviceConfig[7].Mode, 0); + } + + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[0],= SerialIoConfig->UartDeviceConfig[0].Mode, 2); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[1],= SerialIoConfig->UartDeviceConfig[1].Mode, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[2],= SerialIoConfig->UartDeviceConfig[2].Mode, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[3],= SerialIoConfig->UartDeviceConfig[3].Mode, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[4],= SerialIoConfig->UartDeviceConfig[4].Mode, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[5],= SerialIoConfig->UartDeviceConfig[5].Mode, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[6],= SerialIoConfig->UartDeviceConfig[6].Mode, 0); + + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow= [0], SerialIoConfig->UartDeviceConfig[0].Attributes.AutoFlow, 1); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow= [1], SerialIoConfig->UartDeviceConfig[1].Attributes.AutoFlow, 1); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow= [2], SerialIoConfig->UartDeviceConfig[2].Attributes.AutoFlow, 1); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow= [3], SerialIoConfig->UartDeviceConfig[3].Attributes.AutoFlow, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow= [4], SerialIoConfig->UartDeviceConfig[4].Attributes.AutoFlow, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow= [5], SerialIoConfig->UartDeviceConfig[5].Attributes.AutoFlow, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow= [6], SerialIoConfig->UartDeviceConfig[6].Attributes.AutoFlow, 0); + + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGat= ing[0], SerialIoConfig->UartDeviceConfig[0].PowerGating, 2); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGat= ing[1], SerialIoConfig->UartDeviceConfig[1].PowerGating, 2); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGat= ing[2], SerialIoConfig->UartDeviceConfig[2].PowerGating, 2); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGat= ing[3], SerialIoConfig->UartDeviceConfig[3].PowerGating, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGat= ing[4], SerialIoConfig->UartDeviceConfig[4].PowerGating, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGat= ing[5], SerialIoConfig->UartDeviceConfig[5].PowerGating, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGat= ing[6], SerialIoConfig->UartDeviceConfig[6].PowerGating, 0); + + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnabl= e[0], SerialIoConfig->UartDeviceConfig[0].DmaEnable, 1); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnabl= e[1], SerialIoConfig->UartDeviceConfig[1].DmaEnable, 1); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnabl= e[2], SerialIoConfig->UartDeviceConfig[2].DmaEnable, 1); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnabl= e[3], SerialIoConfig->UartDeviceConfig[3].DmaEnable, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnabl= e[4], SerialIoConfig->UartDeviceConfig[4].DmaEnable, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnabl= e[5], SerialIoConfig->UartDeviceConfig[5].DmaEnable, 0); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnabl= e[6], SerialIoConfig->UartDeviceConfig[6].DmaEnable, 0); + +} + + +/** + Update PCIe Root Port Configuration + + @param[in] SiPolicy Pointer to SI_POLICY_PPI + @param[in] FspsUpd Pointer to FspsUpd structure + // @param[in] PchSetup Pointer to PCH_SETUP buffer + // @param[in] SetupVariables Pointer to SETUP_DATA buffer +**/ +VOID +UpdatePcieRpConfig ( + IN SI_POLICY_PPI *SiPolicy, + IN VOID *FspsUpd + ) +{ + UINT8 Index; + EFI_STATUS Status; + PCH_PCIE_CONFIG *PchPcieConfig; + UINTN MaxPciePorts; + + MaxPciePorts =3D GetPchMaxPciePortNum (); + + PchPcieConfig =3D NULL; + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPchPcieConfigGuid, (VOID= *) &PchPcieConfig); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return; + } + + // + // PCI express config + // + for (Index =3D 0; Index < MaxPciePorts; Index++) { + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpMaxPayload[Ind= ex], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.M= axPayload, PchPcieMaxPayload256); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpPhysicalSlotNu= mber[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.P= hysicalSlotNumber, (UINT8) Index); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpClkReqDetect[I= ndex], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.C= lkReqDetect, TRUE); + } +} + +/** + This function performs PCH PEI Policy initialization. + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicy ( + VOID + ) +{ + EFI_STATUS Status; + VOID *FspsUpd; + SI_POLICY_PPI *SiPolicy; + VOID *FspmUpd; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + CPU_SECURITY_PREMEM_CONFIG *CpuSecurityPreMemConfig; + + DEBUG ((DEBUG_INFO, "Update PeiPchPolicyUpdate Pos-Mem Start\n")); + + FspsUpd =3D NULL; + FspmUpd =3D NULL; + SiPolicy =3D NULL; + CpuSecurityPreMemConfig =3D NULL; + SiPreMemPolicyPpi =3D NULL; + + Status =3D PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &= SiPolicy); + ASSERT_EFI_ERROR (Status); + + UpdatePcieRpConfig (SiPolicy, FspsUpd); + UpdateSerialIoConfig (SiPolicy, FspsUpd); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyU= pdateLib/PeiPchPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy= /Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h new file mode 100644 index 0000000000..133660c59e --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi= b/PeiPchPolicyUpdate.h @@ -0,0 +1,24 @@ +/** @file + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _PEI_PCH_POLICY_UPDATE_H_ +#define _PEI_PCH_POLICY_UPDATE_H_ + +// +// External include files do NOT need to be explicitly specified in real E= DKII +// environment +// +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyU= pdateLib/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/= Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c new file mode 100644 index 0000000000..47ecd41b39 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi= b/PeiPchPolicyUpdatePreMem.c @@ -0,0 +1,124 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initiali= zation. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PeiPchPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +UpdatePcieClockInfo ( + PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig, + IN VOID *FspmUpd, + UINTN Index, + UINT64 Data + ) +{ + PCD64_BLOB Pcd64; + + Pcd64.Blob =3D Data; + DEBUG ((DEBUG_INFO, "UpdatePcieClockInfo ClkIndex %x ClkUsage %x, Suppor= ted %x\n", Index, Pcd64.PcieClock.ClockUsage, Pcd64.PcieClock.ClkReqSupport= ed)); + + UPDATE_POLICY (((FSPM_UPD *)FspmUpd)->FspmConfig.PcieClkSrcUsage[Index],= PcieRpPreMemConfig->PcieClock[Index].Usage, (UINT8)Pcd64.PcieClock.ClockUs= age); + UPDATE_POLICY (((FSPM_UPD *)FspmUpd)->FspmConfig.PcieClkSrcClkReq[Index]= , PcieRpPreMemConfig->PcieClock[Index].ClkReq, Pcd64.PcieClock.ClkReqSuppor= ted ? (UINT8)Index : 0xFF); +} + +/** + Update PcieRp pre mem policies. + + @param[in] SiPreMemPolicy Pointer to SI_PREMEM_POLICY_PPI + @param[in] FspsUpm Pointer to FSPM_UPD + @param[in] PchSetup Pointer to PCH_SETUP +**/ +STATIC +VOID +UpdatePcieRpPreMemPolicy ( + IN SI_PREMEM_POLICY_PPI *SiPreMemPolicy, + IN VOID *FspmUpd + ) +{ + UINT32 RpIndex; + UINT32 RpEnabledMask; + PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig; + EFI_STATUS Status; + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfig= Guid, (VOID *) &PcieRpPreMemConfig); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return; + } + + GET_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PcieRpEnableMask, PcieRpP= reMemConfig->RpEnabledMask, RpEnabledMask); + + for (RpIndex =3D 0; RpIndex < GetPchMaxPciePortNum (); RpIndex ++) { + RpEnabledMask |=3D (UINT32) (1 << RpIndex); + } + // RpEnabledMask value is related with Setup value, Need to check Policy= Default + COMPARE_AND_UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PcieRpEnab= leMask, PcieRpPreMemConfig->RpEnabledMask, RpEnabledMask); + + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 0, PcdGet64(PcdPcieClo= ck0)); + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 1, PcdGet64(PcdPcieClo= ck1)); + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 2, PcdGet64(PcdPcieClo= ck2)); + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 3, PcdGet64(PcdPcieClo= ck3)); + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 4, PcdGet64(PcdPcieClo= ck4)); + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 5, PcdGet64(PcdPcieClo= ck5)); + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 6, PcdGet64(PcdPcieClo= ck6)); + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 7, PcdGet64(PcdPcieClo= ck7)); + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 8, PcdGet64(PcdPcieClo= ck8)); + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 9, PcdGet64(PcdPcieClo= ck9)); + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 10, PcdGet64(PcdPcieCl= ock10)); + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 11, PcdGet64(PcdPcieCl= ock11)); + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 12, PcdGet64(PcdPcieCl= ock12)); + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 13, PcdGet64(PcdPcieCl= ock13)); + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 14, PcdGet64(PcdPcieCl= ock14)); + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 15, PcdGet64(PcdPcieCl= ock15)); + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 16, PcdGet64(PcdPcieCl= ock16)); + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 17, PcdGet64(PcdPcieCl= ock17)); + +} + +/** + This function performs PCH PEI Policy initialization. + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicyPreMem ( + VOID + ) +{ + EFI_STATUS Status; + VOID *FspmUpd; + SI_PREMEM_POLICY_PPI *SiPreMemPolicy; + + DEBUG ((DEBUG_INFO, "Update PeiPchPolicyUpdate Pre-Mem Start\n")); + + FspmUpd =3D NULL; + SiPreMemPolicy =3D NULL; + + Status =3D PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID= **) &SiPreMemPolicy); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return Status; + } + + UpdatePcieRpPreMemPolicy (SiPreMemPolicy, FspmUpd); + return EFI_SUCCESS; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyU= pdateLib/PeiPolicyUpdateLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Poli= cy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf new file mode 100644 index 0000000000..844e4c9967 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi= b/PeiPolicyUpdateLib.inf @@ -0,0 +1,208 @@ +### @file +# Module Information file for PEI PolicyUpdateLib Library +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiPolicyUpdateLib + FILE_GUID =3D D42F5BB8-E0CE-47BD-8C52-476C79055FC6 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + LIBRARY_CLASS =3D PeiPolicyUpdateLib|PEIM PEI_CORE SEC + +[LibraryClasses] + HobLib + BaseCryptLib + CpuPlatformLib + IoLib + ConfigBlockLib + MemoryAllocationLib + PeiServicesTablePointerLib + PcdLib + Tpm2CommandLib + Tpm12CommandLib + Tpm2DeviceLib + Tpm12DeviceLib + BoardConfigLib + PciSegmentLib + SiPolicyLib + PeiServicesLib + FirmwareBootMediaLib + SpiLib + BmpSupportLib + PeiGetFvInfoLib + TimerLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + AlderlakeSiliconPkg/SiPkg.dec + SecurityPkg/SecurityPkg.dec + CryptoPkg/CryptoPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + BoardModulePkg/BoardModulePkg.dec + +[FixedPcd] + gBoardModuleTokenSpaceGuid.PcdDefaultBoardId = ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase = ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize = ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize = ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize = ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize = ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize = ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize = ## CONSUMES + gSiPkgTokenSpaceGuid.PcdBiosSize = ## CONSUMES + gSiPkgTokenSpaceGuid.PcdTsegSize = ## CONSUMES + +[Pcd] + gSiPkgTokenSpaceGuid.PcdMchBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdGttMmAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdBoardId ## CONSUMES + + # SA Misc Config + gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2Dram ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2DramSize ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdData ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcLp5CccConfig ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcCmdMirror ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMask ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMaskEcc ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSaMiscDisableMrcRetrainingOnRtcPowerLoss #= # CONSUMES + + # Display DDI + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## CONSUMES + + # PCIE RTD3 GPIO + gBoardModuleTokenSpaceGuid.PcdRootPortIndex ## CONSUMES + + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdSpdPresent ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable4 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable5 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable6 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable7 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable8 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable9 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable10 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable11 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable12 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable13 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable14 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable15 ## CONSUMES + + + # PCIe Clock Info + gBoardModuleTokenSpaceGuid.PcdPcieClock0 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock1 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock2 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock3 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock4 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock5 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock6 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock7 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock8 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock9 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock10 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock11 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock12 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock13 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock14 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock15 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock16 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock17 ## CONSUMES + + + # Pch SerialIo I2c Pads Termination + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c6PadInternalTerm ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c7PadInternalTerm ## CONSUMES + + gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem ## CONSUMES + +[Sources] + PeiPchPolicyUpdatePreMem.c + PeiPchPolicyUpdate.c + PeiCpuPolicyUpdatePreMem.c + PeiCpuPolicyUpdate.c + PeiSaPolicyUpdate.c + PeiSaPolicyUpdatePreMem.c + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES + gWdtPpiGuid ## CONSUMES + gPchSpiPpiGuid ## CONSUMES + gSiPolicyPpiGuid ## CONSUMES + gSiPreMemPolicyPpiGuid ## CONSUMES + gFspmArchConfigPpiGuid ## PRODUCES + gReadyForGopConfigPpiGuid ## PRODUCES + gPeiGraphicsPlatformPpiGuid ## CONSUMES + gPeiGraphicsFramebufferReadyPpiGuid ## CONSUMES + +[Guids] + gEfiGlobalVariableGuid ## CONSUMES + gMemoryConfigVariableGuid ## CONSUMES + gEfiCapsuleVendorGuid ## CONSUMES + gEfiMemoryTypeInformationGuid ## CONSUMES + gEfiMemoryOverwriteControlDataGuid ## CONSUMES + gSiPreMemConfigGuid ## CONSUMES + gSiConfigGuid ## CONSUMES + gCpuSecurityPreMemConfigGuid ## CONSUMES + gCpuConfigLibPreMemConfigGuid ## CONSUMES + gCpuConfigGuid ## CONSUMES + gVmdPeiConfigGuid ## CONSUMES + gCpuPcieRpPrememConfigGuid ## CONSUMES + gVmdInfoHobGuid ## CONSUMES + gPciePreMemConfigGuid ## CONSUMES + gPlatformInitFvLocationGuid ## CONSUMES + gHostBridgePeiPreMemConfigGuid ## CONSUMES + gEfiGraphicsInfoHobGuid ## CONSUMES + gPchDmiPreMemConfigGuid ## CONSUMES + gGraphicsPeiConfigGuid ## CONSUMES + gMemoryConfigGuid ## CONSUMES + gMemoryConfigNoCrcGuid ## CONSUMES + gPchPcieConfigGuid ## CONSUMES + gSerialIoConfigGuid ## CONSUMES + gPcieRpPreMemConfigGuid ## CONSUMES + gSaMiscPeiPreMemConfigGuid ## CONSUMES diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyU= pdateLib/PeiSaPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/= Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c new file mode 100644 index 0000000000..c62b0a14ef --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi= b/PeiSaPolicyUpdate.c @@ -0,0 +1,214 @@ +/** @file +Do Platform Stage System Agent initialization. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PeiSaPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + + +EFI_STATUS +EFIAPI +PeiGraphicsPolicyUpdateCallback ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + EFI_PEI_GRAPHICS_INFO_HOB *PlatformGraphicsOutput; + EFI_PEI_HOB_POINTERS Hob; + UINT8 *HobStart; + GRAPHICS_PEI_CONFIG *GtConfig; + SI_POLICY_PPI *SiPolicyPpi; + + PlatformGraphicsOutput =3D NULL; + HobStart =3D NULL; + + GtConfig =3D NULL; + SiPolicyPpi =3D NULL; + Status =3D PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &= SiPolicyPpi); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid= , (VOID *) &GtConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); + HobStart =3D Hob.Raw; + + if (!EFI_ERROR (Status)) { + if (HobStart !=3D NULL) { + if ((Hob.Raw =3D GetNextGuidHob (&gEfiGraphicsInfoHobGuid, HobStart)= ) !=3D NULL) { + DEBUG ((DEBUG_INFO, "Found EFI_PEI_GRAPHICS_INFO_HOB\n")); + PlatformGraphicsOutput =3D GET_GUID_HOB_DATA (Hob.Guid); + } + } + } + + if (PlatformGraphicsOutput !=3D NULL) { + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.HorizontalResolution= , GtConfig->HorizontalResolution, PlatformGraphicsOutput->GraphicsMode.Ho= rizontalResolution); + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.VerticalResolution, = GtConfig->VerticalResolution, PlatformGraphicsOutput->GraphicsMode.Ve= rticalResolution); + } else { + DEBUG ((DEBUG_INFO, "Not able to find EFI_PEI_GRAPHICS_INFO_HOB\n")); + } + + return Status; +} + +STATIC +EFI_PEI_NOTIFY_DESCRIPTOR mPeiGfxPolicyUpdateNotifyList =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST), + &gPeiGraphicsFramebufferReadyPpiGuid, + PeiGraphicsPolicyUpdateCallback +}; + +/** + UpdatePeiSaPolicy performs SA PEI Policy initialization + + @retval EFI_SUCCESS The policy is installed and initialized= . +**/ +EFI_STATUS +EFIAPI +UpdatePeiSaPolicy ( + VOID + ) +{ + EFI_GUID BmpImageGuid; + EFI_STATUS Status; + EFI_GUID FileGuid; + VOID *Buffer; + UINT32 Size; + VOID *VmdVariablePtr; + GRAPHICS_PEI_CONFIG *GtConfig; + SI_POLICY_PPI *SiPolicyPpi; + CPU_PCIE_CONFIG *CpuPcieRpConfig; + VMD_PEI_CONFIG *VmdPeiConfig; + EFI_PEI_PPI_DESCRIPTOR *ReadyForGopConfigPpiDesc; + VOID *VbtPtr; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Blt; + UINTN BltSize; + UINTN Height; + UINTN Width; + + DEBUG ((DEBUG_INFO, "Update PeiSaPolicyUpdate Pos-Mem Start\n")); + + Size =3D 0; + Blt =3D NULL; + BltSize =3D 0; + + GtConfig =3D NULL; + SiPolicyPpi =3D NULL; + CpuPcieRpConfig =3D NULL; + VmdVariablePtr =3D NULL; + Buffer =3D NULL; + + Status =3D PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &= SiPolicyPpi); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid= , (VOID *) &GtConfig); + ASSERT_EFI_ERROR(Status); + + + + VmdPeiConfig =3D NULL; + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gVmdPeiConfigGuid, (VO= ID *) &VmdPeiConfig); + ASSERT_EFI_ERROR(Status); + + CopyMem(&BmpImageGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid), sizeof(Bm= pImageGuid)); + + if (!EFI_ERROR (Status)) { + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SkipFspGop, = GtConfig->SkipFspGop, 0x0); + Buffer =3D NULL; + + CopyMem(&FileGuid, &BmpImageGuid, sizeof(FileGuid)); + PeiGetSectionFromFv(FileGuid, &Buffer, &Size); + if (Buffer =3D=3D NULL) { + DEBUG((DEBUG_ERROR, "Could not locate VBT\n")); + } + + GtConfig->GraphicsConfigPtr =3D Buffer; + DEBUG ((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", = GtConfig->GraphicsConfigPtr)); + DEBUG ((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Siz= e)); + GET_POLICY ((VOID *) ((FSPS_UPD *) FspsUpd)->FspsConfig.GraphicsConfig= Ptr, GtConfig->GraphicsConfigPtr, VbtPtr); + + // + // Install ReadyForGopConfig PPI to trigger PEI phase GopConfig callba= ck. + // + ReadyForGopConfigPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPo= ol (sizeof (EFI_PEI_PPI_DESCRIPTOR)); + if (ReadyForGopConfigPpiDesc =3D=3D NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + ReadyForGopConfigPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_P= EI_PPI_DESCRIPTOR_TERMINATE_LIST; + ReadyForGopConfigPpiDesc->Guid =3D &gReadyForGopConfigPpiGuid; + ReadyForGopConfigPpiDesc->Ppi =3D VbtPtr; + Status =3D PeiServicesInstallPpi (ReadyForGopConfigPpiDesc); + + Status =3D TranslateBmpToGopBlt ( + Buffer, + Size, + &Blt, + &BltSize, + &Height, + &Width + ); + + if (Status =3D=3D EFI_BUFFER_TOO_SMALL) { + Blt =3D NULL; + Status =3D TranslateBmpToGopBlt ( + Buffer, + Size, + &Blt, + &BltSize, + &Height, + &Width + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "TranslateBmpToGopBlt, Status =3D %r\n", Stat= us)); + ASSERT_EFI_ERROR (Status); + return Status; + } + } + + // + // Initialize Blt, BltSize + // + GtConfig->BltBufferAddress =3D Blt; + + UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.BltBufferSize, GtC= onfig->BltBufferSize, BltSize); + + DEBUG ((DEBUG_INFO, "Calling mPeiGfxPolicyUpdateNotifyList\n")); + Status =3D PeiServicesNotifyPpi (&mPeiGfxPolicyUpdateNotifyList); + + } + + // + // VMD related settings from setup variable + // + COMPARE_AND_UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.VmdEnable,= VmdPeiConfig->VmdEnable, 0); + VmdPeiConfig->VmdVariablePtr =3D VmdVariablePtr; + DEBUG ((DEBUG_INFO, "VmdVariablePtr from PeiGetSectionFromFv is 0x%x\n",= VmdVariablePtr)); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyU= pdateLib/PeiSaPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/= Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h new file mode 100644 index 0000000000..64f97b672b --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi= b/PeiSaPolicyUpdate.h @@ -0,0 +1,27 @@ +/** @file + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _PEI_SA_POLICY_UPDATE_H_ +#define _PEI_SA_POLICY_UPDATE_H_ + +// +// External include files do NOT need to be explicitly specified in real E= DKII +// environment +// +#include +#include +#include +#include +#include +#include "PeiPchPolicyUpdate.h" +#include +#include +#include + +#define WDT_TIMEOUT 60 + +#endif + diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyU= pdateLib/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/P= olicy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c new file mode 100644 index 0000000000..a4ceda76c3 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi= b/PeiSaPolicyUpdatePreMem.c @@ -0,0 +1,389 @@ +/** @file +Do Platform Stage System Agent initialization. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PeiSaPolicyUpdate.h" +#include "MemoryConfig.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/// +/// Memory Reserved should be between 125% to 150% of the Current required= memory +/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resum= e issues. +/// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTy= peInformation[] =3D { + { EfiACPIReclaimMemory, FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemory= Size) }, // ASL + { EfiACPIMemoryNVS, FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize= ) }, // ACPI NVS (including S3 related) + { EfiReservedMemoryType, FixedPcdGet32 (PcdPlatformEfiReservedMemorySiz= e) }, // BIOS Reserved (including S3 related) + { EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize)= }, // Runtime Service Data + { EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize)= }, // Runtime Service Code + { EfiMaxMemoryType, 0 } +}; + +#define PEI_MIN_MEMORY_SIZE (10 * 0x800000) // 80MB + +/** + UpdatePeiSaPolicyPreMem performs SA PEI Policy initialization + + @retval EFI_SUCCESS The policy is installed and initialized= . +**/ +EFI_STATUS +EFIAPI +UpdatePeiSaPolicyPreMem ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices; + UINTN VariableSize; + SA_MEMORY_RCOMP *RcompData; + WDT_PPI *gWdtPei; + UINT8 WdtTimeout; + + UINT8 Index; + UINTN DataSize; + EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryT= ype + 1]; + EFI_BOOT_MODE BootMode; + UINT8 MorControl; + UINT64 PlatformMemorySize; + VOID *MemorySavedData; + VOID *NullSpdPtr; + UINT32 RpEnabledMask; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + MEMORY_CONFIGURATION *MemConfig; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; + EFI_PEI_PPI_DESCRIPTOR *FspmArchConfigPpiDesc; + FSPM_ARCH_CONFIG_PPI *FspmArchConfigPpi; + HOST_BRIDGE_PREMEM_CONFIG *HostBridgePreMemConfig; + UINT16 AdjustedMmioSize; + UINT8 SaDisplayConfigTable[16]= ; + EFI_BOOT_MODE SysBootMode; + UINT32 ProcessorTraceTotalMemSi= ze; + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx; + UINT32 CapsuleSupportMemSize; + + DEBUG ((DEBUG_INFO, "Update PeiSaPolicyUpdate Pre-Mem Start\n")); + ZeroMem ((VOID*) SaDisplayConfigTable, sizeof (SaDisplayConfigTable)); + WdtTimeout =3D 0; + SysBootMode =3D 0; + RcompData =3D NULL; + PlatformMemorySize =3D 0; + RpEnabledMask =3D 0; + SiPreMemPolicyPpi =3D NULL; + MemConfig =3D NULL; + MemConfigNoCrc =3D NULL; + + + MiscPeiPreMemConfig =3D NULL; + HostBridgePreMemConfig =3D NULL; + FspmArchConfigPpi =3D NULL; + + ProcessorTraceTotalMemSize =3D 0; + CapsuleSupportMemSize =3D 0; + + AdjustedMmioSize =3D PcdGet16 (PcdSaMiscMmioSizeAdjustment); + + Status =3D PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID= **) &SiPreMemPolicyPpi); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gHostBridgePeiPr= eMemConfigGuid, (VOID *) &HostBridgePreMemConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemC= onfigGuid, (VOID *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigGuid= , (VOID *) &MemConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCr= cGuid, (VOID *) &MemConfigNoCrc); + ASSERT_EFI_ERROR(Status); + + RcompData =3D MemConfigNoCrc->RcompData; + + // + // Locate system configuration variable + // + Status =3D PeiServicesLocatePpi( + &gEfiPeiReadOnlyVariable2PpiGuid, // GUID + 0, // INSTANCE + NULL, // EFI_PEI_PPI_DESCRIPTOR + (VOID **) &VariableServices // PPI + ); + ASSERT_EFI_ERROR(Status); + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + // + // Initialize S3 Data variable (S3DataPtr) + // + VariableSize =3D 0; + MemorySavedData =3D NULL; + Status =3D VariableServices->GetVariable ( + VariableServices, + L"MemoryConfig", + &gMemoryConfigVariableGuid, + NULL, + &VariableSize, + MemorySavedData + ); + if (Status =3D=3D EFI_BUFFER_TOO_SMALL) { + MemorySavedData =3D AllocateZeroPool (VariableSize); + ASSERT (MemorySavedData !=3D NULL); + + Status =3D VariableServices->GetVariable ( + VariableServices, + L"MemoryConfig", + &gMemoryConfigVariableGuid, + NULL, + &VariableSize, + MemorySavedData + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Fail to retrieve Variable: MemoryConfig, Statu= s =3D %r\n", Status)); + ASSERT_EFI_ERROR (Status); + } + } + FspmArchConfigPpi =3D (FSPM_ARCH_CONFIG_PPI *) AllocateZeroPool (sizeof = (FSPM_ARCH_CONFIG_PPI)); + if (FspmArchConfigPpi =3D=3D NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + FspmArchConfigPpi->Revision =3D 1; + FspmArchConfigPpi->NvsBufferPtr =3D MemorySavedData; + MiscPeiPreMemConfig->S3DataPtr =3D MemorySavedData; + + FspmArchConfigPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (s= izeof (EFI_PEI_PPI_DESCRIPTOR)); + if (FspmArchConfigPpiDesc =3D=3D NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + FspmArchConfigPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PP= I_DESCRIPTOR_TERMINATE_LIST; + FspmArchConfigPpiDesc->Guid =3D &gFspmArchConfigPpiGuid; + FspmArchConfigPpiDesc->Ppi =3D FspmArchConfigPpi; + + // + // Install FSP-M Arch Config PPI + // + Status =3D PeiServicesInstallPpi (FspmArchConfigPpiDesc); + ASSERT_EFI_ERROR (Status); + + VariableSize =3D sizeof (MorControl); + Status =3D VariableServices->GetVariable( + VariableServices, + MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME, + &gEfiMemoryOverwriteControlDataGuid, + NULL, + &VariableSize, + &MorControl + ); + if (EFI_ERROR (Status)) { + MorControl =3D 0; + } + + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.UserBd, MiscPeiPre= MemConfig->UserBd, 0); // It's a CRB mobile board by default (btCRBMB) + + MiscPeiPreMemConfig->TxtImplemented =3D 0; + + if (PcdGet32 (PcdMrcRcompTarget)) { + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.RcompTarget, (= VOID *)RcompData->RcompTarget, (VOID *)(UINTN)PcdGet32 (PcdMrcRcompTarget),= sizeof (UINT16) * MRC_MAX_RCOMP_TARGETS); + } + + if (PcdGetBool (PcdMrcDqPinsInterleavedControl)) { + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.DqPinsInterleaved, M= emConfig->DqPinsInterleaved, PcdGetBool (PcdMrcDqPinsInterleaved)); + } + + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[0], Mi= scPeiPreMemConfig->SpdAddressTable[0], PcdGet8 (PcdMrcSpdAddressTable0)); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[1], Mi= scPeiPreMemConfig->SpdAddressTable[1], PcdGet8 (PcdMrcSpdAddressTable1)); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[2], Mi= scPeiPreMemConfig->SpdAddressTable[2], PcdGet8 (PcdMrcSpdAddressTable2)); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[3], Mi= scPeiPreMemConfig->SpdAddressTable[3], PcdGet8 (PcdMrcSpdAddressTable3)); + if (PcdGet8 (PcdMrcLp5CccConfig)) { + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.Lp5CccConfig, MemCon= fig->Lp5CccConfig, PcdGet8 (PcdMrcLp5CccConfig)); + } + + + NullSpdPtr =3D AllocateZeroPool (SPD_DATA_SIZE); + ASSERT (NullSpdPtr !=3D NULL); + + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[4], Mi= scPeiPreMemConfig->SpdAddressTable[4], PcdGet8 (PcdMrcSpdAddressTable4)); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[5], Mi= scPeiPreMemConfig->SpdAddressTable[5], PcdGet8 (PcdMrcSpdAddressTable5)); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[6], Mi= scPeiPreMemConfig->SpdAddressTable[6], PcdGet8 (PcdMrcSpdAddressTable6)); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[7], Mi= scPeiPreMemConfig->SpdAddressTable[7], PcdGet8 (PcdMrcSpdAddressTable7)); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[8], Mi= scPeiPreMemConfig->SpdAddressTable[8], PcdGet8 (PcdMrcSpdAddressTable8)); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[9], Mi= scPeiPreMemConfig->SpdAddressTable[9], PcdGet8 (PcdMrcSpdAddressTable9)); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[10], M= iscPeiPreMemConfig->SpdAddressTable[10], PcdGet8 (PcdMrcSpdAddressTable10))= ; + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[11], M= iscPeiPreMemConfig->SpdAddressTable[11], PcdGet8 (PcdMrcSpdAddressTable11))= ; + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[12], M= iscPeiPreMemConfig->SpdAddressTable[12], PcdGet8 (PcdMrcSpdAddressTable12))= ; + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[13], M= iscPeiPreMemConfig->SpdAddressTable[13], PcdGet8 (PcdMrcSpdAddressTable13))= ; + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[14], M= iscPeiPreMemConfig->SpdAddressTable[14], PcdGet8 (PcdMrcSpdAddressTable14))= ; + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[15], M= iscPeiPreMemConfig->SpdAddressTable[15], PcdGet8 (PcdMrcSpdAddressTable15))= ; + if (PcdGet32 (PcdMrcRcompResistor)) { + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.RcompResistor, Rcomp= Data->RcompResistor, (UINT8) PcdGet32 (PcdMrcRcompResistor)); + } + if (PcdGet32 (PcdMrcDqsMapCpu2Dram)) { + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.DqsMapCpu2Dram= Mc0Ch0, (VOID *)MemConfigNoCrc->DqDqsMap->DqsMapCpu2Dram, (VOID *)(UINTN)Pc= dGet32 (PcdMrcDqsMapCpu2Dram), sizeof (UINT8) * MEM_CFG_MAX_CONTROLLERS * M= EM_CFG_MAX_CHANNELS * MEM_CFG_NUM_BYTES_MAPPED); + } + if (PcdGet32 (PcdMrcDqMapCpu2Dram)) { + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.DqMapCpu2DramM= c0Ch0, (VOID *)MemConfigNoCrc->DqDqsMap->DqMapCpu2Dram, (VOID *)(UINTN)PcdG= et32 (PcdMrcDqMapCpu2Dram), sizeof (UINT8) * MEM_CFG_MAX_CONTROLLERS * MEM_= CFG_MAX_CHANNELS * MEM_CFG_NUM_BYTES_MAPPED * 8); + } + if (PcdGetBool (PcdSpdPresent)) { + // Clear SPD data so it can be filled in by the MRC init code + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr00= 0, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][0][0], (VOID *)(UINT32) Nul= lSpdPtr, SPD_DATA_SIZE); + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr01= 0, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][1][0], (VOID *)(UINT32) Nul= lSpdPtr, SPD_DATA_SIZE); + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr02= 0, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][2][0], (VOID *)(UINT32) Nul= lSpdPtr, SPD_DATA_SIZE); + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr03= 0, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][3][0], (VOID *)(UINT32) Nul= lSpdPtr, SPD_DATA_SIZE); + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr10= 0, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][0][0], (VOID *)(UINT32) Nul= lSpdPtr, SPD_DATA_SIZE); + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr11= 0, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][1][0], (VOID *)(UINT32) Nul= lSpdPtr, SPD_DATA_SIZE); + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr12= 0, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][2][0], (VOID *)(UINT32) Nul= lSpdPtr, SPD_DATA_SIZE); + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr13= 0, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][3][0], (VOID *)(UINT32) Nul= lSpdPtr, SPD_DATA_SIZE); + } else { + if (PcdGet32 (PcdMrcSpdData)) { + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr= 000, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][0][0], (VOID *)(UINTN)PcdG= et32 (PcdMrcSpdData), SPD_DATA_SIZE); + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr= 010, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][1][0], (VOID *)(UINTN)PcdG= et32 (PcdMrcSpdData), SPD_DATA_SIZE); + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr= 020, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][2][0], (VOID *)(UINTN)PcdG= et32 (PcdMrcSpdData), SPD_DATA_SIZE); + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr= 030, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][3][0], (VOID *)(UINTN)PcdG= et32 (PcdMrcSpdData), SPD_DATA_SIZE); + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr= 100, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][0][0], (VOID *)(UINTN)PcdG= et32 (PcdMrcSpdData), SPD_DATA_SIZE); + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr= 110, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][1][0], (VOID *)(UINTN)PcdG= et32 (PcdMrcSpdData), SPD_DATA_SIZE); + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr= 120, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][2][0], (VOID *)(UINTN)PcdG= et32 (PcdMrcSpdData), SPD_DATA_SIZE); + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr= 130, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][3][0], (VOID *)(UINTN)PcdG= et32 (PcdMrcSpdData), SPD_DATA_SIZE); + } + } + + HostBridgePreMemConfig->MchBar =3D (UINTN) PcdGet64 (PcdMchBaseAddress= ); + HostBridgePreMemConfig->DmiBar =3D (UINTN) PcdGet64 (PcdDmiBaseAddress= ); + HostBridgePreMemConfig->EpBar =3D (UINTN) PcdGet64 (PcdEpBaseAddress)= ; + HostBridgePreMemConfig->EdramBar =3D (UINTN) PcdGet64 (PcdEdramBaseAddre= ss); + MiscPeiPreMemConfig->SmbusBar =3D (UINTN) PcdGet16 (PcdSmbusBaseAddress)= ; + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.TsegSize, Mi= scPeiPreMemConfig->TsegSize, PcdGet32 (PcdTsegSize)); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.UserBd, Mi= scPeiPreMemConfig->UserBd, PcdGet8 (PcdSaMiscUserBd)); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.DisableMrcRetrainingOn= RtcPowerLoss,MiscPeiPreMemConfig->DisableMrcRetrainingOnRtcPowerLoss, Pcd= Get8(PcdSaMiscDisableMrcRetrainingOnRtcPowerLoss)); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.MmioSizeAdjustment, Ho= stBridgePreMemConfig->MmioSizeAdjustment, PcdGet16 (PcdSaMiscMmioSizeAdjust= ment)); + // + // Display DDI Initialization ( default Native GPIO as per board during = AUTO case) + // + CopyMem (SaDisplayConfigTable, (VOID *) (UINTN) PcdGet32 (PcdSaDisplayCo= nfigTable), (UINTN)PcdGet16 (PcdSaDisplayConfigTableSize)); + + gWdtPei =3D NULL; + Status =3D PeiServicesLocatePpi( + &gWdtPpiGuid, + 0, + NULL, + (VOID **) &gWdtPei + ); + if (gWdtPei !=3D NULL) { + WdtTimeout =3D gWdtPei->CheckStatus(); + } else { + WdtTimeout =3D FALSE; + } + + if ((WdtTimeout =3D=3D FALSE)) { + // + // If USER custom profile is selected, we will start the WDT. + // + if (gWdtPei !=3D NULL) { + Status =3D gWdtPei->ReloadAndStart(WDT_TIMEOUT); + } + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.VddVoltage, MemCon= fig->VddVoltage, 0); // Use platform default as the safe value. + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.VddqVoltage, MemCon= fig->VddqVoltage, 0); // Use platform default as the safe value. + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.VppVoltage, MemCon= fig->VppVoltage, 0); // Use platform default as the safe value. + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.Ratio, MemCon= fig->Ratio, 0); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tCL, MemCon= fig->tCL, 0); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tCWL, MemCon= fig->tCWL, 0); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tFAW, MemCon= fig->tFAW, 0); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRAS, MemCon= fig->tRAS, 0); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRCDtRP, MemCon= fig->tRCDtRP, 0); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tREFI, MemCon= fig->tREFI, 0); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRFC, MemCon= fig->tRFC, 0); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRRD, MemCon= fig->tRRD, 0); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRTP, MemCon= fig->tRTP, 0); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tWR, MemCon= fig->tWR, 0); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tWTR, MemCon= fig->tWTR, 0); + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.NModeSupport, MemCon= fig->NModeSupport, 0); + } + + + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.CmdMirror, = MemConfig->CmdMirror, PcdGet8 (PcdMrcCmdMirror)= ); // BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are= Controller 1 Channel [3:0]. 0 =3D No Command Mirror and 1 =3D Command Mir= ror. + + // FirstDimmBitMask defines which DIMM should be populated first on a 2D= PC board + + COMPARE_AND_UPDATE_POLICY(((FSPM_UPD *)FspmUpd)->FspmConfig.FirstDimmBit= Mask, MemConfig->FirstDimmBitMask, PcdGet8(PcdSaMiscFirstDimmBitMask)); + COMPARE_AND_UPDATE_POLICY(((FSPM_UPD *)FspmUpd)->FspmConfig.FirstDimmBit= MaskEcc, MemConfig->FirstDimmBitMaskEcc, PcdGet8(PcdSaMiscFirstDimmBitMaskE= cc)); + + // + // Update CleanMemory variable from Memory overwrite request value. Igno= re if we are performing capsule update. + // + if ((BootMode !=3D BOOT_ON_FLASH_UPDATE) && (BootMode !=3D BOOT_ON_S3_RE= SUME)) { + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.CleanMemory, MemConf= igNoCrc->CleanMemory, (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK)); + } + + DataSize =3D sizeof (MemoryData); + Status =3D VariableServices->GetVariable ( + VariableServices, + EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME, + &gEfiMemoryTypeInformationGuid, + NULL, + &DataSize, + &MemoryData + ); + /// + /// Accumulate maximum amount of memory needed + /// + PlatformMemorySize =3D MemConfigNoCrc->PlatformMemorySize; + AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, &Ebx.Uint3= 2, NULL, NULL); + + if (EFI_ERROR (Status)) { + /// + /// Use default value to avoid memory fragment. + /// OS boot/installation fails if there is not enough continuous memor= y available + /// + PlatformMemorySize =3D PEI_MIN_MEMORY_SIZE + ProcessorTraceTotalMemSiz= e + CapsuleSupportMemSize; + DataSize =3D sizeof (mDefaultMemoryTypeInformation); + CopyMem (MemoryData, mDefaultMemoryTypeInformation, DataSize); + } else { + /// + /// Start with at least PEI_MIN_MEMORY_SIZE of memory for the DXE Core= and the DXE Stack + /// + PlatformMemorySize =3D PEI_MIN_MEMORY_SIZE + ProcessorTraceTotalMemSiz= e + CapsuleSupportMemSize; + } + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PlatformMemorySize, Me= mConfigNoCrc->PlatformMemorySize, PlatformMemorySize); + + if (BootMode !=3D BOOT_IN_RECOVERY_MODE) { + for (Index =3D 0; Index < DataSize / sizeof (EFI_MEMORY_TYPE_INFORMATI= ON); Index++) { + PlatformMemorySize +=3D MemoryData[Index].NumberOfPages * EFI_PAGE_S= IZE; + } + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PlatformMemorySize, = MemConfigNoCrc->PlatformMemorySize, PlatformMemorySize); + + /// + /// Build the GUID'd HOB for DXE + /// + BuildGuidDataHob ( + &gEfiMemoryTypeInformationGuid, + MemoryData, + DataSize + ); + } + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSilicon= PolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/AlderlakeOpe= nBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLi= b.inf new file mode 100644 index 0000000000..c2bdd599a8 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyU= pdateLib/PeiSiliconPolicyUpdateLib.inf @@ -0,0 +1,65 @@ +## @file +# Provide Silicon policy update functionality. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile= . +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconPolicyUpdateLib + FILE_GUID =3D 34435831-33D7-4742-992F-3A3C7B860BC5 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconPolicyUpdateLib + + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +##########################################################################= ###### +# +# Sources Section - list of files that are required for the build to succe= ed. +# +##########################################################################= ###### + +[Sources] + PeiSiliconPolicyUpdatePreMem.c + PeiSiliconPolicyUpdatePostMem.c + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec + +[LibraryClasses.IA32] + BaseMemoryLib + BaseLib + DebugLib + PeiServicesTablePointerLib + PeiServicesLib + PcdLib + PeiPolicyUpdateLib + +[FixedPcd] + +[Ppis] + +[Guids] diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSilicon= PolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c b/Platform/Intel/AlderlakeO= penBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdate= PostMem.c new file mode 100644 index 0000000000..181b491c4c --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyU= pdateLib/PeiSiliconPolicyUpdatePostMem.c @@ -0,0 +1,39 @@ +/** @file + This file is SampleCode for Intel PEI Platform Policy initialization in = post-memory. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +VOID +EFIAPI +SiliconPolicyUpdatePostMemFirmwareConfig ( + VOID + ) +{ + // + // Update and override all platform related and customized settings be= low. + // + UpdatePeiPchPolicy (); + UpdatePeiSaPolicy (); + UpdatePeiCpuPolicy (); +} + +VOID * +EFIAPI +SiliconPolicyUpdatePostMem ( + IN OUT VOID *Policy + ) +{ + Policy =3D NULL; + + SiliconPolicyUpdatePostMemFirmwareConfig (); + + return Policy; +} diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSilicon= PolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOp= enBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateP= reMem.c new file mode 100644 index 0000000000..42e6ac34c2 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyU= pdateLib/PeiSiliconPolicyUpdatePreMem.c @@ -0,0 +1,37 @@ +/** @file + This file is SampleCode for Intel PEI Platform Policy initialization in = pre-memory. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +VOID +EFIAPI +SiliconPolicyUpdatePreMemFirmwareConfig ( + VOID + ) +{ + UpdatePeiPchPolicyPreMem (); + UpdatePeiSaPolicyPreMem (); + UpdatePeiCpuPolicyPreMem (); +} + + +VOID * +EFIAPI +SiliconPolicyUpdatePreMem ( + IN OUT VOID *Policy + ) +{ + Policy =3D NULL; + + SiliconPolicyUpdatePreMemFirmwareConfig (); + + return Policy; +} --=20 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#107583): https://edk2.groups.io/g/devel/message/107583 Mute This Topic: https://groups.io/mt/100494312/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-