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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rosen.chuang@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: fthg5HADeEupOkhJctnNYru2x7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=Jr7oLSTI; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") Reviewed-by: Rosen Chuang < rosen.chuang@intel.com> Thanks, Rosen -----Original Message----- From: Kasbekar, Saloni =20 Sent: Saturday, August 5, 2023 1:38 AM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Oram, Isaac W ; Chuang, Rosen Subject: [PATCH v2 4/7] AlderlakeSiliconPkg/Pch: Add libraries Adds the following libraries: - BasePchPciBdfLib - BaseResetSystemLib - PeiDxeSmmPchCycleDecodingLib Cc: Sai Chaganty Cc: Nate DeSimone Cc: Isaac Oram Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../BasePchPciBdfLib/BasePchPciBdfLib.inf | 32 ++ .../Library/BasePchPciBdfLib/PchPciBdfLib.c | 308 ++++++++++++++++++ .../BaseResetSystemLib/BaseResetSystemLib.c | 114 +++++++ .../BaseResetSystemLib/BaseResetSystemLib.inf | 37 +++ .../PchCycleDecodingLib.c | 194 +++++++++++ .../PeiDxeSmmPchCycleDecodingLib.inf | 41 +++ 6 files changed, 726 insertions(+) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPc= iBdfLib/BasePchPciBdfLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPc= iBdfLib/PchPciBdfLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BaseReset= SystemLib/BaseResetSystemLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BaseReset= SystemLib/BaseResetSystemLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/PeiDxeSmm= PchCycleDecodingLib/PchCycleDecodingLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/PeiDxeSmm= PchCycleDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib= /BasePchPciBdfLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BaseP= chPciBdfLib/BasePchPciBdfLib.inf new file mode 100644 index 0000000000..e65f564c1b --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/Bas +++ ePchPciBdfLib.inf @@ -0,0 +1,32 @@ +## @file +# PCH PCIe Bus Device Function Library. +# +# All functions from this library are available in PEI, DXE, and SMM, #=20 +But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchPciBdfLib +FILE_GUID =3D A36363FC-2951-4DCF-AC81-16F4ED3FDA47 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchPciBdfLib + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PciSegmentLib +PchInfoLib +PchPcieRpLib + +[Packages] +MdePkg/MdePkg.dec +AlderlakeSiliconPkg/SiPkg.dec + +[Sources] +PchPciBdfLib.c diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib= /PchPciBdfLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciB= dfLib/PchPciBdfLib.c new file mode 100644 index 0000000000..c26625e2eb --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/Pch +++ PciBdfLib.c @@ -0,0 +1,308 @@ +/** @file + PCH PCIe Bus Device Function Library. + All functions from this library are available in PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Check if a Device is present for PCH FRU + If the data is defined for PCH RFU return it + If the data is not defined (Device is NOT present) assert. + + @param[in] DataToCheck Device or Function number to check + + @retval Device or Function number value if defined for PCH FRU + 0xFF if not present in PCH FRU **/ +UINT8 +CheckAndReturn ( + UINT8 DataToCheck + ) +{ + if (DataToCheck =3D=3D NOT_PRESENT) { + ASSERT (FALSE); + } + return DataToCheck; +} + +/** + Get P2SB PCI device number + + @retval PCI dev number +**/ +UINT8 +P2sbDevNumber ( + VOID + ) +{ + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_P2SB); } + +/** + Get P2SB PCI function number + + @retval PCI fun number +**/ +UINT8 +P2sbFuncNumber ( + VOID + ) +{ + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_P2SB); } + +/** + Get P2SB controller address that can be passed to the PCI Segment Librar= y functions. + + @retval P2SB controller address in PCI Segment Library representation=20 +**/ +UINT64 +P2sbPciCfgBase ( + VOID + ) +{ + return PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + P2sbDevNumber (), + P2sbFuncNumber (), + 0 + ); +} + + + +/** + Returns PCH SPI Device number + + @retval UINT8 PCH SPI Device number +**/ +UINT8 +SpiDevNumber ( + VOID + ) +{ + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SPI); } + +/** + Returns PCH SPI Function number + + @retval UINT8 PCH SPI Function number +**/ +UINT8 +SpiFuncNumber ( + VOID + ) +{ + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SPI); } + +/** + Returns PCH SPI PCI Config Space base address + + @retval UINT64 PCH SPI Config Space base address **/ +UINT64 +SpiPciCfgBase ( + VOID + ) +{ + return PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + SpiDevNumber (), + SpiFuncNumber (), + 0 + ); +} + +/** + Get XHCI controller PCIe Device Number + + @retval XHCI controller PCIe Device Number **/ +UINT8 +PchXhciDevNumber ( + VOID + ) +{ + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_XHCI); } + +/** + Get XHCI controller PCIe Function Number + + @retval XHCI controller PCIe Function Number **/ +UINT8 +PchXhciFuncNumber ( + VOID + ) +{ + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_XHCI); } + +/** + Get LPC controller PCIe Device Number + + @retval LPC controller PCIe Device Number **/ +UINT8 +LpcDevNumber ( + VOID + ) +{ + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_LPC); } + +/** + Get LPC controller PCIe Function Number + + @retval LPC controller PCIe Function Number **/ +UINT8 +LpcFuncNumber ( + VOID + ) +{ + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_LPC); } + +/** + Returns PCH LPC device PCI base address. + + @retval PCH LPC PCI base address. +**/ +UINT64 +LpcPciCfgBase ( + VOID + ) +{ + return PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + LpcDevNumber (), + LpcFuncNumber (), + 0 + ); +} + + + +/** + Get PCH PCIe controller PCIe Device Number + + @param[in] RpIndex Root port physical number. (0-based) + + @retval PCH PCIe controller PCIe Device Number **/ +UINT8 +PchPcieRpDevNumber ( + IN UINTN RpIndex + ) +{ + switch (RpIndex) { + case 0: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1); + case 1: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_2); + case 2: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_3); + case 3: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_4); + case 4: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5); + case 5: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_6); + case 6: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_7); + case 7: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_8); + case 8: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9); + case 9: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_10); + case 10: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_11); + case 11: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_12); + case 12: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13); + case 13: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_14); + case 14: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_15); + case 15: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_16); + case 16: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17); + case 17: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_18); + case 18: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_19); + case 19: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_20); + case 20: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21); + case 21: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_22); + case 22: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_23); + case 23: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_24); + case 24: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25); + case 25: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26); + case 26: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27); + case 27: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28); + + default: + ASSERT (FALSE); + return 0xFF; + } +} + +/** + Get PCH PCIe controller PCIe Function Number + Note: + For Client PCH generations Function Number can be various + depending on "Root Port Function Swapping". For such cases + Function Number MUST be obtain from proper register. + For Server PCHs we have no "Root Port Function Swapping" + and we can return fixed Function Number. + To address this difference in this, PCH generation independent, + library we should call specific function in PchPcieRpLib. + + @param[in] RpIndex Root port physical number. (0-based) + + @retval PCH PCIe controller PCIe Function Number **/ +UINT8 +PchPcieRpFuncNumber ( + IN UINTN RpIndex + ) +{ + UINTN Device; + UINTN Function; + + GetPchPcieRpDevFun (RpIndex, &Device, &Function); + + return (UINT8)Function; +} + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BaseResetSystemL= ib/BaseResetSystemLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/Bas= eResetSystemLib/BaseResetSystemLib.c new file mode 100644 index 0000000000..86eeff9407 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BaseResetSystemLib/B +++ aseResetSystemLib.c @@ -0,0 +1,114 @@ +/** @file + System reset library services. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include =20 +#include #include #include=20 + #include #include=20 + #include #include=20 + + +/** + Calling this function causes a system-wide reset. This sets + all circuitry within the system to its initial state. This type of=20 +reset + is asynchronous to system operation and operates without regard to + cycle boundaries. + + System reset should not return, if it returns, it means the system=20 +does + not support cold reset. +**/ +VOID +EFIAPI +ResetCold ( + VOID + ) +{ + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET); } + +/** + Calling this function causes a system-wide initialization. The=20 +processors + are set to their initial state, and pending cycles are not corrupted. + + System reset should not return, if it returns, it means the system=20 +does + not support warm reset. +**/ +VOID +EFIAPI +ResetWarm ( + VOID + ) +{ + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_HARDRESET); } + +/** + Calling this function causes the system to enter a power state=20 +equivalent + to the ACPI G2/S5 or G3 states. + + System shutdown should not return, if it returns, it means the system=20 +does + not support shut down reset. +**/ +VOID +EFIAPI +ResetShutdown ( + VOID + ) +{ + UINT16 ABase; + UINT32 Data32; + + ABase =3D PmcGetAcpiBase (); + + /// + /// Firstly, GPE0_EN should be disabled to avoid any GPI waking up=20 + the system from S5 /// + IoWrite32 (ABase + R_ACPI_IO_GPE0_EN_127_96, 0); + + /// + /// Secondly, PwrSts register must be cleared /// /// Write a "1"=20 + to bit[8] of power button status register at /// (PM_BASE +=20 + PM1_STS_OFFSET) to clear this bit /// + IoWrite16 (ABase + R_ACPI_IO_PM1_STS, B_ACPI_IO_PM1_STS_PWRBTN); + + /// + /// Finally, transform system into S5 sleep state /// + Data32 =3D IoRead32 (ABase + R_ACPI_IO_PM1_CNT); + + Data32 =3D (UINT32) ((Data32 &~(B_ACPI_IO_PM1_CNT_SLP_TYP +=20 + B_ACPI_IO_PM1_CNT_SLP_EN)) | V_ACPI_IO_PM1_CNT_S5); + + IoWrite32 (ABase + R_ACPI_IO_PM1_CNT, Data32); + + Data32 =3D Data32 | B_ACPI_IO_PM1_CNT_SLP_EN; + + IoWrite32 (ABase + R_ACPI_IO_PM1_CNT, Data32); + + return; +} + +/** + Calling this function causes the system to enter a power state for platf= orm specific. + + @param[in] DataSize The size of ResetData in bytes. + @param[in] ResetData Optional element used to introduce a pla= tform specific reset. + The exact type of the reset is defined b= y the EFI_GUID that follows + the Null-terminated Unicode string. + +**/ +VOID +EFIAPI +ResetPlatformSpecific ( + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ) +{ + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET); } diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BaseResetSystemL= ib/BaseResetSystemLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/B= aseResetSystemLib/BaseResetSystemLib.inf new file mode 100644 index 0000000000..f0a987d671 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BaseResetSystemLib/B +++ aseResetSystemLib.inf @@ -0,0 +1,37 @@ +## @file +# Component description file for Intel Ich7 Reset System Library. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D BaseResetSystemLib +FILE_GUID =3D D4FF05AA-3C7D-4B8A-A1EE-AA5EFA0B1732 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +UEFI_SPECIFICATION_VERSION =3D 2.00 +LIBRARY_CLASS =3D ResetSystemLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF +# + +[LibraryClasses] +IoLib +BaseLib +DebugLib +PmcLib + + +[Packages] +MdePkg/MdePkg.dec +AlderlakeSiliconPkg/SiPkg.dec + + +[Sources] +BaseResetSystemLib.c + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycl= eDecodingLib/PchCycleDecodingLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Pch/= Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c new file mode 100644 index 0000000000..ccdac7c5ab --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDec +++ odingLib/PchCycleDecodingLib.c @@ -0,0 +1,194 @@ +/** @file + PCH cycle decoding configuration and query library. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include =20 +#include #include #include=20 + #include #include=20 + #include #include=20 + #include #include=20 + #include #include=20 + #include #include=20 + #include #include=20 + + +typedef enum { + SlaveLpcEspiCS0, + SlaveEspiCS1, + SlaveId_Max +} SLAVE_ID_INDEX; + +/** + Get PCH TCO base address. + + @param[out] Address Address of TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +PchTcoBaseGet ( + OUT UINT16 *Address + ) +{ + if (Address =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "PchTcoBaseGet Error. Invalid pointer.\n")); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + // + // Read "TCO Base Address" from DMI + // Don't read TCO base address from SMBUS PCI register since SMBUS might= be disabled. + // + *Address =3D PchDmiGetTcoBase (); + + return EFI_SUCCESS; +} + +/** + Set PCH LPC/eSPI IO decode ranges. + Program LPC/eSPI I/O Decode Ranges in DMI to the same value programmed i= n LPC/eSPI PCI offset 80h. + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition. + Bit 12: FDD range + Bit 9:8: LPT range + Bit 6:4: ComB range + Bit 2:0: ComA range + + @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit sett= ings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchLpcIoDecodeRangesSet ( + IN UINT16 LpcIoDecodeRanges + ) +{ + UINT64 LpcBaseAddr; + EFI_STATUS Status; + + // + // Note: Inside this function, don't use debug print since it's could us= ed before debug print ready. + // + + LpcBaseAddr =3D LpcPciCfgBase (); + + // + // check if setting is identical + // + if (LpcIoDecodeRanges =3D=3D PciSegmentRead16 (LpcBaseAddr + R_LPC_CFG_I= OD)) { + return EFI_SUCCESS; + } + + Status =3D PchDmiSetLpcIoDecodeRanges (LpcIoDecodeRanges); if=20 + (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // program LPC/eSPI PCI offset 80h. + // + PciSegmentWrite16 (LpcBaseAddr + R_LPC_CFG_IOD, LpcIoDecodeRanges); + + return Status; +} + +/** + Set PCH LPC/eSPI and eSPI CS1# IO enable decoding. + Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offse= t 82h (LPC, eSPI CS0#) or A0h (eSPI CS1#). + Note: Bit[15:10] of the source decode register is Read-Only. The IO=20 +range indicated by the Enables field + in LPC/eSPI PCI offset 82h[13:10] or A0h[13:10] is always forwarded by D= MI to subtractive agent for handling. + Please check EDS for detail of Lpc/eSPI IO decode ranges bit definition. + + @param[in] IoEnableDecoding LPC/eSPI IO enable decoding bit se= ttings. + @param[in] SlaveId Target ID (refer to SLAVE_ID_INDEX= ) + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMI configuration is locked +**/ +EFI_STATUS +LpcEspiIoEnableDecodingSetHelper ( + IN UINT16 IoEnableDecoding, + IN SLAVE_ID_INDEX SlaveId + ) +{ + UINT64 LpcBaseAddr; + EFI_STATUS Status; + UINT16 Cs1IoEnableDecodingOrg; + UINT16 Cs0IoEnableDecodingOrg; + UINT16 IoEnableDecodingMerged; + + LpcBaseAddr =3D LpcPciCfgBase (); + + Cs0IoEnableDecodingOrg =3D PciSegmentRead16 (LpcBaseAddr +=20 + R_LPC_CFG_IOE); + + if (IsEspiSecondSlaveSupported ()) { + Cs1IoEnableDecodingOrg =3D PciSegmentRead16 (LpcBaseAddr +=20 + R_ESPI_CFG_CS1IORE); } else { + Cs1IoEnableDecodingOrg =3D 0; + } + + if (SlaveId =3D=3D SlaveEspiCS1) { + if (IoEnableDecoding =3D=3D Cs1IoEnableDecodingOrg) { + return EFI_SUCCESS; + } else { + IoEnableDecodingMerged =3D (Cs0IoEnableDecodingOrg | IoEnableDecodin= g); + } + } else { + if ((IoEnableDecoding | Cs1IoEnableDecodingOrg) =3D=3D Cs0IoEnableDeco= dingOrg) { + return EFI_SUCCESS; + } else { + IoEnableDecodingMerged =3D (Cs1IoEnableDecodingOrg | IoEnableDecodin= g); + } + } + + Status =3D PchDmiSetLpcIoEnable (IoEnableDecodingMerged); if=20 + (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // program PCI offset 82h for LPC/eSPI. + // + PciSegmentWrite16 (LpcBaseAddr + R_LPC_CFG_IOE,=20 + IoEnableDecodingMerged); + + if (SlaveId =3D=3D SlaveEspiCS1) { + // + // For eSPI CS1# device program eSPI PCI offset A0h. + // + PciSegmentWrite16 (LpcBaseAddr + R_ESPI_CFG_CS1IORE,=20 + IoEnableDecoding); } + + return Status; +} + +/** + Set PCH LPC and eSPI CS0# IO enable decoding. + Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offse= t 82h. + Note: Bit[15:10] of the source decode register is Read-Only. The IO=20 +range indicated by the Enables field + in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to subtract= ive agent for handling. + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition. + + @param[in] LpcIoEnableDecoding LPC IO enable decoding bit setting= s. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchLpcIoEnableDecodingSet ( + IN UINT16 LpcIoEnableDecoding + ) +{ + return LpcEspiIoEnableDecodingSetHelper (LpcIoEnableDecoding,=20 +SlaveLpcEspiCS0); } diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycl= eDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf b/Silicon/Intel/AlderlakeSili= conPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PeiDxeSmmPchCycleDecodingLi= b.inf new file mode 100644 index 0000000000..a381c0f0f7 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDec +++ odingLib/PeiDxeSmmPchCycleDecodingLib.inf @@ -0,0 +1,41 @@ +## @file +# PCH cycle decoding Lib. +# +# All function in this library is available for PEI, DXE, and SMM, #=20 +But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchCycleDecodingLib FILE_GUID =3D=20 +676C749F-9CD1-46B7-BAFD-4B1BC36B4C8E +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchCycleDecodingLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PciSegmentLib +PchInfoLib +PchPcrLib +PchDmiLib +EspiLib +PchPciBdfLib + +[Packages] +MdePkg/MdePkg.dec +AlderlakeSiliconPkg/SiPkg.dec + +[Sources] +PchCycleDecodingLib.c + +[Pcd] +gSiPkgTokenSpaceGuid.PcdSiHpetBaseAddress ## CONSUMES +gSiPkgTokenSpaceGuid.PcdSiIoApicBaseAddress ## CONSUMES -- 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#107778): https://edk2.groups.io/g/devel/message/107778 Mute This Topic: https://groups.io/mt/100551003/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-