From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 6155E7803DA for ; Fri, 15 Sep 2023 13:29:00 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=oVmfgV4P9FZsmojMDLT9KWMwMOssPvjSeEx0EtETU7s=; c=relaxed/simple; d=groups.io; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:From:To:CC:Subject:Thread-Topic:Thread-Index:Date:Message-ID:References:In-Reply-To:Accept-Language:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1694784539; v=1; b=N/gQxvzHz0e7qfxneSXDd917FOxO2r5f2f5vhFwYCRpmQSiYK3NB1GUpYnCxKUhyomfsOYXW U53qBXmk1nK5aZaRBY2PrroyTOEsnfd7R0qB7q0l+6rgcunJ6wjNajZBmgQ7F9IdsKki9JfbCvI 0bbtuVVwsdw3I4TvlQUNAoYk= X-Received: by 127.0.0.2 with SMTP id rMW9YY7687511xYfkZFZ1b0H; Fri, 15 Sep 2023 06:28:59 -0700 X-Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web11.20373.1694784538412203812 for ; Fri, 15 Sep 2023 06:28:58 -0700 X-IronPort-AV: E=McAfee;i="6600,9927,10834"; a="378160846" X-IronPort-AV: E=Sophos;i="6.02,149,1688454000"; d="scan'208";a="378160846" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2023 06:28:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10834"; a="774319083" X-IronPort-AV: E=Sophos;i="6.02,149,1688454000"; d="scan'208";a="774319083" X-Received: from orsmsx601.amr.corp.intel.com ([10.22.229.14]) by orsmga008.jf.intel.com with ESMTP/TLS/AES256-GCM-SHA384; 15 Sep 2023 06:28:57 -0700 X-Received: from orsmsx603.amr.corp.intel.com (10.22.229.16) by ORSMSX601.amr.corp.intel.com (10.22.229.14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Fri, 15 Sep 2023 06:28:57 -0700 X-Received: from orsedg603.ED.cps.intel.com (10.7.248.4) by orsmsx603.amr.corp.intel.com (10.22.229.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32 via Frontend Transport; Fri, 15 Sep 2023 06:28:57 -0700 X-Received: from NAM11-BN8-obe.outbound.protection.outlook.com (104.47.58.168) by edgegateway.intel.com (134.134.137.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.32; Fri, 15 Sep 2023 06:28:56 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=GhtL3/wQTzkljX8OvPxIUmUwJpgh+GyDSDZD0MIy3K7TNyXpa47idjEvCh7VPYRlMO8d676osyAWmBNgxXlGCoVOaJDRXCG1WRwF+pBaHvQDpErvz7xhH5OBMmgil1afA+3tCMdzfHjX/Y908PLx0vVrBjJH6kSvlXQOWOYm6wURMRc/oYIdCE5P+I0j9Yj2wDlpag3bcRD9v7iUkEMTf5sEzXhzr5IQu9rspAmmSzKTuvIeTec62B5lZPHADLBOMmzrM+Skqs6f6duJkVSi0P0+Fps76b+9NBbe5btCJe2PPtk/PHT7IMys3MCQKcBVVWeGYw3UjmaoHZhiAFCR+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=W3fG+Y5dIUYB/l19DcxSnTDaOWfpKMggvJfdHVAyUIQ=; b=dsHHTWljfnMBlhKGXwaR49PWGMsP2SiyEaS1aaAPvp4v+PauAXucGODRJf8zCcu28p6PWyHkS6dlL75SdcCZRXJY+CDBSimCZmFw6Vw88j/MsjJiEpmHBrbHmaT2weZK8wNkVYHYBJrufbUXugdgw2bxTAnqhSFIL+MnXA0/xI3Fwzxi+TdqBgzDJsB07INVXWAxia67nkaoM5/LfQX3So9aqC6nk14Jx3opzlBz/HXLUG11+pkrQm2lvsyXoDmFC0mJB0/pPmzr/2b6tQo6HjrgM3sh58tiCyxI98z7bI7jEPPcmWsYb6lbBPcFaPgggx4P6tYlfCjj7YlOP0bAWw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none X-Received: from PH0PR11MB5626.namprd11.prod.outlook.com (2603:10b6:510:ee::15) by LV3PR11MB8578.namprd11.prod.outlook.com (2603:10b6:408:1b3::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6768.31; Fri, 15 Sep 2023 13:28:52 +0000 X-Received: from PH0PR11MB5626.namprd11.prod.outlook.com ([fe80::68a8:9cc5:ec4d:ca44]) by PH0PR11MB5626.namprd11.prod.outlook.com ([fe80::68a8:9cc5:ec4d:ca44%7]) with mapi id 15.20.6792.021; Fri, 15 Sep 2023 13:28:52 +0000 From: "Chuang, Rosen" To: "Chaganty, Rangasai V" , "Kasbekar, Saloni" , "devel@edk2.groups.io" CC: "Desimone, Nathaniel L" Subject: Re: [edk2-devel] [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes Thread-Topic: [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes Thread-Index: AQHZ54+VRkf4UrahukifOly3FpIqtLAbX+0AgACCD0A= Date: Fri, 15 Sep 2023 13:28:52 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PH0PR11MB5626:EE_|LV3PR11MB8578:EE_ x-ms-office365-filtering-correlation-id: 619a1011-d751-4510-0519-08dbb5efb426 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam-message-info: dKEAFllL20TLhqjCgs/6ix+S7KfEjSyWzB8bj7zQ08KsA7FuSpH0uoHreyS6MZJREX2htFawbklMF7SxuknROnx5u5hXGPmL8RX1vbdoSF/YyFICdjsbJDQWmTR6kAHtGJueap/ETazSuya+c2uHpE087ccauDizycLY3SPXrJKHXN0x68cYHbQuRgmh1vIw2yERxiz0ZrHUG67sGTqnPBk1hD2AxLLYYDG5EYOq9A8Cw+dffo6gtL+4TxRY5Pe8tCncqCKsznDy+akfPspY0zhuHb026YsCfqRvdE6ncTjc3pI5M+Vnb4uCiPMV+TnaaptUeLQzd4mt9hq/CUMjQjHpD/Ff6SLz2RXZXRJqjY3ULdjcmMbT68r3dDmAQiLEX+dABkaXIJr4Qep4s/r+xcO9ugjLkRoK31iS0VcHxyPpCHVFZuBq8GeeItBeMaxPGCuQzHUDISQgTJdG90RRHbmxgL8K2JcvKCWHGbujkznIb9tGzA4rIA87GobfORvwbmRlFJ3aY2xdaG6KXXC++gbCttf0aSOOmZO9a32/GsBsOcmAzDxULd/ZCtEfd4R6GG6Qc7SpfTuq70ndH9DJ3cTF9OZMvqPdRUHXq5w1qW7GAs5D10ZOPrpauAjFdhBy x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?o965OYZYeqVXMpzsfWsj6o/Lw0RZwJqw0kzm0QTlDs0+GWYp8fXYWktvw/7+?= =?us-ascii?Q?IgyTaIHZ1oZG/s+V3mtmkIqD2eoG4Jv8Y6jMJiqFR/FmDZdEY4BFS9pWB0NV?= =?us-ascii?Q?OZ7UCaRc7BdRdJ6no9OmyJpcf7oCg0yXezgIHRM31CH2vDzSyPlSUdN6YmHj?= =?us-ascii?Q?fHegY02gDGH6dqeKlzdRG/uuX7bKvEfUL+aGSTNltIFLIQ31yh6X87vi0PnE?= =?us-ascii?Q?coFH38sixamkyQTxK4eJaCXgUaJG+V1QJsZSf2edJt+UdXARiety2wlleZ2I?= =?us-ascii?Q?RSxa5uZF8tQbqY6ztcsj+QP9g6VPPC0u3l8677oyAyZyyYb5mB1ziDGNYkX9?= =?us-ascii?Q?Yvvswq/t8w0MGz+9WDTRZjpxggypt/8eA9XRtXDXdbwrYPbQJHQuluJNXIwU?= =?us-ascii?Q?GiPYKAay2jfmM3gFiXqj2Wm86QQOISFVb6S2l5LlfqZ3BSsuzW+KsxATmMyQ?= =?us-ascii?Q?Cn3c9KsvgfsK8S+xCq2QFzcez8DkqFNEz1VulIiypDoI0TV835zAVhc6WlNJ?= =?us-ascii?Q?HlQPae3NKy1CTyKfmtxY39E+3xXKeh+6iLe0519lca10siH5L/rP2oxavvfv?= =?us-ascii?Q?lcskIvGq0rUtkABFwSgx5v+tCmvZ/pcNJNus/sAZtlNofVjnClcV30ODOo6Y?= =?us-ascii?Q?KwpXPkUFs2eNyEMdikTKY+PWhH6G/7fwDnc8dtEOdtKoUWjohMrqx+hHDf2T?= =?us-ascii?Q?c/MFcn7DX0nFI6zViI5sYqfcdsgdvSAJM1m8W+ibqD306Yf36+jo1Ct0HhsM?= =?us-ascii?Q?bVt8+9xUdIKjZocngSIbxUMwiGdg1Pvvwem8IX4jCMPXPC97EZF16rZZO0K2?= =?us-ascii?Q?ZZbaabWKUm3FlvABaiWqxxhqXmTpPZqiieS2KGhd77R7RKdhgK5DixhYEO8i?= =?us-ascii?Q?/VaTW/HNJvKzfPyjPVoq9n2aVeARi+xipSaqN29z2K1XZyWRG+us+nhSeNiV?= =?us-ascii?Q?Z714ZWs5nV7aw4LOD+CJRfwBeLbOdWlqIiRPMhqdfC01evU2mU5+VGtUVxoU?= =?us-ascii?Q?Ut+1BkQmjyCODinpTPaJCXsilcAUzl7pWJM9VSDR/TVgPha3xXwU7y8OoC+b?= =?us-ascii?Q?9bct8sNt0kmEaS3S8ZYykwamjGOcabMBs3GCcMurGuDHHuCPFe95eryd0q87?= =?us-ascii?Q?RxzlGHoCCHR3iKh0ga+IskB6+z8tgh/tTmjthlntX9ferBFxAMdZLU/Z12mi?= =?us-ascii?Q?IMOxPMALM8Llz+MPXX2dJvur9bnv0pMXn/UgKckP8rn98bUTr/O3xrd47aPR?= =?us-ascii?Q?LZ3l9kVLz4dXgYsOFe9x5/ckyYi9FrwCBR9pgRulGfiYc2BqGrZTH4XwXp+d?= =?us-ascii?Q?oVnAOUnJZCuOQJpSOML+1/dpauETso/AZB8CNDMpWfKzcTl/DD7pXpfPFGEh?= =?us-ascii?Q?cG4XHkImtnqbcq7aRqGNUdyXt/V55iL/D5BT4AbeVTVHmOPPUkYEWP4pcgx+?= =?us-ascii?Q?OopScowepEPQddZ4UurgSftoL9s9uTLP+4wokAIwD1s/Zp11QoSndy1XQqeN?= =?us-ascii?Q?Cs+VI2rSv3GJ3G0ngmeHfzl7eKfV74Snqu12s+HesCEq1ULzcYDV7TozvvD7?= =?us-ascii?Q?jNVGkzyavWxH0lxuN1x3O3LL24tske04GAQltXmy?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH0PR11MB5626.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 619a1011-d751-4510-0519-08dbb5efb426 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Sep 2023 13:28:52.7095 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: rk4VgoxphM/fozCQdvLjAE2uUKeXpn5RaS9vVBFay3Wc9NDKHaKeOE3j0EtTevsw1pQ9UIjKvc54GJ6whlcbtg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR11MB8578 X-OriginatorOrg: intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rosen.chuang@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: FGA5SP9nAnNdRsOBxWYP2o3yx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="N/gQxvzH"; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Reviewed-by: Rosen Chuang -----Original Message----- From: Chaganty, Rangasai V =20 Sent: Friday, September 15, 2023 1:43 PM To: Kasbekar, Saloni ; devel@edk2.groups.io Cc: Desimone, Nathaniel L ; Chuang, Rosen <= rosen.chuang@intel.com> Subject: RE: [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Re= gister, Other Includes Reviewed-by: Sai Chaganty -----Original Message----- From: Kasbekar, Saloni =20 Sent: Thursday, September 14, 2023 9:46 PM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Chuang, Rosen Subject: [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Regist= er, Other Includes Adds the following Includes: - Include/ - Include/Protocol - Include/Register Cc: Sai Chaganty Cc: Nate DeSimone Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../AlderlakeSiliconPkg/Include/ConfigBlock.h | 53 +++ .../AlderlakeSiliconPkg/Include/CpuPcieHob.h | 48 +++ .../Include/Protocol/IgdOpRegion.h | 22 ++ .../Include/Protocol/Spi.h | 346 ++++++++++++++++++ .../Include/Protocol/Wdt.h | 111 ++++++ .../Include/Register/FlashRegs.h | 73 ++++ .../Include/Register/GpioRegs.h | 103 ++++++ .../Include/Register/GpioRegsVer2.h | 211 +++++++++++ .../Include/Register/PchDmi14Regs.h | 49 +++ .../Include/Register/PchDmiRegs.h | 51 +++ .../Include/Register/PchPcieRpRegs.h | 45 +++ .../Include/Register/PchRegsLpc.h | 77 ++++ .../Include/Register/PmcRegs.h | 134 +++++++ .../Include/Register/RtcRegs.h | 44 +++ .../Include/Register/TcoRegs.h | 71 ++++ .../Include/SerialIoDevices.h | 226 ++++++++++++ .../AlderlakeSiliconPkg/Include/SiConfigHob.h | 17 + .../Include/SiPolicyStruct.h | 64 ++++ 18 files changed, 1745 insertions(+) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdO= pRegion.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.= h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.= h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/Flas= hRegs.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/Gpio= Regs.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/Gpio= RegsVer2.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchD= mi14Regs.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchD= miRegs.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchP= cieRpRegs.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchR= egsLpc.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcR= egs.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcR= egs.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoR= egs.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevic= es.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruc= t.h diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h b/Sili= con/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h new file mode 100644 index 0000000000..2e609bc8d9 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h @@ -0,0 +1,53 @@ +/** @file + Header file for Config Block Lib implementation + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CONFIG_BLOCK_H_ +#define _CONFIG_BLOCK_H_ + +#include +#include +#include +#include + +#pragma pack (push,1) + +/// +/// Config Block Header +/// +typedef struct _CONFIG_BLOCK_HEADER { + EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID e= xtension HOB header + UINT8 Revision; ///< Offset 24 Revisi= on of this config block + UINT8 Attributes; ///< Offset 25 The ma= in revision for config block + UINT8 Reserved[2]; ///< Offset 26-27 Reserv= ed for future use +} CONFIG_BLOCK_HEADER; + +/// +/// Config Block +/// +typedef struct _CONFIG_BLOCK { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Header= of config block + // + // Config Block Data + // +} CONFIG_BLOCK; + +/// +/// Config Block Table Header +/// +typedef struct _CONFIG_BLOCK_TABLE_STRUCT { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 GUID n= umber for main entry of config block + UINT8 Rsvd0[2]; ///< Offset 28-29 Reserv= ed for future use + UINT16 NumberOfBlocks; ///< Offset 30-31 Number= of config blocks (N) + UINT32 AvailableSize; ///< Offset 32-35 Curren= t config block table size +/// +/// Individual Config Block Structures are added here in memory as part of= AddConfigBlock() +/// +} CONFIG_BLOCK_TABLE_HEADER; +#pragma pack (pop) + +#endif // _CONFIG_BLOCK_H_ + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h b/Silic= on/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h new file mode 100644 index 0000000000..dccd6e7d7a --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h @@ -0,0 +1,48 @@ +/** @file + The GUID definition for CpuPcieHob + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _CPU_PCIE_HOB_H_ +#define _CPU_PCIE_HOB_H_ + +#include +#include +#include + +extern EFI_GUID gCpuPcieHobGuid; +#pragma pack (push,1) + + +/** + The CPU_PCIE_HOB block describes the expected configuration of the CpuPc= ie controllers +**/ +typedef struct { + /// + /// These members describe the configuration of each CPU PCIe root port. + /// + EFI_HOB_GUID_TYPE EfiHobGuidType; //= /< Offset 0 - 23: GUID Hob type structure for gCpuPcieHobGuid + CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS]; + UINT8 L1SubStates[CPU_PCIE_MAX_ROOT_PORTS]; ///< = The L1 Substates configuration of the root port + + UINT32 DekelFwVersionMinor; //= /< Dekel Firmware Minor Version + UINT32 DekelFwVersionMajor; //= /< Dekel Firmware Major Version + BOOLEAN InitPcieAspmAfterOprom; //= /< 1=3Dinitialize PCIe ASPM after Oprom; 0=3Dbefore (This will be set basin= g on policy) + UINT32 RpEnabledMask; //= /< Rootport enabled mask based on DEVEN register + UINT32 RpEnMaskFromDevEn; //= /< Rootport enabled mask based on Device Id + UINT8 DisableClkReqMsg[CPU_PCIE_MAX_ROOT_PORTS]; = ///< 1=3DClkReqMsg disabled, 0=3DClkReqMsg enabled + UINT8 SlotSelection; //= /< 1=3DM2 slot, 0=3DCEMx4 slot + BOOLEAN ComplianceTest; //= /< Compliance Test based on policy + UINT32 HsPhyRecipeVersionMajor; //= /< HS-Phy Recipe Major Version + UINT32 HsPhyRecipeVersionMinor; //= /< HS-Phy Recipe Minor Version + UINT32 HsPhyFwProdMajor; //= /< HS-Phy Firmware Product Major Verison + UINT32 HsPhyFwProdMinor; //= /< HS-Phy Firmware Product Minor Verison + UINT32 HsPhyFwHotFix; //= /< HS-Phy Firmware Hot Fix Version + UINT32 HsPhyFwBuild; //= /< HS-Phy Firmware Build version + UINT32 HsPhyFwEvBitProgMajor; //= /< HS-Phy Firmware EV Bit Prog Major + UINT32 HsPhyFwEvBitProgMinor; //= /< HS-Phy Firmware EV Bit Prog Minor + UINT32 HsPhyMap; //= /< HS-Phy Mapping Based on HS-Py supported ports +} CPU_PCIE_HOB; +#pragma pack (pop) +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion= .h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h new file mode 100644 index 0000000000..9f69671f35 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h @@ -0,0 +1,22 @@ +/** @file + This file is part of the IGD OpRegion Implementation. The IGD OpRegion = is + an interface between system BIOS, ASL code, and Graphics drivers. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _IGD_OPREGION_PROTOCOL_H_ +#define _IGD_OPREGION_PROTOCOL_H_ + +#include + +extern EFI_GUID gIgdOpRegionProtocolGuid; + +/// +/// IGD OpRegion Protocol +/// +typedef struct { + IGD_OPREGION_STRUCTURE *OpRegion; ///< IGD Operation Region Structure +} IGD_OPREGION_PROTOCOL; + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h b/Sil= icon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h new file mode 100644 index 0000000000..cbf2883fa4 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h @@ -0,0 +1,346 @@ +/** @file + This file defines the PCH SPI Protocol which implements the + Intel(R) PCH SPI Host Controller Compatibility Interface. + + @note The APIs in this file are designed to be backward compatible with + previous versions. Any change in behavior of these APIs will result in + newer version of the API. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_SPI_PROTOCOL_H_ +#define _PCH_SPI_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchSpiProtocolGuid; +extern EFI_GUID gPchSmmSpiProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL; + +// +// SPI protocol data structures and definitions +// + +/** + Flash Region Type +**/ +typedef enum { + FlashRegionDescriptor, + FlashRegionBios, + FlashRegionMe, + FlashRegionGbE, + FlashRegionPlatformData, + FlashRegionDer, + FlashRegionSecondaryBios, + FlashRegionuCodePatch, + FlashRegionEC, + FlashRegionDeviceExpansion2, + FlashRegionIE, + FlashRegion10Gbe_A, + FlashRegion10Gbe_B, + FlashRegion13, + FlashRegion14, + FlashRegion15, + FlashRegionAll, + FlashRegionMax +} FLASH_REGION_TYPE; + +// +// Protocol member functions +// + +/** + Read data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= . + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich + is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a + region for which BIOS has access permiss= ions. + @param[in] ByteCount Number of bytes in the data portion of t= he + SPI cycle. + @param[out] Buffer The Pointer to caller-allocated buffer + containing the dada received. + It is the caller's responsibility to mak= e + sure Buffer is large enough for the tota= l + number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *Buffer + ); + +/** + Write data to the flash part. Remark: Erase may be needed before write t= o the + flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= . + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich + is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a + region for which BIOS has access permiss= ions. + @param[in] ByteCount Number of bytes in the data portion of t= he + SPI cycle. + @param[in] Buffer Pointer to caller-allocated buffer conta= ining + the data sent during the SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_WRITE) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + IN UINT8 *Buffer + ); + +/** + Erase area on the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= . + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich + is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a + region for which BIOS has access permiss= ions. + @param[in] ByteCount Number of bytes in the data portion of t= he + SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_ERASE) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount + ); + +/** + Read SFDP data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= . + @param[in] ComponentNumber The Componen Number for chip select + @param[in] Address The starting byte address for SFDP data = read. + @param[in] ByteCount Number of bytes in SFDP data portion of = the + SPI cycle + @param[out] SfdpData The Pointer to caller-allocated buffer + containing the SFDP data received + It is the caller's responsibility to mak= e + sure Buffer is large enough for the tota= l + number of bytes read + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_SFDP) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *SfdpData + ); + +/** + Read Jedec Id from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= . + @param[in] ComponentNumber The Componen Number for chip select + @param[in] ByteCount Number of bytes in JedecId data portion = of + the SPI cycle, the data size is 3 typica= lly + @param[out] JedecId The Pointer to caller-allocated buffer + containing JEDEC ID received. + It is the caller's responsibility to mak= e + sure Buffer is large enough for the tota= l + number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_JEDEC_ID) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 ByteCount, + OUT UINT8 *JedecId + ); + +/** + Write the status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= . + @param[in] ByteCount Number of bytes in Status data portion o= f the + SPI cycle, the data size is 1 typically + @param[in] StatusValue The Pointer to caller-allocated buffer + containing the value of Status register = writing + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_WRITE_STATUS) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + IN UINT8 *StatusValue + ); + +/** + Read status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= . + @param[in] ByteCount Number of bytes in Status data portion o= f the + SPI cycle, the data size is 1 typically + @param[out] StatusValue The Pointer to caller-allocated buffer + containing the value of Status register = received. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_STATUS) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + OUT UINT8 *StatusValue + ); + +/** + Get the SPI region base and size, based on the enum type + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= . + @param[in] FlashRegionType The Flash Region type for for the base a= ddress + which is listed in the Descriptor. + @param[out] BaseAddress The Flash Linear Address for the Region = 'n' + Base + @param[out] RegionSize The size for the Region 'n' + + @retval EFI_SUCCESS Read success + @retval EFI_INVALID_PARAMETER Invalid region type given + @retval EFI_DEVICE_ERROR The region is not used +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_GET_REGION_ADDRESS) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + OUT UINT32 *BaseAddress, + OUT UINT32 *RegionSize + ); + +/** + Read PCH Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= . + @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA= . + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of + the SPI cycle + @param[out] SoftStrapValue The Pointer to caller-allocated buffer + containing PCH Soft Strap Value. + If the value of ByteCount is 0, the data= type + of SoftStrapValue should be UINT16 and + SoftStrapValue will be PCH Soft Strap Le= ngth. + It is the caller's responsibility to mak= e sure + Buffer is large enough for the total num= ber of + bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_READ_PCH_SOFTSTRAP) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + Read CPU Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= . + @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUS= BA. + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of + the SPI cycle. + @param[out] SoftStrapValue The Pointer to caller-allocated buffer + containing CPU Soft Strap Value. + If the value of ByteCount is 0, the data= type + of SoftStrapValue should be UINT16 and + SoftStrapValue will be PCH Soft Strap Le= ngth + It is the caller's responsibility to mak= e sure + Buffer is large enough for the total num= ber + of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_READ_CPU_SOFTSTRAP) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + These protocols/PPI allows a platform module to perform SPI operations + through the Intel PCH SPI Host Controller Interface. +**/ +struct _PCH_SPI_PROTOCOL { + /** + This member specifies the revision of this structure. This field is + used to indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + PCH_SPI_FLASH_READ FlashRead; ///< Read data fro= m the flash part. + PCH_SPI_FLASH_WRITE FlashWrite; ///< Write data to= the flash part. Remark: Erase may be needed before write to the flash part= . + PCH_SPI_FLASH_ERASE FlashErase; ///< Erase some ar= ea on the flash part. + PCH_SPI_FLASH_READ_SFDP FlashReadSfdp; ///< Read SFDP dat= a from the flash part. + PCH_SPI_FLASH_READ_JEDEC_ID FlashReadJedecId; ///< Read Jedec Id= from the flash part. + PCH_SPI_FLASH_WRITE_STATUS FlashWriteStatus; ///< Write the sta= tus register in the flash part. + PCH_SPI_FLASH_READ_STATUS FlashReadStatus; ///< Read status r= egister in the flash part. + PCH_SPI_GET_REGION_ADDRESS GetRegionAddress; ///< Get the SPI r= egion base and size + PCH_SPI_READ_PCH_SOFTSTRAP ReadPchSoftStrap; ///< Read PCH Soft= Strap Values + PCH_SPI_READ_CPU_SOFTSTRAP ReadCpuSoftStrap; ///< Read CPU Soft= Strap Values +}; + +/** + PCH SPI PPI/PROTOCOL revision number + + Revision 1: Initial version +**/ +#define PCH_SPI_SERVICES_REVISION 1 + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h b/Sil= icon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h new file mode 100644 index 0000000000..a68085fa54 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h @@ -0,0 +1,111 @@ +/** @file + Watchdog Timer protocol + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _DXE_WDT_H_ +#define _DXE_WDT_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gWdtProtocolGuid; +// +// Forward reference for ANSI C compatibility +// +typedef struct _WDT_PROTOCOL WDT_PROTOCOL; + +/** + Reloads WDT with new timeout value and starts it. Also sets Unexpected R= eset bit, which + causes the next reset to be treated as watchdog expiration - unless Allo= wKnownReset() + function was called too. + + @param[in] TimeoutValue Time in seconds before WDT times out. Su= pported range =3D 1 - 1024. + + @retval EFI_SUCCESS if everything's OK + @retval EFI_INVALID_PARAMETER if TimeoutValue parameter is wrong +**/ +typedef +EFI_STATUS +(EFIAPI *WDT_RELOAD_AND_START) ( + UINT32 TimeoutValue + ); + +/** + Returns WDT failure status. + + @retval V_PCH_OC_WDT_CTL_STATUS_FAILURE If there was WDT expiration or= unexpected reset + @retval V_PCH_OC_WDT_CTL_STATUS_OK Otherwise +**/ +typedef +UINT8 +(EFIAPI *WDT_CHECK_STATUS) ( + VOID + ); + +/** + Returns information if WDT coverage for the duration of BIOS execution + was requested by an OS application. + + @retval TRUE if WDT was requested + @retval FALSE if WDT was not requested +**/ +typedef +UINT8 +(EFIAPI *IS_WDT_REQUIRED) ( + VOID + ); + +/** + Returns WDT enabled/disabled status. + + @retval TRUE if WDT is enabled + @retval FALSE if WDT is disabled +**/ +typedef +UINT8 +(EFIAPI *IS_WDT_ENABLED) ( + VOID + ); + +/** + Disables WDT timer. +**/ +typedef +VOID +(EFIAPI *WDT_DISABLE) ( + VOID + ); + +/** + Normally, each reboot performed while watchdog runs is considered a fail= ure. + This function allows platform to perform expected reboots with WDT runni= ng, + without being interpreted as failures. + In DXE phase, it is enough to call this function any time before reset. + In PEI phase, between calling this function and performing reset, Reload= AndStart() + must not be called. +**/ +typedef +VOID +(EFIAPI *WDT_ALLOW_KNOWN_RESET) ( + VOID + ); + +/** + These protocols and PPI allow a platform module to perform watch dog tim= er operations + through the Intel PCH LPC Host Controller Interface. The WDT protocol an= d WDT PPI + implement the Intel (R) Watch Dog timer for DXE, and PEI environments, r= espectively. + WDT_PROTOCOL referenced hereafter represents both WDT_PROTOCOL and WDT_P= PI, as they + share the identical data structure. +**/ +struct _WDT_PROTOCOL { + WDT_RELOAD_AND_START ReloadAndStart; ///< Reloads WDT with new timeou= t value and starts it. + WDT_CHECK_STATUS CheckStatus; ///< Returns WDT failure status. + WDT_DISABLE Disable; ///< Disables WDT timer. + WDT_ALLOW_KNOWN_RESET AllowKnownReset; ///< Perform expected reboots wi= th WDT running, without being interpreted as failures. + IS_WDT_REQUIRED IsWdtRequired; ///< Returns information if WDT = coverage for the duration of BIOS execution was requested by an OS applicat= ion. + IS_WDT_ENABLED IsWdtEnabled; ///< Returns WDT enabled/disable= d status. +}; + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h= b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h new file mode 100644 index 0000000000..860f823655 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h @@ -0,0 +1,73 @@ +/** @file + Register names for Flash registers + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name= . + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _FLASH_REGS_H_ +#define _FLASH_REGS_H_ + + +// +// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0 +// +#define R_FLASH_FDBAR_FLASH_MAP0 0x04 +#define B_FLASH_FDBAR_NC 0x00000300 //= /< Number Of Components +#define N_FLASH_FDBAR_NC 8 //= /< Number Of Components +#define R_FLASH_FDBAR_FLASH_MAP1 0x08 +#define B_FLASH_FDBAR_FPSBA 0x00FF0000 //= /< PCH Strap Base Address, [23:16] represents [11:4] +#define N_FLASH_FDBAR_FPSBA 16 //= /< PCH Strap base Address bit position +#define N_FLASH_FDBAR_FPSBA_REPR 4 //= /< PCH Strap base Address bit represents position +#define B_FLASH_FDBAR_PCHSL 0xFF000000 //= /< PCH Strap Length, [31:24] represents number of Dwords +#define N_FLASH_FDBAR_PCHSL 24 //= /< PCH Strap Length bit position +#define R_FLASH_FDBAR_FLASH_MAP2 0x0C +#define B_FLASH_FDBAR_FCPUSBA 0x00000FFC //= /< CPU Strap Base Address [11:2] +#define N_FLASH_FDBAR_FCPUSBA 2 //= /< CPU Strap Base Address bit position +#define B_FLASH_FDBAR_CPUSL 0x00FF0000 //= /< CPU Strap Length, [23:16] represents number of Dwords +#define N_FLASH_FDBAR_CPUSL 16 //= /< CPU Strap Length bit position + +// +// Flash Component Base Address (FCBA) from Flash Region 0 +// +#define R_FLASH_FCBA_FLCOMP 0x00 //= /< Flash Components Register +#define B_FLASH_FLCOMP_COMP1_MASK 0xF0 //= /< Flash Component 1 Size MASK +#define N_FLASH_FLCOMP_COMP1 4 //= /< Flash Component 1 Size bit position +#define B_FLASH_FLCOMP_COMP0_MASK 0x0F //= /< Flash Component 0 Size MASK +#define V_FLASH_FLCOMP_COMP_512KB 0x80000 +// +// Descriptor Upper Map Section from Flash Region 0 +// +#define R_FLASH_UMAP1 0xEFC //= /< Flash Upper Map 1 +#define B_FLASH_UMAP1_MDTBA 0xFF000000 //= /< MIP Descriptor Table Base Address +#define N_FLASH_UMAP1_MDTBA 24 //= /< MDTBA bits position +#define N_FLASH_UMAP1_MDTBA_REPR 4 //= /< MDTBA address representation position +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h = b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h new file mode 100644 index 0000000000..c89dccb7bd --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h @@ -0,0 +1,103 @@ +/** @file + Register names for PCH GPIO + +Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name= . + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _GPIO_REGS_H_ +#define _GPIO_REGS_H_ + +// +// PADCFG register is split into multiple DW registers +// S_GPIO_PCR_PADCFG refers to number of bytes used by all those registers= for one pad +// +#define S_GPIO_PCR_PADCFG 0x10 + +// +// Pad Configuration Register DW0 +// + + +//RX Raw Override to 1 +#define B_GPIO_PCR_RX_RAW1 BIT28 +#define N_GPIO_PCR_RX_RAW1 28 + +//RX Level/Edge Configuration +#define B_GPIO_PCR_RX_LVL_EDG (BIT26 | BIT25) +#define N_GPIO_PCR_RX_LVL_EDG 25 + +//RX Invert +#define B_GPIO_PCR_RXINV BIT23 +#define N_GPIO_PCR_RXINV 23 + +//GPIO Input Route IOxAPIC +#define B_GPIO_PCR_RX_APIC_ROUTE BIT20 + +//GPIO Input Route SCI +#define B_GPIO_PCR_RX_SCI_ROUTE BIT19 + +//GPIO Input Route SMI +#define B_GPIO_PCR_RX_SMI_ROUTE BIT18 + +//GPIO Input Route NMI +#define B_GPIO_PCR_RX_NMI_ROUTE BIT17 +#define N_GPIO_PCR_RX_NMI_ROUTE 17 + +//GPIO Pad Mode +#define B_GPIO_PCR_PAD_MODE (BIT12 | BIT11 | BIT10) +#define N_GPIO_PCR_PAD_MODE 10 + +//GPIO RX Disable +#define B_GPIO_PCR_RXDIS BIT9 + +//GPIO TX Disable +#define B_GPIO_PCR_TXDIS BIT8 +#define N_GPIO_PCR_TXDIS 8 + +//GPIO TX State +#define B_GPIO_PCR_TX_STATE BIT0 +#define N_GPIO_PCR_TX_STATE 0 + +//Termination +#define B_GPIO_PCR_TERM (BIT13 | BIT12 | BIT11 | BIT10) +#define N_GPIO_PCR_TERM 10 + + +/// +/// GPIO SMI data used for EFI_SMM_GPI_DISPATCH2_PROTOCOL +/// Below defines are to be used internally by PCH SMI dispatcher only +/// +#define PCH_GPIO_NUM_SUPPORTED_GPIS 512 +#define S_GPIO_PCR_GP_SMI_STS 4 + +#endif // _GPIO_REGS_H_ + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer= 2.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h new file mode 100644 index 0000000000..7789236b5e --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h @@ -0,0 +1,211 @@ +/** @file + Register names for VER2 GPIO + +Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name= . + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _GPIO_REGS_VER2_H_ +#define _GPIO_REGS_VER2_H_ + +#define GPIO_VER2_PCH_LP_GPIO_GPP_B_PAD_MAX 26 +#define GPIO_VER2_PCH_LP_GPIO_GPP_A_PAD_MAX 25 +#define GPIO_VER2_PCH_LP_GPIO_GPP_R_PAD_MAX 8 +#define GPIO_VER2_PCH_LP_GPIO_GPD_PAD_MAX 17 +#define GPIO_VER2_PCH_LP_GPIO_GPP_S_PAD_MAX 8 +#define GPIO_VER2_PCH_LP_GPIO_GPP_H_PAD_MAX 24 +#define GPIO_VER2_PCH_LP_GPIO_GPP_D_PAD_MAX 21 +#define GPIO_VER2_PCH_LP_GPIO_GPP_F_PAD_MAX 25 +#define GPIO_VER2_PCH_LP_GPIO_GPP_C_PAD_MAX 24 +#define GPIO_VER2_PCH_LP_GPIO_GPP_E_PAD_MAX 25 + +// +// GPIO Community 0 Private Configuration Registers +// +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PAD_OWN 0x20 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PAD_OWN 0x38 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCK 0x80 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCKTX 0x84 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCK 0x90 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCKTX 0x94 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_HOSTSW_OWN 0xB0 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_HOSTSW_OWN 0xB8 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IS 0x0100 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IS 0x0108 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IE 0x0120 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IE 0x0128 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_STS 0x0140 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_STS 0x0148 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_EN 0x0160 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_EN 0x0168 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_STS 0x0180 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_EN 0x01A0 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_STS 0x01C0 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_EN 0x01E0 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFG_OFFSET 0x700 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFG_OFFSET 0x9A0 + +// +// GPIO Community 1 Private Configuration Registers +// +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PAD_OWN 0x20 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PAD_OWN 0x24 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PAD_OWN 0x30 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCK 0x80 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCKTX 0x84 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCK 0x88 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCKTX 0x8C +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCK 0x90 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCKTX 0x94 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_HOSTSW_OWN 0xB0 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_HOSTSW_OWN 0xB4 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_HOSTSW_OWN 0xB8 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IS 0x0100 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IS 0x0104 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IS 0x0108 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IE 0x0120 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IE 0x0124 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IE 0x0128 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_STS 0x0140 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_STS 0x0144 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_STS 0x0148 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_EN 0x0160 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_EN 0x0164 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_EN 0x0168 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_STS 0x0188 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_EN 0x01A8 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_STS 0x01C8 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_EN 0x01E8 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFG_OFFSET 0x700 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFG_OFFSET 0x780 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFG_OFFSET 0x900 +// +// GPIO Community 2 Private Configuration Registers +// +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PAD_OWN 0x20 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCK 0x80 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCKTX 0x84 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_HOSTSW_OWN 0xB0 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IS 0x0100 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IE 0x0120 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_STS 0x0140 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_EN 0x0160 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFG_OFFSET 0x700 + +// +// GPIO Community 4 Private Configuration Registers +// +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PAD_OWN 0x20 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PAD_OWN 0x2C +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PAD_OWN 0x40 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCK 0x80 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCKTX 0x84 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCK 0x88 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCKTX 0x8C +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCK 0x98 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCKTX 0x9C + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_HOSTSW_OWN 0xB0 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_HOSTSW_OWN 0xB4 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_HOSTSW_OWN 0xBC + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IS 0x0100 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IS 0x0104 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IS 0x010C + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IE 0x0120 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IE 0x0124 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IE 0x012C + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_STS 0x0140 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_STS 0x0144 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_STS 0x014C + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_EN 0x0160 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_EN 0x0164 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_EN 0x016C + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_STS 0x0180 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_STS 0x018C + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_EN 0x01A0 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_EN 0x01AC + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_STS 0x01C0 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_STS 0x01CC + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_EN 0x01E0 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_EN 0x01EC + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFG_OFFSET 0x700 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFG_OFFSET 0x880 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFG_OFFSET 0xA70 + +// +// GPIO Community 5 Private Configuration Registers +// +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PAD_OWN 0x20 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCK 0x80 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCKTX 0x84 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_HOSTSW_OWN 0xB0 + +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IS 0x0100 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IE 0x0120 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_STS 0x0140 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_EN 0x0160 +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFG_OFFSET 0x700 + +#endif // _GPIO_REGS_VER2_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Reg= s.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h new file mode 100644 index 0000000000..f30bf62614 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h @@ -0,0 +1,49 @@ +/** @file + Register names for PCH DMI SIP14 + +Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name= . + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_DMI14_REGS_H_ +#define _PCH_DMI14_REGS_H_ + +// +// DMI Chipset Configuration Registers (PID:DMI) +// + +// +// DMI Control +// +#define R_PCH_DMI14_PCR_DMIC 0x2234 = ///< DMI Control +#define B_PCH_DMI14_PCR_DMIC_SRL BIT31 = ///< Secured register lock + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.= h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h new file mode 100644 index 0000000000..649e8dd17b --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h @@ -0,0 +1,51 @@ +/** @file + Register names for PCH DMI and OP-DMI + +Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name= . + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_DMI_REGS_H_ +#define _PCH_DMI_REGS_H_ + +// +// PCH DMI Chipset Configuration Registers (PID:DMI) +// + +// +// PCH DMI Source Decode PCRs (Common) +// +#define R_PCH_DMI_PCR_LPCIOD 0x2770 = ///< LPC I/O Decode Ranges +#define R_PCH_DMI_PCR_LPCIOE 0x2774 = ///< LPC I/O Enables +#define R_PCH_DMI_PCR_TCOBASE 0x2778 = ///< TCO Base Address +#define B_PCH_DMI_PCR_TCOBASE_TCOBA 0xFFE0 = ///< TCO Base Address Mask + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRe= gs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h new file mode 100644 index 0000000000..17c68cbaaa --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h @@ -0,0 +1,45 @@ +/** @file + Register names for PCH PCI-E root port devices + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name= . + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_REGS_PCIE_H_ +#define _PCH_REGS_PCIE_H_ + +// +// PCIE PCRs (PID:SPA SPB SPC SPD SPE SPF) +// +#define R_SPX_PCR_PCD 0 ///<= Port configuration and disable +#define B_SPX_PCR_PCD_RP1FN (BIT2 | BIT1 | BIT0) ///<= Port 1 Function Number +#define S_SPX_PCR_PCD_RP_FIELD 4 ///<= 4 bits for each RP FN +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.= h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h new file mode 100644 index 0000000000..326b266352 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h @@ -0,0 +1,77 @@ +/** @file + Register names for PCH LPC/eSPI device + +Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name= . + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_REGS_LPC_H_ +#define _PCH_REGS_LPC_H_ + +// +// PCI to LPC Bridge Registers +// + +#define R_LPC_CFG_IOD 0x80 +#define R_LPC_CFG_IOE 0x82 +#define R_ESPI_CFG_CS1IORE 0xA0 + +#define R_LPC_CFG_ULKMC 0x94 +#define B_LPC_CFG_ULKMC_A20PASSEN BIT5 +#define B_LPC_CFG_ULKMC_64WEN BIT3 +#define B_LPC_CFG_ULKMC_64REN BIT2 +#define B_LPC_CFG_ULKMC_60WEN BIT1 +#define B_LPC_CFG_ULKMC_60REN BIT0 + +// +// APM Registers +// +#define R_PCH_IO_APM_CNT 0xB2 +#define R_PCH_IO_APM_STS 0xB3 +#define R_LPC_CFG_BC 0xDC ///< Bio= s Control +#define S_LPC_CFG_BC 1 +#define N_LPC_CFG_BC_LE 1 + +// +// Reset Generator I/O Port +// +#define R_PCH_IO_RST_CNT 0xCF9 +#define V_PCH_IO_RST_CNT_FULLRESET 0x0E +#define V_PCH_IO_RST_CNT_HARDRESET 0x06 +// +// eSPI PCR Registers +// +#define R_ESPI_PCR_CFG_VAL 0xC00C ///< ESPI En= abled Strap +#define B_ESPI_PCR_CFG_VAL_ESPI_EN BIT0 ///< ESPI En= abled Strap bit position +#define R_ESPI_PCR_SOFTSTRAPS 0xC210 ///< eSPI So= fstraps Register 0 +#define B_ESPI_PCR_SOFTSTRAPS_CS1_EN BIT12 ///< CS1# En= able + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h b= /Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h new file mode 100644 index 0000000000..f7153b931c --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h @@ -0,0 +1,134 @@ +/** @file + Register names for PCH PMC device + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name= . + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_REGS_PMC_H_ +#define _PCH_REGS_PMC_H_ + +// +// ACPI and legacy I/O register offsets from ACPIBASE +// +#define R_ACPI_IO_PM1_STS 0x00 +#define S_ACPI_IO_PM1_STS 2 +#define B_ACPI_IO_PM1_STS_PRBTNOR BIT11 +#define B_ACPI_IO_PM1_STS_PWRBTN BIT8 +#define N_ACPI_IO_PM1_STS_RTC 10 +#define N_ACPI_IO_PM1_STS_PWRBTN 8 +#define N_ACPI_IO_PM1_STS_TMROF 0 + +#define R_ACPI_IO_PM1_EN 0x02 +#define S_ACPI_IO_PM1_EN 2 +#define B_ACPI_IO_PM1_EN_PWRBTN BIT8 +#define N_ACPI_IO_PM1_EN_RTC 10 +#define N_ACPI_IO_PM1_EN_PWRBTN 8 +#define N_ACPI_IO_PM1_EN_TMROF 0 + +#define R_ACPI_IO_PM1_CNT 0x04 = ///< Power Management 1 Control +#define B_ACPI_IO_PM1_CNT_SLP_EN BIT13 = ///< Sleep Enable +#define B_ACPI_IO_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10) = ///< Sleep Type +#define V_ACPI_IO_PM1_CNT_S0 0 +#define V_ACPI_IO_PM1_CNT_S1 BIT10 +#define V_ACPI_IO_PM1_CNT_S3 (BIT12 | BIT10) +#define V_ACPI_IO_PM1_CNT_S4 (BIT12 | BIT11) +#define V_ACPI_IO_PM1_CNT_S5 (BIT12 | BIT11 | BIT10) +#define B_ACPI_IO_PM1_CNT_SCI_EN BIT0 = ///< SCI Enable + +#define R_ACPI_IO_PM1_TMR 0x08 = ///< Power Management 1 Timer +#define B_ACPI_IO_PM1_TMR_TMR_VAL 0xFFFFFF = ///< Timer Value +#define V_ACPI_IO_PM1_TMR_MAX_VAL 0x1000000 ///< The = timer is 24 bit overflow + +#define R_ACPI_IO_SMI_EN 0x30 = ///< SMI Control and Enable +#define S_ACPI_IO_SMI_EN 4 +#define B_ACPI_IO_SMI_EN_LEGACY_USB2 BIT17 +#define B_ACPI_IO_SMI_EN_TCO BIT13 +#define B_ACPI_IO_SMI_EN_SWSMI_TMR BIT6 +#define B_ACPI_IO_SMI_EN_APMC BIT5 +#define B_ACPI_IO_SMI_EN_LEGACY_USB BIT3 +#define B_ACPI_IO_SMI_EN_EOS BIT1 = ///< End of SMI +#define B_ACPI_IO_SMI_EN_GBL_SMI BIT0 +#define N_ACPI_IO_SMI_EN_LEGACY_USB3 31 +#define N_ACPI_IO_SMI_EN_PERIODIC 14 +#define N_ACPI_IO_SMI_EN_TCO 13 +#define N_ACPI_IO_SMI_EN_MCSMI 11 +#define N_ACPI_IO_SMI_EN_SWSMI_TMR 6 +#define N_ACPI_IO_SMI_EN_APMC 5 +#define N_ACPI_IO_SMI_EN_ON_SLP_EN 4 +#define N_ACPI_IO_SMI_EN_LEGACY_USB 3 + +#define R_ACPI_IO_SMI_STS 0x34 = ///< SMI Status Register +#define S_ACPI_IO_SMI_STS 4 +#define B_ACPI_IO_SMI_STS_GPIO_UNLOCK BIT27 +#define B_ACPI_IO_SMI_STS_TCO BIT13 +#define B_ACPI_IO_SMI_STS_APM BIT5 +#define N_ACPI_IO_SMI_STS_LEGACY_USB3 31 +#define N_ACPI_IO_SMI_STS_SPI 26 +#define N_ACPI_IO_SMI_STS_SMBUS 16 +#define N_ACPI_IO_SMI_STS_SERIRQ 15 +#define N_ACPI_IO_SMI_STS_PERIODIC 14 +#define N_ACPI_IO_SMI_STS_TCO 13 +#define N_ACPI_IO_SMI_STS_MCSMI 11 +#define N_ACPI_IO_SMI_STS_GPIO_SMI 10 +#define N_ACPI_IO_SMI_STS_GPE0 9 +#define N_ACPI_IO_SMI_STS_PM1_STS_REG 8 +#define N_ACPI_IO_SMI_STS_SWSMI_TMR 6 +#define N_ACPI_IO_SMI_STS_APM 5 +#define N_ACPI_IO_SMI_STS_ON_SLP_EN 4 +#define N_ACPI_IO_SMI_STS_LEGACY_USB 3 + +#define R_ACPI_IO_GPE0_STS_127_96 0x6C = ///< General Purpose Event 0 Status [127:96] +#define S_ACPI_IO_GPE0_STS_127_96 4 +#define B_ACPI_IO_GPE0_STS_127_96_WADT BIT18 +#define N_ACPI_IO_GPE0_STS_127_96_PME_B0 13 +#define N_ACPI_IO_GPE0_STS_127_96_PME 11 +#define R_ACPI_IO_GPE0_EN_127_96 0x7C = ///< General Purpose Event 0 Enable [127:96] +#define S_ACPI_IO_GPE0_EN_127_96 4 +#define B_ACPI_IO_GPE0_EN_127_96_WADT BIT18 +#define N_ACPI_IO_GPE0_EN_127_96_PME_B0 13 +#define N_ACPI_IO_GPE0_EN_127_96_PME 11 + +// +// PWRM Registers +// +#define R_PMC_PWRM_GEN_PMCON_A 0x1020 = ///< General PM Configuration A +#define B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL 0xC0 +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS 0xC0 +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS 0x80 +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS 0x40 +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS 0x00 +#define B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL (BIT2|BIT1) = ///< Period SMI Select +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S 0x0000 +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S 0x0002 +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S 0x0004 +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S 0x0006 +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h b= /Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h new file mode 100644 index 0000000000..8424ef5897 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h @@ -0,0 +1,44 @@ +/** @file + Register names for RTC device + +Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name= . + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _REGS_RTC_H_ +#define _REGS_RTC_H_ + +#define R_RTC_IO_INDEX_ALT 0x74 +#define R_RTC_IO_TARGET_ALT 0x75 +#define R_RTC_IO_EXT_INDEX_ALT 0x76 +#define R_RTC_IO_REGD 0x0D + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h b= /Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h new file mode 100644 index 0000000000..c3afcd5079 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h @@ -0,0 +1,71 @@ +/** @file + Register names for PCH TCO device + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name= . + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _TCO_REGS_H_ +#define _TCO_REGS_H_ + +// +// TCO register I/O map +// +#define R_TCO_IO_TCO1_STS 0x04 +#define S_TCO_IO_TCO1_STS 2 +#define B_TCO_IO_TCO1_STS_DMISERR BIT12 +#define B_TCO_IO_TCO1_STS_DMISMI BIT10 +#define B_TCO_IO_TCO1_STS_DMISCI BIT9 +#define B_TCO_IO_TCO1_STS_BIOSWR BIT8 +#define B_TCO_IO_TCO1_STS_NEWCENTURY BIT7 +#define B_TCO_IO_TCO1_STS_TIMEOUT BIT3 +#define B_TCO_IO_TCO1_STS_TCO_INT BIT2 +#define B_TCO_IO_TCO1_STS_SW_TCO_SMI BIT1 +#define N_TCO_IO_TCO1_STS_DMISMI 10 +#define N_TCO_IO_TCO1_STS_BIOSWR 8 +#define N_TCO_IO_TCO1_STS_NEWCENTURY 7 +#define N_TCO_IO_TCO1_STS_TIMEOUT 3 +#define N_TCO_IO_TCO1_STS_SW_TCO_SMI 1 +#define N_TCO_IO_TCO1_STS_NMI2SMI 0 + +#define R_TCO_IO_TCO2_STS 0x06 +#define S_TCO_IO_TCO2_STS 2 +#define N_TCO_IO_TCO2_STS_INTRD_DET 0 + +#define R_TCO_IO_TCO1_CNT 0x08 +#define S_TCO_IO_TCO1_CNT 2 +#define N_TCO_IO_TCO1_CNT_NMI2SMI_EN 9 + +#define R_TCO_IO_TCO2_CNT 0x0A +#define S_TCO_IO_TCO2_CNT 2 +#define N_TCO_IO_TCO2_CNT_INTRD_SEL 2 + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h b/= Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h new file mode 100644 index 0000000000..1829fb90ff --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h @@ -0,0 +1,226 @@ +/** @file + Serial IO policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SERIAL_IO_DEVICES_H_ +#define _SERIAL_IO_DEVICES_H_ + +#include +#include + +#pragma pack (push,1) + +/** + Available working modes for SerialIo SPI Host Controller + + 0: SerialIoSpiDisabled; + - Device is placed in D3 + - Gpio configuration is skipped + - PSF: + !important! If given device is Function 0 and other higher funct= ions on given device + are enabled, PSF disabling is skipped. PSF default w= ill remain and device PCI CFG Space will still be visible. + This is needed to allow PCI enumerator access functi= ons above 0 in a multifunction device. + 1: SerialIoSpiPci; + - Gpio pin configuration in native mode for each assigned pin + - Device will be enabled in PSF + - Only BAR0 will be enabled + 2: SerialIoSpiHidden; + - Gpio pin configuration in native mode for each assigned pin + - Device disabled in the PSF + - Both BARs are enabled, BAR1 becomes devices Pci Config Space + - BAR0 assigned from the global PCH reserved memory range, repor= ted as motherboard resource by SIRC + @note + If this controller is located at function 0 and it's mode is se= t to hidden it will not be visible in the PCI space. +**/ +typedef enum { + SerialIoSpiDisabled, + SerialIoSpiPci, + SerialIoSpiHidden +} SERIAL_IO_SPI_MODE; + +/** + Used to set Inactive/Idle polarity of Spi Chip Select +**/ +typedef enum { + SerialIoSpiCsActiveLow =3D 0, + SerialIoSpiCsActiveHigh =3D 1 +} SERIAL_IO_CS_POLARITY; + +/** + SPI signals pin muxing settings. If signal can be enable only on a singl= e pin + then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_SP= Ix_* in GpioPins*.h + for supported settings on a given platform +**/ +typedef struct { + UINT32 Cs[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< CS Pin mux configura= tion. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS_* + UINT32 Clk; ///< CLK Pin mux configur= ation. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK_* + UINT32 Miso; ///< MISO Pin mux configu= ration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO_* + UINT32 Mosi; ///< MOSI Pin mux configu= ration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI_* +} SPI_PIN_MUX; + +/** + The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial I= O SPI controller +**/ +typedef struct { + UINT8 Mode; ///< Seria= lIoSpiPci see SERIAL_IO_SPI_MODE + UINT8 DefaultCsOutput; ///< 0 =3D= CS0 CS1, CS2, CS3. Default CS used by the SPI HC + UINT8 CsPolarity[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< Selects = SPI ChipSelect signal polarity, 0 =3D low 1 =3D High + UINT8 CsEnable[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< 0 =3D= Enable 1 =3D Disable. Based on this setting GPIO for given SPIx CSx wi= ll be configured in Native mode + UINT8 CsMode; ///< 0 =3D= HW Control 1 =3D SW Control. Sets Chip Select Control mode Hardware or= Software. + UINT8 CsState; ///< 0 =3D= CS is set to low 1 =3D CS is set to high + SPI_PIN_MUX PinMux; ///< SPI Pinm= ux configuration +} SERIAL_IO_SPI_CONFIG; + +/** + Available working modes for SerialIo UART Host Controller + + 0: SerialIoUartDisabled; + - Device is placed in D3 + - Gpio configuration is skipped + - PSF: + !important! If given device is Function 0 and other higher funct= ions on given device + are enabled, PSF disabling is skipped. PSF default w= ill remain and device PCI CFG Space will still be visible. + This is needed to allow PCI enumerator access functi= ons above 0 in a multifunction device. + 1: SerialIoUartPci; + - Designated for Serial IO UART OS driver usage + - Gpio pin configuration in native mode for each assigned pin + - Device will be enabled in PSF + - Only BAR0 will be enabled + 2: SerialIoUartHidden; + - Designated for BIOS and/or DBG2 OS kernel debug + - Gpio pin configuration in native mode for each assigned pin + - Device disabled in the PSF + - Both BARs are enabled, BAR1 becomes devices Pci Config Space + - BAR0 assigned from the global PCH reserved memory range, repor= ted as motherboard resource by SIRC + @note + If this controller is located at function 0 and it's mode is se= t to hidden it will not be visible in the PCI space. + 3: SerialIoUartCom; + - Designated for 16550/PNP0501 compatible COM device + - Gpio pin configuration in native mode for each assigned pin + - Device disabled in the PSF + - Both BARs are enabled, BAR1 becomes devices Pci Config Space + - BAR0 assigned from the global PCH reserved memory range, repor= ted as motherboard resource by SIRC + 4: SerialIoUartSkipInit; + - Gpio configuration is skipped + - PSF configuration is skipped + - BAR assignemnt is skipped + - D-satate setting is skipped + +**/ +typedef enum { + SerialIoUartDisabled, + SerialIoUartPci, + SerialIoUartHidden, + SerialIoUartCom, + SerialIoUartSkipInit +} SERIAL_IO_UART_MODE; + +/** + UART Settings +**/ +typedef struct { + UINT32 BaudRate; ///< 115200 Max 6000000 MdePkg.dec P= cdUartDefaultBaudRate + UINT8 Parity; ///< 1 - No Parity see EFI_PARITY_TYPE = MdePkg.dec PcdUartDefaultParity + UINT8 DataBits; ///< 8 MdePkg.dec PcdUartDefaultDataBits + UINT8 StopBits; ///< 1 - One Stop Bit see EFI_STOP_BITS_= TYPE MdePkg.dec PcdUartDefaultStopBits + UINT8 AutoFlow; ///< FALSE IntelFrameworkModulePkg.dsc = PcdIsaBusSerialUseHalfHandshake +} SERIAL_IO_UART_ATTRIBUTES; + +/** + UART signals pin muxing settings. If signal can be enable only on a sing= le pin + then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_UA= RTx_* in GpioPins*.h + for supported settings on a given platform +**/ +typedef struct { + UINT32 Rx; ///< RXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIA= LIO_UARTx_RXD_* + UINT32 Tx; ///< TXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIA= LIO_UARTx_TXD_* + UINT32 Rts; ///< RTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIA= LIO_UARTx_RTS_* + UINT32 Cts; ///< CTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIA= LIO_UARTx_CTS_* +} UART_PIN_MUX; + +/** + Serial IO UART Controller Configuration +**/ +typedef struct { + SERIAL_IO_UART_ATTRIBUTES Attributes; ///< see SERIAL_IO_UART_ATTRIBUTE= S + UART_PIN_MUX PinMux; ///< UART pin mux configuration + UINT8 Mode; ///< SerialIoUartPci see= SERIAL_IO_UART_MODE + UINT8 DBG2; ///< FALSE If TRUE adds = UART to DBG2 table and overrides UartPg to SerialIoUartPgDisabled + UINT8 PowerGating; ///< SerialIoUartPgAuto = Applies to Hidden/COM/SkipInit see SERIAL_IO_UART_PG + UINT8 DmaEnable; ///< TRUE Applies to Ser= ialIoUartPci only. Informs OS driver to use DMA, if false it will run in PI= O mode +} SERIAL_IO_UART_CONFIG; + +typedef enum { + SerialIoUartPgDisabled, ///< No _PS0/_PS3 support, device left in D0, a= fter initialization +/** + In mode: SerialIoUartCom; + _PS0/_PS3 that supports getting device out of reset + In mode: SerialIoUartPci + Keeps UART in D0 and assigns Fixed MMIO for SEC/PEI usage only +**/ + SerialIoUartPgEnabled, + SerialIoUartPgAuto ///< _PS0 and _PS3, detection through ACPI if d= evice was initialized prior to first PG. If it was used (DBG2) PG is disabl= ed, +} SERIAL_IO_UART_PG; + +/** + Available working modes for SerialIo I2C Host Controller + + 0: SerialIoI2cDisabled; + - Device is placed in D3 + - Gpio configuration is skipped + - PSF: + !important! If given device is Function 0 and other higher funct= ions on given device + are enabled, PSF disabling is skipped. PSF default w= ill remain and device PCI CFG Space will still be visible. + This is needed to allow PCI enumerator access functi= ons above 0 in a multifunction device. + 1: SerialIoI2cPci; + - Gpio pin configuration in native mode for each assigned pin + - Device will be enabled in PSF + - Only BAR0 will be enabled + 2: SerialIoI2cHidden; + - Gpio pin configuration in native mode for each assigned pin + - Device disabled in the PSF + - Both BARs are enabled, BAR1 becomes devices Pci Config Space + - BAR0 assigned from the global PCH reserved memory range, repor= ted as motherboard resource by SIRC + @note + If this controller is located at function 0 and it's mode is se= t to hidden it will not be visible in the PCI space. +**/ +typedef enum { + SerialIoI2cDisabled, + SerialIoI2cPci, + SerialIoI2cHidden +} SERIAL_IO_I2C_MODE; + +/** + I2C signals pin muxing settings. If signal can be enable only on a singl= e pin + then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_I2= Cx_* in GpioPins*.h + for supported settings on a given platform +**/ +typedef struct { + UINT32 Sda; ///< SDA Pin mux configuration. Refer to GPIO_*_MUXING_S= ERIALIO_I2Cx_SDA_* + UINT32 Scl; ///< SCL Pin mux configuration. Refer to GPIO_*_MUXING_S= ERIALIO_I2Cx_SCL_* +} I2C_PIN_MUX; + +/** + Serial IO I2C Controller Configuration +**/ +typedef struct { + UINT8 Mode; /// SerialIoI2cPci see SERIAL_IO_I2C_MO= DE + /** + I2C Pads Internal Termination. + For more information please see Platform Design Guide. + Supported values (check GPIO_ELECTRICAL_CONFIG for reference): + GpioTermNone: No termination, + GpioTermWpu1K: 1kOhm weak pull-up, + GpioTermWpu5K: 5kOhm weak pull-up, + GpioTermWpu20K: 20kOhm weak pull-up + **/ + UINT8 PadTermination; + UINT8 Reserved[2]; + I2C_PIN_MUX PinMux; ///< I2C pin mux configuration +} SERIAL_IO_I2C_CONFIG; + +#pragma pack (pop) + +#endif // _SERIAL_IO_DEVICES_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h b/Sili= con/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h new file mode 100644 index 0000000000..089141d143 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h @@ -0,0 +1,17 @@ +/** @file + Silicon Config HOB is used for gathering platform + related Intel silicon information and config setting. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SI_CONFIG_HOB_H_ +#define _SI_CONFIG_HOB_H_ + +#include + +extern EFI_GUID gSiConfigHobGuid; + +// Rename SI_CONFIG_HOB into SI_CONFIG_HOB_DATA for it does not follow HOB= structure. +typedef CONST SI_CONFIG SI_CONFIG_HOB_DATA; +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h b/S= ilicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h new file mode 100644 index 0000000000..4dacba242e --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h @@ -0,0 +1,64 @@ +/** @file + Intel reference code configuration policies. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SI_POLICY_STRUCT_H_ +#define _SI_POLICY_STRUCT_H_ + +#include +#include +#include + +/** + Silicon Policy revision number + Any change to this structure will result in an update in the revision nu= mber + + This member specifies the revision of the Silicon Policy. This field is = used to indicate change + to the policy structure. + + Revision 1: + - Initial version. +**/ +#define SI_POLICY_REVISION 1 + +/** + Silicon pre-memory Policy revision number + Any change to this structure will result in an update in the revision nu= mber + + Revision 1: + - Initial version. +**/ +#define SI_PREMEM_POLICY_REVISION 1 + + +/** + SI Policy PPI in Pre-Mem\n + All SI config block change history will be listed here\n\n + + - Revision 1: + - Initial version.\n +**/ +struct _SI_PREMEM_POLICY_STRUCT { + CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table He= ader +/* + Individual Config Block Structures are added here in memory as part of A= ddConfigBlock() +*/ +}; + +/** + SI Policy PPI\n + All SI config block change history will be listed here\n\n + + - Revision 1: + - Initial version.\n +**/ +struct _SI_POLICY_STRUCT { + CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table He= ader +/* + Individual Config Block Structures are added here in memory as part of A= ddConfigBlock() +*/ +}; + +#endif --=20 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108725): https://edk2.groups.io/g/devel/message/108725 Mute This Topic: https://groups.io/mt/101373951/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-