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LsQCRbbpYrbhBZhtHwKNdJt5x7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="B/Ql/aC5"; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") Reviewed-by: Rosen Chuang -----Original Message----- From: Chaganty, Rangasai V =20 Sent: Friday, September 15, 2023 1:43 PM To: Kasbekar, Saloni ; devel@edk2.groups.io Cc: Desimone, Nathaniel L ; Chuang, Rosen <= rosen.chuang@intel.com> Subject: RE: [PATCH v2 05/10] AlderlakeSiliconPkg/Include: Add ConfigBlock = headers Reviewed-by: Sai Chaganty -----Original Message----- From: Kasbekar, Saloni =20 Sent: Thursday, September 14, 2023 9:46 PM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Chuang, Rosen Subject: [PATCH v2 05/10] AlderlakeSiliconPkg/Include: Add ConfigBlock head= ers Adds the header includes for the ConfigBlocks Cc: Sai Chaganty Cc: Nate DeSimone Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../CpuPcieRp/Gen3/CpuPcieConfigGen3.h | 48 ++ .../CpuPcieRp/Gen4/CpuPcieConfig.h | 240 ++++++++ .../Include/ConfigBlock/Espi/LpcConfig.h | 38 ++ .../Include/ConfigBlock/Fivr/FivrConfig.h | 183 ++++++ .../Include/ConfigBlock/Gpio/GpioDevConfig.h | 37 ++ .../Graphics/Gen12/GraphicsConfig.h | 212 +++++++ .../HostBridge/Ver1/HostBridgeConfig.h | 58 ++ .../ConfigBlock/Itss/InterruptConfig.h | 38 ++ .../ConfigBlock/Memory/Ver2/MemoryConfig.h | 551 ++++++++++++++++++ .../Include/ConfigBlock/PchDmi/PchDmiConfig.h | 65 +++ .../PcieRp/PchPcieRp/PchPcieRpConfig.h | 180 ++++++ .../Include/ConfigBlock/PcieRp/PcieConfig.h | 408 +++++++++++++ .../ConfigBlock/PcieRp/PciePreMemConfig.h | 36 ++ .../Include/ConfigBlock/Pmc/AdrConfig.h | 76 +++ .../Include/ConfigBlock/Pmc/PmConfig.h | 86 +++ .../Include/ConfigBlock/Rtc/RtcConfig.h | 37 ++ .../ConfigBlock/SerialIo/SerialIoConfig.h | 33 ++ .../Include/ConfigBlock/SiConfig.h | 105 ++++ .../Include/ConfigBlock/SiPreMemConfig.h | 63 ++ .../Include/ConfigBlock/Smbus/SmbusConfig.h | 49 ++ .../ConfigBlock/Spi/FlashProtectionConfig.h | 54 ++ .../Include/ConfigBlock/Tcss/TcssPeiConfig.h | 71 +++ .../Include/ConfigBlock/Vmd/VmdPeiConfig.h | 60 ++ .../Include/ConfigBlock/Wdt/WatchDogConfig.h | 30 + 24 files changed, 2758 insertions(+) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/C= puPcieRp/Gen3/CpuPcieConfigGen3.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/C= puPcieRp/Gen4/CpuPcieConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/E= spi/LpcConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/F= ivr/FivrConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/G= pio/GpioDevConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/G= raphics/Gen12/GraphicsConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/H= ostBridge/Ver1/HostBridgeConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/I= tss/InterruptConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/M= emory/Ver2/MemoryConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/P= chDmi/PchDmiConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/P= cieRp/PchPcieRp/PchPcieRpConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/P= cieRp/PcieConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/P= cieRp/PciePreMemConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/P= mc/AdrConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/P= mc/PmConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/R= tc/RtcConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/S= erialIo/SerialIoConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/S= iConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/S= iPreMemConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/S= mbus/SmbusConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/S= pi/FlashProtectionConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/T= css/TcssPeiConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/V= md/VmdPeiConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/W= dt/WatchDogConfig.h diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieR= p/Gen3/CpuPcieConfigGen3.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Conf= igBlock/CpuPcieRp/Gen3/CpuPcieConfigGen3.h new file mode 100644 index 0000000000..5b437c8311 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/= CpuPcieConfigGen3.h @@ -0,0 +1,48 @@ +/** @file +Pcie root port policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_PCIE_CONFIG_GEN3_H_ +#define _CPU_PCIE_CONFIG_GEN3_H_ + +#include +#include +#include +#include +#include + +#pragma pack(push, 1) + + +#define L0_SET BIT0 +#define L1_SET BIT1 + + +/// +/// SA GPIO Data Structure +/// +typedef struct { + GPIO_PAD GpioPad; ///< Offset 0: GPIO Pad + UINT8 Value; ///< Offset 4: GPIO Value + UINT8 Rsvd0[3]; ///< Offset 5: Reserved for 4 bytes alignm= ent + UINT32 Active : 1; ///< Offset 8: 0=3DActive Low; 1=3DActive = High + UINT32 RsvdBits0 : 31; +} SA_GPIO_INFO_PCIE; + +/// +/// SA Board PEG GPIO Info +/// +typedef struct { + SA_GPIO_INFO_PCIE SaPeg0ResetGpio; ///< Offset 0: PEG0 PERST# GPIO = assigned, must be a PCH GPIO pin + SA_GPIO_INFO_PCIE SaPeg3ResetGpio; ///< Offset 12: PEG3 PERST# GPIO = assigned, must be a PCH GPIO pin + BOOLEAN GpioSupport; ///< Offset 24: 1=3DSupported; 0= =3DNot Supported + UINT8 Rsvd0[3]; ///< Offset 25: Reserved for 4 by= tes alignment +} PEG_GPIO_DATA; + + +#pragma pack (pop) + +#endif // _CPU_PCIE_CONFIG_GEN3_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieR= p/Gen4/CpuPcieConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBl= ock/CpuPcieRp/Gen4/CpuPcieConfig.h new file mode 100644 index 0000000000..999748d711 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/= CpuPcieConfig.h @@ -0,0 +1,240 @@ +/** @file + Pcie root port policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_PCIE_CONFIG_H_ +#define _CPU_PCIE_CONFIG_H_ + +#include +#include +#include +#include +#include + +#pragma pack(push, 1) + +#define CPU_PCIE_RP_PREMEM_CONFIG_REVISION 1 + +/** + Making any setup structure change after code frozen + will need to maintain backward compatibility, bump up + structure revision and update below history table\n + Revision 1: - Initial version. +**/ + +#define CPU_PCIE_CONFIG_REVISION 10 + +#define L0_SET BIT0 +#define L1_SET BIT1 + +/** + CPU PCIe Root Port Pre-Memory Configuration + Contains Root Port settings and capabilities + Revision 1: - Initial version. + Revision 2: - Adding Dekel Suqelch Workaround Setup Variable + Revision 3: - Deprecate Dekel Suqelch Workaround Setup Variable + Revision 4: - Adding New FOM Setup Variable + Revision 5: - Add CdrRelock Policy to CPU_PCIE_RP_PREMEM_CONFIG. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config= Block Header + /** + Root Port enabling mask. + Bit0 presents RP1, Bit1 presents RP2, and so on. + 0: Disable; 1: Enable. + **/ + UINT32 RpEnabledMask; + /** + Assertion on Link Down GPIOs + - Disabled (0x0) : Disable assertion on Link Down GPIOs(Default) + - Enabled (0x1) : Enable assertion on Link Down GPIOs + **/ + UINT8 LinkDownGpios; + /** + Enable ClockReq Messaging + - Disabled (0x0) : Disable ClockReq Messaging(Default) + - Enabled (0x1) : Enable ClockReq Messaging + **/ + UINT8 ClkReqMsgEnable; + /** + Dekel Recipe Workaround + 2 + 1=3DMinimal, 9=3DMaximum, + **/ + UINT8 DekelSquelchWa; // Deprecated variable + UINT8 Rsvd0[1]; + /** + Determines each PCIE Port speed capability. + 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 (see: CPU_PCIE_SPEED) + **/ + UINT8 PcieSpeed[CPU_PCIE_MAX_ROOT_PORTS]; + + /** + Enable ClockReq Messaging Policy is for all Rootports + - Disabled (0x0) : Disable ClockReq Messaging(Default) + - Enabled (0x1) : Enable ClockReq Messaging + **/ + UINT8 ClkReqMsgEnableRp[CPU_PCIE_MAX_ROOT_PORTS]; + /** + To Enable/Disable New FOM + 0: Disable; 1: Enable + **/ + UINT8 NewFom[CPU_PCIE_MAX_ROOT_PORTS]; + /** + To Enable/Disable CDR Relock + 0: Disable; 1: Enable + **/ + UINT8 CdrRelock[CPU_PCIE_MAX_ROOT_PORTS]; +} CPU_PCIE_RP_PREMEM_CONFIG; + +/** + Represent lane specific PCIe Gen3 equalization parameters. +**/ +typedef struct { + UINT8 Cm; ///< Coefficient C-1 + UINT8 Cp; ///< Coefficient C+1 + UINT8 PegGen3RootPortPreset; ///< (Test) Us= ed for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is defaul= t for each lane + UINT8 PegGen3EndPointPreset; ///< (Test) Us= ed for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is defaul= t for each lane + UINT8 PegGen3EndPointHint; ///< (Test) Hi= nt value per lane for the PEG Gen3 End Point. Range: 0-6, 2 is default for = each lane + UINT8 PegGen4RootPortPreset; ///< (Test) Us= ed for programming PEG Gen4 preset values per lane. Range: 0-9, 8 is defaul= t for each lane + UINT8 PegGen4EndPointPreset; ///< (Test) Us= ed for programming PEG Gen4 preset values per lane. Range: 0-9, 7 is defaul= t for each lane + UINT8 PegGen4EndPointHint; ///< (Test) Hi= nt value per lane for the PEG Gen4 End Point. Range: 0-6, 2 is default for = each lane +} CPU_PCIE_EQ_LANE_PARAM; + +/** + The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each= CPU PCIe root port. +**/ +typedef struct { + + UINT32 ExtSync : 1; ///< Indicate whether th= e extended synch is enabled. 0: Disable; 1: Enable. + UINT32 MultiVcEnabled : 1; ///< Multiple Virtual Ch= annel. 0: Disable; 1: Enable + UINT32 RsvdBits0 : 30; ///< Reserved bits + /** + PCIe Gen4 Equalization Method + - HwEq (0x1) : Hardware Equalization (Default) + - StaticEq (0x2) : Static Equalization + **/ + UINT8 Gen4EqPh3Method; + UINT8 FomsCp; ///< FOM Score Board Con= trol Policy + UINT8 RsvdBytes0[2]; ///< Reserved bytes + + // + // Gen3 Equalization settings + // + UINT32 Gen3Uptp : 4; ///< (Test) Upstr= eam Port Transmitter Preset used during Gen3 Link Equalization. Used for al= l lanes. Default is 7. + UINT32 Gen3Dptp : 4; ///< (Test) Downs= tream Port Transmiter Preset used during Gen3 Link Equalization. Used for a= ll lanes. Default is 7. + // + // Gen4 Equalization settings + // + UINT32 Gen4Uptp : 4; ///< (Test) Upstr= eam Port Transmitter Preset used during Gen4 Link Equalization. Used for al= l lanes. Default is 7. + UINT32 Gen4Dptp : 4; ///< (Test) Downs= tream Port Transmiter Preset used during Gen4 Link Equalization. Used for a= ll lanes. Default is 7. + // + // Gen5 Equalization settings + // + UINT32 Gen5Uptp : 4; ///< (Test) Upstr= eam Port Transmitter Preset used during Gen5 Link Equalization. Used for al= l lanes. Default is 5. + UINT32 Gen5Dptp : 4; ///< (Test) Downs= tream Port Transmiter Preset used during Gen5 Link Equalization. Used for a= ll lanes. Default is 7. + UINT32 RsvdBits1 : 8; ///< Reserved Bits + + PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; = ///< (Test) Includes policies which are common to = both SA and PCH RootPort + +} CPU_PCIE_ROOT_PORT_CONFIG; + +typedef struct { + UINT8 PcieGen3PresetCoeffSelection; ///Revision 1< / b>: + -Initial version. + Revision 2: + - SlotSelection policy added + Revision 3 + - Deprecate PegGen3ProgramStaticEq and PegGen4ProgramStaticEq + Revision 4: + - Deprecating SetSecuredRegisterLock + Revision 5: + - Moved ClockGating policy to PCIE_ROOT_PORT_COMMON_CONFIG + - Moved PowerGating policy to PCIE_ROOT_PORT_COMMON_CONFIG + - Deprecate VcEnabled policy + Revision 7: + - Deprecating Gen3PresetCoeffSelection and Gen4PresetCoeffSelection + Revision 8: + - Added Serl policy + Revision 9: + - Align revision with CPU_PCIE_CONFIG_REVISION value + Revision 10: + - Deprecate EqPh3LaneParam.Cm and EqPh3LaneParam.Cp +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config = Block Header + /// + /// These members describe the configuration of each SA PCIe root port. + /// + CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS]; + /// + /// Gen3 Equalization settings for physical PCIe lane, index 0 represent= s PCIe lane 1, etc. + /// Corresponding entries are used when root port EqPh3Method is PchPcie= EqStaticCoeff (default). + /// + CPU_PCIE_EQ_LANE_PARAM EqPh3LaneParam[SA_PEG_MAX_LANE]; //@ = Deprecated Policy + /// + /// List of coefficients used during equalization (applicable to both so= ftware and hardware EQ) + /// + PCIE_EQ_PARAM HwEqGen4CoeffList[PCIE_HWEQ_COEFFS_MAX= ]; //@ Deprecated Policy + + PCIE_COMMON_CONFIG PcieCommonConfig; /// < (Test) Includes policies which are common to both SA and PCH PCIe + + UINT32 FiaProgramming : 1; /// < Skip Fia Conf= iguration and lock if enable + // Deprecated Policy + /** + (Test) Program PEG Gen3 EQ Phase1 Static Presets + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programming = (Default) + **/ + UINT32 PegGen3ProgramStaticEq : 1; + + // Deprecated Policy + /** + (Test) Program PEG Gen4 EQ Phase1 Static Presets + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programming = (Default) + **/ + UINT32 PegGen4ProgramStaticEq : 1; + /** + (Test) Cpu Pcie Secure Register Lock + - Disabled (0x0) + - Enabled (0x1) + **/ + UINT32 SetSecuredRegisterLock : 1; // Deprecated Policy + /// + /// This member allows to select between the PCI Express M2 or CEMx4 slo= t 1: PCIe M2; 0: CEMx4 slot. + /// + UINT32 SlotSelection : 1; + + UINT32 Serl : 1; + + UINT32 RsvdBits0 : 26; + + /** + PCIe device override table + The PCIe device table is being used to override PCIe device ASPM setti= ngs. + This is a pointer points to a 32bit address. And it's only used in Pos= tMem phase. + Please refer to PCIE_DEVICE_OVERRIDE structure for the table. + Last entry VendorId must be 0. + The prototype of this policy is: + PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr; + **/ + UINT32 PcieDeviceOverrideTablePtr; + CPU_PCIE_ROOT_PORT_CONFIG2 RootPort2[CPU_PCIE_MAX_ROOT_PORTS]; + PCIE_COMMON_CONFIG2 PcieCommonConfig2; + } CPU_PCIE_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_PCIE_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Espi/Lpc= Config.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Espi/LpcCo= nfig.h new file mode 100644 index 0000000000..324facde78 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Espi/LpcConfig.= h @@ -0,0 +1,38 @@ +/** @file + Lpc policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _LPC_CONFIG_H_ +#define _LPC_CONFIG_H_ + +#define PCH_LPC_PREMEM_CONFIG_REVISION 1 +extern EFI_GUID gLpcPreMemConfigGuid; + +#pragma pack (push,1) + +/** + This structure contains the policies which are related to LPC. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Enhance the port 8xh decoding. + Original LPC only decodes one byte of port 80h, with this enhancement = LPC can decode word or dword of port 80h-83h. + @note: this will occupy one LPC generic IO range register. While this = is enabled, read from port 80h always return 0x00. + 0: Disable, 1: Enable + **/ + UINT32 EnhancePort8xhDecoding : 1; + /** + Hardware Autonomous Enable. + When enabled, LPC will automatically engage power gating when it has re= ached its idle condition. + 0: Disable, 1: Enable + **/ + UINT32 LpcPmHAE : 1; + UINT32 RsvdBits : 30; ///< Reserved bits +} PCH_LPC_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _LPC_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Fivr/Fiv= rConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Fivr/Fivr= Config.h new file mode 100644 index 0000000000..501e00c0e1 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig= .h @@ -0,0 +1,183 @@ +/** @file + PCH FIVR policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _FIVR_CONFIG_H_ +#define _FIVR_CONFIG_H_ + +/** + Revision 1: - Initial version. +**/ +#define PCH_FIVR_CONFIG_REVISION 1 +extern EFI_GUID gFivrConfigGuid; + +#pragma pack (push,1) + +/** + Rail support in S0ix and Sx + Settings other than FivrRailDisabled can be OR'ed +**/ +typedef enum { + FivrRailDisabled =3D 0, + FivrRailInS0i1S0i2 =3D BIT0, + FivrRailInS0i3 =3D BIT1, + FivrRailInS3 =3D BIT2, + FivrRailInS4 =3D BIT3, + FivrRailInS5 =3D BIT4, + FivrRailInS0ix =3D FivrRailInS0i1S0i2 | FivrRailInS0i3, + FivrRailInSx =3D FivrRailInS3 | FivrRailInS4 | FivrRailInS5, + FivrRailAlwaysOn =3D FivrRailInS0ix | FivrRailInSx +} FIVR_RAIL_SX_STATE; + +typedef enum { + FivrRetentionActive =3D BIT0, + FivrNormActive =3D BIT1, + FivrMinActive =3D BIT2, + FivrMinRetention =3D BIT3 +} FIVR_RAIL_SUPPORTED_VOLTAGE; + +/** + Structure for V1p05/Vnn VR rail configuration +**/ +typedef struct { + /** + Mask to enable the usage of external VR rail in specific S0ix or Sx st= ates + Use values from FIVR_RAIL_SX_STATE + The default is FivrRailDisabled. + **/ + UINT32 EnabledStates : 6; + + /** + VR rail voltage value that will be used in S0i2/S0i3 states. + This value is given in 2.5mV increments (0=3D0mV, 1=3D2.5mV, 2=3D5mV..= .) + The default for Vnn is set to 420 - 1050 mV. + **/ + UINT32 Voltage : 11; + /** + @deprecated + THIS POLICY IS DEPRECATED, PLEASE USE IccMaximum INSTEAD + VR rail Icc Max Value + Granularity of this setting is 1mA and maximal possible value is 500mA + The default is 0mA . + **/ + UINT32 IccMax : 8; + /** + UINT32 Alignement + **/ + UINT32 RsvdBits1 : 7; + /** + This register holds the control hold off values to be used when + changing the rail control for external bypass value in us + **/ + UINT32 CtrlRampTmr : 8; + + /** + Mask to set the supported configuration in VR rail. + Use values from FIVR_RAIL_SUPPORTED_VOLTAGE + **/ + UINT32 SupportedVoltageStates : 4; + + /** + VR rail Icc Maximum Value + Granularity of this setting is 1mA and maximal possible value is 500mA + The default is 0mA . + **/ + UINT32 IccMaximum : 16; + /** + UINT32 Alignment + **/ + UINT32 RsvdBits2 : 4; + +} FIVR_EXT_RAIL_CONFIG; + + +/** + Structure for VCCIN_AUX voltage rail configuration +**/ +typedef struct { + /** + Transition time in microseconds from Low Current Mode Voltage to High Cu= rrent Mode Voltage. + Voltage transition time required by motherboard voltage regulator when P= CH changes + the VCCIN_AUX regulator set point from the low current mode voltage and = high current mode voltage. + This field has 1us resolution. + When value is 0 PCH will not transition VCCIN_AUX to low current mode vo= ltage. + The default is 0xC . + **/ + UINT8 LowToHighCurModeVolTranTime; + + /** + Transition time in microseconds from Retention Mode Voltage to High Curr= ent Mode Voltage. + Voltage transition time required by motherboard voltage regulator when P= CH changes + the VCCIN_AUX regulator set point from the retention mode voltage to hig= h current mode voltage. + This field has 1us resolution. + When value is 0 PCH will not transition VCCIN_AUX to retention voltage. + The default is 0x36 . + **/ + UINT8 RetToHighCurModeVolTranTime; + + /** + Transition time in microseconds from Retention Mode Voltage to Low Curre= nt Mode Voltage. + Voltage transition time required by motherboard voltage regulator when P= CH changes + the VCCIN_AUX regulator set point from the retention mode voltage to low= current mode voltage. + This field has 1us resolution. + When value is 0 PCH will not transition VCCIN_AUX to retention voltage. + The default is 0x2B . + **/ + UINT8 RetToLowCurModeVolTranTime; + UINT8 RsvdByte1; + /** + Transition time in microseconds from Off (0V) to High Current Mode Volta= ge. + Voltage transition time required by motherboard voltage regulator when P= CH changes + the VCCIN_AUX regulator set point from 0V to the high current mode volta= ge. + This field has 1us resolution. + 0 =3D Transition to 0V is disabled + Setting this field to 0 sets VCCIN_AUX as a fixed rail that stays on + in all S0 & Sx power states after initial start up on G3 exit + The default is 0x96 . + **/ + UINT32 OffToHighCurModeVolTranTime : 11; + UINT32 RsvdBits1 : 21; +} FIVR_VCCIN_AUX_CONFIG; + +/** + The PCH_FIVR_CONFIG block describes FIVR settings. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + External V1P05 VR rail configuration. + **/ + FIVR_EXT_RAIL_CONFIG ExtV1p05Rail; + /** + External Vnn VR rail configuration. + **/ + FIVR_EXT_RAIL_CONFIG ExtVnnRail; + /** + Additional External Vnn VR rail configuration that will get applied + in Sx entry SMI callback. Required only if External Vnn VR + needs different settings for Sx than those specified in ExtVnnRail. + **/ + FIVR_EXT_RAIL_CONFIG ExtVnnRailSx; + /** + VCCIN_AUX voltage rail configuration. + **/ + FIVR_VCCIN_AUX_CONFIG VccinAux; + + /** + Enable/Disable FIVR Dynamic Power Management + Default is 1 . + **/ + UINT32 FivrDynPm : 1; + /** + Enable/Disable Bypass of FIVR configuration + Default is 0 . + **/ + UINT32 BypassFivrConfig : 1; + UINT32 RsvdBits2 : 30; +} PCH_FIVR_CONFIG; + +#pragma pack (pop) + +#endif // _FIVR_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Gpio/Gpi= oDevConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Gpio/G= pioDevConfig.h new file mode 100644 index 0000000000..5652df0259 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevCon= fig.h @@ -0,0 +1,37 @@ +/** @file + GPIO device policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _GPIO_DEV_CONFIG_H_ +#define _GPIO_DEV_CONFIG_H_ + +extern EFI_GUID gGpioDxeConfigGuid; + +#define GPIO_DXE_CONFIG_REVISION 1 + +#pragma pack (push,1) + +/** + This structure contains the DXE policies which are related to GPIO devic= e. + + Revision 1: + - Inital version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + If GPIO ACPI device is not used by OS it can be hidden. In such case + no other device exposed to the system can reference GPIO device in one + of its resources through GpioIo(..) or GpioInt(..) ACPI descriptors. + 0: Disable; 1: Enable + **/ + UINT32 HideGpioAcpiDevice : 1; + UINT32 RsvdBits : 31; ///< Reserved bits + +} GPIO_DXE_CONFIG; + +#pragma pack (pop) + +#endif // _GPIO_DEV_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Graphics= /Gen12/GraphicsConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigB= lock/Graphics/Gen12/GraphicsConfig.h new file mode 100644 index 0000000000..c6a2f36612 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/= GraphicsConfig.h @@ -0,0 +1,212 @@ +/** @file + Policy definition for Internal Graphics Config Block. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _GRAPHICS_CONFIG_H_ +#define _GRAPHICS_CONFIG_H_ +#pragma pack(push, 1) + +#define GRAPHICS_DXE_CONFIG_REVISION 2 + +#define MAX_BCLM_ENTRIES 20 + + +// +// DDI defines +// +typedef enum { + DdiDisable =3D 0x00, + DdiDdcEnable =3D 0x01, +} DDI_DDC_TBT_VAL; + +typedef enum { + DdiHpdDisable =3D 0x00, + DdiHpdEnable =3D 0x01, +} DDI_HPD_VAL; + +typedef enum { + DdiPortDisabled =3D 0x00, + DdiPortEdp =3D 0x01, + DdiPortMipiDsi =3D 0x02, +} DDI_PORT_SETTINGS; + +/** + This structure configures the Native GPIOs for DDI port per VBT settings= . +**/ +typedef struct { + UINT8 DdiPortAConfig; /// The Configuration of DDI port A, this settings= must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPor= tA, DdiPortEdp - Set DdiPortA to eDP, DdiPortMipiDsi - Set DdiPortA = to MIPI DSI + UINT8 DdiPortBConfig; /// The Configuration of DDI port B, this settings= must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPor= tB, DdiPortEdp - Set DdiPortB to eDP, DdiPortMipiDsi - Set DdiPortB = to MIPI DSI + UINT8 DdiPortAHpd; /// The HPD setting of DDI Port A, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable = - Enable HPD + UINT8 DdiPortBHpd; /// The HPD setting of DDI Port B, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - En= able HPD + UINT8 DdiPortCHpd; /// The HPD setting of DDI Port C, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable = - Enable HPD + UINT8 DdiPort1Hpd; /// The HPD setting of DDI Port 1, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable = - Enable HPD + UINT8 DdiPort2Hpd; /// The HPD setting of DDI Port 2, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable = - Enable HPD + UINT8 DdiPort3Hpd; /// The HPD setting of DDI Port 3, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable = - Enable HPD + UINT8 DdiPort4Hpd; /// The HPD setting of DDI Port 4, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable = - Enable HPD + UINT8 DdiPortADdc; /// The DDC setting of DDI Port A, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - E= nable DDC + UINT8 DdiPortBDdc; /// The DDC setting of DDI Port B, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - Enabl= e DDC + UINT8 DdiPortCDdc; /// The DDC setting of DDI Port C, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - E= nable DDC + UINT8 DdiPort1Ddc; /// The DDC setting of DDI Port 1, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - E= nable DDC + UINT8 DdiPort2Ddc; /// The DDC setting of DDI Port 2, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - E= nable DDC + UINT8 DdiPort3Ddc; /// The DDC setting of DDI Port 3, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - E= nable DDC + UINT8 DdiPort4Ddc; /// The DDC setting of DDI Port 4, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - E= nable DDC +} DDI_CONFIGURATION; + +/** + This Configuration block is to configure GT related PreMem data/variable= s.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config = Block Header + /** + Offset 28 + Selection of the primary display device: 0=3DiGFX, 1=3DPEG, 2=3DPCIe G= raphics on PCH, 3=3DAUTO, 4=3DSwitchable Graphics\n + When AUTO mode selected, the priority of display devices is: PCIe Grap= hics on PCH > PEG > iGFX + **/ + UINT8 PrimaryDisplay; + /** + Offset 29 + Intel Gfx Support. It controls enabling/disabling iGfx device. + When AUTO mode selected, iGFX will be turned off when external graphic= s detected. + If FALSE, all other polices can be ignored. + 2 =3D AUTO; + 0 =3D FALSE; + 1 =3D TRUE. + **/ + UINT8 InternalGraphics; + /** + Offset 30 + Pre-allocated memory for iGFX\n + 0 =3D 0MB,1 or 247 =3D 32MB,\n + 2 =3D 64MB,\n + 240 =3D 4MB, 241 =3D 8MB,\n + 242 =3D 12MB, 243 =3D 16MB,\n + 244 =3D 20MB, 245 =3D 24MB,\n + 246 =3D 28MB, 248 =3D 36MB,\n + 249 =3D 40MB, 250 =3D 44MB,\n + 251 =3D 48MB, 252 =3D 52MB,\n + 253 =3D 56MB, 254 =3D 60MB,\n + Note: enlarging pre-allocated memory for iGFX may need to reduce Mm= ioSize because of 4GB boundary limitation + **/ + UINT16 IgdDvmt50PreAlloc; + UINT8 PanelPowerEnable; ///< Offset 32 :(Test) = Control for enabling/disabling VDD force bit (Required only for early enabl= ing of eDP panel): 0=3DFALSE, 1=3DTRUE + UINT8 ApertureSize; ///< Offset 33 :Graphics apert= ure size (256MB is the recommended size as per BWG) : 0=3D128MB, 1=3D256= MB, 3=3D512MB, 7=3D1024MB, 15=3D2048MB. + UINT8 GtPsmiSupport; ///< Offset 34 :PSMI support O= n/Off: 0=3DFALSE, 1=3DTRUE + UINT8 PsmiRegionSize; ///< Offset 35 :Psmi region si= ze: 0=3D32MB, 1=3D288MB, 2=3D544MB, 3=3D800MB, 4=3D1056MB + UINT8 DismSize; ///< Offset 36 :DiSM Size for = 2LM Sku: 0=3D0GB, 1=3D1GB, 2=3D2GB, 3=3D3GB, 4=3D4GB, 5=3D5GB, 6=3D6= GB, 7=3D7GB + UINT8 DfdRestoreEnable; ///< Offset 37 :(Deprecated) D= isplay memory map programming for DFD Restore 0- Disable, 1- Enable + UINT16 GttSize; ///< Offset 38 :Selection of i= GFX GTT Memory size: 1=3D2MB, 2=3D4MB, 3=3D8MB + /** + Offset 40 + Temp Address of System Agent GTTMMADR: Default is 0xAF000000 + **/ + UINT32 GttMmAdr; + UINT32 GmAdr; ///< Offset 44 Obsolete not to= be used, use GmAdr64 + DDI_CONFIGURATION DdiConfiguration; ///< Offset 48 DDI configurati= on, need to match with VBT settings. + + UINT8 GtClosEnable; ///< Offset 50 Gt ClOS + UINT8 Rsvd0[7]; ///< Offset 51 Reserved for 4 = bytes of alignment + /** + Offset 58 + Temp Address of System Agent GMADR: Default is 0xB0000000 + **/ + UINT64 GmAdr64; + UINT16 DeltaT12PowerCycleDelay; ///< Offset 66 Power Cycle= Delay required for eDP as per VESA standard.0 - 0 ms, 0xFFFF - Auto cal= culate to max 500 ms<\b> + UINT8 DisplayAudioLink; ///< Offset 68 Enable/Disa= ble Display Audio Links in Pre-OS.0- Disable, 1- Enable + UINT8 OemT12DelayOverride; ///< Offset 69 :Oem T12 De= lay Override Disable<\b>,Enable-Enable T12 Time. + UINT8 Rsvd2[4]; ///< Offset 70 Reserved fo= r 4 bytes of alignment +} GRAPHICS_PEI_PREMEM_CONFIG; + +/** + This configuration block is to configure IGD related variables used in P= ostMem PEI. + If Intel Gfx Device is not supported, all policies can be ignored. + Revision 1: + - Initial version. + Revision 2: + - Removed DfdRestoreEnable. + Revision 3: + - Removed DdiConfiguration. + Revision 4: + - Added new CdClock frequency + Revision 5: + - Added GT Chicket bits + Revision 6: + - Added LogoPixelHeight and LogoPixelWidth + Revision 7: + - Added SkipFspGop + Revision 8: + - Added VerticalResolution and HorizontalResolution + +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header + UINT8 RenderStandby; ///< Offset 28 :(Test)= This field is used to enable or disable RC6 (Render Standby): 0=3DFALSE, <= b>1=3DTRUE + UINT8 PmSupport; ///< Offset 29 :(Test)= Configure GT to use along with PM Support TRUE/FALSE: 0=3DFALSE, 1=3DTR= UE + /** + Offset 30 + CdClock Frequency select\n + 0xFF =3D Auto. Max CdClock freq based on Reference Clk \n + 0: 192 Mhz, 1: 307.2 Mhz, 2: 312 Mhz, 3: 324 Mhz, 4: 326.4 Mhz, 5: 55= 2 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz + + **/ + UINT16 CdClock; + UINT8 PeiGraphicsPeimInit; ///< Offset 32 : This policy = is used to enable/disable Intel Gfx PEIM.0- Disable, 1- Enable + UINT8 CdynmaxClampEnable; ///< Offset 33 : This policy = is used to enable/disable CDynmax Clamping Feature (CCF) 1- Enable, = 0- Disable + UINT16 GtFreqMax; ///< Offset 34 : (Test) Max GT frequency limited by user in multiples of 50MHz: Default value whi= ch indicates normal frequency is 0xFF + UINT8 DisableTurboGt; ///< Offset 36 : This policy = is used to enable/disable DisableTurboGt 0- Disable, 1- Enable + UINT8 SkipCdClockInit; ///< Offset 37 : SKip full CD= clock initialization. 0- Disable, 1- Enable + UINT8 RC1pFreqEnable; ///< Offset 38 : This policy = is used to enable/disable RC1p Frequency. 0- Disable, 1- Enable + UINT8 PavpEnable; ///< Offset 39 :IGD PAVP TRUE= /FALSE: 0=3DFALSE, 1=3DTRUE + VOID* LogoPtr; ///< Offset 40 Address of Int= el Gfx PEIM Logo to be displayed + UINT32 LogoSize; ///< Offset 44 Intel Gfx PEIM= Logo Size + VOID* GraphicsConfigPtr; ///< Offset 48 Address of the= Graphics Configuration Table + VOID* BltBufferAddress; ///< Offset 52 Address of Blt= buffer for PEIM Logo use + UINT32 BltBufferSize; ///< Offset 56 The size for B= lt Buffer, calculating by PixelWidth * PixelHeight * 4 bytes (the size of E= FI_GRAPHICS_OUTPUT_BLT_PIXEL) + UINT8 ProgramGtChickenBits; ///< Offset 60 Program GT Chi= cket bits in GTTMMADR + 0xD00 BITS [3:1]. + UINT8 SkipFspGop; ///< Offset 61 This policy is= used to skip PEIM GOP in FSP.0- Use FSP provided GOP driver, 1- Ski= p FSP provided GOP driver + UINT8 Rsvd1[2]; ///< Offset 62 Reserved for 4= bytes alignment + UINT32 LogoPixelHeight; ///< Offset 64 Address of Log= oPixelHeight for PEIM Logo use + UINT32 LogoPixelWidth; ///< Offset 68 Address of Log= oPixelWidth for PEIM Logo use + UINT32 VerticalResolution; ///< Offset 72 Address of Ver= ticalResolution for PEIM Logo use + UINT32 HorizontalResolution; ///< Offset 76 Address of Hor= izontalResolution for PEIM Logo use +} GRAPHICS_PEI_CONFIG; + +/** + This configuration block is to configure IGD related variables used in D= XE. + If Intel Gfx Device is not supported or disabled, all policies will be i= gnored. + The data elements should be initialized by a Platform Module.\n + Revision 1: + - Initial version. + Revision 2: + - Removed IgdDvmtMemSize. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config= Block Header + UINT32 Size; ///< Offset 28 - 31: Thi= s field gives the size of the GOP VBT Data buffer + EFI_PHYSICAL_ADDRESS VbtAddress; ///< Offset 32 - 39: Thi= s field points to the GOP VBT data buffer + UINT8 PlatformConfig; ///< Offset 40: This fie= ld gives the Platform Configuration Information (0=3DPlatform is S0ix Capab= le for ULT SKUs only, 1=3DPlatform is not S0ix Capable, 2=3DForce Pl= atform is S0ix Capable for All SKUs) + UINT8 AlsEnable; ///< Offset 41: Ambient = Light Sensor Enable: 0=3DDisable, 2=3DEnable + UINT8 BacklightControlSupport; ///< Offset 42: Backligh= t Control Support: 0=3DPWM Inverted, 2=3DPWM Normal + UINT8 IgdBootType; ///< Offset 43: IGD Boot= Type CMOS option: 0=3DDefault, 0x01=3DCRT, 0x04=3DEFP, 0x08=3DLFP, = 0x20=3DEFP3, 0x40=3DEFP2, 0x80=3DLFP2 + UINT32 IuerStatusVal; ///< Offset 44 - 47: Off= set 16 This field holds the current status of all the supported Ultrabook e= vents (Intel(R) Ultrabook Event Status bits) + CHAR16 GopVersion[0x10]; ///< Offset 48 - 79:This= field holds the GOP Driver Version. It is an Output Protocol and updated b= y the Silicon code + /** + Offset 80: IGD Panel Type CMOS option\n + 0=3DDefault, 1=3D640X480LVDS, 2=3D800X600LVDS, 3=3D1024X768LVDS= , 4=3D1280X1024LVDS, 5=3D1400X1050LVDS1\n + 6=3D1400X1050LVDS2, 7=3D1600X1200LVDS, 8=3D1280X768LVDS, 9=3D1680X1050= LVDS, 10=3D1920X1200LVDS, 13=3D1600X900LVDS\n + 14=3D1280X800LVDS, 15=3D1280X600LVDS, 16=3D2048X1536LVDS, 17=3D1366X76= 8LVDS + **/ + UINT8 IgdPanelType; + UINT8 IgdPanelScaling; ///< Offset 81: IGD Pane= l Scaling: 0=3DAUTO, 1=3DOFF, 6=3DForce scaling + UINT8 IgdBlcConfig; ///< Offset 82: Backligh= t Control Support: 0=3DPWM Inverted, 2=3DPWM Normal + UINT8 IgdDvmtMemSize; ///< Offset 83: @depreca= ted IGD DVMT Memory Size: 1=3D128MB, 2=3D256MB, 3=3DMAX + UINT8 GfxTurboIMON; ///< Offset 84: IMON Cur= rent Value: 14=3DMinimal, 31=3DMaximum + UINT8 Reserved[3]; ///< Offset 85: Reserved= for DWORD alignment. + UINT16 BCLM[MAX_BCLM_ENTRIES]; ///< Offset 88: IGD Back= light Brightness Level Duty cycle Mapping Table. +} GRAPHICS_DXE_CONFIG; +#pragma pack(pop) + +#endif // _GRAPHICS_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/HostBrid= ge/Ver1/HostBridgeConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Conf= igBlock/HostBridge/Ver1/HostBridgeConfig.h new file mode 100644 index 0000000000..11ef7b119c --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/HostBridge/Ver1= /HostBridgeConfig.h @@ -0,0 +1,58 @@ +/** @file + Configurations for HostBridge + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _HOST_BRIDGE_CONFIG_H_ +#define _HOST_BRIDGE_CONFIG_H_ + +#include + + +extern EFI_GUID gHostBridgePeiPreMemConfigGuid; +extern EFI_GUID gHostBridgePeiConfigGuid; + +#pragma pack (push,1) + +/** + This configuration block describes HostBridge settings in PreMem.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header + UINT32 MchBar; ///< Offset 28 Address of Sys= tem Agent MCHBAR: 0xFEDC0000(TGL)/0xFEA80000(JSL) + UINT32 DmiBar; ///< Offset 32 Address of Sys= tem Agent DMIBAR: 0xFEDA0000 + UINT32 EpBar; ///< Offset 36 Address of Sys= tem Agent EPBAR: 0xFEDA1000 + UINT32 GdxcBar; ///< Offset 40 Address of Sys= tem Agent GDXCBAR: 0xFED84000 + UINT32 RegBar; ///< Offset 44 Address of Sys= tem Agent REGBAR: 0xFB000000 + UINT32 EdramBar; ///< Offset 48 Address of Sys= tem Agent EDRAMBAR: 0xFED80000 + /** + Offset 52 : + Size of reserved MMIO space for PCI devices\n + 0=3DAUTO, 512=3D512MB, 768=3D768MB, 1024=3D1024MB, 1280=3D1280M= B, 1536=3D1536MB, 1792=3D1792MB, + 2048=3D2048MB, 2304=3D2304MB, 2560=3D2560MB, 2816=3D2816MB, 3072=3D307= 2MB\n + When AUTO mode selected, the MMIO size will be calculated by required = MMIO size from PCIe devices detected. + **/ + UINT32 MmioSize; + UINT32 MmioSizeAdjustment; ///< Offset 56 Increase (give= n positive value) or Decrease (given negative value) the Reserved MMIO size= when Dynamic Tolud/AUTO mode enabled (in MBs): 0=3Dno adjustment + UINT8 EnableAbove4GBMmio; ///< Offset 60 Enable/disable= above 4GB MMIO resource support: 0=3DDisable, 1=3DEnable + UINT8 Reserved[3]; ///< Offset 61 Reserved for f= uture use. +} HOST_BRIDGE_PREMEM_CONFIG; + + +/** + This configuration block describes HostBridge settings in Post-Mem.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header + UINT8 SkipPamLock; ///< Offset 28 :To skip PAM r= egister locking. @note It is still recommended to set PCI Config space B0: = D0: F0: Offset 80h[0]=3D1 in platform code even Silicon code skipped this.\= n 0=3DAll PAM registers will be locked in Silicon code, 1=3DSkip loc= k PAM registers in Silicon code. + UINT8 Reserved[3]; ///< Offset 29 Reserved for f= uture use. +} HOST_BRIDGE_PEI_CONFIG; + +#pragma pack (pop) + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Itss/Int= erruptConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Itss= /InterruptConfig.h new file mode 100644 index 0000000000..926c7ab6ab --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptC= onfig.h @@ -0,0 +1,38 @@ +/** @file + Interrupt policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _INTERRUPT_CONFIG_H_ +#define _INTERRUPT_CONFIG_H_ + +extern EFI_GUID gInterruptConfigGuid; + +#pragma pack (push,1) + +// +// --------------------- Interrupts Config ------------------------------ +// +typedef enum { + PchNoInt, ///< No Interrupt Pin + PchIntA, + PchIntB, + PchIntC, + PchIntD +} PCH_INT_PIN; + +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and= interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see= PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} PCH_DEVICE_INTERRUPT_CONFIG; + + +#pragma pack (pop) + +#endif // _INTERRUPT_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Memory/V= er2/MemoryConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/= Memory/Ver2/MemoryConfig.h new file mode 100644 index 0000000000..2be85da5a8 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/Mem= oryConfig.h @@ -0,0 +1,551 @@ +/** @file + Policy definition of Memory Config Block + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _MEMORY_CONFIG_H_ +#define _MEMORY_CONFIG_H_ + + +#pragma pack(push, 1) + +// MEMORY_CONFIGURATION_REVISION: +// 3 - Adds DDR5 PDA Enumeration training +// 4 - Adds LPDDR4 Command Mirroring +// 5 - Adds PprEnableType +// 6 - Removed IbeccParity +// 7 - Adds MarginLimitCheck training within MEMORY_CONFIGURATION +// 8 - Adds LpddrRttCa, LpddrRttWr +// 9 - Adds VddqVoltage, VppVoltage +// 10 - Changes PprEnableType to PprEnable +// 11 - Changes DisableDimmChannel to DisableChannel +// 12 - Added DIMMDFE +// 13 - Added ExtendedBankHashing +// 14 - Added IBECC Error Injection knobs: IbeccErrInjControl, IbeccErrInj= Address, IbeccErrInjMask, IbeccErrInjCount +// 15 - Added DynamicMemoryBoost +// 16 - Added ReuseAdlDdr5Board +// 17 - Added RefreshWm; Deprecated RefreshPanicWm and RefreshHpWm +// 18 - Added DebugValue +// 19 - Added McRefreshRate; Deprecated McRefresh2X +// 20 - Added RealtimeMemoryFrequency +// 21 - Added PeriodicDcc and LpMode +// 22 - Added Tx Dqs Dcc Training +// 23 - Added tRFCpb, tRFC2, tRFC4, tRRD_L, tRRD_S, tWTR_L, tCCD_L, tWTR_S +// 24 - Added EccErrInjAddress, EccErrInjMask, EccErrInjCount +// 25 - Added FreqLimitMixedConfig, FirstDimmBitMask, UserBd +// 26 - Added SagvSwitchFactorIA/GT/IO/Stall, SagvHeuristicsDownControl, S= agvHeuristicsUpControl +// 27 - Added DRAMDCA +// 28 - Added FreqLimitMixedConfig_1R1R_8GB, FreqLimitMixedConfig_1R1R_16G= B, FreqLimitMixedConfig_1R1R_8GB_16GB, FreqLimitMixedConfig_2R2R +// 29 - Added LctCmdEyeWidth +// 30 - Added FirstDimmBitMaskEcc +// 31 - Added Lp5BankMode +// 32 - Added WRDS +// 33 - Added EARLYDIMMDFE for Early DIMM DFE Training +// 34 - Added OverloadSAM +#define MEMORY_CONFIGURATION_REVISION 34 + +// MEMORY_CONFIG_NO_CRC_REVISION: +// 3 - adds DDR5 SetMemoryPmicVoltage in SA_FUNCTION_CALLS +#define MEMORY_CONFIG_NO_CRC_REVISION 3 + +/// +/// MEMORY_CONFIGURATION interface definitions +/// +#define MRC_MAX_RCOMP_TARGETS 5 +/// +/// Memory SubSystem Definitions +/// +#define MEM_CFG_MAX_CONTROLLERS 2 +#define MEM_CFG_MAX_CHANNELS 4 +#define MEM_CFG_MAX_DIMMS 2 +#define MEM_CFG_NUM_BYTES_MAPPED 2 +#define MEM_CFG_MAX_SPD_SIZE 1024 +#define MEM_CFG_MAX_SOCKETS (MEM_CFG_MAX_CONTROLLERS * MEM_CF= G_MAX_CHANNELS * MEM_CFG_MAX_DIMMS) +#ifndef MEM_MAX_SAGV_POINTS +#define MEM_MAX_SAGV_POINTS 4 +#endif +#define MEM_MAX_IBECC_REGIONS 8 + +/// +/// SA SPD profile selections. +/// +typedef enum { + DEFAULT_SPD, ///< Standard DIMM profile select. + CUSTOM_PROFILE, ///< XMP enthusiast settings: User specifies variou= s override values + XMP_PROFILE_1, ///< XMP enthusiast settings: XMP profile #1 + XMP_PROFILE_2, ///< XMP enthusiast settings: XMP profile #2 + XMP_PROFILE_3, ///< XMP enthusiast settings: XMP profile #3 + XMP_USER_PROFILE_4, ///< XMP enthusiast settings: XMP user profile #4 + XMP_USER_PROFILE_5, ///< XMP enthusiast settings: XMP user profile #5 + SPDProfileMax =3D 0xFF ///< Ensures SA_SPD is UINT8 +} SA_SPD; + +/// +/// Define the boot modes used by the SPD read function. +/// +typedef enum { + SpdCold, ///< Cold boot + SpdWarm, ///< Warm boot + SpdS3, ///< S3 resume + SpdFast, ///< Fast boot + SpdBootModeMax ///< Delimiter +} SPD_BOOT_MODE; + +/** + SPD Data Buffer +**/ +typedef struct { + UINT8 SpdData[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_MAX= _DIMMS][MEM_CFG_MAX_SPD_SIZE]; ///< SpdData +//Next Field Offset 2048 +} SPD_DATA_BUFFER; + +/** + DqDqs Mapping +**/ +typedef struct { + UINT8 DqsMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_= CFG_NUM_BYTES_MAPPED]; ///< DqsMapCpu2Dram + UINT8 DqMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_C= FG_NUM_BYTES_MAPPED][8]; ///< DqMapCpu2Dram +//Next Field Offset 16 +} SA_MEMORY_DQDQS_MAPPING; + +/** + Rcomp Policies +**/ +typedef struct { + UINT16 RcompResistor; ///< Offset 0: Reference RCO= MP resistors on motherboard ~ 100 ohms + UINT16 RcompTarget[MRC_MAX_RCOMP_TARGETS]; ///< Offset 1: RCOMP target = values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv +//Next Field Offset 16 +} SA_MEMORY_RCOMP; + +/** + SPD Offset Table +**/ +typedef struct { + UINT16 Start; ///< Offset 0 + UINT16 End; ///< Offset 2 + UINT8 BootMode; ///< Offset 4 + UINT8 Reserved3[3]; ///< Offset 5 Reserved for future use +} SPD_OFFSET_TABLE; + +/// +/// SA memory address decode. +/// +typedef struct +{ + UINT8 Controller; ///< Offset 0 Zero based Controller number + UINT8 Channel; ///< Offset 1 Zero based Channel number + UINT8 Dimm; ///< Offset 2 Zero based DIMM number + UINT8 Rank; ///< Offset 3 Zero based Rank number + UINT8 BankGroup; ///< Offset 4 Zero based Bank Group number + UINT8 Bank; ///< Offset 5 Zero based Bank number + UINT16 Cas; ///< Offset 6 Zero based CAS number + UINT32 Ras; ///< Offset 8 Zero based RAS number +} SA_ADDRESS_DECODE; + +typedef UINT8 (EFIAPI * SA_IO_READ_8) (UINTN IoAddress)= ; = = ///< CPU I/O port 8-bit read. +typedef UINT16 (EFIAPI * SA_IO_READ_16) (UINTN IoAddress)= ; = = ///< CPU I/O port 16-bit read. +typedef UINT32 (EFIAPI * SA_IO_READ_32) (UINTN IoAddress)= ; = = ///< CPU I/O port 32-bit read. +typedef UINT8 (EFIAPI * SA_IO_WRITE_8) (UINTN IoAddress,= UINT8 Value); = = ///< CPU I/O port 8-bit write. +typedef UINT16 (EFIAPI * SA_IO_WRITE_16) (UINTN IoAddress,= UINT16 Value); = = ///< CPU I/O port 16-bit write. +typedef UINT32 (EFIAPI * SA_IO_WRITE_32) (UINTN IoAddress,= UINT32 Value); = = ///< CPU I/O port 32-bit write. +typedef UINT8 (EFIAPI * SA_MMIO_READ_8) (UINTN Address); = = = ///< Memory Mapped I/O port 8-bit read. +typedef UINT16 (EFIAPI * SA_MMIO_READ_16) (UINTN Address); = = = ///< Memory Mapped I/O port 16-bit read. +typedef UINT32 (EFIAPI * SA_MMIO_READ_32) (UINTN Address); = = = ///< Memory Mapped I/O port 32-bit read. +typedef UINT64 (EFIAPI * SA_MMIO_READ_64) (UINTN Address); = = = ///< Memory Mapped I/O port 64-bit read. +typedef UINT8 (EFIAPI * SA_MMIO_WRITE_8) (UINTN Address, U= INT8 Value); = = ///< Memory Mapped I/O port 8-bit write. +typedef UINT16 (EFIAPI * SA_MMIO_WRITE_16) (UINTN Address, U= INT16 Value); = = ///< Memory Mapped I/O port 16-bit write. +typedef UINT32 (EFIAPI * SA_MMIO_WRITE_32) (UINTN Address, U= INT32 Value); = = ///< Memory Mapped I/O port 32-bit write. +typedef UINT64 (EFIAPI * SA_MMIO_WRITE_64) (UINTN Address, U= INT64 Value); = = ///< Memory Mapped I/O port 64-bit write. +typedef UINT8 (EFIAPI * SA_SMBUS_READ_8) (UINTN Address, R= ETURN_STATUS *Status); = = ///< Smbus 8-bit read. +typedef UINT16 (EFIAPI * SA_SMBUS_READ_16) (UINTN Address, R= ETURN_STATUS *Status); = = ///< Smbus 16-bit read. +typedef UINT8 (EFIAPI * SA_SMBUS_WRITE_8) (UINTN Address, U= INT8 Value, RETURN_STATUS *Status); = = ///< Smbus 8-bit write. +typedef UINT16 (EFIAPI * SA_SMBUS_WRITE_16) (UINTN Address, U= INT16 Value, RETURN_STATUS *Status); = = ///< Smbus 16-bit write. +typedef UINT32 (EFIAPI * SA_GET_PCI_DEVICE_ADDRESS) (UINT8 Bus, UINT8= Device, UINT8 Function, UINT8 Offset); = = ///< Get PCI device address. +typedef UINT32 (EFIAPI * SA_GET_PCIE_DEVICE_ADDRESS) (UINT8 Bus, UINT8= Device, UINT8 Function, UINT8 Offset); = = ///< Get PCI express device address. +typedef VOID (EFIAPI * SA_GET_RTC_TIME) (UINT8 *Second, U= INT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year); = = ///< Get the current time value. +typedef UINT64 (EFIAPI * SA_GET_CPU_TIME) (VOID); = = = ///< The current CPU time in milliseconds. +typedef VOID * (EFIAPI * SA_MEMORY_COPY) (VOID *Destinatio= n, CONST VOID *Source, UINTN NumBytes); = = ///< Perform byte copy operation. +typedef VOID * (EFIAPI * SA_MEMORY_SET_BYTE) (VOID *Buffer, UI= NTN NumBytes, UINT8 Value); = = ///< Perform byte initialization operation. +typedef VOID * (EFIAPI * SA_MEMORY_SET_WORD) (VOID *Buffer, UI= NTN NumWords, UINT16 Value); = = ///< Perform word initialization operation. +typedef VOID * (EFIAPI * SA_MEMORY_SET_DWORD) (VOID *Buffer, UI= NTN NumDwords, UINT32 Value); = = ///< Perform dword initialization operation. +typedef UINT64 (EFIAPI * SA_LEFT_SHIFT_64) (UINT64 Data, UIN= TN NumBits); = = ///< Left shift the 64-bit data value by specifie= d number of bits. +typedef UINT64 (EFIAPI * SA_RIGHT_SHIFT_64) (UINT64 Data, UIN= TN NumBits); = = ///< Right shift the 64-bit data value by specifi= ed number of bits. +typedef UINT64 (EFIAPI * SA_MULT_U64_U32) (UINT64 Multiplic= and, UINT32 Multiplier); = = ///< Multiply a 64-bit data value by a 32-bit dat= a value. +typedef UINT64 (EFIAPI * SA_DIV_U64_U64) (UINT64 Dividend,= UINT64 Divisor, UINT64 *Remainder); = = ///< Divide a 64-bit data value by a 64-bit data = value. +typedef BOOLEAN (EFIAPI * SA_GET_SPD_DATA) (SPD_BOOT_MODE Bo= otMode, UINT8 SpdAddress, UINT8 *Buffer, UINT8 *Ddr3Table, UINT32 Ddr3Table= Size, UINT8 *Ddr4Table, UINT32 Ddr4TableSize, UINT8 *LpddrTable, UINT32 Lpd= drTableSize); ///< Read the SPD data over the SMBus, at the giv= en SmBus SPD address and copy the data to the data structure. +typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_DECODE) (UINT64 Address, = SA_ADDRESS_DECODE *DramAddress); +typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_ENCODE) (SA_ADDRESS_DECOD= E *DramAddress, UINT64 Address); +typedef BOOLEAN (EFIAPI * SA_GET_RANDOM_NUMBER) (UINT32 *Rand); = = = ///< Get the next random 32-bit number. +typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_READ) (UINT32 Type, UIN= T32 Command, UINT32 *Value, UINT32 *Status); = = ///< Perform a CPU mailbox read. +typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_WRITE) (UINT32 Type, UIN= T32 Command, UINT32 Value, UINT32 *Status); = = ///< Perform a CPU mailbox write. +typedef UINT32 (EFIAPI * SA_GET_MEMORY_VDD) (VOID *GlobalData= , UINT32 DefaultVdd); = = ///< Get the current memory voltage (VDD). +typedef UINT32 (EFIAPI * SA_SET_MEMORY_VDD) (VOID *GlobalData= , UINT32 DefaultVdd, UINT32 Value); = = ///< Set the memory voltage (VDD) to the given va= lue. +typedef UINT32 (EFIAPI * SA_SET_MEMORY_PMIC_VOLTAGE) (VOID *GlobalData= , UINT8 SpdAddress, UINT32 Vdd, UINT32 Vddq, UINT32 Vpp); = = ///< Set DDR5 memory voltages (VDD, VDDQ, VPP) to= the given values. +typedef UINT32 (EFIAPI * SA_CHECKPOINT) (VOID *GlobalData= , UINT32 CheckPoint, VOID *Scratch); = = ///< Check point that is called at various points= in the MRC. +typedef VOID (EFIAPI * SA_DEBUG_HOOK) (VOID *GlobalData= , UINT16 DisplayDebugNumber); = = ///< Typically used to display to the I/O port 80= h. +typedef UINT8 (EFIAPI * SA_CHANNEL_EXIST) (VOID *Outputs, U= INT8 Channel); = = ///< Returns whether Channel is or is not present= . +typedef INT32 (EFIAPI * SA_PRINTF) (VOID *Debug, UIN= T32 Level, char *Format, ...); = = ///< Print to output stream/device. +typedef VOID (EFIAPI * SA_DEBUG_PRINT) (VOID *String); = = = ///< Output a string to the debug stream/device. +typedef UINT32 (EFIAPI * SA_CHANGE_MARGIN) (VOID *GlobalData= , UINT8 Param, INT32 Value0, INT32 Value1, UINT8 EnMultiCast, UINT8 Channel= , UINT8 RankIn, UINT8 Byte, UINT8 BitIn, UINT8 UpdateMrcData, UINT8 SkipWai= t, UINT32 RegFileParam); ///< Change the margin. +typedef UINT8 (EFIAPI * SA_SIGN_EXTEND) (UINT8 Value, UIN= T8 OldMsb, UINT8 NewMsb); = = ///< Sign extends OldMSB to NewMSB Bits (Eg: Bit = 6 to Bit 7). +typedef VOID (EFIAPI * SA_SHIFT_PI_COMMAND_TRAIN) (VOID *GlobalData= , UINT8 Channel, UINT8 Iteration, UINT8 RankMask, UINT8 GroupMask, INT32 Ne= wValue, UINT8 UpdateHost); = ///< Move CMD/CTL/CLK/CKE PIs during training. +typedef VOID (EFIAPI * SA_UPDATE_VREF) (VOID *GlobalData= , UINT8 Channel, UINT8 RankMask, UINT16 DeviceMask, UINT8 VrefType, INT32 O= ffset, BOOLEAN UpdateMrcData, BOOLEAN PDAmode, BOOLEAN SkipWait); = ///< Update the Vref value and wait until it is s= table. +typedef UINT8 (EFIAPI * SA_GET_RTC_CMOS) (UINT8 Location);= = = ///< Get the current value of the specified RTC C= MOS location. +typedef UINT64 (EFIAPI * SA_MSR_READ_64) (UINT32 Location)= ; = = ///< Get the current value of the specified MSR l= ocation. +typedef UINT64 (EFIAPI * SA_MSR_WRITE_64) (UINT32 Location,= UINT64 Data); = = ///< Set the current value of the specified MSR l= ocation. +typedef VOID (EFIAPI * SA_MRC_RETURN_FROM_SMC) (VOID *GlobalData= , UINT32 MrcStatus); = = ///< Hook function after returning from MrcStartM= emoryConfiguration() +typedef VOID (EFIAPI * SA_MRC_DRAM_RESET) (UINT32 PciEBaseA= ddress, UINT32 ResetValue); = = ///< Assert or deassert DRAM_RESET# pin; this is = used in JEDEC Reset. +typedef VOID (EFIAPI * SA_DELAY_NS) (VOID *GlobalData= , UINT32 DelayNs); = = ///< Delay (stall) for the given amount of nanose= conds. +typedef VOID (EFIAPI * SA_SET_LOCK_PRMRR) (UINT64 PrmrrBase= Address, UINT32 PrmrrSize); + + +/// +/// Function calls into the SA. +/// +typedef struct { + SA_IO_READ_8 IoRead8; ///< Offset 0: - CPU= I/O port 8-bit read. + SA_IO_READ_16 IoRead16; ///< Offset 4: - CPU= I/O port 16-bit read. + SA_IO_READ_32 IoRead32; ///< Offset 8: - CPU= I/O port 32-bit read. + SA_IO_WRITE_8 IoWrite8; ///< Offset 12: - CPU= I/O port 8-bit write. + SA_IO_WRITE_16 IoWrite16; ///< Offset 16: - CPU= I/O port 16-bit write. + SA_IO_WRITE_32 IoWrite32; ///< Offset 20: - CPU= I/O port 32-bit write. + SA_MMIO_READ_8 MmioRead8; ///< Offset 24: - Mem= ory Mapped I/O port 8-bit read. + SA_MMIO_READ_16 MmioRead16; ///< Offset 28: - Mem= ory Mapped I/O port 16-bit read. + SA_MMIO_READ_32 MmioRead32; ///< Offset 32: - Mem= ory Mapped I/O port 32-bit read. + SA_MMIO_READ_64 MmioRead64; ///< Offset 36: - Mem= ory Mapped I/O port 64-bit read. + SA_MMIO_WRITE_8 MmioWrite8; ///< Offset 40: - Mem= ory Mapped I/O port 8-bit write. + SA_MMIO_WRITE_16 MmioWrite16; ///< Offset 44: - Mem= ory Mapped I/O port 16-bit write. + SA_MMIO_WRITE_32 MmioWrite32; ///< Offset 48: - Mem= ory Mapped I/O port 32-bit write. + SA_MMIO_WRITE_64 MmioWrite64; ///< Offset 52: - Mem= ory Mapped I/O port 64-bit write. + SA_SMBUS_READ_8 SmbusRead8; ///< Offset 56: - Smb= us 8-bit read. + SA_SMBUS_READ_16 SmbusRead16; ///< Offset 60: - Smb= us 16-bit read. + SA_SMBUS_WRITE_8 SmbusWrite8; ///< Offset 64: - Smb= us 8-bit write. + SA_SMBUS_WRITE_16 SmbusWrite16; ///< Offset 68: - Smb= us 16-bit write. + SA_GET_PCI_DEVICE_ADDRESS GetPciDeviceAddress; ///< Offset 72: - Get= PCI device address. + SA_GET_PCIE_DEVICE_ADDRESS GetPcieDeviceAddress; ///< Offset 76: - Get= PCI express device address. + SA_GET_RTC_TIME GetRtcTime; ///< Offset 80: - Get= the current time value. + SA_GET_CPU_TIME GetCpuTime; ///< Offset 84: - The= current CPU time in milliseconds. + SA_MEMORY_COPY CopyMem; ///< Offset 88: - Per= form byte copy operation. + SA_MEMORY_SET_BYTE SetMem; ///< Offset 92: - Per= form byte initialization operation. + SA_MEMORY_SET_WORD SetMemWord; ///< Offset 96: - Per= form word initialization operation. + SA_MEMORY_SET_DWORD SetMemDword; ///< Offset 100: - Per= form dword initialization operation. + SA_LEFT_SHIFT_64 LeftShift64; ///< Offset 104: - Lef= t shift the 64-bit data value by specified number of bits. + SA_RIGHT_SHIFT_64 RightShift64; ///< Offset 108: - Rig= ht shift the 64-bit data value by specified number of bits. + SA_MULT_U64_U32 MultU64x32; ///< Offset 112: - Mul= tiply a 64-bit data value by a 32-bit data value. + SA_DIV_U64_U64 DivU64x64; ///< Offset 116: - Div= ide a 64-bit data value by a 64-bit data value. + SA_GET_SPD_DATA GetSpdData; ///< Offset 120: - Rea= d the SPD data over the SMBus, at the given SmBus SPD address and copy the = data to the data structure. + SA_GET_RANDOM_NUMBER GetRandomNumber; ///< Offset 124: - Get= the next random 32-bit number. + SA_CPU_MAILBOX_READ CpuMailboxRead; ///< Offset 128: - Per= form a CPU mailbox read. + SA_CPU_MAILBOX_WRITE CpuMailboxWrite; ///< Offset 132: - Per= form a CPU mailbox write. + SA_GET_MEMORY_VDD GetMemoryVdd; ///< Offset 136: - Get= the current memory voltage (VDD). + SA_SET_MEMORY_VDD SetMemoryVdd; ///< Offset 140: - Set= the memory voltage (VDD) to the given value. + SA_CHECKPOINT CheckPoint; ///< Offset 144: - Che= ck point that is called at various points in the MRC. + SA_DEBUG_HOOK DebugHook; ///< Offset 148: - Typ= ically used to display to the I/O port 80h. + SA_DEBUG_PRINT DebugPrint; ///< Offset 152: - Out= put a string to the debug stream/device. + SA_GET_RTC_CMOS GetRtcCmos; ///< Offset 156: - Get= the current value of the specified RTC CMOS location. + SA_MSR_READ_64 ReadMsr64; ///< Offset 160: - Get= the current value of the specified MSR location. + SA_MSR_WRITE_64 WriteMsr64; ///< Offset 164 - Set= the current value of the specified MSR location. + SA_MRC_RETURN_FROM_SMC MrcReturnFromSmc; ///< Offset 168 - Hoo= k function after returning from MrcStartMemoryConfiguration() + SA_MRC_DRAM_RESET MrcDramReset; ///< Offset 172 - Ass= ert or deassert DRAM_RESET# pin; this is used in JEDEC Reset. + SA_DELAY_NS MrcDelayNs; ///< Offset 176 - Del= ay (stall) for the given amount of nanoseconds. + SA_SET_MEMORY_PMIC_VOLTAGE SetMemoryPmicVoltage; ///< Offset 180: - Set= the memory voltage (VDD/VDDQ/VPP) by PMIC for DDR5. +} SA_FUNCTION_CALLS; + +/// +/// Function calls into the MRC. +/// +typedef struct { + SA_CHANNEL_EXIST MrcChannelExist; ///< Offset 0: - Retu= rns whether Channel is or is not present. + SA_PRINTF MrcPrintf; ///< Offset 4: - Prin= t to output stream/device. + SA_CHANGE_MARGIN MrcChangeMargin; ///< Offset 8: - Chan= ge the margin. + SA_SIGN_EXTEND MrcSignExtend; ///< Offset 12: - Sign= extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7). + SA_SHIFT_PI_COMMAND_TRAIN ShiftPiCommandTrain; ///< Offset 16: - Move= CMD/CTL/CLK/CKE PIs during training. + SA_UPDATE_VREF MrcUpdateVref; ///< Offset 20: - Upda= te the Vref value and wait until it is stable. +} SA_MEMORY_FUNCTIONS; + +/** + Memory Configuration + The contents of this structure are CRC'd by the MRC for option change det= ection. + This structure is copied en mass to the MrcInput structure. If you add fi= elds here, you must update the MrcInput structure. + Revision history is at the top of this file +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header + UINT16 Size; ///< Offset 28 The size of this structur= e, in bytes. Must be the first entry in this structure. + UINT8 HobBufferSize; ///< Offset 30 Size of HOB buffer for MR= C + + UINT8 SpdProfileSelected; ///< Offset 31 SPD XMP profile selection= - for XMP supported DIMM: 0=3DDefault DIMM profile, 1=3DCustom Prof= ile, 2=3DXMP Profile 1, 3=3DXMP Profile 2, 4=3DXMP Profile 3, 5=3DXMP User = Profile 4, 6=3DXMP User Profile 5 + + // The following parameters are used only when SpdProfileSelected is Use= r Defined (CUSTOM_PROFILE) + UINT16 tCL; ///< Offset 32 User defined Memory Timin= g tCL value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 31=3DMaximum. + UINT16 tRCDtRP; ///< Offset 34 User defined Memory Timin= g tRCD value (same as tRP), valid when SpdProfileSelected is CUSTOM_PROFILE= : 0=3DAUTO, 63=3DMaximum + UINT16 tRAS; ///< Offset 36 User defined Memory Timin= g tRAS value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 64=3DMaximum. + UINT16 tWR; ///< Offset 38 User defined Memory Timin= g tWR value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24. + UINT16 tRFC; ///< Offset 40 User defined Memory Timin= g tRFC value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 1023=3DMaximum. + UINT16 tRRD; ///< Offset 42 User defined Memory Timin= g tRRD value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 15=3DMaximum. + UINT16 tWTR; ///< Offset 44 User defined Memory Timin= g tWTR value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 28=3DMaximum. + UINT16 tRTP; ///< Offset 46 User defined Memory Timin= g tRTP value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 15=3DMaximum. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12 + UINT16 tFAW; ///< Offset 48 User defined Memory Timin= g tFAW value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 63=3DMaximum. + UINT16 tCWL; ///< Offset 50 User defined Memory Timin= g tCWL value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 20=3DMaximum. + UINT16 tREFI; ///< Offset 52 User defined Memory Timin= g tREFI value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 65535=3DMaximum. + UINT16 PciIndex; ///< Offset 54 Pci index register addres= s: 0xCF8=3DDefault + UINT16 PciData; ///< Offset 56 Pci data register address= : 0xCFC=3DDefault + UINT16 VddVoltage; ///< Offset 58 DRAM voltage (Vdd) in mil= livolts: 0=3DPlatform Default (no override), 1200=3D1.2V, 1350=3D1.3= 5V etc. + UINT16 Idd3n; ///< Offset 60 EPG Active standby curren= t (Idd3N) in milliamps from DIMM datasheet. + UINT16 Idd3p; ///< Offset 62 EPG Active power-down cur= rent (Idd3P) in milliamps from DIMM datasheet. + + UINT32 EccSupport:1; ///< Offset 64 Bit 0 - DIMM Ecc Supp= ort option - for Desktop only: 0=3DDisable, 1=3DEnable + UINT32 MrcSafeConfig:1; ///< Bit 1 - MRC Safe Mode= : 0=3DDisable, 1=3DEnable + UINT32 RemapEnable:1; ///< Bit 2 - This option i= s used to control whether to enable/disable memory remap above 4GB: 0=3DDis= able, 1=3DEnable. + UINT32 ScramblerSupport:1; ///< Bit 3 - Memory scramb= ler support: 0=3DDisable, 1=3DEnable + UINT32 Vc1ReadMeter:1; ///< Bit 4 - VC1 Read Mete= ring Enable: 0=3DDisable, 1=3DEnable + UINT32 ForceSingleSubchannel:1; ///< Bit 5 - TRUE means us= e SubChannel0 only (for LPDDR4): 0=3DDisable, 1=3DEnable + UINT32 SimicsFlag:1; ///< Bit 6 - Option to Ena= ble SIMICS: 0=3DDisable, 1=3DEnable + UINT32 Ddr4DdpSharedClock:1; ///< Bit 7 - Select if CLK= 0 is shared between Rank0 and Rank1 in DDR4 DDP package. 0=3DNot shared<= /b>, 1=3DShared + UINT32 SharedZqPin:1; ///< Bit 8 - Select if the= ZQ resistor is shared between Ranks in DDR4/LPDDR4 DRAM Packages 0=3DNo= t Shared, 1=3DShared + UINT32 LpDqsOscEn:1; ///< Bit 9 - LPDDR Write D= Q/DQS Retraining: 0=3DDisable, 1=3DEnable + UINT32 RmtPerTask:1; ///< Bit 10 - Rank Margin T= ool Per Task. 0 =3D Disabled, 1 =3D Enabled + UINT32 TrainTrace:1; ///< Bit 11 - Trained state= tracing debug. 0 =3D Disabled, 1 =3D Enabled + UINT32 SafeMode:1; ///< Bit 12 - Define if saf= e mode is enabled for MC/IO + UINT32 MsHashEnable:1; ///< Bit 13 - Controller Ha= sh Enable: 0=3DDisable, 1=3DEnable + UINT32 DisPgCloseIdleTimeout:1; ///< Bit 14 - Disable Page = Close Idle Timeout: 0=3DEnable, 1=3DDisable + UINT32 Ibecc:1; ///< Bit 15 - In-band ECC: = 0=3DDisable, 1=3DEnable + UINT32 IbeccOperationMode:2; ///< Bits 16:17 - In-band E= CC Operation Mode: 0=3DFunctional Mode protects requests based on the addre= ss range, 1=3DMakes all requests non protected and ignore range checks, = 2=3DMakes all requests protected and ignore range checks + UINT32 ChHashOverride:1; ///< Bit 18 - Select if Cha= nnel Hash setting values will be taken from input parameters or automatical= ly taken from POR values depending on DRAM type detected. + UINT32 EccDftEn:1; ///< Bit 19 - ECC DFT suppo= rt option + UINT32 Write0:1; ///< Bit 20 - Write0 featur= e (LP5/DDR5): 0=3DDisable, 1=3DEnable + UINT32 ReuseAdlSDdr5Board:1; ///< Bit 21 - Indicate whet= her adl ddr5 board is reused. + UINT32 PeriodicDcc:1; ///< Bit 22 - Periodic DCC:= 0=3DDisable, 1=3DEnable + UINT32 LpMode:2; ///< Bit 23:24 - LPMode: 0=3DAuto, 1=3DEnabled, 2=3DDisabled, 3=3DReserved + UINT32 RsvdO64B25to31:7; ///< Bits 25:31 reserved + UINT8 DisableChannel[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS]; /= //< Offset 68-75 + UINT8 Ratio; ///< Offset 76 DDR Frequency ratio, to m= ultiply by 133 or 100 MHz depending on RefClk. 0 =3D Auto + UINT8 ProbelessTrace; ///< Offset 77 Probeless Trace: 0=3DD= isabled, 1=3DEnabled + /** + Channel Hash Enable.\n + NOTE: BIT7 will interleave the channels at a 2 cache-line granularity,= BIT8 at 4 and BIT9 at 8\n + 0=3DBIT6, 1=3DBIT7, 2=3DBIT8, 3=3DBIT9 + **/ + UINT8 ChHashInterleaveBit; ///< Offset 78 Option to select interlea= ve Address bit. Valid values are 0 - 3 for BITS 6 - 9 (Valid values for BDW= are 0-7 for BITS 6 - 13) + UINT8 SmramMask; ///< Offset 79 Reserved memory ranges fo= r SMRAM + UINT32 BClkFrequency; ///< Offset 80 Base reference clock valu= e, in Hertz: 100000000 =3D 100Hz, 125000000=3D125Hz, 167000000=3D167= Hz, 250000000=3D250Hz + + /// Training Algorithms 1 Offset 84 + UINT32 ECT:1; ///< Bit 0 - Enable/Disable Early Comman= d Training. Note it is not recommended to change this setting from the defa= ult value: 0=3DDisable, 1=3DEnable. + UINT32 SOT:1; ///< Bit 1 - Enable/Disable Sense Amp Of= fset Training. Note it is not recommended to change this setting from the d= efault value: 0=3DDisable, 1=3DEnable. + UINT32 ERDMPRTC2D:1; ///< Bit 2 - Enable/Disable Early ReadMP= R Timing Centering 2D. Note it is not recommended to change this setting fr= om the default value: 0=3DDisable, 1=3DEnable. + UINT32 RDMPRT:1; ///< Bit 3 - Enable/Disable Read MPR Tra= ining. Note it is not recommended to change this setting from the default v= alue: 0=3DDisable, 1=3DEnable. + UINT32 RCVET:1; ///< Bit 4 - Enable/Disable Receive Enab= le Training. Note it is not recommended to change this setting from the def= ault value: 0=3DDisable, 1=3DEnable. + UINT32 JWRL:1; ///< Bit 5 - Enable/Disable JEDEC Write = Leveling Training. Note it is not recommended to change this setting from t= he default value: 0=3DDisable, 1=3DEnable. + UINT32 EWRTC2D:1; ///< Bit 6 - Enable/Disable Early Write = Time Centering 2D Training. Note it is not recommended to change this setti= ng from the default value: 0=3DDisable, 1=3DEnable. + UINT32 ERDTC2D:1; ///< Bit 7 - Enable/Disable Early Read T= ime Centering 2D Training. Note it is not recommended to change this settin= g from the default value: 0=3DDisable, 1=3DEnable. + UINT32 WRTC1D:1; ///< Bit 8 - Enable/Disable 1D Write Tim= ing Centering Training. Note it is not recommended to change this setting f= rom the default value: 0=3DDisable, 1=3DEnable. + UINT32 WRVC1D:1; ///< Bit 9 - Enable/Disable 1D Write Vol= tage Centering Training. Note it is not recommended to change this setting = from the default value: 0=3DDisable, 1=3DEnable. + UINT32 RDTC1D:1; ///< Bit 10 - Enable/Disable 1D Read Tim= ing Centering Training. Note it is not recommended to change this setting f= rom the default value: 0=3DDisable, 1=3DEnable. + UINT32 DIMMODTT:1; ///< Bit 11 - Enable/Disable DIMM ODT Tr= aining. Note it is not recommended to change this setting from the default = value: 0=3DDisable, 1=3DEnable. + UINT32 DIMMRONT:1; ///< Bit 12 - Enable/Disable DIMM RON tr= aining. Note it is not recommended to change this setting from the default = value: 0=3DDisable, 1=3DEnable. + UINT32 WRDSEQT:1; ///< Bit 13 - Enable/Disable Write Drive= Strength / Equalization Training 2D. Note it is not recommended to change = this setting from the default value: 0=3DDisable, 1=3DEnable. + UINT32 WRSRT:1; ///< Bit 14 - Enable/Disable Write Slew = Rate traning. Note it is not recommended to change this setting from the de= fault value: 0=3DDisable, 1=3DEnable. + UINT32 RDODTT:1; ///< Bit 15 - Enable/Disable Read ODT Tr= aining. Note it is not recommended to change this setting from the default = value: 0=3DDisable, 1=3DEnable. + UINT32 RDEQT:1; ///< Bit 16 - Enable/Disable Read Equali= zation Training. Note it is not recommended to change this setting from the= default value: 0=3DDisable, 1=3DEnable. + UINT32 RDAPT:1; ///< Bit 17 - Enable/Disable Read Amplif= ier Power Training. Note it is not recommended to change this setting from = the default value: 0=3DDisable, 1=3DEnable. + UINT32 WRTC2D:1; ///< Bit 18 - Enable/Disable 2D Write Ti= ming Centering Training. Note it is not recommended to change this setting = from the default value: 0=3DDisable, 1=3DEnable. + UINT32 RDTC2D:1; ///< Bit 19 - Enable/Disable 2D Read Tim= ing Centering Training. Note it is not recommended to change this setting f= rom the default value: 0=3DDisable, 1=3DEnable. + UINT32 WRVC2D:1; ///< Bit 20 - Enable/Disable 2D Write Vo= ltage Centering Training. Note it is not recommended to change this setting= from the default value: 0=3DDisable, 1=3DEnable. + UINT32 RDVC2D:1; ///< Bit 21 - Enable/Disable 2D Read Vol= tage Centering Training. Note it is not recommended to change this setting = from the default value: 0=3DDisable, 1=3DEnable. + UINT32 CMDVC:1; ///< Bit 22 - Enable/Disable Command Vre= f Centering Training. Note it is not recommended to change this setting fro= m the default value 0=3DDisable, 1=3DEnable. + UINT32 LCT:1; ///< Bit 23 - Enable/Disable Late Comman= d Training. Note it is not recommended to change this setting from the defa= ult value: 0=3DDisable, 1=3DEnable. + UINT32 RTL:1; ///< Bit 24 - Enable/Disable Round Trip = Latency function. Note it is not recommended to change this setting from th= e default value: 0=3DDisable, 1=3DEnable. + UINT32 TAT:1; ///< Bit 25 - Enable/Disable Turn Around= Time function. Note it is not recommended to change this setting from the = default value: 0=3DDisable, 1=3DEnable. + UINT32 RMT:1; ///< Bit 26 - Enable/Disable Rank Margin= Tool function: 0=3DDisable, 1=3DEnable. + UINT32 MEMTST:1; ///< Bit 27 - Enable/Disable Memory Test= function: 0=3DDisable, 1=3DEnable. + UINT32 ALIASCHK:1; ///< Bit 28 - Enable/Disable DIMM SPD Al= ias Check: 0=3DDisable, 1=3DEnable + UINT32 RCVENC1D:1; ///< Bit 29 - Enable/Disable Receive Ena= ble Centering Training (LPDDR Only). Note it is not recommended to change t= his setting from the default value: 0=3DDisable, 1=3DEnable + UINT32 RMC:1; ///< Bit 30 - Enable/Disable Retrain Mar= gin Check. Note it is not recommended to change this setting from the defa= ult value: 0=3DDisable, 1=3DEnable + UINT32 WRDSUDT:1; ///< Bit 31 - Enable/Disable Write Drive= Strength Up/Dn independently. Note it is not recommended to change this se= tting from the default value: 0=3DDisable, 1=3DEnable + /// Training Algorithms 2 Offset 88 + UINT32 DCC : 1; ///< Bit 0 - Enable/Disable Duty Cycle = Correction: 0=3DDisable, 1=3DEnable. + UINT32 RDVC1D : 1; ///< Bit 1 - Enable/Disable Read Voltag= e Centering 1D: 0=3DDisable, 1=3DEnable. + UINT32 TXTCO : 1; ///< Bit 2 - Enable/Disable Write TCO C= omp Training: 0=3DDisable, 1=3DEnable. + UINT32 CLKTCO : 1; ///< Bit 3 - Enable/Disable Clock TCO C= omp Training: 0=3DDisable, 1=3DEnable. + UINT32 CMDSR : 1; ///< Bit 4 - Enable/Disable CMD Slew Ra= te Training: 0=3DDisable, 1=3DEnable. + UINT32 CMDDSEQ : 1; ///< Bit 5 - Enable/Disable CMD Drive S= trength and Tx Equalization: 0=3DDisable, 1=3DEnable. + UINT32 DIMMODTCA : 1; ///< Bit 6 - Enable/Disable Dimm ODT CA= Training: 0=3DDisable, 1=3DEnable. + UINT32 TXTCODQS : 1; ///< Bit 7 - Enable/Disable Write TCO D= qs Training: 0=3DDisable, 1=3DEnable. + UINT32 CMDDRUD : 1; ///< Bit 8 - Enable/Disable CMD/CTL Dri= ve Strength Up/Dn 2D: 0=3DDisable, 1=3DEnable. + UINT32 VCCDLLBP : 1; ///< Bit 9 - Enable/Disable VccDLL bypa= ss to VccIOG training: 0=3DDisable, 1=3DEnable. + UINT32 PVTTDNLP : 1; ///< Bit 10 - Enable/Disable PanicVttDnL= p Training: 0=3DDisable, 1=3DEnable. + UINT32 RDVREFDC : 1; ///< Bit 11 - Enable/Disable Read Vref D= ecap Training: 0=3DDisable, 1=3DEnable. + UINT32 VDDQT : 1; ///< Bit 12 - Enable/Disable Vddq Traini= ng: 0=3DDisable, 1=3DEnable. + UINT32 RMTBIT : 1; ///< Bit 13 - Enable/Disable Rank Margin= Tool Per Bit: 0=3DDisable, 1=3DEnable. + UINT32 PDA : 1; ///< BIT 14 - Enable/Disable PDA Enumera= tion Training. Note it is not recommended to change this setting from the d= efault value: 0=3DDisable, 1=3DEnable. + UINT32 DIMMDFE : 1; ///< BIT 15 - Enable/Disable DIMM DFE Tr= aining: 0=3DDisable, 1=3DEnable. + UINT32 TXDQSDCC : 1; ///< BIT 16 - Enable/Disable TX DQS DCC = Training: 0=3DDisable, 1=3DEnable. + UINT32 DRAMDCA : 1; ///< BIT 17 - Enable/Disable DRAM DCA Tr= aining: 0=3DDisable, 1=3DEnable. + UINT32 WRDS : 1; ///< BIT 18 - Enable/Disable Write Drive= r Strength Training: 0=3DDisable, 1=3DEnable. + UINT32 EARLYDIMMDFE : 1; ///< BIT 19 - Enable/Disable EARLY DIMM = DFE Training: 0=3DDisable, 1=3DEnable. + UINT32 ReservedBits2 :12; ///< Bits 20:31 - Reserved + + UINT32 MrcTimeMeasure:1; ///< Offset 92 Bit 0 - Enables serial= debug level to display the MRC execution times only: 0=3DDisable, 1= =3DEnable + UINT32 MrcFastBoot:1; ///< Bit 1 - Enables the MR= C fast boot path for faster cold boot execution: 0=3DDisable, 1=3DEnable= + UINT32 DqPinsInterleaved:1; ///< Bit 2 - Interleaving m= ode of DQ/DQS pins which depends on board routing: 0=3DDisable, 1=3D= Enable + UINT32 RankInterleave:1; ///< Bit 3 - Rank Interleav= e Mode: 0=3DDisable, 1=3DEnable + UINT32 EnhancedInterleave:1; ///< Bit 4 - Enhanced Inter= leave Mode: 0=3DDisable, 1=3DEnable + UINT32 WeaklockEn:1; ///< Bit 5 - Weak Lock Enab= le: 0=3DDisable, 1=3DEnable + UINT32 ChHashEnable:1; ///< Bit 6 - Channel Hash E= nable: 0=3DDisable, 1=3DEnable + UINT32 EnablePwrDn:1; ///< Bit 7 - Enable Power D= own control for DDR: 0=3DPCODE control, 1=3DBIOS control + UINT32 EnablePwrDnLpddr:1; ///< Bit 8 - Enable Power D= own for LPDDR: 0=3DPCODE control, 1=3DBIOS control + UINT32 SrefCfgEna:1; ///< Bit 9 - Enable Self Re= fresh: 0=3DDisable, 1=3DEnable + UINT32 ThrtCkeMinDefeatLpddr:1; ///< Bit 10 - Throttler CKE = min defeature for LPDDR: 0=3DDisable, 1=3DEnable + UINT32 ThrtCkeMinDefeat:1; ///< Bit 11 - Throttler CKE = min defeature: 0=3DDisable, 1=3DEnable + UINT32 AutoSelfRefreshSupport:1; ///< Bit 12 - FALSE =3D No a= uto self refresh support, TRUE =3D auto self refresh support + UINT32 ExtTemperatureSupport:1; ///< Bit 13 - FALSE =3D No e= xtended temperature support, TRUE =3D extended temperature support + UINT32 MobilePlatform:1; ///< Bit 14 - Memory control= ler device id indicates: TRUE if mobile, FALSE if not. Note: This wi= ll be auto-detected and updated. + UINT32 Force1Dpc:1; ///< Bit 15 - TRUE means for= ce one DIMM per channel, FALSE means no limit + UINT32 ForceSingleRank:1; ///< Bit 16 - TRUE means use= Rank0 only (in each DIMM): 0=3DDisable, 1=3DEnable + UINT32 VttTermination:1; ///< Bit 17 - Vtt Terminatio= n for Data ODT: 0=3DDisable, 1=3DEnable + UINT32 VttCompForVsshi:1; ///< Bit 18 - Enable/Disable= Vtt Comparator For Vsshi: 0=3DDisable, 1=3DEnable + UINT32 ExitOnFailure:1; ///< Bit 19 - MRC option for= exit on failure or continue on failure: 0=3DDisable, 1=3DEnable + UINT32 NewFeatureEnable1:1; ///< Bit 20 - Generic enable= knob for new feature set 1 0: Disable ; 1: Enable + UINT32 NewFeatureEnable2:1; ///< Bit 21 - Generic enable= knob for new feature set 2 0: Disable ; 1: Enable + UINT32 RhSelect:2; ///< Bit 22-23 - RH Select: = 0=3DDisable, 1=3DRFM, 2=3DpTRR + UINT32 RefreshPanicWm:4; ///< Bit 24-27 - Deprecated = from revision 17. Use RefreshWm instead. + UINT32 RefreshHpWm:4; ///< Bit 28-31 - Deprecated = from revision 17. Use RefreshWm instead. + UINT32 VddSettleWaitTime; ///< Offset 96 Amount of time in microse= conds to wait for Vdd to settle on top of 200us required by JEDEC spec: = Default=3D0 + UINT16 SrefCfgIdleTmr; ///< Offset 100 Self Refresh idle timer:= 512=3DMinimal, 65535=3DMaximum + UINT16 ChHashMask; ///< Offset 102 Channel Hash Mask: 0x000= 1=3DBIT6 set(Minimal), 0x3FFF=3DBIT[19:6] set(Maximum), 0x30CE=3D BIT[19= :18, 13:12 ,9:7] set + UINT16 DdrFreqLimit; ///< Offset 104 Memory Frequency limit: = 0 =3D Auto, or memory speed value in MT/s: 1067, 1333, 1600 etc. See= the possible values in MrcInterface.h + UINT8 MaxRttWr; ///< Offset 106 Maximum DIMM RTT_WR to u= se in power training: 0=3DODT Off, 1 =3D 120 ohms + UINT8 ThrtCkeMinTmr; ///< Offset 107 Throttler CKE min timer:= 0=3DMinimal, 0xFF=3DMaximum, 0x00=3DDefault + UINT8 ThrtCkeMinTmrLpddr; ///< Offset 108 Throttler CKE min timer = for LPDDR: 0=3DMinimal, 0xFF=3DMaximum, 0x00=3DDefault + BOOLEAN PerBankRefresh; ///< Offset 109 Enables and Disables the= per bank refresh. This only impacts memory technologies that support PBR:= LPDDR4, LPDDR5 and DDR5. FALSE=3DDisabled, TRUE=3DEnabled + UINT8 SaGv; ///< Offset 110 SA GV: 0=3DDisabled, 1=3DPoint1, 2=3DPoint2, 3=3DPoint3, 4=3DPoint4, 5=3DEnabled + UINT8 NModeSupport; ///< Offset 111 Memory N Mode Support - = Enable user to select Auto, 1N or 2N: 0=3DAUTO, 1=3D1N, 2=3D2N. + UINT8 RefClk; ///< Offset 112 Selects the DDR base ref= erence clock. 0x01 =3D 100MHz, 0x00 =3D 133MHz + UINT8 EnCmdRate; ///< Offset 113 CMD Rate Enable: 0=3DDis= able, 5=3D2 CMDs, 7=3D3 CMDs, 9=3D4 CMDs, 11=3D5 CMDs, 13=3D6 CMDs, = 15=3D7 CMDs + UINT8 Refresh2X; ///< Offset 114 Refresh 2x: 0=3DDisab= le, 1=3DEnable for WARM or HOT, 2=3DEnable for HOT only + UINT8 EpgEnable; ///< Offset 115 Enable Energy Performanc= e Gain. + UINT8 UserThresholdEnable; ///< Offset 116 Flag to manually select = the DIMM CLTM Thermal Threshold, 0=3DDisable, 1=3DEnable, 0=3DDefault + UINT8 UserBudgetEnable; ///< Offset 117 Flag to manually select = the Budget Registers for CLTM Memory Dimms , 0=3DDisable, 1=3DEnable, 0= =3DDefault + UINT8 RetrainOnFastFail; ///< Offset 118 Restart MRC in Cold mode= if SW MemTest fails during Fast flow. 0 =3D Disabled, 1 =3D Enabled + UINT8 PowerDownMode; ///< Offset 119 CKE Power Down Mode: = 0xFF=3DAUTO, 0=3DNo Power Down, 1=3D APD mode, 6=3DPPD-DLL Off mode + UINT8 PwdwnIdleCounter; ///< Offset 120 CKE Power Down Mode Idle= Counter: 0=3DMinimal, 255=3DMaximum, 0x80=3D0x80 DCLK + UINT8 CmdRanksTerminated; ///< Offset 121 LPDDR: Bitmask of ranks = that have CA bus terminated. 0x01=3DDefault, Rank0 is terminating and Ra= nk1 is non-terminating + UINT16 MsHashMask; ///< Offset 122 Controller Hash Mask: 0x= 0001=3DBIT6 set(Minimal), 0x3FFF=3DBIT[19:6] set(Maximum), 0x30CE=3D BIT= [19:18, 13:12 ,9:7] set + UINT32 Lp5CccConfig; ///< Offset 124 BitMask where bits [3:0]= are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. = 0 selects Ascending mapping and 1 selects Descending mapping. + UINT8 RMTLoopCount; ///< Offset 128 Indicates the Loop Count= to be used for Rank Margin Tool Testing: 1=3DMinimal, 32=3DMaximum, 0=3DAU= TO, 0=3DDefault + UINT8 MsHashInterleaveBit; ///< Offset 129 Option to select interle= ave Address bit. Valid values are 0 - 3 for BITS 6 - 9 + UINT8 GearRatio; ///< Offset 130 Gear mode when SAGV is d= isabled: 0=3DAuto, 1 - Gear1, 2 - Gear2, 4 - Gear4. + UINT8 Ddr4OneDpc; ///< Offset 131 DDR4 1DPC performance fe= ature: 0 - Disabled; 1 - Enabled on DIMM0 only, 2 - Enabled on DIMM1 only; = 3 - Enabled on both DIMMs. (bit [0] - DIMM0, bit [1] - DIMM1) + UINT32 BclkRfiFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 132 Bclk RFI Frequ= ency for each SAGV point in Hz units. 98000000Hz =3D 98MHz 0 - No RFI Tu= ning. Range is 98Mhz-100Mhz. + UINT16 SaGvFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 148 Frequency per = SAGV point. 0 is Auto, otherwise holds the frequency value expressed as an= integer: 0=3DDefault, 1067, 1333, 1600, 1800, 1867, etc. + UINT8 SaGvGear[MEM_MAX_SAGV_POINTS]; ///< Offset 156 Gear ratio per= SAGV point. 0 is Auto, otherwise holds the Gear ratio expressed as an int= eger: 0=3DAuto, 1, 2, 4 + UINT8 IbeccProtectedRangeEnable[MEM_MAX_IBECC_REGIONS]; ///< Offset 1= 60 Enable use of address range for ECC Protection: 0=3DDisabled, 1= =3DEnabled + UINT32 IbeccProtectedRangeBase[MEM_MAX_IBECC_REGIONS]; ///< Offset 1= 68 Base address for address range of ECC Protection: [0..0x3FFFFFF] + UINT32 IbeccProtectedRangeMask[MEM_MAX_IBECC_REGIONS]; ///< Offset 2= 00 Mask address for address range of ECC Protection: [1..0x3FFFFFF] + + UINT8 McRefresh2X; ///< Offset 232 Deprecated from revision= 19, use McRefreshRate instead + UINT8 Lfsr0Mask; ///< Offset 233 RH pTRR LFSR0 Mask + UINT8 Lfsr1Mask; ///< Offset 234 RH pTRR LFSR1 Mask + UINT8 CmdMirror; ///< Offset 235 BitMask where bits [3:0]= are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. = 0 =3D No Command Mirror and 1 =3D Command Mirror. + UINT8 AllowOppRefBelowWriteThrehold; ///< Offset 236 Option to allow o= pportunistic refreshes while we don't exit power down. + UINT8 WriteThreshold; ///< Offset 237 Option to set number of = writes that can be accumulated while CKE is low before CKE is asserted. + UINT8 PprEnable; ///< Offset 238 Post-Package Repair: 0: = Disabled, 2: Hard PPR + UINT8 MarginLimitCheck; ///< Offset 239 Margin limit check enabl= e: 0=3DDisable, 1=3DL1 only, 2=3DL2 only, 3=3DBoth L1 and L2 + UINT16 MarginLimitL2; ///< Offset 240 Margin limit check L2 th= reshold: 100=3DDefault + UINT8 LpddrRttWr; ///< Offset 242 Initial RttWr for LP4/5 = in Ohms, 0 means Auto + UINT8 LpddrRttCa; ///< Offset 243 Initial RttCa for LP4/5 = in Ohms, 0 means Auto + UINT16 VddqVoltage; ///< Offset 244 DRAM voltage (Vddq) in m= illivolts: 0=3DPlatform Default (no override), 1200=3D1.2V, 1350=3D1= .35V etc. + UINT16 VppVoltage; ///< Offset 246 DRAM voltage (Vpp) in mi= llivolts: 0=3DPlatform Default (no override), 1800=3D1.8V, 2050=3D2.= 05V etc. + UINT8 ExtendedBankHashing; ///< Offset 248 Enable EBH (Extended Ban= k Hashing): 0=3DDisabled; 1 =3D Enabled + UINT8 DynamicMemoryBoost; ///< Offset 249 Enable/Disable Dynamic M= emory Boost Feature. Only valid if SpdProfileSelected is an XMP Profile; ot= herwise ignored. 0=3DDisabled, 1=3DEnabled. + UINT8 IbeccErrInjControl; ///< Offset 250 In-band ECC: Error Injec= tion Control 0: No Error Injection, 1:Inject Correctable Error Address matc= h, 3:Inject Correctable Error on insertion counter, 5: Inject Uncorrectable= Error Address match, 7:Inject Uncorrectable Error on insertion counter + UINT8 RealtimeMemoryFrequency; ///< Offset 251 Enable/Disable Realtime= Memory Frequency feature. Only valid if SpdProfileSelected is an XMP Profi= le; otherwise ignored. 0=3DDisabled, 1=3DEnabled. + UINT32 IbeccErrInjCount; ///< Offset 252 Number of transactions b= etween ECC error injection + UINT64 IbeccErrInjAddress; ///< Offset 256 Address to match against= for ECC error injection + UINT64 IbeccErrInjMask; ///< Offset 264 Mask to match against fo= r ECC error injection + UINT8 RefreshWm; ///< Offset 272 Refresh Watermarks, 0 = =3D Low, 1 =3D High + UINT8 McRefreshRate; ///< Offset 273 Type of solution to be u= sed for RHP - 0/1/2/3 =3D RefreshNORMAL/Refresh1x/Refresh2x/Refresh4x + UINT8 Reserved274[2]; ///< Offset 274-275 Reserved for natural= alignment + UINT32 DebugValue; ///< Offset 276 Debug Value for general = use + UINT16 tRFCpb; ///< Offset 280 User defined Memory Timi= ng tRFCpb value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DA= UTO, 28=3DMaximum. + UINT16 tRFC2; ///< Offset 282 User defined Memory Timi= ng tRFC2 value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAU= TO, 28=3DMaximum. + UINT16 tRFC4; ///< Offset 284 User defined Memory Timi= ng tRFC4 value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAU= TO, 28=3DMaximum. + UINT16 tRRD_L; ///< Offset 286 User defined Memory Timi= ng tRRD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DA= UTO, 28=3DMaximum. + UINT16 tRRD_S; ///< Offset 288 User defined Memory Timi= ng tRRD_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DA= UTO, 28=3DMaximum. + UINT16 tWTR_L; ///< Offset 290 User defined Memory Timi= ng tWTR_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DA= UTO, 28=3DMaximum. + UINT16 tCCD_L; ///< Offset 292 User defined Memory Timi= ng tCCD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DA= UTO, 28=3DMaximum. + UINT16 tWTR_S; ///< Offset 294 User defined Memory Timi= ng tWTR_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DA= UTO, 28=3DMaximum. + UINT64 EccErrInjAddress; ///< Offset 296 Address to match against= for ECC error injection + UINT64 EccErrInjMask; ///< Offset 304 Mask to match against fo= r ECC error injection + UINT32 EccErrInjCount; ///< Offset 312 Number of transactions b= etween ECC error injection + + + UINT16 FreqLimitMixedConfig; ///< Offset 316 Override the reduced spe= ed in mixed 2DPC config or non-POR 2DPC config. 0=3DAuto, otherwise = speed in MT/s: 1067, 1333 etc. See the possible values in MrcInterface.h + UINT8 FirstDimmBitMask; ///< Offset 318 Defines which DIMM shoul= d be populated first on a 2DPC board. + ///< 4 bit mask: Bit[0]: MC0 = DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1. + ///< For each MC, the first D= IMM to be populated should be set to '1'. + ///< Note: this mask is only = for non-ECC DIMM. + UINT8 UserBd; ///< Offset 319 MrcBoardType + ///< 1 - Desktop 1DPC + ///< 2 - Desktop 2DPC, Daisy = Chain, far DIMM should be populated first + ///< 3 - Desktop 2DPC, T-topo= logy with asymmetrical DIMM0/1 routing, has particular DIMM population orde= r + ///< 4 - Desktop 2DPC, T-topo= logy with symmetrical DIMM0/1 routing, no particular DIMM population order + ///< 5 - ULT Mobile + UINT8 SagvSwitchFactorIA; ///< Offset 320 Sagv Switch Factor: 1= , 50=3DMaximum, default 30. + UINT8 SagvSwitchFactorGT; ///< Offset 321 Sagv Switch Factor: 1= , 50=3DMaximum, default 30. + UINT8 SagvSwitchFactorIO; ///< Offset 322 Sagv Switch Factor: 1= , 50=3DMaximum, default 30. + UINT8 SagvSwitchFactorStall; ///< Offset 323 Sagv Switch Factor: 1= , 50=3DMaximum, default 30. + UINT8 SagvHeuristicsUpControl;///< Offset 324 Sagv duration in ms befo= re heuristics up: 1 , 50=3DMaximum, default 1ms. + UINT8 SagvHeuristicsDownControl; ///< Offset 325 Sagv duration in ms b= efore heuristics down: 1 , 50=3DMaximum, default 1ms. + UINT16 FreqLimitMixedConfig_1R1R_8GB; ///< Offset 326 The frequen= cy limit for mixed DIMM configuration 1R1R_8GB (1R 8GB and 1R 8GB in one ch= annel). + ///< It's to be set by cust= omer. Customer can connect it to a setup option, or an UPD, etc. By default= , the value will be 2000. + UINT16 FreqLimitMixedConfig_1R1R_16GB; ///< Offset 328 The frequen= cy limit for mixed DIMM configuration 1R1R_16GB (1R 16GB and 1R 16GB in one= channel). + ///< It's to be set by cust= omer. Customer can connect it to a setup option, or an UPD, etc. By default= , the value will be 2000. + UINT16 FreqLimitMixedConfig_1R1R_8GB_16GB; ///< Offset 330 The frequen= cy limit for mixed DIMM configuration 1R1R_8GB_16GB (1R 8GB and 1R 16GB in = one channel). + ///< It's to be set by cust= omer. Customer can connect it to a setup option, or an UPD, etc. By default= , the value will be 2000. + UINT16 FreqLimitMixedConfig_2R2R; ///< Offset 332 The frequen= cy limit for mixed DIMM configuration 2R_2R (2R 32GB and 2R 32GB in one cha= nnel). + ///< It's to be set by cust= omer. Customer can connect it to a setup option, or an UPD, etc. By default= , the value will be 2000. + UINT16 LctCmdEyeWidth; ///< Offset 334 LCT Comman= d eyewidth + UINT8 FirstDimmBitMaskEcc; ///< Offset 336 Defines whi= ch ECC DIMM should be populated first on a 2DPC board. + ///< 4 bit mask:= Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1= . + ///< For each MC= , the first DIMM to be populated should be set to '1'. + ///< For example= , if one MC is T-topology, there is no special population rule, can put it = as 11 for this MC and it means either D0 or D1 can be + ///< be populate= d firstly. + ///< Note: this = mask is only for ECC DIMM, not for non-ECC DIMM. + UINT8 Lp5BankMode; ///< Offset 337 LP5 Bank M= ode + UINT8 OverloadSAM; ///< Offset 338 Overload S= AM to copy the sagv frquency point. + UINT8 Reserved339[5]; ///< Offset 339-343 Reserve= d for natural alignment +} MEMORY_CONFIGURATION; + +/// Memory Configuration +/// The contents of this structure are not CRC'd by the MRC for option cha= nge detection. +/// Revision 1: - Initial version. +/// Revision 2: - Added MemTestOnWarmBoot +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Bl= ock Header + SA_FUNCTION_CALLS SaCall; ///< Offset 28 Function = calls into the SA. + SA_MEMORY_FUNCTIONS MrcCall; ///< Offset 212 Function = calls into the MRC. + SPD_DATA_BUFFER *SpdData; ///< Offset 236 Memory SP= D data, will be used by the MRC when SPD SmBus address is zero. + SA_MEMORY_DQDQS_MAPPING *DqDqsMap; ///< Offset 240 LPDDR DQ = bit and DQS byte swizzling between CPU and DRAM. + SA_MEMORY_RCOMP *RcompData; ///< Offset 244 DDR RCOMP= resistors and target values. + UINT64 PlatformMemorySize; ///< Offset 248 The minim= um platform memory size required to pass control into DXE + UINT32 CleanMemory:1; ///< Offset 256 Ask MRC t= o clear memory content: FALSE=3DDo not Clear Memory; TRUE=3DClear Me= mory + UINT32 ReservedBits5:31; + /** + Sets the serial debug message level\n + 0x00 =3D Disabled\n + 0x01 =3D Errors only\n + 0x02 =3D Errors and Warnings\n + 0x03 =3D Errors, Warnings, and Info\n + 0x04 =3D Errors, Warnings, Info, and Events\n + 0x05 =3D Displays Memory Init Execution Time Summary only\n + **/ + UINT8 SerialDebugLevel; ///< Offset 260 + UINT8 MemTestOnWarmBoot; ///< Offset 261 Run Base = Memory Test On WarmBoot: 0=3DDisabled, 1=3DEnabled + UINT8 Reserved11[2]; ///< Offset 262 - 263 Res= erved +} MEMORY_CONFIG_NO_CRC; +#pragma pack(pop) + +#endif // _MEMORY_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PchDmi/P= chDmiConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PchDm= i/PchDmiConfig.h new file mode 100644 index 0000000000..84cc21091f --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiCo= nfig.h @@ -0,0 +1,65 @@ +/** @file + DMI policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_DMI_CONFIG_H_ +#define _PCH_DMI_CONFIG_H_ + +extern EFI_GUID gPchDmiConfigGuid; + +/* +Revision 1: - Initial version. +*/ +#define PCH_DMI_PREMEM_CONFIG_REVISION 1 +extern EFI_GUID gPchDmiPreMemConfigGuid; + +#pragma pack (push,1) + +#define PCH_DMI_HWEQ_COEFFS_MAX 8 +/** + Lane specific Dmi Gen3, Gen4 equalization parameters. +**/ +typedef struct { + UINT8 Cm; ///< Coefficient C-1 + UINT8 Cp; ///< Coefficient C+1 + UINT8 Rsvd0[2]; ///< Reserved bytes +} PCH_DMI_EQ_PARAM; + +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block + PCH_DMI_EQ_PARAM DmiHwEqGen3CoeffList[PCH_DMI_HWEQ_COEFFS_MAX]; + UINT8 DmiHweq; + UINT8 Reserved[3]; +} PCH_DMI_PREMEM_CONFIG; + + +/** + The PCH_DMI_CONFIG block describes the expected configuration of the PCH = for DMI. + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + + UINT32 PwrOptEnable : 1; ///< 0: Disable; 1: Enable = DMI Power Optimizer on PCH side. + UINT32 DmiAspmCtrl : 8; ///< ASPM configuration on the PCH= side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig + UINT32 CwbEnable : 1; ///< 0: Disable; 1: Enable = Central Write Buffer feature configurable and enabled by default + UINT32 L1RpCtl : 1; ///< 0: Disable; 1: Enable = Allow DMI enter L1 when all root ports are in L1, L0s or link down. Disable= d by default. + /** + When set to TRUE turns on: + - L1 State Controller Power Gating + - L1 State PHY Data Lane Power Gating + - PHY Common Lane Power Gating + - Hardware Autonomous Enable + - PMC Request Enable and Sleep Enable + **/ + UINT32 DmiPowerReduction : 1; + UINT32 ClockGating : 1; ///< 0: Disable; 1: Enable clock g= ating. + UINT32 Rsvdbits : 19; ///< Reserved bits +} PCH_DMI_CONFIG; + +#pragma pack (pop) + +#endif // _PCH_DMI_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/P= chPcieRp/PchPcieRpConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Conf= igBlock/PcieRp/PchPcieRp/PchPcieRpConfig.h new file mode 100644 index 0000000000..d97f3b878a --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieR= p/PchPcieRpConfig.h @@ -0,0 +1,180 @@ +/** @file + PCH Pcie root port policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_PCIERP_CONFIG_H_ +#define _PCH_PCIERP_CONFIG_H_ + +#include +#include +#include + + + + + +/* + Making any setup structure change after code frozen + will need to maintain backward compatibility, bump up + structure revision and update below history table\n + +Revision 1: - Initial version. +*/ +#define PCIE_RP_DXE_CONFIG_REVISION 1 + +extern EFI_GUID gPchPcieConfigGuid; +extern EFI_GUID gPcieRpPreMemConfigGuid; + +#pragma pack (push,1) + +typedef enum { + PchPcieOverrideDisabled =3D 0, + PchPcieL1L2Override =3D 0x01, + PchPcieL1SubstatesOverride =3D 0x02, + PchPcieL1L2AndL1SubstatesOverride =3D 0x03, + PchPcieLtrOverride =3D 0x04 +} PCH_PCIE_OVERRIDE_CONFIG; + +/// +/// The values before AutoConfig match the setting of PCI Express Base Spe= cification 1.1, please be careful for adding new feature +/// +typedef enum { + PchPcieAspmDisabled, + PchPcieAspmL0s, + PchPcieAspmL1, + PchPcieAspmL0sL1, + PchPcieAspmAutoConfig, + PchPcieAspmMax +} PCH_PCIE_ASPM_CONTROL; + +/** + Refer to PCH EDS for the PCH implementation values corresponding + to below PCI-E spec defined ranges +**/ +typedef enum { + PchPcieL1SubstatesDisabled, + PchPcieL1SubstatesL1_1, + PchPcieL1SubstatesL1_1_2, + PchPcieL1SubstatesMax +} PCH_PCIE_L1SUBSTATES_CONTROL; + +enum PCH_PCIE_MAX_PAYLOAD { + PchPcieMaxPayload128 =3D 0, + PchPcieMaxPayload256, + PchPcieMaxPayloadMax +}; + + +/** + PCH_PCIE_CLOCK describes PCIe source clock generated by PCH. +**/ +typedef struct { + UINT8 Usage; ///< Purpose of given clock (see PCH_PCIE_CLO= CK_USAGE). Default: Unused, 0xFF + UINT8 ClkReq; ///< ClkSrc - ClkReq mapping. Default: 1:1 ma= pping with Clock numbers + UINT8 RsvdBytes[2]; ///< Reserved byte + UINT32 ClkReqGpioPinMux; /// Muxed GPIO details. Refer GPIO_*_MUXING_S= RC_CLKREQ_x* +} PCH_PCIE_CLOCK; + + +/** + The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability= of each PCH PCIe root port. +**/ +typedef struct { + PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///an instance of Pcie= Common Config + UINT8 ExtSync; ///< Indicate whether the extended synch is= enabled. 0: Disable; 1: Enable. + // + // Error handlings + // + UINT8 SystemErrorEnable; ///< Indicate whether the System Error is e= nabled. 0: Disable; 1: Enable. + /** + The Multiple VC (MVC) supports hardware to avoid HoQ block for latency= sensitive TC. + Currently it is only applicable to Root Ports with 2pX4 port configura= tion with 2 VCs,or + DMI port configuration with 3 VCs. For Root Ports 2pX4 configuration, = two RPs (RP0, + RP2) shall support two PCIe VCs (VC0 & VC1) and the other RPs (RP1, RP= 3) shall be + disabled. + 0: Disable; 1: Enable + **/ + UINT8 MvcEnabled; + /** + Virtual Pin Port is industry standard introduced to PCIe Hot Plug supp= ort in systems + when GPIO pins expansion is needed. It is server specific feature. + 0x00: Default; 0xFF: Disabled + **/ + UINT8 VppPort; + UINT8 VppAddress; ///< PCIe Hot Plug VPP= SMBus Address. Default is zero. + UINT8 RsvdBytes0[3]; ///< Reserved bytes +} PCH_PCIE_ROOT_PORT_CONFIG; + +/** + The PCH_PCIE_CONFIG block describes the expected configuration of the PC= H PCI Express controllers + Revision 1: + - Initial version. + Revision 2: + - Moved EnablePort8xhDecode policy to PCIE_COMMON_CONFIG +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /// + /// These members describe the configuration of each PCH PCIe root port. + /// + PCIE_COMMON_CONFIG PcieCommonConfig; + PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS]; + PCH_PCIE_ROOT_PORT_CONFIG DmiPort; + + /// + /// (Test) The Index of PCIe Port that is selected for Port8xh De= code (0 Based) + /// + UINT8 PchPciePort8xhDecodePortIndex; + UINT8 DmiPowerReduction; + UINT8 RsvdBytes0[2]; +} PCH_PCIE_CONFIG; + +/** + The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the= PCH PCI Express controllers + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config= Block Header + /** + Root Port enabling mask. + Bit0 presents RP1, Bit1 presents RP2, and so on. + 0: Disable; 1: Enable. + **/ + UINT32 RpEnabledMask; + /// Configuration of PCIe source clocks + /// + PCH_PCIE_CLOCK PcieClock[PCH_MAX_PCIE_CLOCKS]; + + /** + Per Controller Bifurcation Configuration + 0: Disabled; 1: 4x1; 2: 1x2_2x1; 3: 2x2; 4: 1x4; 5: 4x2; 6: 1x4= _2x2; 7: 2x2_1x4; 8: 2x4; 9: 1x8 (see: PCIE_BIFURCATION_CONFIG) + **/ + UINT8 Bifurcation[PCH_MAX_PCIE_CONTROLLERS]; + UINT8 Rsvd4[(4 - PCH_MAX_PCIE_CONTROLLERS % 4) % 4]; +} PCH_PCIE_RP_PREMEM_CONFIG; + +/** + The PCIE_RP_DXE_CONFIG block describes the expected configuration of the= PCH PCI Express controllers in DXE phase + + Revision 1: + - Init version +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block H= eader + + /** + PCIe device override table + The PCIe device table is being used to override PCIe device ASPM setti= ngs. + And it's only used in DXE phase. + Please refer to PCIE_DEVICE_OVERRIDE structure for the table. + Last entry VendorId must be 0. + **/ + PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr; +} PCIE_RP_DXE_CONFIG; + +#pragma pack (pop) + +#endif // _PCH_PCIERP_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/P= cieConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/= PcieConfig.h new file mode 100644 index 0000000000..07a5644f43 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConf= ig.h @@ -0,0 +1,408 @@ +/** @file + PCIe Config Block + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCIE_CONFIG_H_ +#define _PCIE_CONFIG_H_ +#include + +#define PCIE_LINK_EQ_COEFFICIENTS_MAX 10 +#define PCIE_LINK_EQ_PRESETS_MAX 11 +extern EFI_GUID gPcieConfigGuid; + +#pragma pack (push,1) + +enum PCIE_COMPLETION_TIMEOUT { + PcieCompletionTO_Default, + PcieCompletionTO_50_100us, + PcieCompletionTO_1_10ms, + PcieCompletionTO_16_55ms, + PcieCompletionTO_65_210ms, + PcieCompletionTO_260_900ms, + PcieCompletionTO_1_3P5s, + PcieCompletionTO_4_13s, + PcieCompletionTO_17_64s, + PcieCompletionTO_Disabled +}; + +typedef enum { + PcieAuto, + PcieGen1, + PcieGen2, + PcieGen3, + PcieGen4, + PcieGen5 +} PCIE_SPEED; + +typedef enum { + PcieDisabled, + PcieL1SUB_1, + PcieL1SUB_1_2 +}L1_SUBSTATES; + +/** + Represent lane specific PCIe Gen3 equalization parameters. +**/ +typedef struct { + UINT8 Cm; ///< Coefficient C-1 + UINT8 Cp; ///< Coefficient C+1 + UINT8 Rsvd0[2]; ///< Reserved bytes +} PCIE_EQ_PARAM; + +typedef struct { + UINT16 LtrMaxSnoopLatency; ///< (Test) Laten= cy Tolerance Reporting, Max Snoop Latency. + UINT16 LtrMaxNoSnoopLatency; ///< (Test) Laten= cy Tolerance Reporting, Max Non-Snoop Latency. + UINT8 SnoopLatencyOverrideMode; ///< (Test) Laten= cy Tolerance Reporting, Snoop Latency Override Mode. + UINT8 SnoopLatencyOverrideMultiplier; ///< (Test) Laten= cy Tolerance Reporting, Snoop Latency Override Multiplier. + UINT16 SnoopLatencyOverrideValue; ///< (Test) Laten= cy Tolerance Reporting, Snoop Latency Override Value. + UINT8 NonSnoopLatencyOverrideMode; ///< (Test) Laten= cy Tolerance Reporting, Non-Snoop Latency Override Mode. + UINT8 NonSnoopLatencyOverrideMultiplier; ///< (Test) Laten= cy Tolerance Reporting, Non-Snoop Latency Override Multiplier. + UINT16 NonSnoopLatencyOverrideValue; ///< (Test) Laten= cy Tolerance Reporting, Non-Snoop Latency Override Value. + UINT8 LtrConfigLock; ///< 0: Disable; = 1: Enable. + UINT8 ForceLtrOverride; + UINT16 RsvdByte1; +} PCIE_LTR_CONFIG; + + +/** + Specifies the form factor that the slot + implements. For custom form factors that + do not require any special handling please + set PcieFormFactorOther. +**/ +typedef enum { + PcieFormFactorOther =3D 0, + PcieFormFactorCem, + PcieFormFactorMiniPci, + PcieFormFactorM2, + PcieFormFactorOcuLink, + PcieFormFactorExpressModule, // Also known as Server IO module(SIOM) + PcieFormFactorExpressCard, + PcieFormFactorU2 // Also known as SF-8639 +} PCIE_FORM_FACTOR; + +typedef enum { + PcieLinkHardwareEq =3D 0, ///< Hardware is responsible for performing c= oefficient/preset search. + PcieLinkFixedEq ///< No coefficient/preset search is performed.= Fixed values are used. +} PCIE_LINK_EQ_METHOD; + +typedef enum { + PcieLinkEqPresetMode =3D 0, ///< Use presets during PCIe link equaliza= tion + PcieLinkEqCoefficientMode ///< Use coefficients during PCIe link equal= ization +} PCIE_LINK_EQ_MODE; + +typedef struct { + UINT32 PreCursor; ///< Pre-cursor coefficient + UINT32 PostCursor; ///< Post-cursor coefficient +} PCIE_LINK_EQ_COEFFICIENTS; + +/** + PCIe Link EQ Platform Settings +**/ +typedef struct { + UINT8 PcieLinkEqMethod; ///< Tells BI= OS which link EQ method should be used for this port. Please refer to PCIE_= LINK_EQ_METHOD for details of supported methods. Default: PcieLinkHardwareE= q + UINT8 PcieLinkEqMode; ///< Tells BI= OS which mode should be used for PCIe link EQ. Please refer to PCIE_LINK_EQ= _MODE for details of supported modes. Default: depends on SoC + /** + Specifies if BIOS should perform local transmitter override during pha= se 2 of EQ process. + If enabled value in Ph2LocalTransmitterOverridePreset must be valid. + 0: Disabled; 1: Enabled + **/ + UINT8 LocalTransmitterOverrideEnable; + /** + Tells BIOS how many presets/coefficients should be used during link EQ= . + Entries in the Ph3CoefficientsList or Ph3PresetList(depending on chose= n mode) need to be valid up to the number specified in this field. + **/ + UINT8 Ph3NumberOfPresetsOrCoefficients; + + PCIE_LINK_EQ_COEFFICIENTS Ph3CoefficientsList[PCIE_LINK_EQ_COEFFICIENTS= _MAX]; ///< List of the PCIe coefficients to be used during equalization p= rocess. Only valid if PcieLinkEqMode is PcieLinkEqCoefficientMode + UINT32 Ph3PresetList[PCIE_LINK_EQ_PRESETS_MAX]; = ///< List of the PCIe preset values to be used during equalization = process. Only valid if PcieLinkEqMode is PcieLinkEqPresetMode + UINT32 Ph1DownstreamPortTransmitterPreset; ///< Spe= cifies the value of the downstream port transmitter preset to be used durin= g phase 1 of the equalization process. Will be applied to all lanes + UINT32 Ph1UpstreamPortTransmitterPreset; ///< Spe= cifies the value of the upstream port transmitter preset to be used during = phase 1 of the equalization process. Will be applied to all lanes + /** + Specifies the preset that should be used during local transmitter over= ride during phase 2 of EQ process. + Used only if LocalTransmitterOverrideEnable is TRUE. Will be applied t= o all PCIe lanes of the root port. + Valid up to the PCIE_LINK_EQ_PRESET_MAX value. Default: 0<\b> + **/ + UINT32 Ph2LocalTransmitterOverridePreset; + UINT32 PCETTimer; ///< PCET Timer v= alue for single PCIe speed. + UINT8 RemotePresetCoeffoverride; ///< Remote Trans= mitter Preset Coefficient Override for single PCIe speed. + /** + PCIe Equalization Phase 3 Enable Control + - Disabled (0x0) : Disable phase 3 (Default) + - Enabled (0x1) : Enable phase 3 + **/ + UINT8 EqPh3Bypass; + /** + PCIe Equalization Phase 2-3 Enable Control + - Disabled (0x0) : Disable Phase 2 - Phase 3 (Default) + - Enabled (0x1) : Enable Phase 2 - Phase 3 + **/ + UINT8 EqPh23Bypass; + UINT8 TsLockTimer; ///< 8.0GT/s Tra= ining Sequence Wait Latency For Presets / Coefficients Evaluation - Gen3 TS= Lock Timer +} PCIE_LINK_EQ_PLATFORM_SETTINGS; + +//Note: This structure will be expanded to hold all common PCIe policies b= etween SA and PCH RootPort +typedef struct { + UINT32 HotPlug : 1; ///< Indicate whether th= e root port is hot plug available. 0: Disable; 1: Enable. + UINT32 PmSci : 1; ///< Indicate whether th= e root port power manager SCI is enabled. 0: Disable; 1: Enable. + UINT32 TransmitterHalfSwing : 1; ///< Indicate whether th= e Transmitter Half Swing is enabled. 0: Disable; 1: Enable. + UINT32 AcsEnabled : 1; ///< Indicate whether th= e ACS is enabled. 0: Disable; 1: Enable. + // + // Error handlings + // + UINT32 AdvancedErrorReporting : 1; ///< Indicate whether th= e Advanced Error Reporting is enabled. 0: Disable; 1: Enable. + UINT32 UnsupportedRequestReport : 1; ///< Indicate whether th= e Unsupported Request Report is enabled. 0: Disable; 1: Enable. + UINT32 FatalErrorReport : 1; ///< Indicate whether th= e Fatal Error Report is enabled. 0: Disable; 1: Enable. + UINT32 NoFatalErrorReport : 1; ///< Indicate whether th= e No Fatal Error Report is enabled. 0: Disable; 1: Enable. + UINT32 CorrectableErrorReport : 1; ///< Indicate whether th= e Correctable Error Report is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether th= e System Error on Fatal Error is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether th= e System Error on Non Fatal Error is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether th= e System Error on Correctable Error is enabled. 0: Disable; 1: Enabl= e. + /** + Max Payload Size supported, Default 128B, see enum CPU_PCIE_MAX= _PAYLOAD + Changes Max Payload Size Supported field in Device Capabilities of the= root port. + **/ + UINT32 MaxPayload : 2; + UINT32 DpcEnabled : 1; ///< Downstream Port Con= tainment. 0: Disable; 1: Enable + UINT32 RpDpcExtensionsEnabled : 1; ///< RP Extensions for D= ownstream Port Containment. 0: Disable; 1: Enable + /** + Indicates how this root port is connected to endpoint. 0: built-in dev= ice; 1: slot + Built-in is incompatible with hotplug-capable ports. + **/ + UINT32 SlotImplemented : 1; + UINT32 PtmEnabled : 1; ///< Enables PTM capabil= ity + UINT32 SlotPowerLimitScale : 2; ///< (Test) Speci= fies scale used for slot power limit value. Leave as 0 to set to default. D= efault is zero. + UINT32 SlotPowerLimitValue : 12; //< (Test) Specif= ies upper limit on power supplies by slot. Leave as 0 to set to default. De= fault is zero. + /** + Probe CLKREQ# signal before enabling CLKREQ# based power management. + Conforming device shall hold CLKREQ# low until CPM is enabled. This fe= ature attempts + to verify CLKREQ# signal is connected by testing pad state before enab= ling CPM. + In particular this helps to avoid issues with open-ended PCIe slots. + This is only applicable to non hot-plug ports. + 0: Disable; 1: Enable. + **/ + UINT32 ClkReqDetect : 1; + /** + Set if the slot supports manually operated retention latch. + **/ + UINT32 MrlSensorPresent : 1; + UINT32 RelaxedOrder : 1; + UINT32 NoSnoop : 1; + /// + /// This member describes whether Peer Memory Writes are enabled on the = platform. 0: Disable; 1: Enable. + /// + UINT32 EnablePeerMemoryWrite : 1; + /// + /// This member describes whether the PCI Express Clock Gating for each = root port + /// is enabled by platform modules. 0: Disable; 1: Enable. + /// + UINT32 ClockGating : 1; + /// + /// This member describes whether the PCI Express Power Gating for each = root port + /// is enabled by platform modules. 0: Disable; 1: Enable. + /// + UINT32 PowerGating : 1; + UINT32 RsvdBits0 : 25; ///< Reserved bits. + /** + PCIe Gen3 Equalization Phase 3 Method (see CPU_PCIE_EQ_METHOD). + 0: DEPRECATED, hardware equalization; 1: hardware equalization;= 4: Fixed Coefficients + **/ + UINT8 Gen3EqPh3Method; + UINT8 PhysicalSlotNumber; ///< Indicates the slot = number for the root port. Default is the value as root port index. + UINT8 CompletionTimeout; ///< The completion time= out configuration of the root port (see: CPU_PCIE_COMPLETION_TIMEOUT). Defa= ult is PchPcieCompletionTO_Default. + // + // Power Management + // + UINT8 Aspm; ///< The ASPM configurat= ion of the root port (see: CPU_PCIE_ASPM_CONTROL). Default is PchPcieAsp= mAutoConfig. + UINT8 L1Substates; ///< The L1 Substates co= nfiguration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). Default i= s PchPcieL1SubstatesL1_1_2. + UINT8 LtrEnable; ///< Latency Tolerance R= eporting Mechanism. 0: Disable; 1: Enable. + UINT8 EnableCpm; ///< Enables Clock Power= Management; even if disabled, CLKREQ# signal can still be controlled by L1= PM substates mechanism + UINT8 PcieSpeed; ///< Contains speed of P= CIe bus (see: PCIE_SPEED) + /** + (Test) + Forces LTR override to be permanent + The default way LTR override works is: + rootport uses LTR override values provided by BIOS until connected devic= e sends an LTR message, then it will use values from the message + This settings allows force override of LTR mechanism. If it's enabled, t= hen: + rootport will use LTR override values provided by BIOS forever; LTR mess= ages sent from connected device will be ignored + **/ + PCIE_LTR_CONFIG PcieRpLtrConfig; ///< (Test)= Latency Tolerance Reporting Policies including LTR limit and Override + /** + The number of milliseconds reference code will wait for link to exit D= etect state for enabled ports + before assuming there is no device and potentially disabling the port. + It's assumed that the link will exit detect state before root port ini= tialization (sufficient time + elapsed since PLTRST de-assertion) therefore default timeout is zero. = However this might be useful + if device power-up seqence is controlled by BIOS or a specific device = requires more time to detect. + In case of non-common clock enabled the default timout is 15ms. + Default: 0 + **/ + UINT16 DetectTimeoutMs; + UINT8 FormFactor; // Please check PCIE_FORM_FACTOR for supported value= s + UINT8 L1Low; ///< L1.LOW enable/disab= le. 0: Disable; 1: Enable. + UINT8 LinkDownGpios; + /// + /// 0: Use project default equalization settings; 1: Use equaliza= tion settings from PcieLinkEqPlatformSettings + /// + UINT8 OverrideEqualizationDefaults; + UINT8 Reserved[2]; + PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen3LinkEqPlatformSettings; ///< = Global PCIe Gen3 link EQ settings that BIOS will use during PCIe link EQ fo= r every port. + PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen4LinkEqPlatformSettings; ///< = Global PCIe Gen4 link EQ settings that BIOS will use during PCIe link EQ fo= r every port. + PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen5LinkEqPlatformSettings; ///< = Global PCIe Gen5 link EQ settings that BIOS will use during PCIe link EQ fo= r every port. +} PCIE_ROOT_PORT_COMMON_CONFIG; + +/** + PCIe Common Config + @note This structure will be expanded to hold all common PCIe policies b= etween SA and PCH +**/ +typedef struct { + /** + RpFunctionSwap allows BIOS to use root port function number swapping w= hen root port of function 0 is disabled. + A PCIE device can have higher functions only when Function0 exists. To= satisfy this requirement, + BIOS will always enable Function0 of a device that contains more than = 0 enabled root ports. + - Enabled: One of enabled root ports get assigned to Function0. + This offers no guarantee that any particular root port will be avail= able at a specific DevNr:FuncNr location + - Disabled: Root port that corresponds to Function0 will be kept visib= le even though it might be not used. + That way rootport - to - DevNr:FuncNr assignment is constant. This o= ption will impact ports 1, 9, 17. + NOTE: This option will not work if ports 1, 9, 17 are fused or confi= gured for RST PCIe storage or disabled through policy + In other words, it only affects ports that would become hidden= because they have no device connected. + NOTE: Disabling function swap may have adverse impact on power manag= ement. This option should ONLY + be used when each one of root ports 1, 9, 17: + - is configured as PCIe and has correctly configured ClkReq signal= , or + - does not own any mPhy lanes (they are configured as SATA or USB) + **/ + UINT32 RpFunctionSwap : 1; + /** + Compliance Test Mode shall be enabled when using Compliance Load Board= . + 0: Disable, 1: Enable + **/ + UINT32 ComplianceTestMode : 1; + UINT32 RsvdBits0 : 30; ///< Reserved bits + /// + /// (Test) This member describes whether PCIE root port Port 8xh = Decode is enabled. 0: Disable; 1: Enable. + /// + UINT8 EnablePort8xhDecode; + UINT8 RsvdBytes0[3]; + /// + /// List of coefficients used during equalization (applicable to both so= ftware and hardware EQ) + /// Deprecated Policy + /// + PCIE_EQ_PARAM HwEqGen3CoeffList[PCIE_HWEQ_COEFFS_MAX]= ; +} PCIE_COMMON_CONFIG; + +typedef struct { + PCIE_EQ_PARAM HwEqGen3CoeffList[CPU_PCIE_MAX_= ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX]; + PCIE_EQ_PARAM HwEqGen4CoeffList[CPU_PCIE_MAX_= ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX]; + PCIE_EQ_PARAM HwEqGen5CoeffList[CPU_PCIE_MAX_= ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX]; +} PCIE_COMMON_CONFIG2; + + +/** + PCIe device table entry entry + + The PCIe device table is being used to override PCIe device ASPM setting= s. + To take effect table consisting of such entries must be instelled as PPI + on gPchPcieDeviceTablePpiGuid. + Last entry VendorId must be 0. +**/ +typedef struct { + UINT16 VendorId; ///< The vendor Id of Pci Express c= ard ASPM setting override, 0xFFFF means any Vendor ID + UINT16 DeviceId; ///< The Device Id of Pci Express c= ard ASPM setting override, 0xFFFF means any Device ID + UINT8 RevId; ///< The Rev Id of Pci Express card= ASPM setting override, 0xFF means all steppings + UINT8 BaseClassCode; ///< The Base Class Code of Pci Exp= ress card ASPM setting override, 0xFF means all base class + UINT8 SubClassCode; ///< The Sub Class Code of Pci Expr= ess card ASPM setting override, 0xFF means all sub class + UINT8 EndPointAspm; ///< Override device ASPM (see: PCH= _PCIE_ASPM_CONTROL) + ///< Bit 1 must be set in OverrideC= onfig for this field to take effect + UINT16 OverrideConfig; ///< The override config bitmap (se= e: PCH_PCIE_OVERRIDE_CONFIG). + /** + The L1Substates Capability Offset Override. (applicable if bit 2 is se= t in OverrideConfig) + This field can be zero if only the L1 Substate value is going to be ov= erride. + **/ + UINT16 L1SubstatesCapOffset; + /** + L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideCo= nfig) + Set to zero then the L1 Substate Capability [3:0] is ignored, and only= L1s values are override. + Only bit [3:0] are applicable. Other bits are ignored. + **/ + UINT8 L1SubstatesCapMask; + /** + L1 Substate Port Common Mode Restore Time Override. (applicable if bit= 2 is set in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sCommonModeRestoreTime; + /** + L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set= in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sTpowerOnScale; + /** + L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set= in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sTpowerOnValue; + + /** + SnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 ar= e valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in t= hese bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Snoop Latency Value. The value in these bits will be mul= tiplied with + the scale in bits 12:10 + + This field takes effect only if bit 3 is set in OverrideConfig. + **/ + UINT16 SnoopLatency; + /** + NonSnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 ar= e valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in t= hese bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be= multiplied with + the scale in bits 12:10 + + This field takes effect only if bit 3 is set in OverrideConfig. + **/ + UINT16 NonSnoopLatency; + + /** + Forces LTR override to be permanent + The default way LTR override works is: + rootport uses LTR override values provided by BIOS until connected d= evice sends an LTR message, then it will use values from the message + This settings allows force override of LTR mechanism. If it's enabled,= then: + rootport will use LTR override values provided by BIOS forever; LTR = messages sent from connected device will be ignored + **/ + UINT8 ForceLtrOverride; + UINT8 Reserved[3]; +} PCIE_DEVICE_OVERRIDE; + +#pragma pack (pop) +#endif // _PCIE_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/P= ciePreMemConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/P= cieRp/PciePreMemConfig.h new file mode 100644 index 0000000000..fe0be3ec12 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PciePreM= emConfig.h @@ -0,0 +1,36 @@ +/** @file + PCIe Config Block PreMem + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCIE_PREMEM_CONFIG_H_ +#define _PCIE_PREMEM_CONFIG_H_ + + +extern EFI_GUID gPciePreMemConfigGuid; + +#pragma pack (push,1) + +/** + PCIe IMR Config +**/ +typedef struct { + UINT8 ImrEnabled; ///< PCIe IMR. 0: Disabl= e; 1: Enable. + UINT8 ImrRpLocation; ///< 0: PCH_PCIe; 1: CPU_PC= Ie. If PCIeImrEnabled is TRUE then this will use to select the Root port lo= cation from PCH PCIe or CPU PCIe.Refer PCIE_IMR_ROOT_PORT_LOCATION above + UINT16 ImrSize; ///< PCIe IMR size in megab= ytes + UINT8 ImrRpSelection; ///< Index of root port tha= t is selected for PCIe IMR (0 based) + UINT8 Rsvd0[3]; +} PCIE_IMR_CONFIG; + +/** + PCIe Pre-Memory Configuration + Revision 1: - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header + PCIE_IMR_CONFIG PcieImr; ///< IMR Configuration +} PCIE_PREMEM_CONFIG; + +#pragma pack (pop) +#endif // _PCIE_PREMEM_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrC= onfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConf= ig.h new file mode 100644 index 0000000000..35ecb53ed2 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h @@ -0,0 +1,76 @@ +/** @file + ADR policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ADR_CONFIG_H_ +#define _ADR_CONFIG_H_ + +#include + +extern EFI_GUID gAdrConfigGuid; + +#pragma pack (push,1) + + +/** + ADR Source Enable +**/ +typedef union { + struct { + UINT32 Reserved1 : 1; + UINT32 AdrSrcPbo : 1; + UINT32 AdrSrcPmcUncErr : 1; + UINT32 AdrSrcPchThrm : 1; + UINT32 AdrSrcMePbo : 1; + UINT32 AdrSrcCpuThrm : 1; + UINT32 AdrSrcMegbl : 1; + UINT32 AdrSrcLtReset : 1; + UINT32 AdrSrcPmcWdt : 1; + UINT32 AdrSrcMeWdt : 1; + UINT32 AdrSrcPmcFw : 1; + UINT32 AdrSrcPchpwrFlr : 1; + UINT32 AdrSrcSyspwrFlr : 1; + UINT32 Reserved2 : 1; + UINT32 AdrSrcMiaUxsErr : 1; + UINT32 AdrSrcMiaUxErr : 1; + UINT32 AdrSrcCpuThrmWdt : 1; + UINT32 AdrSrcMeUncErr : 1; + UINT32 AdrSrcAdrGpio : 1; + UINT32 AdrSrcOcwdtNoicc : 1; + UINT32 AdrSrcOcwdtIcc : 1; + UINT32 AdrSrcCseHecUncErr : 1; + UINT32 AdrSrcPmcSramUncErr : 1; + UINT32 AdrSrcPmcIromParity : 1; + UINT32 AdrSrcPmcRfFusaErr : 1; + UINT32 Reserved3 : 4; + UINT32 AdrSrcPpbrParityErr : 1; + UINT32 Reserved4 : 2; + } Field; + UINT32 Value; +} ADR_SOURCE_ENABLE; + +/** + ADR Configuration + Revision 1: - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 AdrEn : 2; ///< Determine if Adr is enabl= ed - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE + UINT32 AdrTimerEn : 2; ///< Determine if Adr timer op= tions are enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE + UINT32 AdrTimer1Val : 8; ///< Determines the Timeout va= lue used for the ADR timer 1. A value of zero bypasses the timer + UINT32 AdrMultiplier1Val : 3; ///< Specifies the tick freque= ncy upon which the timer 1 will increment. ADR_TIMER_SCALE should be used t= o encode values + UINT32 AdrTimer2Val : 8; ///< Determines the Timeout va= lue used for the ADR timer 2. A value of zero bypasses the timer + UINT32 AdrMultiplier2Val : 3; ///< Specifies the tick freque= ncy upon which the timer 2 will increment. ADR_TIMER_SCALE should be used t= o encode values + UINT32 AdrHostPartitionReset : 2; ///< Determine if Host Partiti= on Reset is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE + UINT32 AdrSrcOverride : 1; ///< Check if default ADR sour= ces will be overriten with custom 0: Not overwritten, 1: Overwritten + UINT32 AdrPlatAckEn : 2; ///< Determine if Platform Ack= nowledge is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE + UINT32 ReservedBits : 1; + ADR_SOURCE_ENABLE AdrSrcSel; ///< Determine which ADR sourc= es are enabled - 0: Enabled, 1: Disabled +} ADR_CONFIG; + +#pragma pack (pop) + +#endif // _ADR_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/PmCo= nfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig= .h new file mode 100644 index 0000000000..0a2ae50e6a --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h @@ -0,0 +1,86 @@ +/** @file + Power Management policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PM_CONFIG_H_ +#define _PM_CONFIG_H_ + +#include + +extern EFI_GUID gPmConfigGuid; + +#pragma pack (push,1) + +/** + Description of Global Reset Trigger/Event Mask register +**/ +typedef union { + struct { + UINT32 Reserved1 : 1; + UINT32 Pbo : 1; + UINT32 PmcUncErr : 1; + UINT32 PchThrm : 1; + UINT32 MePbo : 1; + UINT32 CpuThrm : 1; + UINT32 Megbl : 1; + UINT32 LtReset : 1; + UINT32 PmcWdt : 1; + UINT32 MeWdt : 1; + UINT32 PmcFw : 1; + UINT32 PchpwrFlr : 1; + UINT32 SyspwrFlr : 1; + UINT32 Reserved2 : 1; + UINT32 MiaUxsErr : 1; + UINT32 MiaUxErr : 1; + UINT32 CpuThrmWdt : 1; + UINT32 MeUncErr : 1; + UINT32 AdrGpio : 1; + UINT32 OcwdtNoicc : 1; + UINT32 OcwdtIcc : 1; + UINT32 CseHecUncErr : 1; + UINT32 PmcSramUncErr : 1; + UINT32 PmcIromParity : 1; + UINT32 PmcRfFusaErr : 1; + UINT32 Reserved3 : 4; + UINT32 PpbrParityErr : 1; + UINT32 Reserved4 : 2; + } Field; + UINT32 Value; +} PMC_GLOBAL_RESET_MASK; + +typedef union { + struct { + UINT32 HostResetTimeout : 1; + UINT32 SxEntryTimeout : 1; + UINT32 HostRstProm : 1; + UINT32 HsmbMsg : 1; + UINT32 Pmc3Strike : 1; + UINT32 FwGblrstScratch5 : 1; + UINT32 PmcDmaTimeout : 1; + UINT32 EspiType7 : 1; + UINT32 EspiType8 : 1; + UINT32 FwGblRstScratch10 : 1; + UINT32 FwGblRstScratch11 : 1; + UINT32 LpmFwErr : 1; + UINT32 BscanMode : 1; + UINT32 SlpLvlRspErr : 1; + UINT32 FwGblrstScratch15 : 1; + UINT32 FwGblrstScratch16 : 1; + UINT32 FwGblrstScratch17 : 1; + UINT32 FwGblrstScratch18 : 1; + UINT32 FwGblrstScratch19 : 1; + UINT32 FwGblrstScratch20 : 1; + UINT32 FwGblrstScratch21 : 1; + UINT32 FwGblrstScratch22 : 1; + UINT32 FwGblrstScratch23 : 1; + UINT32 Rsvd : 9; + } Field; + UINT32 Value; +} PMC_GLOBAL_RESET_MASK1; + + +#pragma pack (pop) + +#endif // _PM_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcC= onfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConf= ig.h new file mode 100644 index 0000000000..62f8303558 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h @@ -0,0 +1,37 @@ +/** @file + RTC policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _RTC_CONFIG_H_ +#define _RTC_CONFIG_H_ + +extern EFI_GUID gRtcConfigGuid; + +#pragma pack (push,1) + +/** + The RTC_CONFIG block describes the expected configuration of RTC configu= ration. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + When set, prevents RTC TS (BUC.TS) from being changed. + This BILD bit has different function compared to LPC/eSPI, SPI. + 0: Disabled; 1: Enabled + **/ + UINT32 BiosInterfaceLock : 1; + /** + When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are lock= ed + and cannot be accessed. + Writes will be droipped and reads will not return any guaranteed data. + 0: Disabled; 1: Enabled + **/ + UINT32 MemoryLock : 1; + UINT32 RsvdBits0 : 30; +} RTC_CONFIG; + +#pragma pack (pop) + +#endif // _RTC_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SerialIo= /SerialIoConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/S= erialIo/SerialIoConfig.h new file mode 100644 index 0000000000..b5c3b21606 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SerialIo/Serial= IoConfig.h @@ -0,0 +1,33 @@ +/** @file + Serial IO policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SERIAL_IO_CONFIG_H_ +#define _SERIAL_IO_CONFIG_H_ + +extern EFI_GUID gSerialIoConfigGuid; + +#include + +#pragma pack (push,1) + +/** + The SERIAL_IO_CONFIG block provides the configurations to set the Serial= IO controllers + + Revision 1: + - Inital version. + Revision 2: + - Modified SPI Config to support pinmux functionality. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; = ///< Config Block Header + SERIAL_IO_SPI_CONFIG SpiDeviceConfig[PCH_MAX_SERIALIO_SPI_CONTROLLERS];= ///< SPI Configuration + SERIAL_IO_I2C_CONFIG I2cDeviceConfig[PCH_MAX_SERIALIO_I2C_CONTROLLERS];= ///< I2C Configuration + SERIAL_IO_UART_CONFIG UartDeviceConfig[PCH_MAX_SERIALIO_UART_CONTROLLERS= ]; ///< UART Configuration +} SERIAL_IO_CONFIG; + +#pragma pack (pop) + +#endif // _SERIAL_IO_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiConfig= .h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiConfig.h new file mode 100644 index 0000000000..5b59f08df2 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiConfig.h @@ -0,0 +1,105 @@ +/** @file + Si Config Block + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SI_CONFIG_H_ +#define _SI_CONFIG_H_ + +#define SI_CONFIG_REVISION 1 + +extern EFI_GUID gSiConfigGuid; + + +#pragma pack (push,1) + +/** + The Silicon Policy allows the platform code to publish a set of configur= ation + information that the RC drivers will use to configure the silicon hardwa= re. + + Revision 1: - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header + // + // Platform specific common policies that used by several silicon compon= ents. + // + UINT8 CsmFlag; ///< offset 28 CSM status flag.@deprecate= d. + /** + This is used to skip the SSID programming in silicon code. + When set to TRUE, silicon code will not do any SSID programming and pl= atform code + needs to handle that by itself properly. + 0: FALSE, 1: TRUE + **/ + UINT8 SkipSsidProgramming; ///< offset 29 + UINT8 RsvdBytes0[2]; ///< offset 30 - 31 + /** + When SkipSsidProgramming is FALSE, silicon code will use this as defau= lt value + to program the SVID for all internal devices. + 0: use silicon default SVID 0x8086 , Non-zero: use customized S= VID. + **/ + UINT16 CustomizedSvid; ///< offset 32 - 33 + /** + When SkipSsidProgramming is FALSE, silicon code will use this as defau= lt value + to program the Sid for all internal devices. + 0: use silicon default SSID 0x7270 , Non-zero: use customized S= SID. + **/ + UINT16 CustomizedSsid; ///< offset 34 - 35 + UINT32 *SsidTablePtr; ///< offset 36 - 39 + /** + Number of valid enties in SsidTablePtr. + This is valid when SkipSsidProgramming is FALSE; + Default is 0. + **/ + UINT16 NumberOfSsidTableEntry; ///< offset 40 - 41 + UINT8 RsvdBytes1[2]; ///< offset 42 - 43 + /** + This is used to skip setting BIOS_DONE MSR during firmware update boot= mode. + When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, + skip setting BIOS_DONE MSR at EndofPei. + 0: FALSE, 1: TRUE + **/ + UINT8 SkipBiosDoneWhenFwUpdate; ///< Offset 44 + UINT8 RsvdBytes2[3]; ///< Offset 45 - 47 +} SI_CONFIG; + +#pragma pack (pop) + + +/// +/// Subsystem Vendor ID / Subsystem ID +/// +typedef struct { + UINT16 SubSystemVendorId; + UINT16 SubSystemId; +} SVID_SID_VALUE; + +// +// Below is to match PCI_SEGMENT_LIB_ADDRESS () which can directly send to= PciSegmentRead/Write functions. +// +typedef struct { + union { + struct { + UINT32 Register:12; + UINT32 Function:3; + UINT32 Device:5; + UINT32 Bus:8; + UINT32 Reserved1:4; + UINT32 Segment:16; + UINT32 Reserved2:16; + } Bits; + UINT64 SegBusDevFuncRegister; + } Address; + SVID_SID_VALUE SvidSidValue; + UINT32 Reserved; +} SVID_SID_INIT_ENTRY; + + +typedef struct { + UINT32 SkipBus; + UINT32 SkipDevice; + UINT32 SkipFunction; +} SVID_SID_SKIP_TABLE; + +#endif // _SI_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiPreMem= Config.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiPreMemCo= nfig.h new file mode 100644 index 0000000000..584a0d4169 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.= h @@ -0,0 +1,63 @@ +/** @file + Si Config Block PreMem + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SI_PREMEM_CONFIG_H_ +#define _SI_PREMEM_CONFIG_H_ + +#define SI_PREMEM_CONFIG_REVISION 1 + +extern EFI_GUID gSiPreMemConfigGuid; + +typedef enum { + ProbeTypeDisabled =3D 0x00, + ProbeTypeDciOob =3D 0x02, + ProbeType2WireDciOob =3D 0x06, + ProbeTypeManual =3D 0x07, + ProbeTypeMax +} PLATFORM_DEBUG_CONSENT_PROBE_TYPE; + +#pragma pack (push,1) +/** + The Silicon PreMem Policy allows the platform code to publish a set of c= onfiguration + information that the RC drivers will use to configure the silicon hardwa= re. + + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header + /** + Platform Debug Consent + As a main switch to enable platform debug capability and relevant sett= ings with specified probe type. + Manual: Do not use Platform Debug Consent to override other debug-rele= vant policies, but the user must set each debug option manually, aimed at a= dvanced users. + + PDC-dependent policies are listed: + DciPreMemConfig->DciEn + CpuTraceHubConfig->EnableMode + CpuTraceHubConfig->CpuTraceHubMemReg0Size + CpuTraceHubConfig->CpuTraceHubMemReg1Size + PchTraceHubPreMemConfig->EnableMode + PchTraceHubPreMemConfig->MemReg0Size + PchTraceHubPreMemConfig->MemReg1Size + + Note: DCI OOB (aka BSSB) uses CCA probe. + Refer to definition of PLATFORM_DEBUG_CONSENT_PROBE_TYPE + 0:Disabled; 2:DCI OOB (All + TraceHubs); 6:2-wire DCI OOB (Low = power); 7:Manual + **/ + UINT32 PlatformDebugConsent : 4; /// offset 28 - 31 + UINT32 RsvdBits : 28; + /** + This is used to skip override boot mode during firmware update boot mo= de. + When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, + skip setting boot mode to BOOT_WITH_FULL_CONFIGURATION in PEI memory i= nit. + 0: FALSE, 1: TRUE + **/ + UINT8 SkipOverrideBootModeWhenFwUpdate; /// offset 32 + UINT8 RsvdBytes[3]; /// offset 33 - 35 +} SI_PREMEM_CONFIG; + +#pragma pack (pop) +#endif // _SI_PREMEM_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Smbus/Sm= busConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Smbus/S= mbusConfig.h new file mode 100644 index 0000000000..2fc724552b --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConf= ig.h @@ -0,0 +1,49 @@ +/** @file + Smbus policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SMBUS_CONFIG_H_ +#define _SMBUS_CONFIG_H_ + +extern EFI_GUID gSmbusPreMemConfigGuid; + +#pragma pack (push,1) + +#define PCH_MAX_SMBUS_RESERVED_ADDRESS 128 + +/// +/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capabl= e devices in the platform. +/// +typedef struct { + /** + Revision 1: Init version + **/ + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + This member describes whether or not the SMBus controller of PCH shoul= d be enabled. + 0: Disable; 1: Enable. + **/ + UINT32 Enable : 1; + UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, = 0: Disable; 1: Enable. + UINT32 DynamicPowerGating : 1; ///< (Test) Disable = or Enable Smbus dynamic power gating. + /// + /// (Test) SPD Write Disable, 0: leave SPD Write Disable bit; = 1: set SPD Write Disable bit. + /// For security recommendations, SPD write disable bit must be set. + /// + UINT32 SpdWriteDisable : 1; + UINT32 SmbAlertEnable : 1; ///< Enable SMBus Alert pin (SMBAL= ERT#). 0: Disabled, 1: Enabled. + UINT32 RsvdBits0 : 27; ///< Reserved bits + UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space)= . Default is 0xEFA0. + UINT8 Rsvd0; ///< Reserved bytes + UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the= RsvdSmbusAddressTable. + /** + Array of addresses reserved for non-ARP-capable SMBus devices. + **/ + UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS]; +} PCH_SMBUS_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _SMBUS_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Spi/Flas= hProtectionConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock= /Spi/FlashProtectionConfig.h new file mode 100644 index 0000000000..45dc538064 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Spi/FlashProtec= tionConfig.h @@ -0,0 +1,54 @@ +/** @file + FlashProtection policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _FLASH_PROTECTION_CONFIG_H_ +#define _FLASH_PROTECTION_CONFIG_H_ + +extern EFI_GUID gFlashProtectionConfigGuid; + +#pragma pack (push,1) + +// +// Flash Protection Range Register +// +#define PCH_FLASH_PROTECTED_RANGES 5 + +/** + Protected Flash Range +**/ +typedef struct { + UINT32 WriteProtectionEnable : 1; ///< Write or = erase is blocked by hardware. 0: Disable; 1: Enable. + UINT32 ReadProtectionEnable : 1; ///< Read is b= locked by hardware. 0: Disable; 1: Enable. + UINT32 RsvdBits : 30; ///< Reserved + /** + The address of the upper limit of protection + This is a left shifted address by 12 bits with address bits 11:0 are a= ssumed to be FFFh for limit comparison + **/ + UINT16 ProtectedRangeLimit; + /** + The address of the upper limit of protection + This is a left shifted address by 12 bits with address bits 11:0 are a= ssumed to be 0 + **/ + UINT16 ProtectedRangeBase; +} PROTECTED_RANGE; + +/** + The PCH provides a method for blocking writes and reads to specific rang= es + in the SPI flash when the Protected Ranges are enabled. + PROTECTED_RANGE is used to specify if flash protection are enabled, + the write protection enable bit and the read protection enable bit, + and to specify the upper limit and lower base for each register + Platform code is responsible to get the range base by PchGetSpiRegionAdd= resses routine, + and set the limit and base accordingly. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< C= onfig Block Header + PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; ///< P= rotected Flash Ranges +} PCH_FLASH_PROTECTION_CONFIG; + +#pragma pack (pop) + +#endif // _FLASH_PROTECTION_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Tcss/Tcs= sPeiConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Tcss/T= cssPeiConfig.h new file mode 100644 index 0000000000..95bcaaa951 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiCon= fig.h @@ -0,0 +1,71 @@ +/** @file + TCSS PEI policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _TCSS_PEI_CONFIG_H_ +#define _TCSS_PEI_CONFIG_H_ + +#include + +extern EFI_GUID gTcssPeiConfigGuid; + +#pragma pack (push,1) + + +#define MAX_IOM_AUX_BIAS_COUNT 4 + +/// +/// The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin. +/// Those GPIO setting for DP Aux Orientation Bias Control when the TypeC = port didn't have re-timer. +/// IOM needs know Pull-Up and Pull-Down pin for Bias control +/// +typedef struct { + UINT32 GpioPullN; ///< GPIO Pull Up Ping number that is for IOM inde= cate the pull up pin from TypeC port. + UINT32 GpioPullP; ///< GPIO Pull Down Ping number that is for IOM in= decate the pull down pin from TypeC port. +} IOM_AUX_ORI_PAD_CONFIG; + +/// +/// The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS a= nd IOM-EC. +/// + +typedef struct { + UINT32 VccSt; ///< IOM VCCST request. (Not equal to actual V= CCST value) + UINT32 UsbOverride; ///< IOM to override USB connection. + UINT32 D3ColdEnable; ///< Enable/disable D3 Cold support in TCSS + UINT32 D3HotEnable; ///< Enable/disable D3 Hot support in TCSS +} IOM_INTERFACE_CONFIG; + +/// +/// The PMC_INTERFACE_CONFIG block describes interaction between BIOS and = PMC +/// +typedef struct { + UINT8 PmcPdEnable; ///< PMC PD Solution Enable + UINT8 Rsvd[3]; +} PMC_INTERFACE_CONFIG; + +/// +/// The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings = for TCSS. +/// +typedef struct { + UINT16 AuxOri; ///< Bits defining value for IOM Aux Orientation R= egister + UINT16 HslOri; ///< Bits defining value for IOM HSL Orientation R= egister +} TCSS_IOM_ORI_OVERRIDE; + +/// +/// The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS. +/// +typedef struct { + IOM_AUX_ORI_PAD_CONFIG IomAuxPortPad[MAX_IOM_AUX_BIAS_COUNT]; ///< = The IOM_AUX_ORI_BIAS_CTRL port config setting. + TCSS_IOM_ORI_OVERRIDE IomOverrides; + IOM_INTERFACE_CONFIG IomInterface; ///< = Config settings are BIOS <-> IOM interface. + PMC_INTERFACE_CONFIG PmcInterface; ///< = Config settings for BIOS <-> PMC interface + UINT8 TcStateLimit; ///< = Tcss C-State deep stage + UINT8 Reserved[3]; ///< = Reserved bytes for future use +} TCSS_IOM_PEI_CONFIG; + + +#pragma pack (pop) + +#endif /* _TCSS_PEI_CONFIG_H_ */ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Vmd/VmdP= eiConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Vmd/VmdP= eiConfig.h new file mode 100644 index 0000000000..37e6439abb --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Vmd/VmdPeiConfi= g.h @@ -0,0 +1,60 @@ +/** @file + VMD PEI policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _VMD_PEI_CONFIG_H_ +#define _VMD_PEI_CONFIG_H_ + +#include + +#pragma pack (push,1) + +#define VMD_MAX_DEVICES 31 + +typedef struct { + UINT8 RpBus; + UINT8 RpDevice; + UINT8 RpFunction; + UINT8 RpEnable; +} RP_BDF_DATA; + +/** + This configuration block is to configure VMD related variables used in P= ostMem PEI. + If VMD Device is not supported, all policies can be ignored. + Revision 1: + - Initial version. + Revision 2: + - Deprecated VmdPortAEnable, VmdPortBEnable, VmdPortCEnable, VmdPortDEna= ble. + - Added VmdPortEnable[VMD_MAX_DEVICES] and structure to hold Vmd EFI Var= iable details. + (Added B/D/F fields along with Port Enable for up to max 31 devices). + Revision 3: + Added policy to get the Bar values from platform PCD. + Revision 4: Added VmdGlobalMapping to map all the storage devices= under VMD +**/ + +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 C= onfig Block Header + UINT8 VmdEnable; ///< Offset 28 Thi= s field used to enable VMD controller 1=3DEnable 0=3DDisable(default) + UINT8 VmdPortAEnable; /// Deprecated < O= ffset 29 This field used to enable VMD portA Support 1=3DEnable and 0=3DDi= sable (default) + UINT8 VmdPortBEnable; /// Deprecated < O= ffset 30 This field used to enable VMD portB Support 1=3DEnable and 0=3DDi= sable (default) + UINT8 VmdPortCEnable; /// Deprecated < O= ffset 31 This field used to enable VMD portC Support 1=3DEnable and 0=3DDi= sable (default) + UINT8 VmdPortDEnable; /// Deprecated < O= ffset 32 This field used to enable VMD portD Support 1=3DEnable and 0=3DDi= sable (default) + UINT8 VmdCfgBarSize; ///< Offset 33 Thi= s is used to set the VMD Config Bar Size. 25(32MB) + UINT8 VmdCfgBarAttr; ///< Offset 34 Thi= s is used to set VMD Config Bar Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD= _64BIT_PREFETCH, 2: VMD_64BIT_NONPREFETCH(Default) + UINT8 VmdMemBarSize1; ///< Offset 35 Thi= s is used to set the VMD Mem Bar1 size. 25 (32MB). + UINT8 VmdMemBar1Attr; ///< Offset 36 Thi= s is used to set VMD Mem Bar1 Attributes 0: VMD_32BIT_NONPREFETCH(Defau= lt) 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH + UINT8 VmdMemBarSize2; ///< Offset 37 Thi= s is used to set the VMD Mem Bar2 size. 20(1MB). + UINT8 VmdMemBar2Attr; ///< Offset 38 Thi= s is used to set VMD Mem Bar2 Attributes 0: VMD_32BIT_NONPREFETCH 1: VMD= _64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH + UINT8 VmdGlobalMapping; ///< Offset 39 Thi= s field used to enable Global Mapping 1=3DEnable 0=3DDisable(default) + RP_BDF_DATA VmdPortEnable[VMD_MAX_DEVICES]; ///< Offset 40 to = 163 This field used to to store b/d/f for each root port along with enable = Support 1=3DEnable 0=3DDisable (default) + VOID *VmdVariablePtr; /// This config bl= ock will be updated as per the EFI variable. + UINT32 VmdCfgBarBase; /// Temp Address V= MD CFG BAR Default is 0xA0000000 + UINT32 VmdMemBar1Base; /// Temp Address V= MD CFG BAR Default is 0xA2000000 + UINT32 VmdMemBar2Base; /// Temp Address V= MD CFG BAR Default is 0xA4000000 +} VMD_PEI_CONFIG; + +#pragma pack (pop) + +#endif /* _VMD_PEI_PREMEM_CONFIG_H_ */ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Wdt/Watc= hDogConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Wdt/Wa= tchDogConfig.h new file mode 100644 index 0000000000..ad17488ecc --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogCon= fig.h @@ -0,0 +1,30 @@ +/** @file + WatchDog policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _WATCH_DOG_CONFIG_H_ +#define _WATCH_DOG_CONFIG_H_ + +extern EFI_GUID gWatchDogPreMemConfigGuid; + +#pragma pack (push,1) + +/** + This policy clears status bits and disable watchdog, then lock the + WDT registers. + while WDT is designed to be disabled and locked by Policy, + bios should not enable WDT by WDT PPI. In such case, bios shows the + warning message but not disable and lock WDT register to make sure + WDT event trigger correctly. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 DisableAndLock : 1; ///< (Test) Set 1 to clear = WDT status, then disable and lock WDT registers. 0: Disable; 1: Enab= le. + UINT32 RsvdBits : 31; +} PCH_WDT_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _WATCH_DOG_CONFIG_H_ --=20 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108723): https://edk2.groups.io/g/devel/message/108723 Mute This Topic: https://groups.io/mt/101373949/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-