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Thread-Topic: [PATCH v2 3/4] IntelFsp2Pkg: Adopt FSP 2.4 MultiPhase functions. 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Nate DeSimone > -----Original Message----- > From: Chiu, Chasel > Sent: Tuesday, August 9, 2022 5:48 PM > To: devel@edk2.groups.io > Cc: Chiu, Chasel ; Desimone, Nathaniel L > ; Zeng, Star > Subject: [PATCH v2 3/4] IntelFsp2Pkg: Adopt FSP 2.4 MultiPhase functions. >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3916 >=20 > Adopt MultiPhase functions for both FspSecCoreS and FspSecCoreM. > For backward compatibility, new INF are created for new modules. >=20 > Cc: Nate DeSimone > Cc: Star Zeng > Signed-off-by: Chasel Chiu > --- > IntelFsp2Pkg/FspSecCore/SecFsp.c | 4 ++++ > IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 9 +++++++++ > IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf | 75 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++ > IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf | 59 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > + > IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm | 304 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++ > IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryS.nasm | 101 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++ > IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm | 3 +++ > IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm | 303 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++ > IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryS.nasm | 108 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++ > IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm | 3 +++ > 10 files changed, 969 insertions(+) >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c > b/IntelFsp2Pkg/FspSecCore/SecFsp.c > index d9085ef51f..11be1f97ca 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c > +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c > @@ -135,6 +135,10 @@ FspGlobalDataInit ( > PeiFspData->CoreStack =3D BootLoaderStack; >=20 > PeiFspData->PerfIdx =3D 2; >=20 > PeiFspData->PerfSig =3D FSP_PERFORMANCE_DATA_SIGNATURE; >=20 > + // >=20 > + // Cache FspHobList pointer passed by bootloader via ApiParameter2 >=20 > + // >=20 > + PeiFspData->FspHobListPtr =3D (VOID **)GetFspApiParameter2 (); >=20 >=20 >=20 > SetFspMeasurePoint (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY); >=20 >=20 >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > index 35d223a404..a44fbf2a50 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c > @@ -69,8 +69,17 @@ FspApiCallingCheck ( > Status =3D EFI_UNSUPPORTED; >=20 > } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex= , > ApiParam))) { >=20 > Status =3D EFI_INVALID_PARAMETER; >=20 > + } else if (ApiIdx =3D=3D FspSiliconInitApiIndex) { >=20 > + // >=20 > + // Reset MultiPhase NumberOfPhases to zero >=20 > + // >=20 > + FspData->NumberOfPhases =3D 0; >=20 > } >=20 > } >=20 > + } else if (ApiIdx =3D=3D FspMultiPhaseMemInitApiIndex) { >=20 > + if ((FspData =3D=3D NULL) || ((UINTN)FspData =3D=3D MAX_ADDRESS) || > ((UINTN)FspData =3D=3D MAX_UINT32)) { >=20 > + Status =3D EFI_UNSUPPORTED; >=20 > + } >=20 > } else if (ApiIdx =3D=3D FspSmmInitApiIndex) { >=20 > // >=20 > // FspSmmInitApiIndex check >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf > b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf > new file mode 100644 > index 0000000000..e93e176f15 > --- /dev/null > +++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf > @@ -0,0 +1,75 @@ > +## @file >=20 > +# Sec Core for FSP to support MultiPhase (SeparatePhase) > MemInitialization. >=20 > +# >=20 > +# Copyright (c) 2022, Intel Corporation. All rights reserved.
>=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010005 >=20 > + BASE_NAME =3D Fsp24SecCoreM >=20 > + FILE_GUID =3D C5BC0719-4A23-4F6E-94DA-05FB6A0DFA9= C >=20 > + MODULE_TYPE =3D SEC >=20 > + VERSION_STRING =3D 1.0 >=20 > + >=20 > +# >=20 > +# The following information is for reference only and not required by th= e > build tools. >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 >=20 > +# >=20 > + >=20 > +[Sources] >=20 > + SecMain.c >=20 > + SecMain.h >=20 > + SecFsp.c >=20 > + SecFsp.h >=20 > + SecFspApiChk.c >=20 > + >=20 > +[Sources.IA32] >=20 > + Ia32/Stack.nasm >=20 > + Ia32/Fsp24ApiEntryM.nasm >=20 > + Ia32/FspApiEntryCommon.nasm >=20 > + Ia32/FspHelper.nasm >=20 > + Ia32/ReadEsp.nasm >=20 > + >=20 > +[Sources.X64] >=20 > + X64/Stack.nasm >=20 > + X64/Fsp24ApiEntryM.nasm >=20 > + X64/FspApiEntryCommon.nasm >=20 > + X64/FspHelper.nasm >=20 > + X64/ReadRsp.nasm >=20 > + >=20 > +[Binaries.Ia32] >=20 > + RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + IntelFsp2Pkg/IntelFsp2Pkg.dec >=20 > + UefiCpuPkg/UefiCpuPkg.dec >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseMemoryLib >=20 > + DebugLib >=20 > + BaseLib >=20 > + PciCf8Lib >=20 > + SerialPortLib >=20 > + FspSwitchStackLib >=20 > + FspCommonLib >=20 > + FspSecPlatformLib >=20 > + CpuLib >=20 > + UefiCpuLib >=20 > + FspMultiPhaseLib >=20 > + >=20 > +[Pcd] >=20 > + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## > CONSUMES >=20 > + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## > CONSUMES >=20 > + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## > CONSUMES >=20 > + gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## > CONSUMES >=20 > + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported ## > CONSUMES >=20 > + gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize ## > CONSUMES >=20 > + >=20 > +[Ppis] >=20 > + gEfiTemporaryRamSupportPpiGuid ## PRODUCE= S >=20 > + gFspInApiModePpiGuid ## PRODUCE= S >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf > b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf > new file mode 100644 > index 0000000000..1d44fb67b5 > --- /dev/null > +++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf > @@ -0,0 +1,59 @@ > +## @file >=20 > +# Sec Core for FSP to support MultiPhase (SeparatePhase) SiInitializati= on. >=20 > +# >=20 > +# Copyright (c) 2022, Intel Corporation. All rights reserved.
>=20 > +# >=20 > +# SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +# >=20 > +## >=20 > + >=20 > +[Defines] >=20 > + INF_VERSION =3D 0x00010005 >=20 > + BASE_NAME =3D Fsp24SecCoreS >=20 > + FILE_GUID =3D E039988B-0F21-4D95-AE34-C469B10E13F= 8 >=20 > + MODULE_TYPE =3D SEC >=20 > + VERSION_STRING =3D 1.0 >=20 > + >=20 > +# >=20 > +# The following information is for reference only and not required by th= e > build tools. >=20 > +# >=20 > +# VALID_ARCHITECTURES =3D IA32 X64 >=20 > +# >=20 > + >=20 > +[Sources] >=20 > + SecFspApiChk.c >=20 > + SecFsp.h >=20 > + >=20 > +[Sources.IA32] >=20 > + Ia32/Stack.nasm >=20 > + Ia32/Fsp24ApiEntryS.nasm >=20 > + Ia32/FspApiEntryCommon.nasm >=20 > + Ia32/FspHelper.nasm >=20 > + >=20 > +[Sources.X64] >=20 > + X64/Stack.nasm >=20 > + X64/Fsp24ApiEntryS.nasm >=20 > + X64/FspApiEntryCommon.nasm >=20 > + X64/FspHelper.nasm >=20 > + >=20 > +[Binaries.Ia32] >=20 > + RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC >=20 > + >=20 > +[Packages] >=20 > + MdePkg/MdePkg.dec >=20 > + IntelFsp2Pkg/IntelFsp2Pkg.dec >=20 > + >=20 > +[LibraryClasses] >=20 > + BaseMemoryLib >=20 > + DebugLib >=20 > + BaseLib >=20 > + PciCf8Lib >=20 > + SerialPortLib >=20 > + FspSwitchStackLib >=20 > + FspCommonLib >=20 > + FspSecPlatformLib >=20 > + FspMultiPhaseLib >=20 > + >=20 > +[Ppis] >=20 > + gEfiTemporaryRamSupportPpiGuid ## PRODUCE= S >=20 > + >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm > new file mode 100644 > index 0000000000..997b9c0bff > --- /dev/null > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm > @@ -0,0 +1,304 @@ > +;; @file >=20 > +; Provide FSP API entry points. >=20 > +; >=20 > +; Copyright (c) 2022, Intel Corporation. All rights reserved.
>=20 > +; SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +;; >=20 > + >=20 > + SECTION .text >=20 > + >=20 > +; >=20 > +; Following are fixed PCDs >=20 > +; >=20 > +extern ASM_PFX(PcdGet32(PcdTemporaryRamBase)) >=20 > +extern ASM_PFX(PcdGet32(PcdTemporaryRamSize)) >=20 > +extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize)) >=20 > +extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage)) >=20 > + >=20 > +struc FSPM_UPD_COMMON >=20 > + ; FSP_UPD_HEADER { >=20 > + .FspUpdHeader: resd 8 >=20 > + ; } >=20 > + ; FSPM_ARCH_UPD { >=20 > + .Revision: resb 1 >=20 > + .Reserved: resb 3 >=20 > + .NvsBufferPtr: resd 1 >=20 > + .StackBase: resd 1 >=20 > + .StackSize: resd 1 >=20 > + .BootLoaderTolumSize: resd 1 >=20 > + .BootMode: resd 1 >=20 > + .Reserved1: resb 8 >=20 > + ; } >=20 > + .size: >=20 > +endstruc >=20 > + >=20 > +struc FSPM_UPD_COMMON_FSP24 >=20 > + ; FSP_UPD_HEADER { >=20 > + .FspUpdHeader: resd 8 >=20 > + ; } >=20 > + ; FSPM_ARCH2_UPD { >=20 > + .Revision: resb 1 >=20 > + .Reserved: resb 3 >=20 > + .Length resd 1 >=20 > + .StackBase: resq 1 >=20 > + .StackSize: resq 1 >=20 > + .BootLoaderTolumSize: resd 1 >=20 > + .BootMode: resd 1 >=20 > + .FspEventHandler resq 1 >=20 > + .Reserved1: resb 24 >=20 > + ; } >=20 > + .size: >=20 > +endstruc >=20 > + >=20 > +; >=20 > +; Following functions will be provided in C >=20 > +; >=20 > +extern ASM_PFX(SecStartup) >=20 > +extern ASM_PFX(FspApiCommon) >=20 > + >=20 > +; >=20 > +; Following functions will be provided in PlatformSecLib >=20 > +; >=20 > +extern ASM_PFX(AsmGetFspBaseAddress) >=20 > +extern ASM_PFX(AsmGetFspInfoHeader) >=20 > +extern ASM_PFX(FspMultiPhaseMemInitApiHandler) >=20 > + >=20 > +STACK_SAVED_EAX_OFFSET EQU 4 * 7 ; size of a general purpose > register * eax index >=20 > +API_PARAM1_OFFSET EQU 34h ; ApiParam1 [ sub esp,8 + pushad= + > pushfd + push eax + call] >=20 > +FSP_HEADER_IMGBASE_OFFSET EQU 1Ch >=20 > +FSP_HEADER_CFGREG_OFFSET EQU 24h >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; FspMemoryInit API >=20 > +; >=20 > +; This FSP API is called after TempRamInit and initializes the memory. >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(FspMemoryInitApi) >=20 > +ASM_PFX(FspMemoryInitApi): >=20 > + mov eax, 3 ; FSP_API_INDEX.FspMemoryInitApiIndex >=20 > + jmp ASM_PFX(FspApiCommon) >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; FspMultiPhaseMemoryInitApi API >=20 > +; >=20 > +; This FSP API provides multi-phase Memory initialization, which brings > greater >=20 > +; modularity beyond the existing FspMemoryInit() API. >=20 > +; Increased modularity is achieved by adding an extra API to FSP-M. >=20 > +; This allows the bootloader to add board specific initialization steps > throughout >=20 > +; the MemoryInit flow as needed. >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(FspMultiPhaseMemoryInitApi) >=20 > +ASM_PFX(FspMultiPhaseMemoryInitApi): >=20 > + mov eax, 8 ; FSP_API_INDEX.FspMultiPhaseMemInitApiIndex >=20 > + jmp ASM_PFX(FspApiCommon) >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; TempRamExitApi API >=20 > +; >=20 > +; This API tears down temporary RAM >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(TempRamExitApi) >=20 > +ASM_PFX(TempRamExitApi): >=20 > + mov eax, 4 ; FSP_API_INDEX.TempRamExitApiIndex >=20 > + jmp ASM_PFX(FspApiCommon) >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; FspApiCommonContinue API >=20 > +; >=20 > +; This is the FSP API common entry point to resume the FSP execution >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(FspApiCommonContinue) >=20 > +ASM_PFX(FspApiCommonContinue): >=20 > + ; >=20 > + ; Handle FspMultiPhaseMemInitApiIndex API >=20 > + ; >=20 > + cmp eax, 8 ; FspMultiPhaseMemInitApiIndex >=20 > + jnz NotMultiPhaseMemoryInitApi >=20 > + >=20 > + pushad >=20 > + push DWORD [esp + (4 * 8 + 4)] ; push ApiParam >=20 > + push eax ; push ApiIdx >=20 > + call ASM_PFX(FspMultiPhaseMemInitApiHandler) >=20 > + add esp, 8 >=20 > + mov dword [esp + STACK_SAVED_EAX_OFFSET], eax >=20 > + popad >=20 > + ret >=20 > + >=20 > +NotMultiPhaseMemoryInitApi: >=20 > + >=20 > + ; >=20 > + ; FspMemoryInit API setup the initial stack frame >=20 > + ; >=20 > + >=20 > + ; >=20 > + ; Place holder to store the FspInfoHeader pointer >=20 > + ; >=20 > + push eax >=20 > + >=20 > + ; >=20 > + ; Update the FspInfoHeader pointer >=20 > + ; >=20 > + push eax >=20 > + call ASM_PFX(AsmGetFspInfoHeader) >=20 > + mov [esp + 4], eax >=20 > + pop eax >=20 > + >=20 > + ; >=20 > + ; Create a Task Frame in the stack for the Boot Loader >=20 > + ; >=20 > + pushfd ; 2 pushf for 4 byte alignment >=20 > + cli >=20 > + pushad >=20 > + >=20 > + ; Reserve 8 bytes for IDT save/restore >=20 > + sub esp, 8 >=20 > + sidt [esp] >=20 > + >=20 > + >=20 > + ; Get Stackbase and StackSize from FSPM_UPD Param >=20 > + mov edx, [esp + API_PARAM1_OFFSET] >=20 > + cmp edx, 0 >=20 > + jnz FspStackSetup >=20 > + >=20 > + ; Get UPD default values if FspmUpdDataPtr (ApiParam1) is null >=20 > + push eax >=20 > + call ASM_PFX(AsmGetFspInfoHeader) >=20 > + mov edx, [eax + FSP_HEADER_IMGBASE_OFFSET] >=20 > + add edx, [eax + FSP_HEADER_CFGREG_OFFSET] >=20 > + pop eax >=20 > + >=20 > +FspStackSetup: >=20 > + mov ecx, [edx + FSPM_UPD_COMMON.Revision] >=20 > + cmp ecx, 3 >=20 > + jae FspmUpdCommon2 >=20 > + >=20 > + ; >=20 > + ; StackBase =3D temp memory base, StackSize =3D temp memory size >=20 > + ; >=20 > + mov edi, [edx + FSPM_UPD_COMMON.StackBase] >=20 > + mov ecx, [edx + FSPM_UPD_COMMON.StackSize] >=20 > + jmp ChkFspHeapSize >=20 > + >=20 > +FspmUpdCommon2: >=20 > + mov edi, [edx + FSPM_UPD_COMMON_FSP24.StackBase] >=20 > + mov ecx, [edx + FSPM_UPD_COMMON_FSP24.StackSize] >=20 > + >=20 > +ChkFspHeapSize: >=20 > + ; >=20 > + ; Keep using bootloader stack if heap size % is 0 >=20 > + ; >=20 > + mov bl, BYTE [ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))] >=20 > + cmp bl, 0 >=20 > + jz SkipStackSwitch >=20 > + >=20 > + ; >=20 > + ; Set up a dedicated temp ram stack for FSP if FSP heap size % doesn't > equal 0 >=20 > + ; >=20 > + add edi, ecx >=20 > + ; >=20 > + ; Switch to new FSP stack >=20 > + ; >=20 > + xchg edi, esp ; Exchange edi and esp,= edi will be assigned > to the current esp pointer and esp will be Stack base + Stack size >=20 > + >=20 > +SkipStackSwitch: >=20 > + ; >=20 > + ; If heap size % is 0: >=20 > + ; EDI is FSPM_UPD_COMMON.StackBase and will hold ESP later (boot > loader stack pointer) >=20 > + ; ECX is FSPM_UPD_COMMON.StackSize >=20 > + ; ESP is boot loader stack pointer (no stack switch) >=20 > + ; BL is 0 to indicate no stack switch (EBX will hold > FSPM_UPD_COMMON.StackBase later) >=20 > + ; >=20 > + ; If heap size % is not 0 >=20 > + ; EDI is boot loader stack pointer >=20 > + ; ECX is FSPM_UPD_COMMON.StackSize >=20 > + ; ESP is new stack (FSPM_UPD_COMMON.StackBase + > FSPM_UPD_COMMON.StackSize) >=20 > + ; BL is NOT 0 to indicate stack has switched >=20 > + ; >=20 > + cmp bl, 0 >=20 > + jnz StackHasBeenSwitched >=20 > + >=20 > + mov ebx, edi ; Put FSPM_UPD_COMMON.S= tackBase to > ebx as temp memory base >=20 > + mov edi, esp ; Put boot loader stack= pointer to edi >=20 > + jmp StackSetupDone >=20 > + >=20 > +StackHasBeenSwitched: >=20 > + mov ebx, esp ; Put Stack base + Stac= k size in ebx >=20 > + sub ebx, ecx ; Stack base + Stack si= ze - Stack size as temp > memory base >=20 > + >=20 > +StackSetupDone: >=20 > + >=20 > + ; >=20 > + ; Pass the API Idx to SecStartup >=20 > + ; >=20 > + push eax >=20 > + >=20 > + ; >=20 > + ; Pass the BootLoader stack to SecStartup >=20 > + ; >=20 > + push edi >=20 > + >=20 > + ; >=20 > + ; Pass entry point of the PEI core >=20 > + ; >=20 > + call ASM_PFX(AsmGetFspBaseAddress) >=20 > + mov edi, eax >=20 > + call ASM_PFX(AsmGetPeiCoreOffset) >=20 > + add edi, eax >=20 > + push edi >=20 > + >=20 > + ; >=20 > + ; Pass BFV into the PEI Core >=20 > + ; It uses relative address to calculate the actual boot FV base >=20 > + ; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase > and >=20 > + ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs, >=20 > + ; they are different. The code below can handle both cases. >=20 > + ; >=20 > + call ASM_PFX(AsmGetFspBaseAddress) >=20 > + push eax >=20 > + >=20 > + ; >=20 > + ; Pass stack base and size into the PEI Core >=20 > + ; >=20 > + push ebx >=20 > + push ecx >=20 > + >=20 > + ; >=20 > + ; Pass Control into the PEI Core >=20 > + ; >=20 > + call ASM_PFX(SecStartup) >=20 > + add esp, 4 >=20 > +exit: >=20 > + ret >=20 > + >=20 > +global ASM_PFX(FspPeiCoreEntryOff) >=20 > +ASM_PFX(FspPeiCoreEntryOff): >=20 > + ; >=20 > + ; This value will be patched by the build script >=20 > + ; >=20 > + DD 0x12345678 >=20 > + >=20 > +global ASM_PFX(AsmGetPeiCoreOffset) >=20 > +ASM_PFX(AsmGetPeiCoreOffset): >=20 > + mov eax, dword [ASM_PFX(FspPeiCoreEntryOff)] >=20 > + ret >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; TempRamInit API >=20 > +; >=20 > +; Empty function for WHOLEARCHIVE build option >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(TempRamInitApi) >=20 > +ASM_PFX(TempRamInitApi): >=20 > + jmp $ >=20 > + ret >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; Module Entrypoint API >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(_ModuleEntryPoint) >=20 > +ASM_PFX(_ModuleEntryPoint): >=20 > + jmp $ >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryS.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryS.nasm > new file mode 100644 > index 0000000000..bda99cdd80 > --- /dev/null > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryS.nasm > @@ -0,0 +1,101 @@ > +;; @file >=20 > +; Provide FSP API entry points. >=20 > +; >=20 > +; Copyright (c) 2020, Intel Corporation. All rights reserved.
>=20 > +; SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +;; >=20 > + >=20 > + SECTION .text >=20 > + >=20 > +; >=20 > +; Following functions will be provided in C >=20 > +; >=20 > +extern ASM_PFX(FspApiCommon) >=20 > +extern ASM_PFX(FspMultiPhaseSiInitApiHandlerV2) >=20 > + >=20 > +STACK_SAVED_EAX_OFFSET EQU 4 * 7 ; size of a general purpose > register * eax index >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; NotifyPhase API >=20 > +; >=20 > +; This FSP API will notify the FSP about the different phases in the boo= t >=20 > +; process >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(NotifyPhaseApi) >=20 > +ASM_PFX(NotifyPhaseApi): >=20 > + mov eax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex >=20 > + jmp ASM_PFX(FspApiCommon) >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; FspSiliconInit API >=20 > +; >=20 > +; This FSP API initializes the CPU and the chipset including the IO >=20 > +; controllers in the chipset to enable normal operation of these devices= . >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(FspSiliconInitApi) >=20 > +ASM_PFX(FspSiliconInitApi): >=20 > + mov eax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex >=20 > + jmp ASM_PFX(FspApiCommon) >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; FspMultiPhaseSiInitApi API >=20 > +; >=20 > +; This FSP API provides multi-phase silicon initialization, which brings= greater >=20 > +; modularity beyond the existing FspSiliconInit() API. >=20 > +; Increased modularity is achieved by adding an extra API to FSP-S. >=20 > +; This allows the bootloader to add board specific initialization steps > throughout >=20 > +; the SiliconInit flow as needed. >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(FspMultiPhaseSiInitApi) >=20 > +ASM_PFX(FspMultiPhaseSiInitApi): >=20 > + mov eax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex >=20 > + jmp ASM_PFX(FspApiCommon) >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; FspApiCommonContinue API >=20 > +; >=20 > +; This is the FSP API common entry point to resume the FSP execution >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(FspApiCommonContinue) >=20 > +ASM_PFX(FspApiCommonContinue): >=20 > + ; >=20 > + ; Handle FspMultiPhaseSiInitApiIndex API >=20 > + ; >=20 > + cmp eax, 6 ; FspMultiPhaseSiInitApiIndex >=20 > + jnz NotMultiPhaseSiInitApi >=20 > + >=20 > + pushad >=20 > + push DWORD [esp + (4 * 8 + 4)] ; push ApiParam >=20 > + push eax ; push ApiIdx >=20 > + call ASM_PFX(FspMultiPhaseSiInitApiHandlerV2) >=20 > + add esp, 8 >=20 > + mov dword [esp + STACK_SAVED_EAX_OFFSET], eax >=20 > + popad >=20 > + ret >=20 > + >=20 > +NotMultiPhaseSiInitApi: >=20 > + jmp $ >=20 > + ret >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; TempRamInit API >=20 > +; >=20 > +; Empty function for WHOLEARCHIVE build option >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(TempRamInitApi) >=20 > +ASM_PFX(TempRamInitApi): >=20 > + jmp $ >=20 > + ret >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; Module Entrypoint API >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(_ModuleEntryPoint) >=20 > +ASM_PFX(_ModuleEntryPoint): >=20 > + jmp $ >=20 > + >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm > index 8d8deba28a..87446be779 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm > @@ -67,6 +67,9 @@ FspApiCommon2: > cmp eax, 6 ; FspMultiPhaseSiInitApiIndex API >=20 > jz FspApiCommon3 >=20 >=20 >=20 > + cmp eax, 8 ; FspMultiPhaseMemInitApiIndex API >=20 > + jz FspApiCommon3 >=20 > + >=20 > call ASM_PFX(AsmGetFspInfoHeader) >=20 > jmp ASM_PFX(Loader2PeiSwitchStack) >=20 >=20 >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm > b/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm > new file mode 100644 > index 0000000000..8880721f29 > --- /dev/null > +++ b/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm > @@ -0,0 +1,303 @@ > +;; @file >=20 > +; Provide FSP API entry points. >=20 > +; >=20 > +; Copyright (c) 2022, Intel Corporation. All rights reserved.
>=20 > +; SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +;; >=20 > + >=20 > + SECTION .text >=20 > + >=20 > +%include "PushPopRegsNasm.inc" >=20 > + >=20 > +; >=20 > +; Following are fixed PCDs >=20 > +; >=20 > +extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage)) >=20 > + >=20 > +struc FSPM_UPD_COMMON_FSP24 >=20 > + ; FSP_UPD_HEADER { >=20 > + .FspUpdHeader: resd 8 >=20 > + ; } >=20 > + ; FSPM_ARCH2_UPD { >=20 > + .Revision: resb 1 >=20 > + .Reserved: resb 3 >=20 > + .Length resd 1 >=20 > + .StackBase: resq 1 >=20 > + .StackSize: resq 1 >=20 > + .BootLoaderTolumSize: resd 1 >=20 > + .BootMode: resd 1 >=20 > + .FspEventHandler resq 1 >=20 > + .Reserved1: resb 24 >=20 > + ; } >=20 > + .size: >=20 > +endstruc >=20 > + >=20 > +; >=20 > +; Following functions will be provided in C >=20 > +; >=20 > +extern ASM_PFX(SecStartup) >=20 > +extern ASM_PFX(FspApiCommon) >=20 > + >=20 > +; >=20 > +; Following functions will be provided in PlatformSecLib >=20 > +; >=20 > +extern ASM_PFX(AsmGetFspBaseAddress) >=20 > +extern ASM_PFX(AsmGetFspInfoHeader) >=20 > +extern ASM_PFX(FspMultiPhaseMemInitApiHandler) >=20 > + >=20 > +STACK_SAVED_RAX_OFFSET EQU 8 * 7 ; size of a general purpose > register * rax index >=20 > +FSP_HEADER_IMGBASE_OFFSET EQU 1Ch >=20 > +FSP_HEADER_CFGREG_OFFSET EQU 24h >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; FspMemoryInit API >=20 > +; >=20 > +; This FSP API is called after TempRamInit and initializes the memory. >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(FspMemoryInitApi) >=20 > +ASM_PFX(FspMemoryInitApi): >=20 > + mov rax, 3 ; FSP_API_INDEX.FspMemoryInitApiIndex >=20 > + jmp ASM_PFX(FspApiCommon) >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; FspMultiPhaseMemoryInitApi API >=20 > +; >=20 > +; This FSP API provides multi-phase Memory initialization, which brings > greater >=20 > +; modularity beyond the existing FspMemoryInit() API. >=20 > +; Increased modularity is achieved by adding an extra API to FSP-M. >=20 > +; This allows the bootloader to add board specific initialization steps > throughout >=20 > +; the MemoryInit flow as needed. >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(FspMultiPhaseMemoryInitApi) >=20 > +ASM_PFX(FspMultiPhaseMemoryInitApi): >=20 > + mov rax, 8 ; FSP_API_INDEX.FspMultiPhaseMemInitApiIndex >=20 > + jmp ASM_PFX(FspApiCommon) >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; TempRamExitApi API >=20 > +; >=20 > +; This API tears down temporary RAM >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(TempRamExitApi) >=20 > +ASM_PFX(TempRamExitApi): >=20 > + mov rax, 4 ; FSP_API_INDEX.TempRamExitApiIndex >=20 > + jmp ASM_PFX(FspApiCommon) >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; FspApiCommonContinue API >=20 > +; >=20 > +; This is the FSP API common entry point to resume the FSP execution >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(FspApiCommonContinue) >=20 > +ASM_PFX(FspApiCommonContinue): >=20 > + ; >=20 > + ; Handle FspMultiPhaseMemoInitApiIndex API >=20 > + ; >=20 > + push rdx ; Push a QWORD data for stack alignment >=20 > + >=20 > + cmp rax, 8 ; FspMultiPhaseMemInitApiIndex >=20 > + jnz NotMultiPhaseMemoryInitApi >=20 > + >=20 > + PUSHA_64 >=20 > + mov rdx, rcx ; move ApiParam to rdx >=20 > + mov rcx, rax ; move ApiIdx to rcx >=20 > + sub rsp, 0x20 ; calling C function may need shadow space >=20 > + call ASM_PFX(FspMultiPhaseMemInitApiHandler) >=20 > + add rsp, 0x20 ; restore shadow space >=20 > + mov qword [rsp + STACK_SAVED_RAX_OFFSET], rax >=20 > + POPA_64 >=20 > + add rsp, 0x08 >=20 > + ret >=20 > + >=20 > +NotMultiPhaseMemoryInitApi: >=20 > + ; Push RDX and RCX to form CONTEXT_STACK_64 >=20 > + push rdx ; Push API Parameter2 on stack >=20 > + push rcx ; Push API Parameter1 on stack >=20 > + >=20 > + ; >=20 > + ; FspMemoryInit API setup the initial stack frame >=20 > + ; >=20 > + >=20 > + ; >=20 > + ; Place holder to store the FspInfoHeader pointer >=20 > + ; >=20 > + push rax >=20 > + >=20 > + ; >=20 > + ; Update the FspInfoHeader pointer >=20 > + ; >=20 > + push rax >=20 > + call ASM_PFX(AsmGetFspInfoHeader) >=20 > + mov [rsp + 8], rax >=20 > + pop rax >=20 > + >=20 > + ; >=20 > + ; Create a Task Frame in the stack for the Boot Loader >=20 > + ; >=20 > + pushfq >=20 > + cli >=20 > + PUSHA_64 >=20 > + >=20 > + ; Reserve 16 bytes for IDT save/restore >=20 > + sub rsp, 16 >=20 > + sidt [rsp] >=20 > + >=20 > + ; Get Stackbase and StackSize from FSPM_UPD Param >=20 > + mov rdx, rcx ; Put FSPM_UPD Param to= rdx >=20 > + cmp rdx, 0 >=20 > + jnz FspStackSetup >=20 > + >=20 > + ; Get UPD default values if FspmUpdDataPtr (ApiParam1) is null >=20 > + xchg rbx, rax >=20 > + call ASM_PFX(AsmGetFspInfoHeader) >=20 > + mov edx, [rax + FSP_HEADER_IMGBASE_OFFSET] >=20 > + add edx, [rax + FSP_HEADER_CFGREG_OFFSET] >=20 > + xchg rbx, rax >=20 > + >=20 > +FspStackSetup: >=20 > + mov cl, [rdx + FSPM_UPD_COMMON_FSP24.Revision] >=20 > + cmp cl, 3 >=20 > + jae FspmUpdCommonFsp24 >=20 > + >=20 > + mov rax, 08000000000000002h ; RETURN_INVALID_PARAME= TER >=20 > + sub rsp, 0b8h >=20 > + ret >=20 > + >=20 > +FspmUpdCommonFsp24: >=20 > + ; >=20 > + ; StackBase =3D temp memory base, StackSize =3D temp memory size >=20 > + ; >=20 > + mov rdi, [rdx + FSPM_UPD_COMMON_FSP24.StackBase] >=20 > + mov ecx, [rdx + FSPM_UPD_COMMON_FSP24.StackSize] >=20 > + >=20 > + ; >=20 > + ; Keep using bootloader stack if heap size % is 0 >=20 > + ; >=20 > + mov rbx, ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage)) >=20 > + mov bl, BYTE [rbx] >=20 > + cmp bl, 0 >=20 > + jz SkipStackSwitch >=20 > + >=20 > + ; >=20 > + ; Set up a dedicated temp ram stack for FSP if FSP heap size % doesn't > equal 0 >=20 > + ; >=20 > + add rdi, rcx >=20 > + ; >=20 > + ; Switch to new FSP stack >=20 > + ; >=20 > + xchg rdi, rsp ; Exchange rdi and rsp,= rdi will be assigned to > the current rsp pointer and rsp will be Stack base + Stack size >=20 > + >=20 > +SkipStackSwitch: >=20 > + ; >=20 > + ; If heap size % is 0: >=20 > + ; EDI is FSPM_UPD_COMMON_FSP24.StackBase and will hold ESP later > (boot loader stack pointer) >=20 > + ; ECX is FSPM_UPD_COMMON_FSP24.StackSize >=20 > + ; ESP is boot loader stack pointer (no stack switch) >=20 > + ; BL is 0 to indicate no stack switch (EBX will hold > FSPM_UPD_COMMON_FSP24.StackBase later) >=20 > + ; >=20 > + ; If heap size % is not 0 >=20 > + ; EDI is boot loader stack pointer >=20 > + ; ECX is FSPM_UPD_COMMON_FSP24.StackSize >=20 > + ; ESP is new stack (FSPM_UPD_COMMON_FSP24.StackBase + > FSPM_UPD_COMMON_FSP24.StackSize) >=20 > + ; BL is NOT 0 to indicate stack has switched >=20 > + ; >=20 > + cmp bl, 0 >=20 > + jnz StackHasBeenSwitched >=20 > + >=20 > + mov rbx, rdi ; Put > FSPM_UPD_COMMON_FSP24.StackBase to rbx as temp memory base >=20 > + mov rdi, rsp ; Put boot loader stack= pointer to rdi >=20 > + jmp StackSetupDone >=20 > + >=20 > +StackHasBeenSwitched: >=20 > + mov rbx, rsp ; Put Stack base + Stac= k size in ebx >=20 > + sub rbx, rcx ; Stack base + Stack si= ze - Stack size as temp > memory base >=20 > + >=20 > +StackSetupDone: >=20 > + >=20 > + ; >=20 > + ; Per X64 calling convention, make sure RSP is 16-byte aligned. >=20 > + ; >=20 > + mov rdx, rsp >=20 > + and rdx, 0fh >=20 > + sub rsp, rdx >=20 > + >=20 > + ; >=20 > + ; Pass the API Idx to SecStartup >=20 > + ; >=20 > + push rax >=20 > + >=20 > + ; >=20 > + ; Pass the BootLoader stack to SecStartup >=20 > + ; >=20 > + push rdi >=20 > + >=20 > + ; >=20 > + ; Pass BFV into the PEI Core >=20 > + ; It uses relative address to calculate the actual boot FV base >=20 > + ; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase > and >=20 > + ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs, >=20 > + ; they are different. The code below can handle both cases. >=20 > + ; >=20 > + call ASM_PFX(AsmGetFspBaseAddress) >=20 > + mov r8, rax >=20 > + >=20 > + ; >=20 > + ; Pass entry point of the PEI core >=20 > + ; >=20 > + call ASM_PFX(AsmGetPeiCoreOffset) >=20 > + lea r9, [r8 + rax] >=20 > + >=20 > + ; >=20 > + ; Pass stack base and size into the PEI Core >=20 > + ; >=20 > + mov rcx, rcx >=20 > + mov rdx, rbx >=20 > + >=20 > + ; >=20 > + ; Pass Control into the PEI Core >=20 > + ; RCX =3D SizeOfRam, RDX =3D TempRamBase, R8 =3D BFV, R9 =3D PeiCoreEn= try, Last > 1 Stack =3D BL stack, Last 2 Stack =3D API index >=20 > + ; According to X64 calling convention, caller has to allocate 32 bytes= as a > shadow store on call stack right before >=20 > + ; calling the function. >=20 > + ; >=20 > + sub rsp, 20h >=20 > + call ASM_PFX(SecStartup) >=20 > + add rsp, 20h >=20 > +exit: >=20 > + ret >=20 > + >=20 > +global ASM_PFX(FspPeiCoreEntryOff) >=20 > +ASM_PFX(FspPeiCoreEntryOff): >=20 > + ; >=20 > + ; This value will be patched by the build script >=20 > + ; >=20 > + DD 0x12345678 >=20 > + >=20 > +global ASM_PFX(AsmGetPeiCoreOffset) >=20 > +ASM_PFX(AsmGetPeiCoreOffset): >=20 > + push rbx >=20 > + mov rbx, ASM_PFX(FspPeiCoreEntryOff) >=20 > + mov eax, dword[ebx] >=20 > + pop rbx >=20 > + ret >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; TempRamInit API >=20 > +; >=20 > +; Empty function for WHOLEARCHIVE build option >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(TempRamInitApi) >=20 > +ASM_PFX(TempRamInitApi): >=20 > + jmp $ >=20 > + ret >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; Module Entrypoint API >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(_ModuleEntryPoint) >=20 > +ASM_PFX(_ModuleEntryPoint): >=20 > + jmp $ >=20 > + >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryS.nasm > b/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryS.nasm > new file mode 100644 > index 0000000000..5bbbc5d1d0 > --- /dev/null > +++ b/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryS.nasm > @@ -0,0 +1,108 @@ > +;; @file >=20 > +; Provide FSP API entry points. >=20 > +; >=20 > +; Copyright (c) 2022, Intel Corporation. All rights reserved.
>=20 > +; SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > +;; >=20 > + >=20 > + SECTION .text >=20 > + >=20 > +; >=20 > +; Following functions will be provided in C >=20 > +; >=20 > +extern ASM_PFX(FspApiCommon) >=20 > +extern ASM_PFX(FspMultiPhaseSiInitApiHandlerV2) >=20 > + >=20 > +STACK_SAVED_RAX_OFFSET EQU 8 * 7 ; size of a general purpose > register * rax index >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; NotifyPhase API >=20 > +; >=20 > +; This FSP API will notify the FSP about the different phases in the boo= t >=20 > +; process >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(NotifyPhaseApi) >=20 > +ASM_PFX(NotifyPhaseApi): >=20 > + mov rax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex >=20 > + jmp ASM_PFX(FspApiCommon) >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; FspSiliconInit API >=20 > +; >=20 > +; This FSP API initializes the CPU and the chipset including the IO >=20 > +; controllers in the chipset to enable normal operation of these devices= . >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(FspSiliconInitApi) >=20 > +ASM_PFX(FspSiliconInitApi): >=20 > + mov rax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex >=20 > + jmp ASM_PFX(FspApiCommon) >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; FspMultiPhaseSiInitApi API >=20 > +; >=20 > +; This FSP API provides multi-phase silicon initialization, which brings= greater >=20 > +; modularity beyond the existing FspSiliconInit() API. >=20 > +; Increased modularity is achieved by adding an extra API to FSP-S. >=20 > +; This allows the bootloader to add board specific initialization steps > throughout >=20 > +; the SiliconInit flow as needed. >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > + >=20 > +%include "PushPopRegsNasm.inc" >=20 > + >=20 > +global ASM_PFX(FspMultiPhaseSiInitApi) >=20 > +ASM_PFX(FspMultiPhaseSiInitApi): >=20 > + mov rax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex >=20 > + jmp ASM_PFX(FspApiCommon) >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; FspApiCommonContinue API >=20 > +; >=20 > +; This is the FSP API common entry point to resume the FSP execution >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(FspApiCommonContinue) >=20 > +ASM_PFX(FspApiCommonContinue): >=20 > + ; >=20 > + ; Handle FspMultiPhaseSiInitApiIndex API >=20 > + ; >=20 > + push rdx ; Push a QWORD data for stack alignment >=20 > + >=20 > + cmp rax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex >=20 > + jnz NotMultiPhaseSiInitApi >=20 > + >=20 > + PUSHA_64 >=20 > + mov rdx, rcx ; move ApiParam to rdx >=20 > + mov rcx, rax ; move ApiIdx to rcx >=20 > + sub rsp, 0x20 ; calling C function may need shadow space >=20 > + call ASM_PFX(FspMultiPhaseSiInitApiHandlerV2) >=20 > + add rsp, 0x20 ; restore shadow space >=20 > + mov qword [rsp + STACK_SAVED_RAX_OFFSET], rax >=20 > + POPA_64 >=20 > + add rsp, 0x08 >=20 > + ret >=20 > + >=20 > +NotMultiPhaseSiInitApi: >=20 > + jmp $ >=20 > + ret >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; TempRamInit API >=20 > +; >=20 > +; Empty function for WHOLEARCHIVE build option >=20 > +; >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(TempRamInitApi) >=20 > +ASM_PFX(TempRamInitApi): >=20 > + jmp $ >=20 > + ret >=20 > + >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +; Module Entrypoint API >=20 > +;-----------------------------------------------------------------------= ----- >=20 > +global ASM_PFX(_ModuleEntryPoint) >=20 > +ASM_PFX(_ModuleEntryPoint): >=20 > + jmp $ >=20 > + >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm > b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm > index 718e672e02..dc6b8c99a1 100644 > --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm > +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm > @@ -68,6 +68,9 @@ FspApiCommon2: > cmp rax, 6 ; FspMultiPhaseSiInitApiIndex API >=20 > jz FspApiCommon3 >=20 >=20 >=20 > + cmp rax, 8 ; FspMultiPhaseMemInitApiIndex API >=20 > + jz FspApiCommon3 >=20 > + >=20 > call ASM_PFX(AsmGetFspInfoHeader) >=20 > jmp ASM_PFX(Loader2PeiSwitchStack) >=20 >=20 >=20 > -- > 2.35.0.windows.1