From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id D1D6F7803CC for ; Wed, 4 Oct 2023 18:43:35 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=uqF+Hpwqcl3q/MeTGQVE5UrSKPUgA4rPlSfze2VgQ/g=; c=relaxed/simple; d=groups.io; h=From:To:CC:Subject:Thread-Topic:Thread-Index:Date:Message-ID:References:In-Reply-To:Accept-Language:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type; s=20140610; t=1696445014; v=1; b=GuxxOSKy7bR8Zf2eHGq8Ahlfcnfz8jz6d5huUazyhtn2c8WMNsw+bh1VLHJEMlY2WOL12JWe /a23EYSz5Alp6KEtAdhvbHh72ZwMfW9nqLB7dDvlCsJ6pqwnd0Zo3QV1IkzK/6o+NcSrZ0kc9X7 mAwNMGream6Ae1qp7yYKrYzg= X-Received: by 127.0.0.2 with SMTP id QM5XYY7687511xILgwGEGhiO; Wed, 04 Oct 2023 11:43:34 -0700 X-Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) by mx.groups.io with SMTP id smtpd.web11.1674.1696445014056490950 for ; Wed, 04 Oct 2023 11:43:34 -0700 X-Received: by mail-pf1-f182.google.com with SMTP id d2e1a72fcca58-6907e44665bso98341b3a.1 for ; Wed, 04 Oct 2023 11:43:33 -0700 (PDT) X-Gm-Message-State: GHUa7dsTOdWc39WgKtJ0KEQNx7686176AA= X-Google-Smtp-Source: AGHT+IESmlaYXURfU0lXKTwhZP8QDxBrpsVQCPuCDvTJolqOZu8OE7+mDQDWcEEjA3cFxUM2C+L9hg== X-Received: by 2002:a05:6a20:7f9a:b0:157:64e4:4260 with SMTP id d26-20020a056a207f9a00b0015764e44260mr3874739pzj.9.1696445012699; Wed, 04 Oct 2023 11:43:32 -0700 (PDT) X-Received: from PH7PR10MB6335.namprd10.prod.outlook.com ([2603:1036:30c:842::5]) by smtp.gmail.com with ESMTPSA id j18-20020aa783d2000000b00688965c5227sm3546466pfn.120.2023.10.04.11.43.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 11:43:32 -0700 (PDT) From: "Tuan Phan" To: "devel@edk2.groups.io" , "andrei.warkentin@intel.com" CC: "Kinney, Michael D" , "Gao, Liming" , "Liu, Zhiguang" , "sunilvl@ventanamicro.com" , "git@danielschaefer.me" , "ardb+tianocore@kernel.org" Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode Thread-Topic: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode Thread-Index: AW4tODIziHvCgsu5mbaOVz8ohcW8u9eTdHKAgAAAb4o= X-MS-Exchange-MessageSentRepresentingType: 1 Date: Wed, 4 Oct 2023 18:43:30 +0000 Message-ID: References: <20231003210021.26834-1-tphan@ventanamicro.com> In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-Exchange-Organization-SCL: -1 X-MS-TNEF-Correlator: X-MS-Exchange-Organization-RecordReviewCfmType: 0 MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,tphan@ventanamicro.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_PH7PR10MB6335595206FF79241444004BA7CBAPH7PR10MB6335namp_" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=GuxxOSKy; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io --_000_PH7PR10MB6335595206FF79241444004BA7CBAPH7PR10MB6335namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable https://github.com/pttuan/edk2.git branch: tphan/riscv_mmu_new_pcd From: devel@edk2.groups.io on behalf of Andrei Warke= ntin Date: Wednesday, October 4, 2023 at 11:42 AM To: Tuan Phan , devel@edk2.groups.io Cc: Kinney, Michael D , Gao, Liming , Liu, Zhiguang , sunilvl@ventanamic= ro.com , git@danielschaefer.me , ardb+tianocore@kernel.org Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD = for SATP mode Do you happen to have a link to a Github tree? A > -----Original Message----- > From: Tuan Phan > Sent: Tuesday, October 3, 2023 4:00 PM > To: devel@edk2.groups.io > Cc: Kinney, Michael D ; Gao, Liming > ; Liu, Zhiguang ; > sunilvl@ventanamicro.com; git@danielschaefer.me; Warkentin, Andrei > ; ardb+tianocore@kernel.org; Tuan Phan > > Subject: [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode > > Introduce a PCD to control the maximum SATP mode that MMU allowed to > use. This PCD helps RISC-V platform set bare or minimum SATA mode during > bring up to debug memory map issue. > > Signed-off-by: Tuan Phan > --- > UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 +++++- > UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++ > UefiCpuPkg/UefiCpuPkg.dec | 8 ++++++++ > 3 files changed, 16 insertions(+), 1 deletion(-) > > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > index 9cca5fc128af..826a1d32a1d4 100644 > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > @@ -36,7 +36,7 @@ > #define PTE_PPN_SHIFT 10 #define RISCV_MMU_PAGE_SHIFT 12 - > STATIC UINTN mModeSupport[] =3D { SATP_MODE_SV57, SATP_MODE_SV48, > SATP_MODE_SV39 };+STATIC UINTN mModeSupport[] =3D { SATP_MODE_SV57, > SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF }; STATIC UINTN > mMaxRootTableLevel; STATIC UINTN mBitPerLevel; STATIC UINTN > mTableEntryCount;@@ -590,6 +590,10 @@ RiscVMmuSetSatpMode ( > UINTN Index; EFI_STATUS = Status; + if > (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {+ return > EFI_DEVICE_ERROR;+ }+ switch (SatpMode) { case SATP_MODE_OFF: > return EFI_SUCCESS;diff --git > a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > index 9b28a98cb346..51ebe1750e97 100644 > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > @@ -25,3 +25,6 @@ > [LibraryClasses] BaseLib++[Pcd]+ > gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ## > CONSUMESdiff --git a/UefiCpuPkg/UefiCpuPkg.dec > b/UefiCpuPkg/UefiCpuPkg.dec > index 68473fc640e6..79191af18a05 100644 > --- a/UefiCpuPkg/UefiCpuPkg.dec > +++ b/UefiCpuPkg/UefiCpuPkg.dec > @@ -396,6 +396,14 @@ > # @Prompt Access to non-SMRAM memory is restricted to reserved, > runtime and ACPI NVS type after SmmReadyToLock. > gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|B > OOLEAN|0x3213210F +[PcdsFixedAtBuild.RISCV64]+ ## Indicate the > maximum SATP mode allowed.+ # 0 - Bare mode.+ # 8 - 39bit mode.+ # = 9 - > 48bit mode.+ # 10 - 57bit mode.+ > gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0|UINT32|0x6 > 0000021+ [PcdsDynamic, PcdsDynamicEx] ## Contains the pointer to a CPU > S3 data buffer of structure ACPI_CPU_DATA. # @Prompt The pointer to a C= PU > S3 data buffer.-- > 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109332): https://edk2.groups.io/g/devel/message/109332 Mute This Topic: https://groups.io/mt/101742937/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --_000_PH7PR10MB6335595206FF79241444004BA7CBAPH7PR10MB6335namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

https://github.com/pttuan/edk2.git

branch: tphan/riscv= _mmu_new_pcd

 

From: devel@edk2.groups.i= o <devel@edk2.groups.io> on behalf of Andrei Warkentin <andrei.war= kentin@intel.com>
Date: Wednesday, October 4, 2023 at 11:42 AM
To: Tuan Phan <tphan@ventanamicro.com>, devel@edk2.groups.io &= lt;devel@edk2.groups.io>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>, Gao, Limin= g <gaoliming@byosoft.com.cn>, Liu, Zhiguang <zhiguang.liu@intel.co= m>, sunilvl@ventanamicro.com <sunilvl@ventanamicro.com>, git@danie= lschaefer.me <git@danielschaefer.me>, ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>
Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce= a PCD for SATP mode

Do you happen to have a link to a Github tree?

A

> -----Original Message-----
> From: Tuan Phan <tphan@ventanamicro.com>
> Sent: Tuesday, October 3, 2023 4:00 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming<= br> > <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel= .com>;
> sunilvl@ventanamicro.com; git@danielschaefer.me; Warkentin, Andrei
> <andrei.warkentin@intel.com>; ardb+tianocore@kernel.org; Tuan Ph= an
> <tphan@ventanamicro.com>
> Subject: [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mod= e
>
> Introduce a PCD to control the maximum SATP mode that MMU allowed to > use. This PCD helps RISC-V platform set bare or minimum SATA mode duri= ng
> bring up to debug memory map issue.
>
> Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> ---
>  UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c  = | 6 +++++-
>  UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++ >  UefiCpuPkg/UefiCpuPkg.dec      &nb= sp;            =            | 8 ++++++++ >  3 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> index 9cca5fc128af..826a1d32a1d4 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> @@ -36,7 +36,7 @@
>  #define PTE_PPN_SHIFT       &= nbsp; 10 #define RISCV_MMU_PAGE_SHIFT  12 -
> STATIC UINTN  mModeSupport[] =3D { SATP_MODE_SV57, SATP_MODE_SV48= ,
> SATP_MODE_SV39 };+STATIC UINTN  mModeSupport[] =3D { SATP_MODE_SV= 57,
> SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF }; STATIC UINTN
> mMaxRootTableLevel; STATIC UINTN  mBitPerLevel; STATIC UINTN
> mTableEntryCount;@@ -590,6 +590,10 @@ RiscVMmuSetSatpMode  (
>    UINTN        = ;            &n= bsp;       Index;   EFI_STATUS = ;            &n= bsp;         Status; +  if
> (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {+  &nb= sp; return
> EFI_DEVICE_ERROR;+  }+   switch (SatpMode) {  = ;   case SATP_MODE_OFF:
> return EFI_SUCCESS;diff --git
> a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> index 9b28a98cb346..51ebe1750e97 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> @@ -25,3 +25,6 @@
>   [LibraryClasses]   BaseLib++[Pcd]+
> gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode  ##
> CONSUMESdiff --git a/UefiCpuPkg/UefiCpuPkg.dec
> b/UefiCpuPkg/UefiCpuPkg.dec
> index 68473fc640e6..79191af18a05 100644
> --- a/UefiCpuPkg/UefiCpuPkg.dec
> +++ b/UefiCpuPkg/UefiCpuPkg.dec
> @@ -396,6 +396,14 @@
>    # @Prompt Access to non-SMRAM memory is restricted t= o reserved,
> runtime and ACPI NVS type after SmmReadyToLock.
> gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|B
> OOLEAN|0x3213210F +[PcdsFixedAtBuild.RISCV64]+  ## Indicate the > maximum SATP mode allowed.+  #  0 - Bare mode.+  # = ; 8 - 39bit mode.+  #  9 -
> 48bit mode.+  #  10 - 57bit mode.+
> gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0|UINT32|0x6
> 0000021+ [PcdsDynamic, PcdsDynamicEx]   ## Contains the poin= ter to a CPU
> S3 data buffer of structure ACPI_CPU_DATA.   # @Prompt The p= ointer to a CPU
> S3 data buffer.--
> 2.25.1





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