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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,rangasai.v.chaganty@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: QQlTWcLdGkrVKH0HuemEqXGkx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=elo0GpJD; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") Reviewed-by: Sai Chaganty -----Original Message----- From: Kasbekar, Saloni =20 Sent: Tuesday, August 01, 2023 3:18 PM To: devel@edk2.groups.io Cc: Kasbekar, Saloni ; Chaganty, Rangasai V ; Desimone, Nathaniel L ; Oram, Isaac W ; Chuang, Rosen Subject: [PATCH v2 1/6] AlderlakeOpenBoardPkg: Add package and headers Create the AlderlakeOpenBoardPkg to provide board support code. The package= supports Alderlake Mobile board with LPDDR4. The package serves as a suppo= rt package in the EDK II Minimum Platform design. Cc: Sai Chaganty Cc: Nate DeSimone Cc: Isaac Oram Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../Include/Library/BoardConfigLib.h | 59 ++++ .../Include/Library/PeiGetFvInfoLib.h | 29 ++ .../Include/Library/SpiFlashCommon.h | 99 ++++++ .../Include/PlatformBoardConfig.h | 93 ++++++ .../Include/PlatformBoardId.h | 21 ++ .../Include/PlatformGpioConfig.h | 18 + .../Include/PlatformPostCode.h | 39 +++ .../Include/PolicyUpdateMacro.h | 48 +++ .../AlderlakeOpenBoardPkg/OpenBoardPkg.dec | 307 ++++++++++++++++++ 9 files changed, 713 insertions(+) create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/Bo= ardConfigLib.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/Pe= iGetFvInfoLib.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/Sp= iFlashCommon.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBo= ardConfig.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBo= ardId.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGp= ioConfig.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPo= stCode.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpda= teMacro.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConf= igLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigL= ib.h new file mode 100644 index 0000000000..3a07563c5d --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLi +++ b.h @@ -0,0 +1,59 @@ +/** @file + Function prototype of BoardConfigLib. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _BOARD_CONFIG_LIB_H_ +#define _BOARD_CONFIG_LIB_H_ + +#include +#include + +#define SIZE_OF_FIELD(TYPE, Field) (sizeof (((TYPE *)0)->Field)) + +#define SIZE_OF_TABLE(TABLE, TYPE) (sizeof (TABLE) / sizeof (TYPE)) + +#define BOARD_CONFIG PLATFORM_INFO + +#define PRE_MEM 0 +#define POST_MEM 1 +#define EARLY_PRE_MEM 2 + +/** + Procedure to detect current board HW configuration. + +**/ +VOID +EFIAPI +GetBoardConfig ( + VOID + ); + + +/** + Count the number of GPIO settings in the Table. + + @param[in] GpioTable The pointer of GPIO config table + @param[out] GpioCount The number of GPIO config entries +**/ +VOID +GetGpioTableSize ( + GPIO_INIT_CONFIG *GpioTable, + OUT UINT16 *GpioCount + ); + + +/** + Configure GPIO pads in PEI phase. + + @param[in] GpioTable Pointer to Gpio table **/ VOID GpioInit ( + IN GPIO_INIT_CONFIG *GpioTable + ); + +#endif // _BOARD_CONFIG_LIB_H_ diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvI= nfoLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInf= oLib.h new file mode 100644 index 0000000000..f2e5a77787 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoL +++ ib.h @@ -0,0 +1,29 @@ +/** @file + Header file for PeiGetFvInfoLib.. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PEI_GET_FV_INFO_LIB_H_ +#define _PEI_GET_FV_INFO_LIB_H_ + +/** + PeiGetSectionFromFv finds the file in FV and gets file Address and=20 +Size + + @param[in] NameGuid - File GUID + @param[out] Address - Pointer to the File Address + @param[out] Size - Pointer to File Size + + @retval EFI_SUCCESS Successfull in reading the section fr= om FV +**/ +EFI_STATUS +EFIAPI +PeiGetSectionFromFv ( + IN CONST EFI_GUID NameGuid, + OUT VOID **Address, + OUT UINT32 *Size + ); + +#endif diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashC= ommon.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashComm= on.h new file mode 100644 index 0000000000..76ba3a8094 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommo +++ n.h @@ -0,0 +1,99 @@ +/** @file + The header file includes the common header files, defines + internal structure and functions used by SpiFlashCommonLib. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SPI_FLASH_COMMON_H__ +#define __SPI_FLASH_COMMON_H__ + +#include +#include +#include +#include +#include +#include #include=20 + #include=20 + +#include + +#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size +/** + Enable block protection on the Serial Flash device. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashLock ( + VOID + ); + +/** + Read NumBytes bytes of data from the address specified by + PAddress into Buffer. + + @param[in] Address The starting physical address of the read. + @param[in,out] NumBytes On input, the number of bytes to read. On = output, the number + of bytes actually read. + @param[out] Buffer The destination data buffer for the read. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashRead ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + OUT UINT8 *Buffer + ); + +/** + Write NumBytes bytes of data from Buffer to the address specified by + PAddresss. + + @param[in] Address The starting physical address of the wri= te. + @param[in,out] NumBytes On input, the number of bytes to write. = On output, + the actual number of bytes written. + @param[in] Buffer The source data buffer for the write. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashWrite ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + IN UINT8 *Buffer + ); + +/** + Erase the block starting at Address. + + @param[in] Address The starting physical address of the block t= o be erased. + This library assume that caller garantee tha= t the PAddress + is at the starting address of this block. + @param[in] NumBytes On input, the number of bytes of the logical= block to be erased. + On output, the actual number of bytes erased= . + + @retval EFI_SUCCESS. Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashBlockErase ( + IN UINTN Address, + IN UINTN *NumBytes + ); + +#endif diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConf= ig.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h new file mode 100644 index 0000000000..f9ac991eb4 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h @@ -0,0 +1,93 @@ +/** @file + Header file for Platform Boards Configurations. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PLATFORM_BOARD_CONFIG_H +#define _PLATFORM_BOARD_CONFIG_H + +#include +#include +#include +#include + +#define MAX_GPIO_PINS 130 + +// +// ACPI table information used to update tables thru PCD // +#define ACPI_OEM_TABLE_ID_ADL_P_M 0x4D2D502D4C4441 //ADL-P-M + +#pragma pack(1) + +typedef struct { + UINT8 ClkReqNumber : 4; + UINT8 ClkReqSupported : 1; + UINT8 DeviceResetPadActiveHigh : 1; + UINT32 DeviceResetPad; +} ROOT_PORT_CLK_INFO; + +typedef struct { + UINT8 Section; + UINT8 Pin; +} EXPANDER_GPIO_CONFIG; + +typedef struct { + UINT8 Type; + UINT8 Reserved[3]; // alignment for COMMON_GPIO_CONFIG + union { + UINT32 Pin; + EXPANDER_GPIO_CONFIG Expander; + } u; +} BOARD_GPIO_CONFIG; + +// Do not change the encoding. It must correspond with PCH_PCIE_CLOCK_USAG= E from PCH RC. +#define NOT_USED 0xFF +#define LAN_CLOCK 0x70 +#define PCIE_PEG 0x40 +#define PCIE_PCH 0x00 + +typedef struct { + UINT32 ClockUsage; + UINT32 ClkReqSupported; +} PCIE_CLOCK_CONFIG; + +typedef union { + UINT64 Blob; + BOARD_GPIO_CONFIG BoardGpioConfig; + ROOT_PORT_CLK_INFO Info; + PCIE_CLOCK_CONFIG PcieClock; +} PCD64_BLOB; + +// Having Max CLK config to support both ADL P and ALD S #define=20 +PCH_MAX_PCIE_CLOCKS_SBC 18 + +//seamless board configurations +typedef struct { + UINT32 ClockUsage[PCH_MAX_PCIE_CLOCKS_SBC]; +} PCIE_CLOCKS_USAGE; + +#define SPD_DATA_SIZE 1024 + +//SBC MRC DQS +typedef struct { + UINT8 DqsMapCpu2Dram[8][2]; +} MRC_DQS; + +//SBC MRC DQ +typedef struct { + UINT8 DqMapCpu2Dram[8][2][8]; +} MRC_DQ; + +//SBC SPD DATA +typedef struct { + BOOLEAN OverrideSpd; + UINT8 SpdData[SPD_DATA_SIZE]; +} SPD_DATA; + +#pragma pack() + +#endif // _PLATFORM_BOARD_CONFIG_H diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h= b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h new file mode 100644 index 0000000000..51b317ffec --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h @@ -0,0 +1,21 @@ +/** @file +Defines Platform BoardIds + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PLATFORM_BOARD_ID_H_ +#define _PLATFORM_BOARD_ID_H_ + +// +// Alderlake Sku IDs +// +#define SkuIdAdlPDdr5Rvp 0x000012 +#define AdlPSkuType 2 + +// Alderlake P Board IDs +#define BoardIdAdlPDdr5Rvp 0x12 + +#endif // _PLATFORM_BOARD_ID_H_ diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfi= g.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h new file mode 100644 index 0000000000..d8a4c2ab77 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h @@ -0,0 +1,18 @@ +/** @file +Defines Platform GPIO Configuration Arrary + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#ifndef _PLATFORM_GPIO_CONFIG_H_ +#define _PLATFORM_GPIO_CONFIG_H_ + +typedef struct { + GPIO_INIT_CONFIG GpioConfig[0]; +} GPIO_INIT_CONFIG_ARRAY; + +#endif diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.= h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h new file mode 100644 index 0000000000..4dbdd8e391 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h @@ -0,0 +1,39 @@ +/** @file + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _PLATFORMPOSTCODE_H_ +#define _PLATFORMPOSTCODE_H_ + +// +// GENERAL USAGE GUIDELINES +// + +/** +[definition] +PostCode =3D XYZZ +X - "D"=3Dpremem, "9"=3Dpostmem, "8"=3DSMM, "7"=3DDXE Y - "6"=3Dplatform d= river,=20 +"5"=3Dboard driver ZZ - "00"=3Dentry, "7F"=3Dexit + - 1 - board init premem: entry/exit (0xD500/0xD57F) + - 2 - platform init premem: entry/exit (0xD600/0xD67F) + - 3 - board init postmem: entry/exit (0x9500/0x957F) + - 4 - platform init postmem: entry/exit (0x9600/0x967F) + - 5 - board init DXE: entry/exit (0x7500/0x757F) + - 6 - platform init DXE: entry/exit (0x7600/0x767F) + - 7 - platform SMM init: entry/exit (0x8600/0x867F) + - 8 - BIOS S3 entry (0xB503) means BioS PC 03, to differentiate with=20 +ACPI _PTS PC + - 9 - BIOS S4 entry (0xB504) means BioS PC 04, to differentiate with=20 +ACPI _PTS PC + - 10 - BIOS S5 entry (0B505) means BioS PC 05, to differentiate with=20 +ACPI _PTS PC */ + +#define PLATFORM_INIT_PREMEM_ENTRY 0xD600 +#define PLATFORM_INIT_PREMEM_EXIT 0xD67F +#define PLATFORM_INIT_POSTMEM_ENTRY 0x9600 #define=20 +PLATFORM_INIT_POSTMEM_EXIT 0x967F +#define PLATFORM_SMM_INIT_ENTRY 0x8600 +#define PLATFORM_SMM_INIT_EXIT 0x867F + +#endif diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro= .h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h new file mode 100644 index 0000000000..c9ace9d910 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h @@ -0,0 +1,48 @@ +/** @file + Macros for platform to update different types of policy. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _POLICY_UPDATE_MACRO_H_ +#define _POLICY_UPDATE_MACRO_H_ + +#ifdef UPDATE_POLICY +#undef UPDATE_POLICY +#endif + +#ifdef COPY_POLICY +#undef COPY_POLICY +#endif + +#ifdef GET_POLICY +#undef GET_POLICY +#endif + +#ifdef AND_POLICY +#undef AND_POLICY +#endif + +#ifdef OR_POLICY +#undef OR_POLICY +#endif + +#define UPDATE_POLICY(UpdField, ConfigField, Value) ConfigField =3D=20 +Value; #define COPY_POLICY(UpdField, ConfigField, Value, Size) CopyMem=20 +(ConfigField, Value, Size); #define GET_POLICY(UpdField, ConfigField,=20 +Value) Value =3D ConfigField; #define AND_POLICY(UpdField, ConfigField,= =20 +Value) ConfigField &=3D Value; #define OR_POLICY(UpdField, ConfigField,= =20 +Value) ConfigField |=3D Value; // // Compare Policy Default and Setup=20 +Default when FirstBoot and RvpSupport // + +#define COMPARE_AND_UPDATE_POLICY(UpdField, ConfigField, Value) {\ + UPDATE_POLICY(UpdField, ConfigField, Value);\ } #define=20 +COMPARE_UPDATE_POLICY_ARRAY(UpdField, ConfigField, Value, ArrayIndex)=20 +{\ + UPDATE_POLICY(UpdField, ConfigField, Value);\ } + +#endif //_POLICY_UPDATE_MACRO_H_ diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec b/Platfo= rm/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec new file mode 100644 index 0000000000..0f0ed386f6 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec @@ -0,0 +1,307 @@ +## @file +# +# The DEC files are used by the utilities that parse DSC and # INF=20 +files to generate AutoGen.c and AutoGen.h files # for the build=20 +infrastructure. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +DEC_SPECIFICATION =3D 0x00010017 +PACKAGE_NAME =3D OpenBoardPkg +PACKAGE_VERSION =3D 0.1 +PACKAGE_GUID =3D A840FA72-FBF7-4357-B301-DAE2233F14AB + +[Includes] +Include + +[Guids] + gBoardModuleTokenSpaceGuid =3D {0x72d1fff7, 0xa42a, 0x4219, {0xb9,= 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}} + gPlatformModuleTokenSpaceGuid =3D {0x69d13bf0, 0xaf91, 0x4d96, {0xaa,= 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}} + gPlatformInitFvLocationGuid =3D {0xa564010a, 0x1d90, 0x4b1c, {0x8d,= 0x10, 0xcb, 0xba, 0xff, 0xb2, 0x55, 0x42}} + gVpdFfsGuid =3D {0x338FA35A, 0xCA4A, 0x4DBC, {0xA6,= 0xF4, 0x9B, 0xD1, 0x59, 0x3B, 0x61, 0xBC}} + gMemoryConfigVariableGuid =3D {0xc94f8c4d, 0x9b9a, 0x45fe, = {0x8a, 0x55, 0x23, 0x8b, 0x67, 0x30, 0x26, 0x43}} + +# +# FvImage File +# + gFvAdvancedFileGuid =3D {0xAD198BA5, 0xC330, 0x41CD, {= 0xB0, 0x97, 0x16, 0x48, 0x83, 0x28, 0xB7, 0x98}} + gFvOsBootFileGuid =3D {0xB9020753, 0x84A8, 0x4BB6, {= 0x94, 0x7C, 0xCE, 0x7D, 0x41, 0xF5, 0xCE, 0x39}} + gFvUefiBootFileGuid =3D {0x9E21FD93, 0x9C72, 0x4c15, {= 0x8C, 0x4B, 0xE7, 0x7F, 0x1D, 0xB2, 0xD7, 0x92}} + gTianoLogoGuid =3D {0x7BB28B99, 0x61BB, 0x11D5, = {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}} + + # gUefiShellFileGuid is FILE GUID for MinUefiShell.inf/UefiShell.inf/She= ll.inf. + gUefiShellFileGuid =3D {0x7c04a583, 0x9e3e, 0x4f1c, = {0xad, 0x65, 0xe0, 0x52, 0x68, 0xd0, 0xb4, 0xd1}} + +[Ppis] + gReadyForGopConfigPpiGuid =3D {0x5f252c18, 0x1781, 0x4290= , {0xa7, 0xb6, 0xfd, 0x99, 0x63, 0x4c, 0x6a, 0x8a}} + +[PcdsFixedAtBuild, PcdsPatchableInModule] ## ##=20 +PcdSmbiosOemTypeFirmwareVersionInfo determines the SMBIOS OEM type=20 +(0x80 to 0xFF) defined in SMBIOS, ## values 0-0x7F will be treated as disa= ble FVI reporting. +## FVI structure uses it as SMBIOS OEM type to provide version information= . +## +gPlatformModuleTokenSpaceGuid.PcdSmbiosOemTypeFirmwareVersionInfo|0xDD| +UINT8|0x20000001 + +[PcdsFixedAtBuild] + gBoardModuleTokenSpaceGuid.PcdDefaultBoardId|0|UINT16|0x10101009 + + =20 + gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x1000101 + 0 + =20 + gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|0x1000 + 1011 + + ## + ## The Flash PCDs will be patched based on FDF definitions during build. + ## Set them to 0 here to prevent confusion. + ## + + =20 + gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase|0x00000000|U + INT32|0x20000040 + =20 + gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize|0x00000000|U + INT32|0x20000041 + =20 + gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset|0x00000000 + |UINT32|0x20000042 =20 + gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase|0x00000000|UINT32|0x + 2000004C =20 + gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize|0x00000000|UINT32|0x + 2000004D =20 + gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalOffset|0x00000000|UINT32| + 0x2000004E + + =20 + gBoardModuleTokenSpaceGuid.PcdFlashObbSize|0x00000000|UINT32|0xF0000A5 + 3 + =20 + gBoardModuleTokenSpaceGuid.PcdFlashIbbOffset|0x00000000|UINT32|0xF0000 + A58 + =20 + gBoardModuleTokenSpaceGuid.PcdFlashIbbSize|0x00000000|UINT32|0xF0000A5 + 9 =20 + gBoardModuleTokenSpaceGuid.PcdFlashFvRsvdOffset|0x00000000|UINT32|0x20 + 000A5E =20 + gBoardModuleTokenSpaceGuid.PcdFlashFvRsvdSize|0x00000000|UINT32|0x2000 + 0A5F + =20 + gBoardModuleTokenSpaceGuid.PcdFlashIbbROffset|0x00000000|UINT32|0x2000 + 0A61 + +#(ACPI.inf) +=20 +gPlatformModuleTokenSpaceGuid.PcdApicLocalAddress|0xFEE00000|UINT64|0x9 +000000B =20 +gPlatformModuleTokenSpaceGuid.PcdApicIoAddress|0xFEC00000|UINT64|0x9000 +000D + gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012 +=20 +gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013 + gPlatformModuleTokenSpaceGuid.PcdApicIoIdPch|0x02|UINT8|0x9000001E + +#(BaseMmioInitLib.inf) +gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress|0xFEDA0000|UINT64|0x900 +00003 +gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress|0xFEDA1000|UINT64|0x9000 +0005 + +## This PCD specifies whether StatusCode is reported via SerialIoUart +gPlatformModuleTokenSpaceGuid.PcdStatusCodeUseSerialIoUart|FALSE|BOOLEA +N|0xFF000002 + +## This flag is used to initialize debug output interface. +# BIT0 - RAM debug interface. +# BIT1 - UART debug interface. +# BIT2 - USB debug interface. +# BIT3 - USB3 debug interface. +# BIT4 - Serial IO debug interface. +# BIT5 - TraceHub debug interface. +# BIT6 - Reserved. +# BIT7 - CMOS control. +gPlatformModuleTokenSpaceGuid.PcdStatusCodeFlags|0x82|UINT8|0xF0000111 + +gPlatformModuleTokenSpaceGuid.PcdGttMmAddress|0xAF000000|UINT64|0x90000 +00F +gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress|0xB0000000|UINT64|0x90000 +010 + +gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress|0xFED80000|UINT64|0x9 +0000009 + +gPlatformModuleTokenSpaceGuid.PcdLzmaEnable |FALSE|BOOLEAN|0xF000= 002B + +[PcdsDynamic] + # DRAM Configuration + gBoardModuleTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000174 + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000175 + gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2Dram|0|UINT32|0x00000072 + =20 +gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2DramSize|0|UINT16|0x00000073 + + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000199 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x0000019A + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x0000019B + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x0000019C + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable4|0|UINT8|0x0000019D + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable5|0|UINT8|0x0000019E + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable6|0|UINT8|0x0000019F + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable7|0|UINT8|0x000001A0 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable8|0|UINT8|0x000001A1 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable9|0|UINT8|0x000001A2 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable10|0|UINT8|0x000001A3 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable11|0|UINT8|0x000001A4 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable12|0|UINT8|0x000001A5 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable13|0|UINT8|0x000001A6 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable14|0|UINT8|0x000001A7 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable15|0|UINT8|0x000001A8 + + # Root Port Clock Info + gBoardModuleTokenSpaceGuid.PcdPcieClock0|0|UINT64|0x0000009E + gBoardModuleTokenSpaceGuid.PcdPcieClock1|0|UINT64|0x0000009F + gBoardModuleTokenSpaceGuid.PcdPcieClock2|0|UINT64|0x000000A0 + gBoardModuleTokenSpaceGuid.PcdPcieClock3|0|UINT64|0x000000A1 + gBoardModuleTokenSpaceGuid.PcdPcieClock4|0|UINT64|0x000000A2 + gBoardModuleTokenSpaceGuid.PcdPcieClock5|0|UINT64|0x000000A3 + gBoardModuleTokenSpaceGuid.PcdPcieClock6|0|UINT64|0x000000A4 + gBoardModuleTokenSpaceGuid.PcdPcieClock7|0|UINT64|0x000000A5 + gBoardModuleTokenSpaceGuid.PcdPcieClock8|0|UINT64|0x000000A6 + gBoardModuleTokenSpaceGuid.PcdPcieClock9|0|UINT64|0x000000A7 + gBoardModuleTokenSpaceGuid.PcdPcieClock10|0|UINT64|0x000000A8 + gBoardModuleTokenSpaceGuid.PcdPcieClock11|0|UINT64|0x000000A9 + gBoardModuleTokenSpaceGuid.PcdPcieClock12|0|UINT64|0x000000AA + gBoardModuleTokenSpaceGuid.PcdPcieClock13|0|UINT64|0x000000AB + gBoardModuleTokenSpaceGuid.PcdPcieClock14|0|UINT64|0x000000AC + gBoardModuleTokenSpaceGuid.PcdPcieClock15|0|UINT64|0x000000AD + gBoardModuleTokenSpaceGuid.PcdPcieClock16|0|UINT64|0x000000AE + gBoardModuleTokenSpaceGuid.PcdPcieClock17|0|UINT64|0x000000AF + + + # GPIO Group Tier + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0|0|UINT32|0x000000E9 + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1|0|UINT32|0x000000EA + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2|0|UINT32|0x000000EB + + # Display DDI + =20 + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable|0|UINT32|0x00100033 + =20 + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize|0|UINT16|0x0010 + 0034 + + # MISC + gBoardModuleTokenSpaceGuid.PcdStackBase|0x0|UINT32|0x40000A10 + gBoardModuleTokenSpaceGuid.PcdStackSize|0x0|UINT32|0x40000A11 + + # SA Misc Configuration + gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066 + =20 + gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|0x0000 + 0067 + =20 + gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMask|0|UINT8|0x0000A10 + 3 + =20 + gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMaskEcc|0|UINT8|0x0000 + A104 + =20 + gBoardModuleTokenSpaceGuid.PcdSaMiscDisableMrcRetrainingOnRtcPowerLoss + |0|UINT8|0x0000A105 + + # Board Information + gBoardModuleTokenSpaceGuid.PcdSpdPresent|FALSE|BOOLEAN|0x00101012 + gBoardModuleTokenSpaceGuid.PcdBoardRev|0x0|UINT16|0x00101016 + gBoardModuleTokenSpaceGuid.PcdBoardBomId|0x0|UINT16|0x00101017 + gBoardModuleTokenSpaceGuid.PcdBoardId|0|UINT16|0x00101018 + gBoardModuleTokenSpaceGuid.PcdSkuType|0x0|UINT8|0x0010101F + + # MRC Config + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x00000A68 + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x00000A69 + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x00000A6A + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x00000A6B + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x00000A6C + =20 + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0x00000A6 + D =20 + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALSE|BOOLEA + N|0x00000A6E =20 + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLEAN|0x000 + 00A6F + gBoardModuleTokenSpaceGuid.PcdMrcLp5CccConfig|0|UINT8|0x00000A73 + gBoardModuleTokenSpaceGuid.PcdMrcCmdMirror|0|UINT8|0x00000A74 + gBoardModuleTokenSpaceGuid.PcdRootPortIndex|0xFF|UINT8|0x00000A78 + + # Pch SerialIo I2c Pads Termination + =20 + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm|0x1|UINT8 + |0x00000020 + =20 + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm|0x1|UINT8 + |0x00000021 + =20 + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm|0x1|UINT8 + |0x00000022 + =20 + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm|0x1|UINT8 + |0x00000023 + =20 + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm|0x1|UINT8 + |0x00000030 + =20 + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm|0x1|UINT8 + |0x00000031 + =20 + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c6PadInternalTerm|0x1|UINT8 + |0x00000032 + =20 + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c7PadInternalTerm|0x1|UINT8 + |0x00000033 + +[PcdsDynamicEx] +# Flag to Disable Vpd Gpio +gBoardModuleTokenSpaceGuid.PcdDisableVpdGpioTable|FALSE|BOOLEAN|0x50000 +015 +# Pre-Mem GPIO table + =20 +gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem|{0}|GPIO_INIT_CONFIG +_ARRAY|0x50000017 { + + Pins/GpioPinsVer2Lp.h + Library/GpioLib.h + PlatformGpioConfig.h + + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec +} + + =20 +gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|{0}|GPIO_INIT_CON +FIG[]|0x50000018 { + + Pins/GpioPinsVer2Lp.h + Library/GpioLib.h + Library/GpioConfig.h + + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec +} + +# GPIO table + =20 +gBoardModuleTokenSpaceGuid.PcdBoardGpioTable|{0}|GPIO_INIT_CONFIG_ARRAY +|0x50000019 { + + Pins/GpioPinsVer2Lp.h + Library/GpioLib.h + PlatformGpioConfig.h + + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec +} + =20 +gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable|{0}|GPIO_INIT_CONFIG[]| +0x5000001C { + + Pins/GpioPinsVer2Lp.h + Library/GpioConfig.h + + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec +} + +# PCIE CLOCKS USAGE + =20 +gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|{0}|PCIE_CLOCKS_USAGE| +0x50000022 { + + PlatformBoardConfig.h + + MdePkg/MdePkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec +} + +#SBC SPD DATA + gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData|{0}|SPD_DATA|0x50000025 { + + PlatformBoardConfig.h + + MdePkg/MdePkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec +} + +# SBC MRC DQS MAPPING + =20 +gBoardModuleTokenSpaceGuid.VpdPcdMrcDqsMapCpu2Dram|{0}|MRC_DQS|0x500000 +26 { + + PlatformBoardConfig.h + + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec +} + +# SBC MRC DQ MAPPING + =20 +gBoardModuleTokenSpaceGuid.VpdPcdMrcDqMapCpu2Dram|{0}|MRC_DQ|0x50000027=20 +{ + + PlatformBoardConfig.h + + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderlakeOpenBoardPkg/OpenBoardPkg.dec +} + +# ACPI data + gBoardModuleTokenSpaceGuid.PcdBoardAcpiData|{0}|VOID*|0x5000001A + +# Early Pre-Mem GPIO table + =20 +gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem|{0}|GPIO_INIT_C +ONFIG_ARRAY|0x5000001B { + + Pins/GpioPinsVer2Lp.h + Library/GpioLib.h + PlatformGpioConfig.h + + MdePkg/MdePkg.dec + AlderlakeSiliconPkg/SiPkg.dec + AlderLakeOpenBoardPkg/OpenBoardPkg.dec +} +[PcdsDynamic, PcdsDynamicEx] + +[PcdsPatchableInModule] + +[PcdsFeatureFlag] + gBoardModuleTokenSpaceGuid.PcdIntelGopEnable |FALSE|BOOLEAN|0xF= 0000B54 -- 2.36.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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