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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ted.kuo@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: v5DnDif3PTxmQEuf0Bg3EO2xx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=XZt7nTFv; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Please drop v2. I'm going to update the patch to v3. Thanks, Ted -----Original Message----- From: devel@edk2.groups.io On Behalf Of Kuo, Ted Sent: Thursday, December 21, 2023 6:37 PM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Chiu, Chasel ; Desimone, Nathaniel L = ; Dong, Eric ; S, Ashraf Ali ;= Duggapu, Chinni B ; Gao, Liming Subject: [edk2-devel][edk2-platforms][PATCH v2] MinPlatformPkg: Support Sec= FspWrapperPlatformSecLib in X64 https://bugzilla.tianocore.org/show_bug.cgi?id=3D4623 1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64. 2.Made changes in common file to support both IA32 and X64. 3.Added the PCDs below for FSP-T UPD revisions and reset vector in FSP. - PcdFspWrapperBfvforResetVectorInFsp - PcdFsptUpdHeaderRevision - PcdFsptArchUpdRevision Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Eric Dong Cc: Ashraf Ali S Cc: Chinni B Duggapu Cc: Liming Gao Signed-off-by: Ted Kuo --- .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 +- .../Ia32/SecEntry.nasm | 4 +- .../SecFspWrapperPlatformSecLib.inf | 9 +- .../SecFspWrapperPlatformSecLibFspO.inf | 101 ++++++++ .../SecGetPerformance.c | 11 +- .../SecPlatformInformation.c | 8 +- .../SecRamInitData.c | 73 ++++-- .../X64/PeiCoreEntry.nasm | 218 ++++++++++++++++++ .../X64/SecEntry.nasm | 71 ++++++ .../X64/Stack.nasm | 72 ++++++ .../Ia32 =3D> Include}/Fsp.h | 4 +- .../Intel/MinPlatformPkg/MinPlatformPkg.dec | 15 ++ 12 files changed, 579 insertions(+), 32 deletions(-) create mode 100644 P= latform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib= /SecFspWrapperPlatformSecLibFspO.inf create mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/X64/PeiCoreEntry.nasm create mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/X64/SecEntry.nasm create mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/X64/Stack.nasm rename Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlat= formSecLib/Ia32 =3D> Include}/Fsp.h (86%) diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/FsptCoreUpd.h b/Platform/Intel/MinPlatformPkg/FspWrapper/Lib= rary/SecFspWrapperPlatformSecLib/FsptCoreUpd.h index 7c0f605b92..7c4ddc09a8 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/FsptCoreUpd.h +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat +++ formSecLib/FsptCoreUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2017, Intel Corporation. All rights reserved.
= +Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.
SPD= X-License-Identifier: BSD-2-Clause-Patent **/@@ -10,6 +10,28 @@ SPDX-Licen= se-Identifier: BSD-2-Clause-Patent #pragma pack(1) +#if defined (MDE_CPU_X64)+/** Fsp T Core UPD+**/+typedef= struct {++/** Offset 0x0040+**/+ EFI_PHYSICAL_ADDRESS MicrocodeReg= ionBase;++/** Offset 0x0048+**/+ UINT64 MicrocodeRegi= onSize;++/** Offset 0x0050+**/+ EFI_PHYSICAL_ADDRESS CodeRegionBase= ;++/** Offset 0x0058+**/+ UINT64 CodeRegionSize;+} FS= PT_CORE_UPD;+#else /** Fsp T Core UPD **/ typedef struct {@@ -34,6 +56,7 @@= typedef struct { **/ UINT8 Reserved[16]; } FSPT_CORE_UPD;+#endif #= pragma pack() diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library= /SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm b/Platform/Intel/MinPlatfor= mPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm index 7f6d771e41..de44066a20 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/Ia32/SecEntry.nasm +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat +++ formSecLib/Ia32/SecEntry.nasm @@ -1,6 +1,6 @@ ;-------------------------------------------------------------------------= ----- ;-; Copyright (c) 2019, Intel Corporation. All rights reserved.
+;= Copyright (c) 2019 - 2023, Intel Corporation. All rights reserved.
; S= PDX-License-Identifier: BSD-2-Clause-Patent ; Module Name: ;@@ -13,7 +13,7 = @@ ; ;--------------------------------------------------------------------= ---------- -#include "Fsp.h"+#include SECTION .text diff --git a/P= latform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib= /SecFspWrapperPlatformSecLib.inf b/Platform/Intel/MinPlatformPkg/FspWrapper= /Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf index 2e0d67eae4..2ff931bfe8 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecFspWrapperPlatformSecLib.inf +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat +++ formSecLib/SecFspWrapperPlatformSecLib.inf @@ -1,7 +1,7 @@ ## @file-# Provide FSP wrapper platform sec related function.+# Provide = FSP wrapper platform sec related function for IA32. #-# Copyright (c) 2017= - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 = - 2023, Intel Corporation. All rights reserved.
# # SPDX-License-Identi= fier: BSD-2-Clause-Patent #@@ -25,7 +25,7 @@ # # The following information is for reference only and not required by th= e build tools. #-# VALID_ARCHITECTURES =3D IA32 X64+# VALID_ARC= HITECTURES =3D IA32 # ##########################################= ######################################@@ -47,7 +47,6 @@ Ia32/SecEntry.nasm Ia32/PeiCoreEntry.nasm Ia32/Stack.nasm- Ia32/Fsp= .h #######################################################################= ######### #@@ -96,3 +95,5 @@ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## C= ONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection = ## CONSUMES gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiM= ain ## CONSUMES+ gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevis= ion ## CONSUMES+ gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpd= Revision ## CONSUMESdiff --git a/Platform/Intel/MinPlatformP= kg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecL= ibFspO.inf b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecFspWrapperPlatformSecLibFspO.inf new file mode 100644 index 0000000000..5bbd49bdbf --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat +++ formSecLib/SecFspWrapperPlatformSecLibFspO.inf @@ -0,0 +1,101 @@ +## @file+# Provide FSP wrapper platform sec related function for X64.+#+#= Copyright (c) 2023, Intel Corporation. All rights reserved.
+#+# SPDX-= License-Identifier: BSD-2-Clause-Patent+#+#+##++###########################= #####################################################+#+# Defines Section -= statements that will be processed to create a Makefile.+#+################= ################################################################+[Defines]+= INF_VERSION =3D 0x00010005+ BASE_NAME = =3D SecFspWrapperPlatformSecLib+ FILE_GUID =3D = 94D8AA5C-5BAE-421F-B2C7-DD1A93BB4D3D+ MODULE_TYPE =3D S= EC+ VERSION_STRING =3D 1.0+ LIBRARY_CLASS = =3D PlatformSecLib+++#+# The following information is for reference only = and not required by the build tools.+# This library is only supported in X6= 4 when reset vector is in FSP.+#+# VALID_ARCHITECTURES =3D X64+#= ++#########################################################################= #######+#+# Sources Section - list of files that are required for the build= to succeed.+#+############################################################= ####################++[Sources]+ FspWrapperPlatformSecLib.c+ SecRamInitDa= ta.c+ SecPlatformInformation.c+ SecGetPerformance.c+ SecTempRamDone.c+ = PlatformInit.c+ FsptCoreUpd.h++[Sources.X64]+ X64/SecEntry.nasm+ X64/Pei= CoreEntry.nasm+ X64/Stack.nasm++##########################################= ######################################+#+# Package Dependency Section - lis= t of Package files that are required for+# thi= s module.+#+###############################################################= #################++[Packages]+ MdePkg/MdePkg.dec+ MdeModulePkg/MdeModuleP= kg.dec+ UefiCpuPkg/UefiCpuPkg.dec+ IntelFsp2Pkg/IntelFsp2Pkg.dec+ IntelF= sp2WrapperPkg/IntelFsp2WrapperPkg.dec+ MinPlatformPkg/MinPlatformPkg.dec++= [LibraryClasses]+ LocalApicLib+ SerialPortLib+ FspWrapperPlatformLib+ F= spWrapperApiLib+ SecBoardInitLib+ TestPointCheckLib+ PeiServicesTablePoi= nterLib++[Ppis]+ gEfiSecPlatformInformationPpiGuid ## CONSUMES+ gPe= iSecPerformancePpiGuid ## CONSUMES+ gTopOfTemporaryRamPpiGui= d ## PRODUCES+ gEfiPeiFirmwareVolumeInfoPpiGuid ## PR= ODUCES+ gFspTempRamExitPpiGuid ## CONSUMES+ gPlatformIni= tTempRamExitPpiGuid ## CONSUMES++[Pcd]+ gUefiCpuPkgTokenSpaceGuid.= PcdPeiTemporaryRamStackSize ## CONSUMES+ gIntelFsp2WrapperTo= kenSpaceGuid.PcdFsptBaseAddress ## CONSUMES+ gIntelFsp2Pk= gTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES+ gMinP= latformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## CONSUMES+= +[FixedPcd]+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = ## CONSUMES+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = ## CONSUMES+ gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffse= tInFv ## CONSUMES+ gIntelFsp2WrapperTokenSpaceGuid.PcdFlash= CodeCacheAddress ## CONSUMES+ gIntelFsp2WrapperTokenSpaceGuid.P= cdFlashCodeCacheSize ## CONSUMES+ gIntelFsp2WrapperTokenSpac= eGuid.PcdFspmBaseAddress ## CONSUMES+ gIntelFsp2WrapperTo= kenSpaceGuid.PcdFspModeSelection ## CONSUMES+ gMinPlatform= PkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ## CONSUMES+ gMinP= latformPkgTokenSpaceGuid.PcdFspWrapperBfvforResetVectorInFsp ## CONSUMES+= gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevision ## CO= NSUMES+ gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpdRevision = ## CONSUMESdiff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/= SecFspWrapperPlatformSecLib/SecGetPerformance.c b/Platform/Intel/MinPlatfor= mPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c index ac2deeabec..47c8dca4a1 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecGetPerformance.c +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat +++ formSecLib/SecGetPerformance.c @@ -1,7 +1,7 @@ /** @file Sample to provide SecGetPerformance function. -Copyright (c) 2= 017 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2017 = - 2023, Intel Corporation. All rights reserved.
SPDX-License-Identifier= : BSD-2-Clause-Patent **/@@ -58,6 +58,7 @@ SecGetPerformance ( if (EFI_ERROR (Status)) { return EFI_NOT_FOUND; }+ // // |----= ----------| <- TopOfTemporaryRam - BL // | List Ptr |@@ -77,12 +78,12= @@ SecGetPerformance ( // | TSC[31:00] | // |--------------| //- TopOfTemporaryRam =3D (= UINTN) TopOfTemporaryRamPpi - sizeof (UINT32);- TopOfTemporaryRam -=3D siz= eof (UINT32) * 2;- Count =3D *(UINT32 *)(TopOfTemporaryRam - s= izeof (UINT32));+ TopOfTemporaryRam =3D (UINTN) TopOfTemporaryRamPpi - siz= eof (UINTN);+ TopOfTemporaryRam -=3D sizeof(UINTN) * 2;+ Count = =3D *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32)); Size = =3D Count * sizeof (UINT32); - Ticker =3D *(UINT64 *) (TopOfTemp= oraryRam - sizeof (UINT32) - Size - sizeof (UINT32) * 2);+ Ticker =3D *(UI= NT64 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof (UINT6= 4)); Performance->ResetEnd =3D GetTimeInNanoSecond (Ticker); return EF= I_SUCCESS;diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/Sec= FspWrapperPlatformSecLib/SecPlatformInformation.c b/Platform/Intel/MinPlatf= ormPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformatio= n.c index 24d55ed838..44b38265b0 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecPlatformInformation.c +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat +++ formSecLib/SecPlatformInformation.c @@ -1,7 +1,7 @@ /** @file Provide SecPlatformInformation function. -Copyright (c) 2017 -= 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 202= 3, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD= -2-Clause-Patent **/@@ -59,9 +59,9 @@ SecPlatformInformation ( // This routine copies the BIST information to the buffer pointed by /= / PlatformInformationRecord for output. //- TopOfTemporaryRam =3D (UINTN= ) TopOfTemporaryRamPpi - sizeof (UINT32);- TopOfTemporaryRam -=3D sizeof (= UINT32) * 2;- Count =3D *((UINT32 *)(TopOfTemporaryRam - sizeo= f (UINT32)));+ TopOfTemporaryRam =3D (UINTN) TopOfTemporaryRamPpi - sizeof= (UINTN);+ TopOfTemporaryRam -=3D sizeof (UINTN) * 2;+ Count = =3D *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (UINT32))); Size = =3D Count * sizeof (IA32_HANDOFF_STATUS); if ((*StructureSize) = < (UINT64) Size) {diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Lib= rary/SecFspWrapperPlatformSecLib/SecRamInitData.c b/Platform/Intel/MinPlatf= ormPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c index 355d1e6509..54b555a65e 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecRamInitData.c +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat +++ formSecLib/SecRamInitData.c @@ -1,7 +1,7 @@ /** @file Provide TempRamInitParams data. -Copyright (c) 2017 - 2021, In= tel Corporation. All rights reserved.
+Copyright (c) 2017 - 2023, Intel = Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause= -Patent **/@@ -12,25 +12,70 @@ SPDX-License-Identifier: BSD-2-Clause-Paten= t typedef struct { FSP_UPD_HEADER FspUpdHeader;+#if FixedPcdGet8 (PcdF= sptArchUpdRevision) =3D=3D 1+ FSPT_ARCH_UPD FsptArchUpd;+#elif FixedPc= dGet8 (PcdFsptArchUpdRevision) =3D=3D 2+ FSPT_ARCH2_UPD FsptArchUpd;+#e= ndif FSPT_CORE_UPD FsptCoreUpd;-} FSPT_UPD_CORE_DATA;+ UINT16 = UpdTerminator;+} FSPT_UPD_DATA; -GLOBAL_REMOVE_IF_UNREFERENCED CONST F= SPT_UPD_CORE_DATA FsptUpdDataPtr =3D {+GLOBAL_REMOVE_IF_UNREFERENCED CONST = FSPT_UPD_DATA FsptUpdDataPtr =3D { {- 0x4450555F54505346,- 0x00,- = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,- 0x00,= 0x00, 0x00, 0x00, 0x00, 0x00, 0x00+ 0x4450555F54505346, = // FSP-T UPD Header Signature - FSPT_UPD+ Fix= edPcdGet8 (PcdFsptUpdHeaderRevision), // FSP-T UPD Hea= der Revision+ { = // Reserved[23]+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00,+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00= ,+ 0x00, 0x00, 0x00 } },+#if FixedPcdGet8 (PcdFsptArchUpdRevisio= n) =3D=3D 1 {- FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32= (PcdMicrocodeOffsetInFv),- FixedPcdGet32 (PcdFlashFvMicrocodeSize) - Fi= xedPcdGet32 (PcdMicrocodeOffsetInFv),- 0, // Set CodeRegionBase= as 0, so that caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize : Co= deRegionSize) will be used.- FixedPcdGet32 (PcdFlashCodeCacheSize),- = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,+ 0x01, = // FSP-T ARCH UPD Revi= sion+ { // R= eserved[3]+ 0x00, 0x00, 0x00+ },+ 0x00000020, = // Length of FSP-T ARCH UPD+ 0, = // FspDebugHandler+ {= // Reserved1[2= 0]+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,+ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00+ }+ },+#elif= FixedPcdGet8 (PcdFsptArchUpdRevision) =3D=3D 2+ {+ 0x02, = // FSP-T ARCH2 UPD Revision+ = { // Reserved[3= ]+ 0x00, 0x00, 0x00+ },+ 0x00000020, = // Length of FSP-T ARCH2 UPD+ 0, = // FspDebugHandler+ { = // Reserved1[16]+ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x= 00, 0x00, 0x00, 0x00, 0x00 }- }+ },+#endif+#if defined (MDE_CPU_X64)+= {+ FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicroco= deOffsetInFv), // MicrocodeRegionBase+ FixedPcdGet32 (PcdFlashFvMicrocod= eSize) - FixedPcdGet32 (PcdMicrocodeOffsetInFv), // MicrocodeRegionSize+ = 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(CodeRegionSize= > LLCSize ? LLCSize : CodeRegionSize) will be used.+ FixedPcdGet32 (Pcd= FlashCodeCacheSize) // CodeRegi= onSize+ },+#else+ {+ FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPc= dGet32 (PcdMicrocodeOffsetInFv), // MicrocodeRegionBase+ FixedPcdGet32 (= PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeOffsetInFv), // Micro= codeRegionSize+ 0, // Set CodeRegionBase as 0, so that caching will be 4= GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.+ = FixedPcdGet32 (PcdFlashCodeCacheSize), = // CodeRegionSize+ { = // Reserved[16]+ 0x00, 0x00, 0x00,= 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,+ 0x00, 0x00, 0x00, 0x00, 0x= 00, 0x00+ }+ },+#endif+ 0x55AA };-diff --git a/Platform/Intel/MinPlatf= ormPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm= b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSe= cLib/X64/PeiCoreEntry.nasm new file mode 100644 index 0000000000..653368c155 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat +++ formSecLib/X64/PeiCoreEntry.nasm @@ -0,0 +1,218 @@ +;-------------------------------------------------------------------------= -----+;+; Copyright (c) 2023, Intel Corporation. All rights reserved.
+;= SPDX-License-Identifier: BSD-2-Clause-Patent+;+; Module Name:+;+; PeiCore= Entry.nasm+;+; Abstract:+;+; Find and call SecStartup+;+;----------------= --------------------------------------------------------------++SECTION .te= xt++extern ASM_PFX(SecStartup)+extern ASM_PFX(PlatformInit)+extern ASM_PFX(= PcdGet64 (PcdFspWrapperBfvforResetVectorInFsp))++;-------------------------= ----------------------------------------------------+; Macro: PUSHA= _64+;+; Description: Saves all registers on stack+;+; Input: None= +;+; Output: None+;-------------------------------------------------= ----------------------------+%macro PUSHA_64 0+ push r8+ push r9+= push r10+ push r11+ push r12+ push r13+ push r14+ pus= h r15+ push rax+ push rcx+ push rdx+ push rbx+ push = rsp+ push rbp+ push rsi+ push rdi+%endmacro++;-----------------= ------------------------------------------------------------+; Macro: = POPA_64+;+; Description: Restores all registers from stack+;+; Input:= None+;+; Output: None+;-------------------------------------= ----------------------------------------+%macro POPA_64 0+ pop rdi+ = pop rsi+ pop rbp+ pop rsp+ pop rbx+ pop rdx+ pop rcx= + pop rax+ pop r15+ pop r14+ pop r13+ pop r12+ pop = r11+ pop r10+ pop r9+ pop r8+%endmacro++;+; args 1:XMM, 2:REG, = 3:IDX+;+%macro LXMMN 3+ pextrq %2, %1, (%3 & 3)+%endmacro++;+; arg= s 1:YMM, 2:XMM, 3:IDX (0 - lower 128bits, 1 - upper 128bits)+;+%macro LYMMN= 3+ vextractf128 %2, %1, %3+%endmacro++%macro LOAD_TS 1+ LYM= MN ymm6, xmm5, 1+ LXMMN xmm5, %1, 1+%endmacro++global ASM_PFX(CallPeiC= oreEntryPoint)+ASM_PFX(CallPeiCoreEntryPoint):+ ;+ ; Per X64 calling conv= ention, make sure RSP is 16-byte aligned.+ ;+ mov rax, rsp+ and = rax, 0fh+ sub rsp, rax++ ;+ ; Platform init+ ;+ PUSHA_64+ sub = rsp, 20h+ call ASM_PFX(PlatformInit)+ add rsp, 20h+ POPA_64++ ;= + ; Set stack top pointer+ ;+ mov rsp, r8++ ;+ ; Push the hob list= pointer+ ;+ push rcx++ ;+ ; RBP holds start of BFV passed from Vtf0= . Save it to r10.+ ;+ mov r10, rbp++ ;+ ; Save the value+ ; RDX:= start of range+ ; r8: end of range+ ;+ mov rbp, rsp+ push rdx= + push r8+ mov r14, rdx+ mov r15, r8++ ;+ ; Push processor = count to stack first, then BIST status (AP then BSP)+ ;+ mov eax, 1+ = cpuid+ shr ebx, 16+ and ebx, 0000000FFh+ cmp bl, 1+ jae = PushProcessorCount++ ;+ ; Some processors report 0 logical processors. = Effectively 0 =3D 1.+ ; So we fix up the processor count+ ;+ inc eb= x++PushProcessorCount:+ sub rsp, 4+ mov rdi, rsp+ mov DWORD = [rdi], ebx++ ;+ ; We need to implement a long-term solution for BIST capt= ure. For now, we just copy BSP BIST+ ; for all processor threads+ ;+ xo= r ecx, ecx+ mov cl, bl+PushBist:+ sub rsp, 4+ mov rdi, r= sp+ movd eax, mm0+ mov DWORD [rdi], eax+ loop PushBist++ ; Sa= ve Time-Stamp Counter+ LOAD_TS rax+ push rax++ ;+ ; Per X64 calling = convention, make sure RSP is 16-byte aligned.+ ;+ mov rax, rsp+ and = rax, 0fh+ sub rsp, rax++ ;+ ; Pass entry point of the PEI core+ = ;+ mov rdi, 0FFFFFFE0h+ mov edi, DWORD [rdi]+ mov r9, rdi++= ;+ ; Pass BFV into the PEI Core+ ;+ ; Reset Vector and initial SEC cor= e (to initialize Temp Ram) is part of FSP-O.+ ; Default UefiCpuPkg Reset V= ector locates FSP-O as BFV. However the actual+ ; SEC core that launches P= EI is part of another FV. We need to pass that FV+ ; as BFV to PEI core.+ = ;+ mov r8, ASM_PFX (PcdGet64 (PcdFspWrapperBfvforResetVectorInFsp))+ = mov rcx, QWORD[r8]+ mov r8, rcx++ ;+ ; Pass stack size into th= e PEI Core+ ;+ mov rcx, r15 ; Start of TempRam+ mov rdx, r14 ;= End of TempRam++ sub rcx, rdx ; Size of TempRam++ ;+ ; Pass Contro= l into the PEI Core+ ;+ sub rsp, 20h+ call ASM_PFX(SecStartup)+di= ff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPl= atformSecLib/X64/SecEntry.nasm b/Platform/Intel/MinPlatformPkg/FspWrapper/L= ibrary/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm new file mode 100644 index 0000000000..0ee3b25ff7 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat +++ formSecLib/X64/SecEntry.nasm @@ -0,0 +1,71 @@ +;-------------------------------------------------------------------------= -----+;+; Copyright (c) 2023, Intel Corporation. All rights reserved.
+;= SPDX-License-Identifier: BSD-2-Clause-Patent+; Module Name:+;+; SecEntry.= nasm+;+; Abstract:+;+; This is the code that passes control to PEI core.+;= +;-------------------------------------------------------------------------= -----++#include ++SECTION .text++extern ASM_PFX(CallPeiCoreEntryPo= int)+extern ASM_PFX(FsptUpdDataPtr)+; Pcds+extern ASM_PFX(PcdGet32 (Pcd= FspTemporaryRamSize))++;---------------------------------------------------= -------------------------+;+; Procedure: _ModuleEntryPoint+;+; Input: = None+;+; Output: None+;+; Destroys: Assume all registers+;+;= Description:+;+; After TempRamInit done, pass control to PEI core.+;+; Re= turn: None+;+; MMX Usage:+; MM0 =3D BIST State+;+;-----= -----------------------------------------------------------------------++BI= TS 64+align 16+global ASM_PFX(_ModuleEntryPoint)+ASM_PFX(_ModuleEntryPoint)= :+ push rax+ mov rax, ASM_PFX(FsptUpdDataPtr) ; This is dummy cod= e to include TempRamInitParams in SecCore for FSP-O.+#if FixedPcdGet8(PcdFs= pModeSelection) =3D=3D 1+ mov rax, ASM_PFX(PcdGet32 (PcdFspTemporaryRa= mSize))+ sub edx, dword [rax] ; TemporaryRam for FSP+#end= if+ pop rax++ mov r8, rdx+ mov rdx, rcx+ xor ecx, ecx = ; zero - no Hob List Yet+ mov rsp, r8++ ;+ ; Pe= r X64 calling convention, make sure RSP is 16-byte aligned.+ ;+ mov r= ax, rsp+ and rax, 0fh+ sub rsp, rax++ call ASM_PFX(CallPeiCor= eEntryPoint)++ jmp $diff --git a/Platform/Intel/MinPlatformPkg/FspWrap= per/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm b/Platform/Intel/Min= PlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/X64/Stack.nasm new file mode 100644 index 0000000000..d7ae97c5da --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat +++ formSecLib/X64/Stack.nasm @@ -0,0 +1,72 @@ +;-------------------------------------------------------------------------= -----+;+; Copyright (c) 2023, Intel Corporation. All rights reserved.
+;= SPDX-License-Identifier: BSD-2-Clause-Patent+; Abstract:+;+; Switch the = stack from temporary memory to permanent memory.+;+;-----------------------= -------------------------------------------------------++ SECTION .text+= +;-------------------------------------------------------------------------= -----+; VOID+; EFIAPI+; SecSwitchStack (+; UINT32 TemporaryMemoryBase,+= ; UINT32 PermanentMemoryBase+; );+;----------------------------------= --------------------------------------------+global ASM_PFX(SecSwitchStack)= +ASM_PFX(SecSwitchStack):+ ;+ ; Save four register: rax, rbx, rcx, rd= x+ ;+ push rax+ push rbx+ push rcx+ push rdx++ ;+ = ; !!CAUTION!! this function address's is pushed into stack after+ ; migr= ation of whole temporary memory, so need save it to permanent+ ; memory = at first!+ ;++ mov rbx, rcx ; Save the first parame= ter+ mov rcx, rdx ; Save the second parameter++ ;+ = ; Save this function's return address into permanent memory at first.+ = ; Then, Fixup the esp point to permanent memory+ ;+ mov rax, rsp+= sub rax, rbx+ add rax, rcx+ mov rdx, qword [rsp] ; = copy pushed register's value to permanent memory+ mov qword [rax], rdx= + mov rdx, qword [rsp + 8]+ mov qword [rax + 8], rdx+ mov rd= x, qword [rsp + 16]+ mov qword [rax + 16], rdx+ mov rdx, qword [r= sp + 24]+ mov qword [rax + 24], rdx+ mov rdx, qword [rsp + 32] = ; Update this function's return address into permanent memory+ mov qw= ord [rax + 32], rdx+ mov rsp, rax ; From now, rsp is p= ointed to permanent memory++ ;+ ; Fixup the rbp point to permanent me= mory+ ;+ mov rax, rbp+ sub rax, rbx+ add rax, rcx+ mov= rbp, rax ; From now, rbp is pointed to permanent memory+= + pop rdx+ pop rcx+ pop rbx+ pop rax+ ret+diff --git= a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSe= cLib/Ia32/Fsp.h b/Platform/Intel/MinPlatformPkg/Include/Fsp.h similarity index 86% rename from Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperP= latformSecLib/Ia32/Fsp.h rename to Platform/Intel/MinPlatformPkg/Include/Fsp.h index 9f6cdcf476..1b86912583 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/Ia32/Fsp.h +++ b/Platform/Intel/MinPlatformPkg/Include/Fsp.h @@ -36,7 +36,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // // Fsp Header //-#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C-#define F= SP_HEADER_TEMPRAMINIT_OFFSET 0x30+#define FSP_HEADER_IMAGEBASE_OFFSET 0= x1C+#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30 #endifdiff --git a/Platform= /Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/Intel/MinPlatformPkg/Mi= nPlatformPkg.dec index a14c6b2db5..3d60d4bbc2 100644 --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec @@ -393,6 +393,21 @@ # gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE|B= OOLEAN|0xF00000A8 + ## BFV Location for Reset Vector in FSP+ # The defaul= t of BFV Location for Reset Vector in FSP is 0x00000000FFFF0000.+ #+ gMin= PlatformPkgTokenSpaceGuid.PcdFspWrapperBfvforResetVectorInFsp|0x00000000FFF= F0000|UINT64|0xF00000A9++ ## FSP-T UPD Header Revision+ # The default of = FSP-T UPD Header Revision is 0.+ #+ gMinPlatformPkgTokenSpaceGuid.PcdFspt= UpdHeaderRevision|0x0|UINT8|0xF00000AA++ ## FSP-T ARCH UPD Revision+ # Th= e default of FSP-T ARCH UPD Revision is 0.+ #+ gMinPlatformPkgTokenSpaceG= uid.PcdFsptArchUpdRevision|0x0|UINT8|0xF00000AC+ [PcdsFeatureFlag] gMinP= latformPkgTokenSpaceGuid.PcdStopAfterDebugInit |FALSE|BOOLEAN|0xF00000A= 1--=20 2.40.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112807): https://edk2.groups.io/g/devel/message/112807 Mute This Topic: https://groups.io/mt/103298183/1862468 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [ted.kuo@intel.com] -=3D-= =3D-=3D-=3D-=3D-=3D -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112845): https://edk2.groups.io/g/devel/message/112845 Mute This Topic: https://groups.io/mt/103298183/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-