From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id BDC9374003D for ; Thu, 21 Dec 2023 10:49:54 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=yuQhRFqd3FgBfvyAx8KiIx/nZf96/U5obuUhLKsPNvE=; c=relaxed/simple; d=groups.io; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:From:To:CC:Subject:Thread-Topic:Thread-Index:Date:Message-ID:References:In-Reply-To:Accept-Language:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1703155793; v=1; b=ZIy8RjNTB4bfsD3PX2maUsQst2qgATwtI1KPQfYwnS8C5FO58jmx/vRRwtVse3rAgQ9KvfBj qxVTC2BdAMYcvAfyeW6XJg62NXvPMk02dRm/e7nRDwh7rZPZZCenaarOoRd4BrwBPJRKY2FggDx mwmP7G41yP1yTA/0l4HrmNxM= X-Received: by 127.0.0.2 with SMTP id dYnsYY7687511xe7hNQt57eV; Thu, 21 Dec 2023 02:49:53 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) by mx.groups.io with SMTP id smtpd.web11.48582.1703155792770671262 for ; Thu, 21 Dec 2023 02:49:52 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="3190811" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="3190811" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 02:49:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10930"; a="769901472" X-IronPort-AV: E=Sophos;i="6.04,293,1695711600"; d="scan'208";a="769901472" X-Received: from fmsmsx601.amr.corp.intel.com ([10.18.126.81]) by orsmga007.jf.intel.com with ESMTP/TLS/AES256-GCM-SHA384; 21 Dec 2023 02:49:51 -0800 X-Received: from fmsmsx610.amr.corp.intel.com (10.18.126.90) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 21 Dec 2023 02:49:51 -0800 X-Received: from fmsmsx611.amr.corp.intel.com (10.18.126.91) by fmsmsx610.amr.corp.intel.com (10.18.126.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 21 Dec 2023 02:49:51 -0800 X-Received: from FMSEDG603.ED.cps.intel.com (10.1.192.133) by fmsmsx611.amr.corp.intel.com (10.18.126.91) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35 via Frontend Transport; Thu, 21 Dec 2023 02:49:51 -0800 X-Received: from NAM12-MW2-obe.outbound.protection.outlook.com (104.47.66.40) by edgegateway.intel.com (192.55.55.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Thu, 21 Dec 2023 02:49:50 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=KWx0iBqCe0U36keuHdF2TqA4LrB66chjj1NPkFbsVj7JBEjKjOq5a7+gx0xKueJ9iOdyXqY1QhgFf0mSNlFPqRqyS91OrcrxwhaMr8l4m+8kML4t31jbmYf/8TNtfMPw5I80yJhvVmo7J5qEGbBgdoHSTLuQtvpMVWtuX+U7VnezUEY8Q4Qp+UYaQj+PCOSNtncJE/oj+Bd2oOEmrTBSQzgbnhdkgyABDma0lyvJ7gtlZUoDM0wnHEgKjaPRakMJ8vAgiqLv22O0KRWPnJdGY7DK9ztldCm5lnI2Uq/faRg3djT6X0kRWy0WZb3rFx28OJEbeBIgFkRk9pIPhwVnjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=fzcu7UMV3puv+tMVd//rO3k6y84ffdSYeOfoBxFtRVY=; b=jeZjXt0fI0J/ZSZt+FB2FYT3XsiSr4WOa8ZwTZGw5UHXAAxs0gfTQQDbsddcXQwb28K75a7/coxB1aGT+eKSPW8vRjLCzGf9NrsDQ8zqRD9Fc82DqebJfVPYE0CUPr98HGgY6UaMauCtTGZoLBO9baA+Gbah7J7uoq6Ku5W773QMuE94Zaxbculd9B8P0xZEMOdhkiHLVSXEejI+3r2yMhzwVKKDKlyknUPKPRMGcLXLMxa/z82ziQ+czSQKMyP5bFewRDut1o16/M6nJ7J7jn4gu0/zFhwgdKsWyg9497E1N16Vvw5S8ltRs6Cd0klPC9XFL0Tkif4r/Y5WtTjo6g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none X-Received: from PH7PR11MB7499.namprd11.prod.outlook.com (2603:10b6:510:278::12) by DS0PR11MB6325.namprd11.prod.outlook.com (2603:10b6:8:cf::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7113.18; Thu, 21 Dec 2023 10:49:47 +0000 X-Received: from PH7PR11MB7499.namprd11.prod.outlook.com ([fe80::8496:1b27:4e19:1228]) by PH7PR11MB7499.namprd11.prod.outlook.com ([fe80::8496:1b27:4e19:1228%6]) with mapi id 15.20.7091.034; Thu, 21 Dec 2023 10:49:47 +0000 From: "Kuo, Ted" To: "Desimone, Nathaniel L" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" , "Chiu, Chasel" , "Dong, Eric" , "S, Ashraf Ali" , "Duggapu, Chinni B" , "Gao, Liming" Subject: Re: [edk2-devel][edk2-platforms][PATCH v1] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64 Thread-Topic: [edk2-devel][edk2-platforms][PATCH v1] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64 Thread-Index: AQHaM6JkX1ZVgqjdj0aypyR8d20xLLCzjz5w Date: Thu, 21 Dec 2023 10:49:47 +0000 Message-ID: References: <4b738d12c89b75385473339b2da9b3ee76425d44.1702871727.git.ted.kuo@intel.com> In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PH7PR11MB7499:EE_|DS0PR11MB6325:EE_ x-ms-office365-filtering-correlation-id: 5a922136-7bbc-4dbc-b2d7-08dc02128cc4 x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam-message-info: eIjnCQUC1Tzdo30WammuHGyYQbolmnyxNT29FVwZBfJtTudyrMN/sSJdEFzDDaKFuit3Vhz3oqMUk7x96whDSIIBjxjxMzTkbTxdLKAT/O/ZGXJXMgWqTC7epvy4rDQXGuzzozkNxZHSnLQDV+ZPurcCPAB/zdmXEflVLqRVQEJqpBVBLmXlMtdYrVO5jkY7hv8WHV6nRBkaP5KE+PfFffvYflQPtpfvnFMWkJaL6xkxnUF01xf8SWjBe/wLpuapXiCGFU3lcOOIl7ZbCrxh4239zZ81gsh/w9roswsaWHo4ZcLQ2OzlOPaE6AxGxarQAGFe0DypiK3L+a5e/GMm3QdAeJOkYHAO+CKT7iauOXtHDUAtOPrxxB9/qHegXjGA98kI5ffLmdVdZAc6wjJWYL8hXpO7z2KKaK7x40we7dD9baY3SvySxyVQ1aQI/Kxq3pox+rDSVu2oQ1GXshYR0ANZkmLp36aEkXcC++WDvr8UxvtoOXPiWl2kcv13xWnv7Cub4Qu0MR2Vl7HMFI3fh3zz6ZUWIaIlAGrsidrDoSeEUj41Pl/3ZARHNCBEv0vyI/9rN3ywKwH0r/8WEOMephzMc1nbOAvnJWbcBCnuFFjIkHnUL9MBnmzhlm+h9TW2nbKvFspYHsS9sayVxBgomyBi1nPJOL8w66JnOiJE8Nna7MGoK3v8OO0mrPVnbuH8RD1KbXkLP6ju3k8CenOMbRuax6DIyTlMSqWO7va1NzE= x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?RltXmhMgv5pKdHd9Ir2mNPkH4pcXfBTm2qFUOMD/wt8q8g/IEdnzEAjWLbdC?= =?us-ascii?Q?w12yZLQDBS05XsA/KfN7llYB+jFqfuZpHl6tj2ZM+xi5aFKxQATiwoZgun3t?= =?us-ascii?Q?datVdz36yDKpJiCMvhSahAimYaHc4gTU1vV0fYZMyK39NCpIfvls3BXG3LEC?= =?us-ascii?Q?C/eGVeKK4eZCKghwOIXL/hnBFuVqTUeGq8ZGueTgMNWXKL+J/i180ePiBt08?= =?us-ascii?Q?gH5rpF8NjU5FL/eabPt99AcncorUjuuDfqYzWOF6E4O+vNqNyDljB1kBM7+3?= =?us-ascii?Q?mFtqMb6L4V3n05RY1JZVFTkpVj0yUa6oEC3uPikpQsW+jz8voSL3apmQ/lVy?= =?us-ascii?Q?zckHATE1nfU887ewlj9M29rT3FnAtolBtOY3jl6LnA25in+Qvl4c2c2PnJ1r?= =?us-ascii?Q?7Cu5OiBSSeD7b5ZK69FoxB9Ban565Q1xzOboZkVg+GD9nuKAm2LMBJnpYQCp?= =?us-ascii?Q?zOCl6/9fWpYMFNI36G/LcDHwCiJYlTox1yc8zYxlnBjWCUVHkWACd2eVMdSj?= =?us-ascii?Q?4+EioU14r9ADDXiFOC72A+4ixLAl3u0MWqVHTxggkvYKv2/PXc82FFbcmtlG?= =?us-ascii?Q?I0PZP8/Lz7eS9O5Pq+5f0HhwEh8O7dgeu3B5y+2Sa/UEy6ZpfayUoOyQoCvU?= =?us-ascii?Q?waFeN5Kpu3KVuapbfJHgnn1hSovXRYcfeH1DY2F7uptTuYb0ebPRf0nxAuGK?= =?us-ascii?Q?m2zNZXRUhFkvsdL0HWm7+z+fWmiKc/DhxW2oISjjXDHOYoLxO1twLFX/Y0dt?= =?us-ascii?Q?pxYWCjsv+xw3nMc+4Aw/ifC6TICGzEfZiGYRzGRQVH4saFmr1gBY3ZSxxvqY?= =?us-ascii?Q?uaqo1mvdG2J6p7kPOWb1FVUkS9wqF6er8bN3jRQtJu3ki5IqHDKtXE5JuSQE?= =?us-ascii?Q?7G1O8fILPkJiomh6Rtrx5B62kBVjpEbPgl/SU60Gua/45U7qhDKACq7Kfzqv?= =?us-ascii?Q?JviYRQRNl2Y3ZQ4IpSR3SsYFEDBSlkV8wWknfV1KW7RmJGxG2MFCxtpOTSUu?= =?us-ascii?Q?paB38lObbUyax/eqeeMo3NYUOHqRk4RXMFctNfiSfKO2zQUJasoRSvnO3jFI?= =?us-ascii?Q?cJZ5kTzb1aH5yZniPbeYjk+NG6xSxji7Y0kOb4mEiKPQlkG5FDjM5NpYyBV+?= =?us-ascii?Q?z8ZfM57SYS1SRLGBFlVH76MKQ1n2xbSCWNa9Yg3kMT/Lt/k1OrdiJLA94TKP?= =?us-ascii?Q?nTf/aTZvJ5aHKPTIGcMUhJzOd1aYYLDJS4lA3U2BNg9koi4QNTuCY4187sIo?= =?us-ascii?Q?H75OEY7g6806j3ekw89oKn+U09LrU+uWth4N1moM04glJhbm7gJomP/u8jtu?= =?us-ascii?Q?JQKiTWiNzONsd9GXtEG4nPiWfaphG904+IB0oInS3k3YI3JKITf+xu0Ch871?= =?us-ascii?Q?G5bK0yV4KY/afWth3fUmLJf7M7cAEyEDI/pS85Wnr6xGiChEwMWwZBAaGf4e?= =?us-ascii?Q?Bo45QYq+7tgvR3N5+QGdEBOz7KNqeqNhbTHeMQhFQIVhjqBYl/pl5MO7TCNm?= =?us-ascii?Q?G4YWbLU+KbJDQ6Qxvw8KLoxz21vkdqrCl/wegr8aHu8Q5tGudhSAJ0S+fa8w?= =?us-ascii?Q?Pu6XduBd9Oz1ThemtUI=3D?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH7PR11MB7499.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5a922136-7bbc-4dbc-b2d7-08dc02128cc4 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Dec 2023 10:49:47.4039 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: kdkxc9SNXJjIw3FLjPF4hOBpO7vH9OqfgllT2CgmNd9MmB5nIUfKTH1m1Sbidsr8+greI4Ocokt0kYZbRtxX4g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR11MB6325 X-OriginatorOrg: intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ted.kuo@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: Y2hE6Qoa1P5HB9jGUA27X9SWx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=ZIy8RjNT; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") Thanks Nate for the feedback. I've sent out patch v2 according to your comm= ents. Can you please review again? Thanks, Ted -----Original Message----- From: Desimone, Nathaniel L =20 Sent: Thursday, December 21, 2023 8:13 AM To: Kuo, Ted ; devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Chiu, Chasel ; Dong, Eric ; S, Ashraf Ali ; Duggapu, Chinni B ; Gao, Li= ming Subject: RE: [edk2-devel][edk2-platforms][PATCH v1] MinPlatformPkg: Support= SecFspWrapperPlatformSecLib in X64 Hi Ted, Looking at this code, the X64 version will only work if PcdFspWrapperResetV= ectorInFsp =3D=3D TRUE. Moreover, the IA32 version will only work if PcdFsp= WrapperResetVectorInFsp =3D=3D FALSE. So... what is the point of having a P= CD if the PCD must always be set to one value or the other? Please choose o= ne of these options: Option 1: Make the PCD work correctly for all the 4 cases: - IA32 + Bootloader Reset Vector - IA32 + FSP Reset Vector - X64 + Bootloader Reset Vector - X64 + FSP Reset Vector Option 2: Make a separate instance of PlatformSecLib for the case of FSP-O = providing the reset vector. Additional feedback is below inline. Thanks, Nate > -----Original Message----- > From: Kuo, Ted > Sent: Sunday, December 17, 2023 8:03 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V ; Chiu, Chasel=20 > ; Desimone, Nathaniel L=20 > ; Dong, Eric ; S,=20 > Ashraf Ali ; Duggapu, Chinni B=20 > ; Gao, Liming > Subject: [edk2-devel][edk2-platforms][PATCH v1] MinPlatformPkg:=20 > Support SecFspWrapperPlatformSecLib in X64 >=20 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D4623 > 1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64. > 2.Made changes in common file to support both IA32 and X64. > 3.Added the PCDs below for FSP-T UPD revsions and X64 feature. > - PcdFspWrapperResetVectorInFsp > - PcdFspWrapperBfvforResetVectorInFsp > - PcdFsptUpdHeaderRevision > - PcdFsptArchUpdHeaderRevision >=20 > Cc: Sai Chaganty > Cc: Chasel Chiu > Cc: Nate DeSimone > Cc: Eric Dong > Cc: Ashraf Ali S > Cc: Chinni B Duggapu > Cc: Liming Gao > Signed-off-by: Ted Kuo > --- > .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 +- > .../Ia32/SecEntry.nasm | 4 +- > .../SecFspWrapperPlatformSecLib.inf | 12 +- > .../SecGetPerformance.c | 11 +- > .../SecPlatformInformation.c | 8 +- > .../SecRamInitData.c | 56 ++++- > .../X64/PeiCoreEntry.nasm | 224 ++++++++++++++++++ > .../X64/SecEntry.nasm | 214 +++++++++++++++++ > .../X64/Stack.nasm | 72 ++++++ > .../Ia32 =3D> Include}/Fsp.h | 4 +- > .../Intel/MinPlatformPkg/MinPlatformPkg.dec | 21 ++ > 11 files changed, 629 insertions(+), 22 deletions(-) create mode=20 > 100644=20 > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatform > SecLib/X64/PeiCoreEntry.nasm create mode 100644=20 > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatform > SecLib/X64/SecEntry.nasm create mode 100644=20 > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatform > SecLib/X64/Stack.nasm rename=20 > Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlatfor > mSecLib/Ia32 =3D> Include}/Fsp.h (86%) >=20 > diff --git=20 > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/FsptCoreUpd.h=20 > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/FsptCoreUpd.h > index 7c0f605b92..7c4ddc09a8 100644 > ---=20 > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/FsptCoreUpd.h > +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPl > +++ atformSecLib/FsptCoreUpd.h > @@ -1,6 +1,6 @@ > /** @file > =20 > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2017 - 2023, Intel Corporation. All rights=20 > +reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent > =20 > **/ > @@ -10,6 +10,28 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > =20 > #pragma pack(1) > =20 > +#if defined (MDE_CPU_X64) > +/** Fsp T Core UPD > +**/ > +typedef struct { > + > +/** Offset 0x0040 > +**/ > + EFI_PHYSICAL_ADDRESS MicrocodeRegionBase; > + > +/** Offset 0x0048 > +**/ > + UINT64 MicrocodeRegionSize; > + > +/** Offset 0x0050 > +**/ > + EFI_PHYSICAL_ADDRESS CodeRegionBase; > + > +/** Offset 0x0058 > +**/ > + UINT64 CodeRegionSize; > +} FSPT_CORE_UPD; > +#else > /** Fsp T Core UPD > **/ > typedef struct { > @@ -34,6 +56,7 @@ typedef struct { > **/ > UINT8 Reserved[16]; > } FSPT_CORE_UPD; > +#endif > =20 > #pragma pack() > =20 > diff --git=20 > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/Ia32/SecEntry.nasm=20 > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/Ia32/SecEntry.nasm > index 7f6d771e41..de44066a20 100644 > ---=20 > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/Ia32/SecEntry.nasm > +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPl > +++ atformSecLib/Ia32/SecEntry.nasm > @@ -1,6 +1,6 @@ > =20 > ;--------------------------------------------------------------------- > --------- > ; > -; Copyright (c) 2019, Intel Corporation. All rights reserved.
> +; Copyright (c) 2019 - 2023, Intel Corporation. All rights=20 > +reserved.
> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; Module Name: > ; > @@ -13,7 +13,7 @@ > ; > =20 > ;--------------------------------------------------------------------- > --------- > =20 > -#include "Fsp.h" > +#include > =20 > SECTION .text > =20 > diff --git=20 > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/SecFspWrapperPlatformSecLib.inf=20 > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/SecFspWrapperPlatformSecLib.inf > index 2e0d67eae4..99a04cc264 100644 > ---=20 > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/SecFspWrapperPlatformSecLib.inf > +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPl > +++ atformSecLib/SecFspWrapperPlatformSecLib.inf > @@ -1,7 +1,7 @@ > ## @file > # Provide FSP wrapper platform sec related function. > # > -# Copyright (c) 2017 - 2021, Intel Corporation. All rights=20 > reserved.
> +# Copyright (c) 2017 - 2023, Intel Corporation. All rights=20 > +reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -47,7 +47,11 @@ > Ia32/SecEntry.nasm > Ia32/PeiCoreEntry.nasm > Ia32/Stack.nasm > - Ia32/Fsp.h > + > +[Sources.X64] > + X64/SecEntry.nasm > + X64/PeiCoreEntry.nasm > + X64/Stack.nasm > =20 > =20 > ###################################################################### > ########## > # > @@ -96,3 +100,7 @@ > gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ##= CONSUMES > gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ##= CONSUMES > gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ##= CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperResetVectorInFsp ##= CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBfvforResetVectorInFsp ##= CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevision ##= CONSUMES > + gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpdHeaderRevision ##= CONSUMES > diff --git=20 > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/SecGetPerformance.c=20 > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/SecGetPerformance.c > index ac2deeabec..471e9e86a2 100644 > ---=20 > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/SecGetPerformance.c > +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPl > +++ atformSecLib/SecGetPerformance.c > @@ -1,7 +1,7 @@ > /** @file > Sample to provide SecGetPerformance function. > =20 > -Copyright (c) 2017 - 2019, Intel Corporation. All rights=20 > reserved.
> +Copyright (c) 2017 - 2023, Intel Corporation. All rights=20 > +reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent > =20 > **/ > @@ -58,6 +58,7 @@ SecGetPerformance ( > if (EFI_ERROR (Status)) { > return EFI_NOT_FOUND; > } > + > // > // |--------------| <- TopOfTemporaryRam - BL > // | List Ptr | > @@ -77,12 +78,12 @@ SecGetPerformance ( > // | TSC[31:00] | > // |--------------| > // > - TopOfTemporaryRam =3D (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32); > - TopOfTemporaryRam -=3D sizeof (UINT32) * 2; > - Count =3D *(UINT32 *)(TopOfTemporaryRam - sizeof (UINT32))= ; > + TopOfTemporaryRam =3D (UINT32)(UINTN)TopOfTemporaryRamPpi -=20 > + sizeof(UINTN); Why the cast from UINTN to UINT32? This will truncate the value and cause t= he code to break if we map the reset vector to > 4 GB. > + TopOfTemporaryRam -=3D sizeof(UINTN) * 2; > + Count =3D *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof = (UINT32)); > Size =3D Count * sizeof (UINT32); > =20 > - Ticker =3D *(UINT64 *) (TopOfTemporaryRam - sizeof (UINT32) - Size -= =20 > sizeof (UINT32) * 2); > + Ticker =3D *(UINT64 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32) -= =20 > + Size - sizeof (UINT32) * 2); Any reason for using sizeof (UINT32) * 2 instead of sizeof(UINT64)? To me i= t seems somewhat obvious that a TSC value would be 64-bit size even though = EDX:EAX are used to return it. Ticker =3D *(UINT64 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32) - Size = - sizeof (UINT64)); > Performance->ResetEnd =3D GetTimeInNanoSecond (Ticker); > =20 > return EFI_SUCCESS; > diff --git=20 > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/SecPlatformInformation.c=20 > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/SecPlatformInformation.c > index 24d55ed838..68b3fa14c0 100644 > ---=20 > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/SecPlatformInformation.c > +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPl > +++ atformSecLib/SecPlatformInformation.c > @@ -1,7 +1,7 @@ > /** @file > Provide SecPlatformInformation function. > =20 > -Copyright (c) 2017 - 2019, Intel Corporation. All rights=20 > reserved.
> +Copyright (c) 2017 - 2023, Intel Corporation. All rights=20 > +reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent > =20 > **/ > @@ -59,9 +59,9 @@ SecPlatformInformation ( > // This routine copies the BIST information to the buffer pointed by > // PlatformInformationRecord for output. > // > - TopOfTemporaryRam =3D (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32); > - TopOfTemporaryRam -=3D sizeof (UINT32) * 2; > - Count =3D *((UINT32 *)(TopOfTemporaryRam - sizeof (UINT32)= )); > + TopOfTemporaryRam =3D (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof=20 > + (UINTN); Why the cast from UINTN to UINT32? This will truncate the value and cause t= he code to break if we map the reset vector to > 4 GB. > + TopOfTemporaryRam -=3D sizeof(UINTN) * 2; > + Count =3D *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof = (UINT32))); > Size =3D Count * sizeof (IA32_HANDOFF_STATUS); > =20 > if ((*StructureSize) < (UINT64) Size) { diff --git=20 > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/SecRamInitData.c=20 > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/SecRamInitData.c > index 355d1e6509..928049f13b 100644 > ---=20 > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/SecRamInitData.c > +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPl > +++ atformSecLib/SecRamInitData.c > @@ -1,7 +1,7 @@ > /** @file > Provide TempRamInitParams data. > =20 > -Copyright (c) 2017 - 2021, Intel Corporation. All rights=20 > reserved.
> +Copyright (c) 2017 - 2023, Intel Corporation. All rights=20 > +reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent > =20 > **/ > @@ -12,17 +12,59 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > =20 > typedef struct { > FSP_UPD_HEADER FspUpdHeader; > +#if FixedPcdGet8 (PcdFsptArchUpdHeaderRevision) =3D=3D 1 > + FSPT_ARCH_UPD FsptArchUpd; > +#elif FixedPcdGet8 (PcdFsptArchUpdHeaderRevision) =3D=3D 2 > + FSPT_ARCH2_UPD FsptArchUpd; > +#endif > FSPT_CORE_UPD FsptCoreUpd; > -} FSPT_UPD_CORE_DATA; > + UINT16 UpdTerminator; > +} FSPT_UPD_DATA; > =20 > -GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA FsptUpdDataPtr=20 > =3D { > +GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_DATA FsptUpdDataPtr =3D { Please add comments to all the FsptUpdDataPtr initial values below so it is= clear which field is being initialized to which value. > { > 0x4450555F54505346, > - 0x00, > + FixedPcdGet8 (PcdFsptUpdHeaderRevision), > { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00 > } > }, > +#if FixedPcdGet8 (PcdFsptArchUpdHeaderRevision) =3D=3D 1 > + { > + 0x01, > + { > + 0x00, 0x00, 0x00 > + }, > + 0x00000020, > + 0, > + { > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 > + } > + }, > +#elif FixedPcdGet8 (PcdFsptArchUpdHeaderRevision) =3D=3D 2 > + { > + 0x02, > + { > + 0x00, 0x00, 0x00 > + }, > + 0x00000020, > + 0, > + { > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 > + } > + }, > +#endif > +#if defined (MDE_CPU_X64) > + { > + FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocod= eOffsetInFv), > + FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocod= eOffsetInFv), > + 0, // Set CodeRegionBase as 0, so that caching will be 4GB-= (CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used. > + FixedPcdGet32 (PcdFlashCodeCacheSize) > + }, > +#else > { > FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocod= eOffsetInFv), > FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32=20 > (PcdMicrocodeOffsetInFv), @@ -31,6 +73,8 @@ GLOBAL_REMOVE_IF_UNREFERENCED= CONST FSPT_UPD_CORE_DATA FsptUpdDataPtr =3D { > { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 > } > - } > + }, > +#endif > + 0x55AA > }; > =20 > diff --git=20 > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/X64/PeiCoreEntry.nasm=20 > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/X64/PeiCoreEntry.nasm > new file mode 100644 > index 0000000000..c69c3b1116 > --- /dev/null > +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPl > +++ atformSecLib/X64/PeiCoreEntry.nasm > @@ -0,0 +1,224 @@ > +;-------------------------------------------------------------------- > +---------- > +; > +; Copyright (c) 2023, Intel Corporation. All rights reserved.
;=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: > +; > +; PeiCoreEntry.nasm > +; > +; Abstract: > +; > +; Find and call SecStartup > +; > +;-------------------------------------------------------------------- > +---------- > + > +SECTION .text > + > +extern ASM_PFX(SecStartup) > +extern ASM_PFX(PlatformInit) > +extern ASM_PFX(PcdGet32 (PcdFspWrapperBfvforResetVectorInFsp)) > + > +;-----------------------------------------------------------------------= ------ > +; Macro: PUSHA_64 > +; > +; Description: Saves all registers on stack ; > +; Input: None > +; > +; Output: None > +;-----------------------------------------------------------------------= ------ > +%macro PUSHA_64 0 > + push r8 > + push r9 > + push r10 > + push r11 > + push r12 > + push r13 > + push r14 > + push r15 > + push rax > + push rcx > + push rdx > + push rbx > + push rsp > + push rbp > + push rsi > + push rdi > +%endmacro > + > +;-----------------------------------------------------------------------= ------ > +; Macro: POPA_64 > +; > +; Description: Restores all registers from stack ; > +; Input: None > +; > +; Output: None > +;-----------------------------------------------------------------------= ------ > +%macro POPA_64 0 > + pop rdi > + pop rsi > + pop rbp > + pop rsp > + pop rbx > + pop rdx > + pop rcx > + pop rax > + pop r15 > + pop r14 > + pop r13 > + pop r12 > + pop r11 > + pop r10 > + pop r9 > + pop r8 > +%endmacro > + > +; > +; args 1:XMM, 2:REG, 3:IDX > +; > +%macro LXMMN 3 > + pextrq %2, %1, (%3 & 3) > + %endmacro Why are some do some of these macro definitions have %endmacro at the same = indent as %macro and some of them have it indented? Please do it the same w= ay for all the macro definitions in the file. > + > +; > +; args 1:YMM, 2:XMM, 3:IDX (0 - lower 128bits, 1 - upper 128bits) ; > +%macro LYMMN 3 > + vextractf128 %2, %1, %3 > + %endmacro > + > +%macro LOAD_TS 1 > + LYMMN ymm6, xmm5, 1 > + LXMMN xmm5, %1, 1 > + %endmacro > + > +global ASM_PFX(CallPeiCoreEntryPoint) > +ASM_PFX(CallPeiCoreEntryPoint): > + ; > + ; Per X64 calling convention, make sure RSP is 16-byte aligned. > + ; > + mov rax, rsp > + and rax, 0fh > + sub rsp, rax > + > + ; > + ; Platform init > + ; > + PUSHA_64 > + sub rsp, 20h > + call ASM_PFX(PlatformInit) > + add rsp, 20h > + POPA_64 > + > + ; > + ; Set stack top pointer > + ; > + mov rsp, r8 > + > + ; > + ; Push the hob list pointer > + ; > + push rcx > + > + ; > + ; RBP holds start of BFV passed from Vtf0. Save it to r10. > + ; > + mov r10, rbp > + > + ; > + ; Save the value > + ; RDX: start of range > + ; r8: end of range > + ; > + mov rbp, rsp > + push rdx > + push r8 > + mov r14, rdx > + mov r15, r8 > + > + ; > + ; Push processor count to stack first, then BIST status (AP then=20 > + BSP) ; > + mov eax, 1 > + cpuid > + shr ebx, 16 > + and ebx, 0000000FFh > + cmp bl, 1 > + jae PushProcessorCount > + > + ; > + ; Some processors report 0 logical processors. Effectively 0 =3D 1. > + ; So we fix up the processor count > + ; > + inc ebx > + > +PushProcessorCount: > + sub rsp, 4 > + mov rdi, rsp > + mov DWORD [rdi], ebx > + > + ; > + ; We need to implement a long-term solution for BIST capture. For=20 > +now, we just copy BSP BIST > + ; for all processor threads > + ; > + xor ecx, ecx > + mov cl, bl > +PushBist: > + sub rsp, 4 > + mov rdi, rsp > + movd eax, mm0 > + mov DWORD [rdi], eax > + loop PushBist > + > + ; Save Time-Stamp Counter > + LOAD_TS rax > + push rax > + > + ; > + ; Per X64 calling convention, make sure RSP is 16-byte aligned. > + ; > + mov rax, rsp > + and rax, 0fh > + sub rsp, rax > + > + ; > + ; Pass entry point of the PEI core > + ; > + mov rdi, 0FFFFFFE0h > + mov edi, DWORD [rdi] > + mov r9, rdi > + > + ; > + ; Pass BFV into the PEI Core > + ; > +#if FixedPcdGet8(PcdFspWrapperResetVectorInFsp) =3D=3D 1 > + ; > + ; Reset Vector and initial sec core (to initialize Temp Ram) is=20 > +part of FSP O > + ; Default UefiCpuPkg Reset Vector locates FSP O as BFV > + ; However the Actual Sec Core that launches PEI is part of another Fv. > + ; We need to Pass that Fv as BFV to PEI Core > + ; > + xor rcx, rcx > + mov r8, ASM_PFX (PcdGet32 (PcdFspWrapperBfvforResetVectorInFsp)) > + mov ecx, DWORD[r8] This should be UINT64 since it is possible with 64-bit for the reset vector= to be > 4 GB. > + mov r8, rcx > +#else > + mov r8, r10 > +#endif > + > + ; > + ; Pass stack size into the PEI Core ; > + mov rcx, r15 ; Start of TempRam > + mov rdx, r14 ; End of TempRam > + > + sub rcx, rdx ; Size of TempRam > + > + ; > + ; Pass Control into the PEI Core > + ; > + sub rsp, 20h > + call ASM_PFX(SecStartup) > + > diff --git=20 > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/X64/SecEntry.nasm=20 > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/X64/SecEntry.nasm > new file mode 100644 > index 0000000000..c4a95fbe10 > --- /dev/null > +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPl > +++ atformSecLib/X64/SecEntry.nasm > @@ -0,0 +1,214 @@ > +;-------------------------------------------------------------------- > +---------- > +; > +; Copyright (c) 2023, Intel Corporation. All rights reserved.
;=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent ; Module Name: > +; > +; SecEntry.nasm > +; > +; Abstract: > +; > +; This is the code that passes control to PEI core. > +; > +;-------------------------------------------------------------------- > +---------- > + > +#include > + > +IA32_CR4_OSFXSR equ 200h > +IA32_CR4_OSXMMEXCPT equ 400h > +IA32_CR0_MP equ 2h > + > +IA32_CPUID_SSE2 equ 02000000h > +IA32_CPUID_SSE2_B equ 26 > + > +SECTION .text > + > +extern ASM_PFX(CallPeiCoreEntryPoint) > +extern ASM_PFX(FsptUpdDataPtr) > +extern ASM_PFX(BoardBeforeTempRamInit) > +; Pcds > +extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize)) > +extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress)) > + > +;-------------------------------------------------------------------- > +-------- > +; > +; Procedure: _ModuleEntryPoint > +; > +; Input: None > +; > +; Output: None > +; > +; Destroys: Assume all registers > +; > +; Description: > +; > +; Call TempRamInit API from FSP binary. After TempRamInit done, pass=20 > +; control to PEI core. > +; > +; Return: None > +; > +; MMX Usage: > +; MM0 =3D BIST State > +; > +;-------------------------------------------------------------------- > +-------- > + > +BITS 64 > +align 16 > +global ASM_PFX(_ModuleEntryPoint) > +ASM_PFX(_ModuleEntryPoint): > +#if FixedPcdGet8(PcdFspWrapperResetVectorInFsp) =3D=3D 1 > + ; > + ; When Fsp holds reset vector, TempRamInitApi would be called by=20 > +FSP itself > + ; and this will be the first call to FspWrapper. So, Skip calling=20 > +TempRamInitApi > + ; and proceed further to launch PeiCore Entry. > + ; > + jmp CallSecFspInit > +#endif > + > + fninit ; clear any pending Floating poi= nt exceptions > + ; > + ; Store the BIST value in mm0 > + ; > + movd mm0, eax > + cli > + > + ; > + ; Check INIT# is asserted by port 0xCF9 ; > + mov dx, 0CF9h > + in al, dx > + cmp al, 04h > + jz IssueWarmReset > + > + ; Trigger warm reset if PCIEBAR register is not in reset/default=20 > + value state ; > + mov eax, 80000060h ; PCIEX_BAR_REG B0:D0:F0:R60 > + mov dx, 0CF8h > + out dx, eax > + mov dx, 0CFCh > + in eax, dx > + cmp eax, 0 > + jz NotWarmStart > + > +IssueWarmReset: > + ; > + ; @note Issue warm reset, since if CPU only reset is issued not all=20 > +MSRs are restored to their defaults > + ; > + mov dx, 0CF9h > + mov al, 06h > + out dx, al > + jmp $ > + > +NotWarmStart: > + ; Find FSP info header > + mov rax, ASM_PFX(PcdGet32 (PcdFsptBaseAddress)) > + mov edi, [eax] > + > + mov eax, dword [edi + FVH_SIGINATURE_OFFSET] > + cmp eax, FVH_SIGINATURE_VALID_VALUE > + jnz FspHeaderNotFound > + > + xor eax, eax > + mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET] > + cmp ax, 0 > + jnz FspFvExtHeaderExist > + > + xor eax, eax > + mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Head= er > + add edi, eax > + jmp FspCheckFfsHeader > + > +FspFvExtHeaderExist: > + add edi, eax > + mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv = Header > + add edi, eax > + > + ; Round up to 8 byte alignment > + mov eax, edi > + and al, 07h > + jz FspCheckFfsHeader > + > + and edi, 0FFFFFFF8h > + add edi, 08h > + > +FspCheckFfsHeader: > + ; Check the ffs guid > + mov eax, dword [edi] > + cmp eax, FSP_HEADER_GUID_DWORD1 > + jnz FspHeaderNotFound > + > + mov eax, dword [edi + 4] > + cmp eax, FSP_HEADER_GUID_DWORD2 > + jnz FspHeaderNotFound > + > + mov eax, dword [edi + 8] > + cmp eax, FSP_HEADER_GUID_DWORD3 > + jnz FspHeaderNotFound > + > + mov eax, dword [edi + 0Ch] > + cmp eax, FSP_HEADER_GUID_DWORD4 > + jnz FspHeaderNotFound > + > + add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header > + > + ; Check the section type as raw section > + mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET] > + cmp al, 019h > + jnz FspHeaderNotFound > + > + add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header > + jmp FspHeaderFound > + > +FspHeaderNotFound: > + jmp $ > + > +FspHeaderFound: > + ; Get the fsp TempRamInit Api address > + mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET] > + add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET] > + > + ; Setup the hardcode stack > + mov rsp, TempRamInitStack ; move return address to rsp > + mov rcx, ASM_PFX(FsptUpdDataPtr) ; TempRamInitParams > + > + ; Call the fsp TempRamInit Api > + jmp rax > + > +TempRamInitDone: > + mov rbx, 0800000000000000Eh > + cmp rax, rbx ; Check if EFI_NOT_FOUND returned. Err= or code for Microcode Update not found. > + je CallSecFspInit ; If microcode not found, don't hang, = but continue. > + > + test rax, rax ; Check if EFI_SUCCESS returned. > + jnz FspApiFailed > + > + ; RDX: start of range > + ; R8: end of range > +CallSecFspInit: > +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 1 > + push rax > + mov rax, ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize)) > + sub edx, dword [rax] ; TemporaryRam for FSP > + pop rax > +#endif > + > + mov r8, rdx > + mov rdx, rcx > + xor ecx, ecx ; zero - no Hob List Yet > + mov rsp, r8 > + > + ; > + ; Per X64 calling convention, make sure RSP is 16-byte aligned. > + ; > + mov rax, rsp > + and rax, 0fh > + sub rsp, rax > + > + call ASM_PFX(CallPeiCoreEntryPoint) > + > +FspApiFailed: > + jmp $ > + > +align 10h > +TempRamInitStack: > + DQ TempRamInitDone > diff --git=20 > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/X64/Stack.nasm=20 > b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/X64/Stack.nasm > new file mode 100644 > index 0000000000..d7ae97c5da > --- /dev/null > +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPl > +++ atformSecLib/X64/Stack.nasm > @@ -0,0 +1,72 @@ > +;-------------------------------------------------------------------- > +---------- > +; > +; Copyright (c) 2023, Intel Corporation. All rights reserved.
;=20 > +SPDX-License-Identifier: BSD-2-Clause-Patent ; Abstract: > +; > +; Switch the stack from temporary memory to permanent memory. > +; > +;-------------------------------------------------------------------- > +---------- > + > + SECTION .text > + > +;-------------------------------------------------------------------- > +---------- > +; VOID > +; EFIAPI > +; SecSwitchStack ( > +; UINT32 TemporaryMemoryBase, > +; UINT32 PermanentMemoryBase > +; ); > +;-------------------------------------------------------------------- > +---------- > +global ASM_PFX(SecSwitchStack) > +ASM_PFX(SecSwitchStack): > + ; > + ; Save four register: rax, rbx, rcx, rdx > + ; > + push rax > + push rbx > + push rcx > + push rdx > + > + ; > + ; !!CAUTION!! this function address's is pushed into stack after > + ; migration of whole temporary memory, so need save it to permanent > + ; memory at first! > + ; > + > + mov rbx, rcx ; Save the first parameter > + mov rcx, rdx ; Save the second parameter > + > + ; > + ; Save this function's return address into permanent memory at first= . > + ; Then, Fixup the esp point to permanent memory > + ; > + mov rax, rsp > + sub rax, rbx > + add rax, rcx > + mov rdx, qword [rsp] ; copy pushed register's value to per= manent memory > + mov qword [rax], rdx > + mov rdx, qword [rsp + 8] > + mov qword [rax + 8], rdx > + mov rdx, qword [rsp + 16] > + mov qword [rax + 16], rdx > + mov rdx, qword [rsp + 24] > + mov qword [rax + 24], rdx > + mov rdx, qword [rsp + 32] ; Update this function's return addre= ss into permanent memory > + mov qword [rax + 32], rdx > + mov rsp, rax ; From now, rsp is pointed to permane= nt memory > + > + ; > + ; Fixup the rbp point to permanent memory > + ; > + mov rax, rbp > + sub rax, rbx > + add rax, rcx > + mov rbp, rax ; From now, rbp is pointed to permane= nt memory > + > + pop rdx > + pop rcx > + pop rbx > + pop rax > + ret > + > diff --git=20 > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/Ia32/Fsp.h b/Platform/Intel/MinPlatformPkg/Include/Fsp.h > similarity index 86% > rename from=20 > Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatform > SecLib/Ia32/Fsp.h rename to=20 > Platform/Intel/MinPlatformPkg/Include/Fsp.h > index 9f6cdcf476..1b86912583 100644 > ---=20 > a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo > rmSecLib/Ia32/Fsp.h > +++ b/Platform/Intel/MinPlatformPkg/Include/Fsp.h > @@ -36,7 +36,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // //=20 > Fsp Header // > -#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C > -#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30 > +#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C > +#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30 > =20 > #endif > diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec=20 > b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > index a14c6b2db5..8256e62510 100644 > --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > @@ -393,6 +393,27 @@ > # > =20 > gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE|BOO > LEAN|0xF00000A8 > =20 > + ## Reset Vector in FSP > + # FALSE: Reset Vector is in FSP Wrapper # TRUE: Reset Vector is=20 > + in FSP # > + =20 > + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperResetVectorInFsp|FALSE|BO > + OLEAN|0xF00000A9 > + > + ## BFV Location for Reset Vector in FSP # The default of BFV=20 > + Location for Reset Vector in FSP is 0xFFFF0000. > + # > + =20 > + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBfvforResetVectorInFsp|0x > + FFFF0000|UINT32|0xF00000AA This should be UINT64 since it is possible with 64-bit for the reset vector= to be > 4 GB. > + > + ## FSP-T UPD Header Revision > + # The default of FSP-T UPD Header Revision is 0. > + # > + =20 > + gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevision|0x0|UINT8|0xF > + 00000AC > + > + ## FSP-T ARCH UPD Header Revision > + # The default of FSP-T ARCH UPD Header Revision is 0. > + # > + =20 > + gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpdHeaderRevision|0x0|UINT8 > + |0xF00000AD > + > [PcdsFeatureFlag] > =20 > gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit |FALSE|BOOLEAN= |0xF00000A1 > -- > 2.40.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112808): https://edk2.groups.io/g/devel/message/112808 Mute This Topic: https://groups.io/mt/103237142/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-