From: "Attar, AbdulLateef (Abdul Lateef)" <AbdulLateef.Attar@amd.com>
To: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: "devel@edk2.groups.io" <devel@edk2.groups.io>,
Ard Biesheuvel <ardb+tianocore@kernel.org>,
"Chang, Abner" <Abner.Chang@amd.com>,
Michael D Kinney <michael.d.kinney@intel.com>
Subject: Re: [PATCH v2 RESEND 3/4] Platform/AMD/BoarkPkg: Adds SetCacheMtrrLib library
Date: Mon, 20 Mar 2023 10:02:22 +0000 [thread overview]
Message-ID: <PH7PR12MB6466F0C06D6EF6088FC0900CE0809@PH7PR12MB6466.namprd12.prod.outlook.com> (raw)
In-Reply-To: <ZBSObxwuYPk3LlmN@qc-i7.hemma.eciton.net>
[AMD Official Use Only - General]
Thanks for reviewing, will submit V3 patch.
-----Original Message-----
From: Leif Lindholm <quic_llindhol@quicinc.com>
Sent: 17 March 2023 21:30
To: Attar, AbdulLateef (Abdul Lateef) <AbdulLateef.Attar@amd.com>
Cc: devel@edk2.groups.io; Ard Biesheuvel <ardb+tianocore@kernel.org>; Chang, Abner <Abner.Chang@amd.com>; Michael D Kinney <michael.d.kinney@intel.com>
Subject: Re: [PATCH v2 RESEND 3/4] Platform/AMD/BoarkPkg: Adds SetCacheMtrrLib library
Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding.
Typo in subject: BoarkPkg
On Fri, Mar 17, 2023 at 12:20:06 +0530, Abdul Lateef Attar wrote:
> Adds SetCacheMtrrLib library for AMD processor based boards.
> This library sets MTRR value or various memory ranges.
>
> Signed-off-by: Abdul Lateef Attar <abdattar@amd.com>
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> Cc: Leif Lindholm <quic_llindhol@quicinc.com>
> Cc: Abner Chang <abner.chang@amd.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> ---
> Platform/AMD/BoardPkg/BoardPkg.dsc | 10 ++
> .../SetCacheMtrrLib/SetCacheMtrrLib.inf | 37 +++++
> .../Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 132
> ++++++++++++++++++
> 3 files changed, 179 insertions(+)
> create mode 100644
> Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
> create mode 100644
> Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c
>
> diff --git a/Platform/AMD/BoardPkg/BoardPkg.dsc
> b/Platform/AMD/BoardPkg/BoardPkg.dsc
> index cb4065b86c60..aa0ee8287cd8 100644
> --- a/Platform/AMD/BoardPkg/BoardPkg.dsc
> +++ b/Platform/AMD/BoardPkg/BoardPkg.dsc
> @@ -18,3 +18,13 @@ [Defines]
>
> [Packages]
> BoardPkg/BoardPkg.dec
> + MinPlatformPkg/MinPlatformPkg.dec
> + MdePkg/MdePkg.dec
Sort?
> + UefiCpuPkg/UefiCpuPkg.dec
> +
> +[LibraryClasses.common.PEIM]
> +
> +SetCacheMtrrLib|BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
> +
> +[Components.IA32]
> + BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
> +
Please drop blank line at end of file.
> diff --git
> a/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
> b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
> new file mode 100644
> index 000000000000..c66661d3f8dc
> --- /dev/null
> +++ b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.in
> +++ f
> @@ -0,0 +1,37 @@
> +## @file
> +# Component information file for Platform SetCacheMtrr Library.
> +# This library implementation is for AMD processor based platforms.
> +#
> +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights
> +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # ##
> +
> +[Defines]
> + INF_VERSION = 1.29
> + BASE_NAME = PeiSetCacheMtrrLib
> + FILE_GUID = 1E8468E0-5EB4-4088-9B52-BFDC6E4DAE87
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SetCacheMtrrLib
> +
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> + MtrrLib
> +
> +[Packages]
> + MinPlatformPkg/MinPlatformPkg.dec
> + MdePkg/MdePkg.dec
Sort?
> + UefiCpuPkg/UefiCpuPkg.dec
> +
> +[Sources]
> + SetCacheMtrrLib.c
> +
> +[Guids]
> +
> +[Pcd]
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize
> +
Please drop blank line at end of file.
/
Leif
> diff --git
> a/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c
> b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c
> new file mode 100644
> index 000000000000..18404405d9fa
> --- /dev/null
> +++ b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c
> @@ -0,0 +1,132 @@
> +/** @file
> +
> +SetCacheMtrr library functions.
> +This library implementation is for AMD processor based platforms.
> +
> +Copyright (C) 2023 Advanced Micro Devices, Inc. All rights
> +reserved.<BR>
> +
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Uefi.h>
> +#include <PiPei.h>
> +#include <Library/DebugLib.h>
> +#include <Library/MtrrLib.h>
> +
> +/**
> + This function sets the cache MTRR values for PEI phase.
> +**/
> +VOID
> +EFIAPI
> +SetCacheMtrr (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = MtrrSetMemoryAttribute (
> + 0,
> + 0xA0000,
> + CacheWriteBack
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "Error(%r) in setting CacheWriteBack for 0-0x9FFFF\n",
> + Status
> + ));
> + }
> +
> + Status = MtrrSetMemoryAttribute (
> + 0xA0000,
> + 0x20000,
> + CacheUncacheable
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "Error(%r) in setting CacheUncacheable for 0xA0000-0xBFFFF\n",
> + Status
> + ));
> + }
> +
> + Status = MtrrSetMemoryAttribute (
> + 0xC0000,
> + 0x40000,
> + CacheWriteProtected
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "Error(%r) in setting CacheWriteProtected for 0xC0000-0xFFFFF\n",
> + Status
> + ));
> + }
> +
> + Status = MtrrSetMemoryAttribute (
> + 0x100000,
> + 0xAFF00000,
> + CacheWriteBack
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "Error(%r) in setting CacheWriteBack for 0x100000-0xAFFFFFFF\n",
> + Status
> + ));
> + }
> +
> + Status = MtrrSetMemoryAttribute (
> + PcdGet32 (PcdFlashAreaBaseAddress),
> + PcdGet32 (PcdFlashAreaSize),
> + CacheWriteProtected
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "Error(%r) in setting CacheWriteProtected for 0x%X-0x%X\n",
> + Status,
> + PcdGet32 (PcdFlashAreaBaseAddress),
> + PcdGet32 (PcdFlashAreaBaseAddress) + PcdGet32 (PcdFlashAreaSize)
> + ));
> + }
> +
> + MtrrDebugPrintAllMtrrs ();
> + return;
> +}
> +
> +/**
> + Update MTRR setting in EndOfPei phase.
> + This function will set the MTRR value as CacheUncacheable
> + for Flash address.
> +
> + @retval EFI_SUCCESS The function completes successfully.
> + @retval Others Some error occurs.
> +**/
> +EFI_STATUS
> +EFIAPI
> +SetCacheMtrrAfterEndOfPei (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> +
> + Status = MtrrSetMemoryAttribute (
> + PcdGet32 (PcdFlashAreaBaseAddress),
> + PcdGet32 (PcdFlashAreaSize),
> + CacheUncacheable
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "Error(%r) in setting CacheUncacheable for 0x%X-0x%X\n",
> + Status,
> + PcdGet32 (PcdFlashAreaBaseAddress),
> + PcdGet32 (PcdFlashAreaBaseAddress) + PcdGet32 (PcdFlashAreaSize)
> + ));
> + }
> +
> + MtrrDebugPrintAllMtrrs ();
> + return EFI_SUCCESS;
> +}
> --
> 2.25.1
>
next prev parent reply other threads:[~2023-03-20 10:02 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-17 6:50 [PATCH v2 RESEND 0/4] Adds AMD/BoardPkg and AMD/PlatformPkg Abdul Lateef Attar
2023-03-17 6:50 ` [PATCH v2 RESEND 1/4] Platform/AMD: Adds BoardPkg and PlatformPkg Abdul Lateef Attar
2023-03-17 15:41 ` Leif Lindholm
2023-03-17 6:50 ` [PATCH v2 RESEND 2/4] Platform/AMD/PlatformPkg: Adds PciHotPlug init protocol implementation Abdul Lateef Attar
2023-03-17 6:52 ` Chang, Abner
2023-03-17 15:55 ` [edk2-devel] " Leif Lindholm
2023-03-20 10:01 ` Attar, AbdulLateef (Abdul Lateef)
2023-03-17 6:50 ` [PATCH v2 RESEND 3/4] Platform/AMD/BoarkPkg: Adds SetCacheMtrrLib library Abdul Lateef Attar
2023-03-17 6:52 ` Chang, Abner
2023-03-17 15:59 ` Leif Lindholm
2023-03-20 10:02 ` Attar, AbdulLateef (Abdul Lateef) [this message]
2023-03-17 6:50 ` [PATCH v2 RESEND 4/4] Maintainers.txt: Adds AMD/BoardPkg and AMD/PlatformPkg maintainers Abdul Lateef Attar
2023-03-17 6:53 ` Chang, Abner
2023-03-17 16:09 ` Leif Lindholm
2023-03-18 9:03 ` Chang, Abner
2023-03-20 12:54 ` [edk2-devel] " Leif Lindholm
2023-03-18 9:16 ` Chang, Abner
2023-03-18 9:42 ` Ard Biesheuvel
2023-03-18 15:34 ` Chang, Abner
2023-03-20 13:05 ` [edk2-devel] " Leif Lindholm
2023-03-20 14:09 ` Attar, AbdulLateef (Abdul Lateef)
2023-03-20 18:02 ` Leif Lindholm
2023-03-21 3:00 ` Attar, AbdulLateef (Abdul Lateef)
2023-03-22 9:54 ` Chang, Abner
2023-03-22 11:59 ` Attar, AbdulLateef (Abdul Lateef)
2023-03-22 12:29 ` Leif Lindholm
2023-03-20 10:11 ` Attar, AbdulLateef (Abdul Lateef)
2023-03-17 6:54 ` [PATCH v2 RESEND 0/4] Adds AMD/BoardPkg and AMD/PlatformPkg Chang, Abner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=PH7PR12MB6466F0C06D6EF6088FC0900CE0809@PH7PR12MB6466.namprd12.prod.outlook.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox