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Mon, 24 Jan 2022 03:49:27 +0000 From: "Abner Chang" To: Gerd Hoffmann , "devel@edk2.groups.io" CC: Ray Ni , Liming Gao , "Jiewen Yao" , Jordan Justen , "Leif Lindholm" , Ard Biesheuvel , Jian J Wang , Pawel Polawski , Hao A Wu Subject: Re: [PATCH v2 3/6] OvmfPkg/PlatformPei: unfix PcdPciExpressBaseAddress Thread-Topic: [PATCH v2 3/6] OvmfPkg/PlatformPei: unfix PcdPciExpressBaseAddress Thread-Index: AQHYC4lISxo/lUtWgUypu3t10sKazaxxk1gA Date: Mon, 24 Jan 2022 03:49:27 +0000 Message-ID: References: <20220117100146.1965662-1-kraxel@redhat.com> <20220117100146.1965662-4-kraxel@redhat.com> In-Reply-To: <20220117100146.1965662-4-kraxel@redhat.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: e256375e-b27c-4a4b-2cee-08d9deec851b x-ms-traffictypediagnostic: PH7PR84MB2029:EE_ x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:6430; x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Abner Chang > -----Original Message----- > From: Gerd Hoffmann > Sent: Monday, January 17, 2022 6:02 PM > To: devel@edk2.groups.io > Cc: Gerd Hoffmann ; Ray Ni ; > Liming Gao ; Chang, Abner (HPS SW/FW > Technologist) ; Jiewen Yao > ; Jordan Justen ; Leif > Lindholm ; Ard Biesheuvel > ; Jian J Wang ; Pawel > Polawski ; Hao A Wu > Subject: [PATCH v2 3/6] OvmfPkg/PlatformPei: unfix > PcdPciExpressBaseAddress >=20 > Will be set by FdtPciHostBridgeLib, so it can't be an fixed when we > want use that library. >=20 > Signed-off-by: Gerd Hoffmann > --- > OvmfPkg/PlatformPei/PlatformPei.inf | 2 +- > OvmfPkg/PlatformPei/MemDetect.c | 4 ++-- > OvmfPkg/PlatformPei/Platform.c | 4 ++-- > 3 files changed, 5 insertions(+), 5 deletions(-) >=20 > diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf > b/OvmfPkg/PlatformPei/PlatformPei.inf > index 8ef404168c45..44bf482e855a 100644 > --- a/OvmfPkg/PlatformPei/PlatformPei.inf > +++ b/OvmfPkg/PlatformPei/PlatformPei.inf > @@ -92,6 +92,7 @@ [Pcd] > gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes > gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase > gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved > @@ -114,7 +115,6 @@ [Pcd] > [FixedPcd] > gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase > gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidSize > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress > gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS > gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory > gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType > diff --git a/OvmfPkg/PlatformPei/MemDetect.c > b/OvmfPkg/PlatformPei/MemDetect.c > index 1bcb5a08bca6..f87a6f48a1bf 100644 > --- a/OvmfPkg/PlatformPei/MemDetect.c > +++ b/OvmfPkg/PlatformPei/MemDetect.c > @@ -155,8 +155,8 @@ QemuUc32BaseInitialization ( > // [PcdPciExpressBaseAddress, 4GB) range require a very small number= of > // variable MTRRs (preferably 1 or 2). > // > - ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <=3D MAX_UINT32); > - mQemuUc32Base =3D (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress); > + ASSERT (PcdGet64 (PcdPciExpressBaseAddress) <=3D MAX_UINT32); > + mQemuUc32Base =3D (UINT32)PcdGet64 (PcdPciExpressBaseAddress); > return; > } >=20 > diff --git a/OvmfPkg/PlatformPei/Platform.c > b/OvmfPkg/PlatformPei/Platform.c > index d0323c645162..27ada0c17577 100644 > --- a/OvmfPkg/PlatformPei/Platform.c > +++ b/OvmfPkg/PlatformPei/Platform.c > @@ -171,7 +171,7 @@ MemMapInitialization ( > // The MMCONFIG area is expected to fall between the top of low RAM > and > // the base of the 32-bit PCI host aperture. > // > - PciExBarBase =3D FixedPcdGet64 (PcdPciExpressBaseAddress); > + PciExBarBase =3D PcdGet64 (PcdPciExpressBaseAddress); > ASSERT (TopOfLowRam <=3D PciExBarBase); > ASSERT (PciExBarBase <=3D MAX_UINT32 - SIZE_256MB); > PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB); > @@ -302,7 +302,7 @@ PciExBarInitialization ( > // determined in AddressWidthInitialization(), i.e., 36 bits, will suf= fice > // for DXE's page tables to cover the MMCONFIG area. > // > - PciExBarBase.Uint64 =3D FixedPcdGet64 (PcdPciExpressBaseAddress); > + PciExBarBase.Uint64 =3D PcdGet64 (PcdPciExpressBaseAddress); > ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) =3D=3D 0); > ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) =3D=3D 0); >=20 > -- > 2.34.1