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* [PATCH 01/79] ProcessorPkg/Include: Add header files of RISC-V processor package
@ 2022-01-08  4:07 Abner Chang
  2022-01-10 13:10 ` [edk2-devel] " Leif Lindholm
  0 siblings, 1 reply; 19+ messages in thread
From: Abner Chang @ 2022-01-08  4:07 UTC (permalink / raw)
  To: devel; +Cc: abner.chang

(This is migrated from edk2-platforms:Silicon/RISC-V)

RISC-V processor package library definitions.

IndustryStandard/RiscV.h
-Add RiscV.h which conform with RISC-V Privilege Spec v1.10.

RiscVImpl.h
-Definition of EDK2 RISC-V implementation.

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
 .../Include/IndustryStandard/RiscV.h          | 156 ++++++++++++++++++
 .../RISC-V/ProcessorPkg/Include/RiscVImpl.h   |  87 ++++++++++
 2 files changed, 243 insertions(+)
 create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
 create mode 100644 Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h

diff --git a/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
new file mode 100644
index 0000000000..2a992394ed
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/IndustryStandard/RiscV.h
@@ -0,0 +1,156 @@
+/** @file
+  RISC-V package definitions.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_INDUSTRY_STANDARD_H_
+#define RISCV_INDUSTRY_STANDARD_H_
+
+#if defined (MDE_CPU_RISCV64)
+#define RISC_V_XLEN_BITS 64
+#else
+#endif
+
+#define RISC_V_ISA_ATOMIC_EXTENSION                 (0x00000001 << 0)
+#define RISC_V_ISA_BIT_OPERATION_EXTENSION          (0x00000001 << 1)
+#define RISC_V_ISA_COMPRESSED_EXTENSION             (0x00000001 << 2)
+#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION    (0x00000001 << 3)
+#define RISC_V_ISA_RV32E_ISA                        (0x00000001 << 4)
+#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION    (0x00000001 << 5)
+#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION    (0x00000001 << 6)
+#define RISC_V_ISA_RESERVED_1                       (0x00000001 << 7)
+#define RISC_V_ISA_INTEGER_ISA_EXTENSION            (0x00000001 << 8)
+#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION    (0x00000001 << 9)
+#define RISC_V_ISA_RESERVED_2                       (0x00000001 << 10)
+#define RISC_V_ISA_DECIMAL_FP_EXTENSION             (0x00000001 << 11)
+#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION        (0x00000001 << 12)
+#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED   (0x00000001 << 13)
+#define RISC_V_ISA_RESERVED_3                       (0x00000001 << 14)
+#define RISC_V_ISA_PACKED_SIMD_EXTENSION            (0x00000001 << 15)
+#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION      (0x00000001 << 16)
+#define RISC_V_ISA_RESERVED_4                       (0x00000001 << 17)
+#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED      (0x00000001 << 18)
+#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION    (0x00000001 << 19)
+#define RISC_V_ISA_USER_MODE_IMPLEMENTED            (0x00000001 << 20)
+#define RISC_V_ISA_VECTOR_EXTENSION                 (0x00000001 << 21)
+#define RISC_V_ISA_RESERVED_5                       (0x00000001 << 22)
+#define RISC_V_ISA_NON_STANDARD_EXTENSION           (0x00000001 << 23)
+#define RISC_V_ISA_RESERVED_6                       (0x00000001 << 24)
+#define RISC_V_ISA_RESERVED_7                       (0x00000001 << 25)
+
+//
+// RISC-V CSR definitions.
+//
+//
+// Machine information
+//
+#define RISCV_CSR_MACHINE_MVENDORID     0xF11
+#define RISCV_CSR_MACHINE_MARCHID       0xF12
+#define RISCV_CSR_MACHINE_MIMPID        0xF13
+#define RISCV_CSR_MACHINE_HARRID        0xF14
+//
+// Machine Trap Setup.
+//
+#define RISCV_CSR_MACHINE_MSTATUS       0x300
+#define RISCV_CSR_MACHINE_MISA          0x301
+#define RISCV_CSR_MACHINE_MEDELEG       0x302
+#define RISCV_CSR_MACHINE_MIDELEG       0x303
+#define RISCV_CSR_MACHINE_MIE           0x304
+#define RISCV_CSR_MACHINE_MTVEC         0x305
+
+#define RISCV_TIMER_COMPARE_BITS      32
+//
+// Machine Timer and Counter.
+//
+//#define RISCV_CSR_MACHINE_MTIME         0x701
+//#define RISCV_CSR_MACHINE_MTIMEH        0x741
+//
+// Machine Trap Handling.
+//
+#define RISCV_CSR_MACHINE_MSCRATCH      0x340
+#define RISCV_CSR_MACHINE_MEPC          0x341
+#define RISCV_CSR_MACHINE_MCAUSE        0x342
+  #define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f
+  #define MACHINE_MCAUSE_INTERRUPT      (RISC_V_XLEN_BITS - 1)
+#define RISCV_CSR_MACHINE_MBADADDR      0x343
+#define RISCV_CSR_MACHINE_MIP           0x344
+
+//
+// Machine Protection and Translation.
+//
+#define RISCV_CSR_MACHINE_MBASE         0x380
+#define RISCV_CSR_MACHINE_MBOUND        0x381
+#define RISCV_CSR_MACHINE_MIBASE        0x382
+#define RISCV_CSR_MACHINE_MIBOUND       0x383
+#define RISCV_CSR_MACHINE_MDBASE        0x384
+#define RISCV_CSR_MACHINE_MDBOUND       0x385
+
+//
+// Supervisor mode CSR.
+//
+#define RISCV_CSR_SUPERVISOR_SSTATUS    0x100
+  #define SSTATUS_SIE_BIT_POSITION      1
+  #define SSTATUS_SPP_BIT_POSITION      8
+#define RISCV_CSR_SUPERVISOR_SIE        0x104
+#define RISCV_CSR_SUPERVISOR_SSCRATCH   0x140
+#define RISCV_CSR_SUPERVISOR_SEPC       0x141
+#define RISCV_CSR_SUPERVISOR_SCAUSE     0x142
+  #define SCAUSE_USER_SOFTWARE_INT        0
+  #define SCAUSE_SUPERVISOR_SOFTWARE_INT  1
+  #define SCAUSE_USER_TIMER_INT           4
+  #define SCAUSE_SUPERVISOR_TIMER_INT     5
+  #define SCAUSE_USER_EXTERNAL_INT        8
+  #define SCAUSE_SUPERVISOR_EXTERNAL_INT  9
+#define RISCV_CSR_SUPERVISOR_STVAL      0x143
+#define RISCV_CSR_SUPERVISOR_SIP        0x144
+#define RISCV_CSR_SUPERVISOR_SATP       0x180
+
+#if defined (MDE_CPU_RISCV64)
+  #define RISCV_SATP_MODE_MASK          0xF000000000000000
+  #define RISCV_SATP_MODE_BIT_POSITION  60
+#endif
+    #define RISCV_SATP_MODE_OFF         0
+    #define RISCV_SATP_MODE_SV32        1
+    #define RISCV_SATP_MODE_SV39        8
+    #define RISCV_SATP_MODE_SV48        9
+    #define RISCV_SATP_MODE_SV57        10
+    #define RISCV_SATP_MODE_SV64        11
+
+  #define SATP64_ASID_MASK              0x0FFFF00000000000
+  #define SATP64_PPN_MASK               0x00000FFFFFFFFFFF
+
+#define RISCV_CAUSE_MISALIGNED_FETCH        0x0
+#define RISCV_CAUSE_FETCH_ACCESS            0x1
+#define RISCV_CAUSE_ILLEGAL_INSTRUCTION     0x2
+#define RISCV_CAUSE_BREAKPOINT              0x3
+#define RISCV_CAUSE_MISALIGNED_LOAD         0x4
+#define RISCV_CAUSE_LOAD_ACCESS             0x5
+#define RISCV_CAUSE_MISALIGNED_STORE        0x6
+#define RISCV_CAUSE_STORE_ACCESS            0x7
+#define RISCV_CAUSE_USER_ECALL              0x8
+#define RISCV_CAUSE_HYPERVISOR_ECALL        0x9
+#define RISCV_CAUSE_SUPERVISOR_ECALL        0xa
+#define RISCV_CAUSE_MACHINE_ECALL           0xb
+#define RISCV_CAUSE_FETCH_PAGE_FAULT        0xc
+#define RISCV_CAUSE_LOAD_PAGE_FAULT         0xd
+#define RISCV_CAUSE_STORE_PAGE_FAULT        0xf
+#define RISCV_CAUSE_FETCH_GUEST_PAGE_FAULT  0x14
+#define RISCV_CAUSE_LOAD_GUEST_PAGE_FAULT   0x15
+#define RISCV_CAUSE_STORE_GUEST_PAGE_FAULT  0x17
+
+//
+// Machine Read-Write Shadow of Hypervisor Read-Only Registers
+//
+#define RISCV_CSR_HTIMEW                0xB01
+#define RISCV_CSR_HTIMEHW               0xB81
+//
+// Machine Host-Target Interface (Non-Standard Berkeley Extension)
+//
+#define RISCV_CSR_MTOHOST               0x780
+#define RISCV_CSR_MFROMHOST             0x781
+
+#endif
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h b/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h
new file mode 100644
index 0000000000..14092df174
--- /dev/null
+++ b/Silicon/RISC-V/ProcessorPkg/Include/RiscVImpl.h
@@ -0,0 +1,87 @@
+/** @file
+  RISC-V package definitions.
+
+  Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_H_
+#define RISCV_H_
+
+#include <Uefi.h>
+#include <IndustryStandard/RiscV.h>
+
+#define _ASM_FUNC(Name, Section)    \
+  .global   Name                  ; \
+  .section  #Section, "ax"        ; \
+  .type     Name, %function       ; \
+  .p2align  2                     ; \
+  Name:
+
+#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
+
+#if defined (MDE_CPU_RISCV64)
+typedef UINT64 RISC_V_REGS_PROTOTYPE;
+#else
+#endif
+
+//
+// Structure for 128-bit value
+//
+typedef struct {
+  UINT64            Value64_L;
+  UINT64            Value64_H;
+} RISCV_UINT128;
+
+#define RISCV_MACHINE_CONTEXT_SIZE  0x1000
+typedef struct _RISCV_MACHINE_MODE_CONTEXT RISCV_MACHINE_MODE_CONTEXT;
+
+///
+/// Exception handlers in context.
+///
+typedef struct _EXCEPTION_HANDLER_CONTEXT {
+  EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander;
+  EFI_PHYSICAL_ADDRESS InstAccessFaultHander;
+  EFI_PHYSICAL_ADDRESS IllegalInstHander;
+  EFI_PHYSICAL_ADDRESS BreakpointHander;
+  EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander;
+  EFI_PHYSICAL_ADDRESS LoadAccessFaultHander;
+  EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander;
+  EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander;
+  EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander;
+  EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander;
+  EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander;
+  EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander;
+} EXCEPTION_HANDLER_CONTEXT;
+
+///
+/// Exception handlers in context.
+///
+typedef struct _INTERRUPT_HANDLER_CONTEXT {
+  EFI_PHYSICAL_ADDRESS SoftwareIntHandler;
+  EFI_PHYSICAL_ADDRESS TimerIntHandler;
+} INTERRUPT_HANDLER_CONTEXT;
+
+///
+/// Interrupt handlers in context.
+///
+typedef struct _TRAP_HANDLER_CONTEXT {
+  EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext;
+  INTERRUPT_HANDLER_CONTEXT IntHandlerContext;
+} TRAP_HANDLER_CONTEXT;
+
+///
+/// Machine mode context used for saveing hart-local context.
+///
+typedef struct _RISCV_MACHINE_MODE_CONTEXT {
+  EFI_PHYSICAL_ADDRESS PeiService;                /// PEI service.
+  EFI_PHYSICAL_ADDRESS MachineModeTrapHandler;    /// Machine mode trap handler.
+  EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor mode trap handler.
+  EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor mode trap handler.
+  EFI_PHYSICAL_ADDRESS UserModeTrapHandler;       /// USer mode trap handler.
+  TRAP_HANDLER_CONTEXT MModeHandler;              /// Handler for machine mode.
+} RISCV_MACHINE_MODE_CONTEXT;
+
+#endif
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 19+ messages in thread

end of thread, other threads:[~2022-03-03 12:40 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-01-08  4:07 [PATCH 01/79] ProcessorPkg/Include: Add header files of RISC-V processor package Abner Chang
2022-01-10 13:10 ` [edk2-devel] " Leif Lindholm
2022-01-10 15:54   ` Michael D Kinney
2022-01-10 15:58     ` Michael D Kinney
2022-01-13  5:33       ` Abner Chang
2022-01-13 16:37         ` Michael D Kinney
2022-01-14 11:14           ` Abner Chang
2022-01-14 16:21             ` Michael D Kinney
2022-01-21 17:13               ` Abner Chang
2022-01-21 17:37                 ` Michael D Kinney
2022-02-04 16:15                   ` Abner Chang
2022-02-04 20:22                     ` Michael D Kinney
2022-02-05 14:56                       ` Abner Chang
2022-03-01  1:25                         ` RFC: UefiCpuPkg for all processor archs Abner Chang
2022-03-01  7:07                           ` Ni, Ray
2022-03-01  9:56                             ` Abner Chang
     [not found]                             ` <16D8393BAE893ED4.3953@groups.io>
2022-03-03 12:40                               ` [edk2-devel] " Abner Chang
2022-01-13  5:13     ` [edk2-devel] [PATCH 01/79] ProcessorPkg/Include: Add header files of RISC-V processor package Abner Chang
2022-01-13  5:24   ` Abner Chang

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