Re: [edk2-devel] [edk2-platforms][PATCH 11/14] RISC-V/ProcessorPkg: Address Core CI Spelling errors.

["Abner Chang" <abner.chang@hpe.com>]

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Hi Sunil, V2 sent.

Thanks for the review.
Abner
________________________________
From: Sunil V L <sunilvl@ventanamicro.com>
Sent: Friday, January 21, 2022 10:53 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>; Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
Cc: Schaefer, Daniel (ROM Janitor) <daniel.schaefer@hpe.com>
Subject: Re: [edk2-devel] [edk2-platforms][PATCH 11/14] RISC-V/ProcessorPkg: Address Core CI Spelling errors.

On Fri, Jan 21, 2022 at 04:48:45PM +0800, Abner Chang wrote:
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
> Cc: Sunil V L <sunilvl@ventanamicro.com>
> ---
>  .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec    |  4 ++--
>  .../RiscVFirmwareContextSbiLib.inf               |  6 +++---
>  .../RiscVFirmwareContextSscratchLib.inf          |  4 ++--
>  .../Include/Library/RiscVEdk2SbiLib.h            | 16 ++++++++--------
>  .../RISC-V/ProcessorPkg/Include/OpensbiTypes.h   |  4 ++--
>  .../Include/ProcessorSpecificHobData.h           |  2 +-
>  .../Include/SmbiosProcessorSpecificData.h        |  4 ++--
>  .../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c    | 16 ++++++++--------
>  .../RiscVFirmwareContextSbiLib.c                 |  4 ++--
>  .../RiscVFirmwareContextStvecLib.c               |  4 ++--
>  10 files changed, 32 insertions(+), 32 deletions(-)
>
> diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> index 59634f4413..177c1a710d 100644
> --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> +++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> @@ -1,7 +1,7 @@
> -## @file  RiscVProcesssorPkg.dec
> +## @file  RiscVProcessorPkg.dec
>  # This Package provides UEFI RISC-V processor modules and libraries.
>  #
> -# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +# Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent
>  #
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> index 0edf781149..1e4f14724b 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> @@ -1,9 +1,9 @@
>  ## @file
> -# Instance of OpebSBI Firmware Conext Library
> +# Instance of OpenSBI Firmware Context Library
>  #
> -# This iinstance uses RISC-V OpenSBI Firmware Extension SBI.
> +# This instance uses RISC-V OpenSBI Firmware Extension SBI.
>  #
> -#  Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +#  Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>  #
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent
>  #
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
> index 750c1cf51f..09e635fd1d 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
> +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
> @@ -1,9 +1,9 @@
>  ## @file
> -# Instance of OpebSBI Firmware Conext Library
> +# Instance of OpenSBI Firmware Context Library
>  #
>  # This instance uses RISC-V Supervisor mode SCRATCH CSR
>  #
> -#  Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +#  Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>  #
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent
>  #
> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
> index 88d957f002..6089137373 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
> +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
> @@ -1,7 +1,7 @@
>  /** @file
>    Library to call the RISC-V SBI ecalls
>
> -  Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
> +  Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>
>
>    SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -54,7 +54,7 @@ SbiGetSpecVersion (
>  /**
>    Get the SBI implementation ID
>
> -  This ID is used to idenetify a specific SBI implementation in order to work
> +  This ID is used to identify a specific SBI implementation in order to work
>    around any quirks it might have.
>
>    @param[out] ImplId               The ID of the SBI implementation.
> @@ -275,7 +275,7 @@ SbiRemoteFenceI (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.VMA instructions.
>
> -  The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
>
>    The remote fence function acts as a full tlb flush if * StartAddr and size
>    are both 0 * size is equal to 2^XLEN-1
> @@ -305,7 +305,7 @@ SbiRemoteSfenceVma (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.VMA instructions.
>
> -  The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
>    Covers only the given ASID.
>
>    The remote fence function acts as a full tlb flush if * StartAddr and size
> @@ -337,7 +337,7 @@ SbiRemoteSfenceVmaAsid (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
>
> -  The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
>    Covers only the given VMID.
>    This function call is only valid for harts implementing the hypervisor extension.
>
> @@ -373,7 +373,7 @@ SbiRemoteHfenceGvmaVmid (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
>
> -  The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
>    This function call is only valid for harts implementing the hypervisor extension.
>
>    The remote fence function acts as a full tlb flush if * StartAddr and size
> @@ -407,7 +407,7 @@ SbiRemoteHfenceGvma (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
>
> -  The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
>    Covers only the given ASID.
>    This function call is only valid for harts implementing the hypervisor extension.
>
> @@ -443,7 +443,7 @@ SbiRemoteHfenceVvmaAsid (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
>
> -  The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
>    This function call is only valid for harts implementing the hypervisor extension.
>
>    The remote fence function acts as a full tlb flush if * StartAddr and size
> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
> index 8a6ea97708..ca7fc7a4ac 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
> +++ b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
> @@ -1,7 +1,7 @@
>  /** @file
> -  RISC-V OpesbSBI header file reference.
> +  RISC-V OpensbiSBI header file reference.

Please change to just OpenSBI.

>
> -  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +  Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
>    SPDX-License-Identifier: BSD-2-Clause-Patent
>
> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
> index 97285289f7..4b2a92e2f2 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
> +++ b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
> @@ -29,7 +29,7 @@ typedef struct {
>    EFI_GUID CoreGuid;
>    VOID     *Context;        // The additional information of this core which
>                              // built in PEI phase and carried to DXE phase.
> -                            // The content is pocessor or platform specific.
> +                            // The content is processor or platform specific.
>    SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;
>  } RISC_V_PROCESSOR_SPECIFIC_HOB_DATA;
>
> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
> index 81e48cd068..85b8dcbe20 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
> +++ b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
> @@ -1,9 +1,9 @@
>  /** @file
>    Industry Standard Definitions of RISC-V Processor Specific data defined in
> -  below link for complaiant with SMBIOS Table Specification v3.3.0.
> +  below link for compliant with SMBIOS Table Specification v3.3.0.
>    https://github.com/riscv/riscv-smbios
>
> -  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +  Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
>    SPDX-License-Identifier: BSD-2-Clause-Patent
>
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
> index 319526ed8f..a51139542d 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
> +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
> @@ -15,7 +15,7 @@
>    - SbiLegacyRemoteSfenceVmaAsid -> Use SbiRemoteSfenceVmaAsid
>    - SbiLegacyShutdown            -> Wait for new System Reset extension
>
> -  Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
> +  Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>
>    SPDX-License-Identifier: BSD-2-Clause-Patent
>
>    @par Revision Reference:
> @@ -173,7 +173,7 @@ SbiGetSpecVersion (
>  /**
>    Get the SBI implementation ID
>
> -  This ID is used to idenetify a specific SBI implementation in order to work
> +  This ID is used to identify a specific SBI implementation in order to work
>    around any quirks it might have.
>
>    @param[out] ImplId               The ID of the SBI implementation.
> @@ -441,7 +441,7 @@ SbiRemoteFenceI (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.VMA instructions.
>
> -  The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
>
>    The remote fence function acts as a full tlb flush if * StartAddr and size
>    are both 0 * size is equal to 2^XLEN-1
> @@ -483,7 +483,7 @@ SbiRemoteSfenceVma (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.VMA instructions.
>
> -  The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
>    Covers only the given ASID.
>
>    The remote fence function acts as a full tlb flush if * StartAddr and size
> @@ -528,7 +528,7 @@ SbiRemoteSfenceVmaAsid (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
>
> -  The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
>    Covers only the given VMID.
>    This function call is only valid for harts implementing the hypervisor extension.
>
> @@ -577,7 +577,7 @@ SbiRemoteHFenceGvmaVmid (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.GVMA instructions.
>
> -  The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
>    This function call is only valid for harts implementing the hypervisor extension.
>
>    The remote fence function acts as a full tlb flush if * StartAddr and size
> @@ -623,7 +623,7 @@ SbiRemoteHFenceGvma (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
>
> -  The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
>    Covers only the given ASID.
>    This function call is only valid for harts implementing the hypervisor extension.
>
> @@ -672,7 +672,7 @@ SbiRemoteHFenceVvmaAsid (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.VVMA instructions.
>
> -  The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
>    This function call is only valid for harts implementing the hypervisor extension.
>
>    The remote fence function acts as a full tlb flush if * StartAddr and size
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
> index 6125618eaf..a2a18d3eb7 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
> +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
> @@ -1,8 +1,8 @@
>  /** @file
> -  This iinstance uses RISC-V OpenSBI Firmware Extension SBI to
> +  This instance uses RISC-V OpenSBI Firmware Extension SBI to
>    get the pointer of firmware context.
>
> -  Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +  Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
>    SPDX-License-Identifier: BSD-2-Clause-Patent
>  **/
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
> index 7d1675355a..d08b51d3d9 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
> +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
> @@ -1,8 +1,8 @@
>  /** @file
> -  This instance uses This iinstance Supervisor mode STVEC CSR to
> +  This instance uses This instance Supervisor mode STVEC CSR to

Please remove extra "This instance"

Regards
Sunil
>    get/set the pointer of firmware context.
>
> -  Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +  Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
>    SPDX-License-Identifier: BSD-2-Clause-Patent
>  **/
> --
> 2.31.1
>
>
>
> 
>
>

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