From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by mx.groups.io with SMTP id smtpd.web11.6087.1642838130582076711 for ; Fri, 21 Jan 2022 23:55:30 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@hpe.com header.s=pps0720 header.b=dddpIjdT; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: hpe.com, ip: 148.163.147.86, mailfrom: prvs=00215b754f=abner.chang@hpe.com) Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20M4bsUX012193; Sat, 22 Jan 2022 07:55:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hpe.com; h=from : to : cc : subject : date : message-id : references : in-reply-to : content-type : mime-version; s=pps0720; bh=t/UNmSSnS0AvMSUY/mGH70pwxMScB+KVEp3vO8f5l4o=; b=dddpIjdTbVkrrPbSt5XyfQH07s/bNWJAmlYa8d4hav8b6PNghfUd2Qz+2Sfczvd+qsQy bNNM4TA/CVWg4aDv7dx4XAqkSYBgqSBEAwCKv8kZG9+4mtQmmvM/b2DN0l5G0ofoA9/n hsYLrnwyE21e2yFfad5wBoJQ7cxUuGkTY18hNQJNDUXu1WI7Lfh+dSyQeJXOTlFl22ez sKZmB6EBPvsYmZdRsCDWEll34OnlaGVsh20CKnQRfotMfKRlqXnTCANzOLQt57ReqfXa RjT5au074mTk09rjVQNBauaevCnINMCEMmw4gZja/TcQi+LdroBU1tRzdzZBJJk2dgaH Vg== Received: from g2t2352.austin.hpe.com (g2t2352.austin.hpe.com [15.233.44.25]) by mx0b-002e3701.pphosted.com (PPS) with ESMTPS id 3drb2n0s2y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 22 Jan 2022 07:55:29 +0000 Received: from G4W9120.americas.hpqcorp.net (exchangepmrr1.us.hpecorp.net [16.210.21.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by g2t2352.austin.hpe.com (Postfix) with ESMTPS id 18A5B9C; Sat, 22 Jan 2022 07:55:29 +0000 (UTC) Received: from G9W8454.americas.hpqcorp.net (2002:10d8:a104::10d8:a104) by G4W9120.americas.hpqcorp.net (2002:10d2:150f::10d2:150f) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Sat, 22 Jan 2022 07:55:28 +0000 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (15.241.52.11) by G9W8454.americas.hpqcorp.net (16.216.161.4) with Microsoft SMTP Server (TLS) id 15.0.1497.23 via Frontend Transport; Sat, 22 Jan 2022 07:55:28 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=gH8KnZaUFXhWX6Lpz6Ow1lMe+xC0JrVc5nr/d9Z62HUAl4HrhQLIE66Xex9xVzenDSDf2pA2lixut43ajCNJqzDRjRNWYKwdPZ4gYS/pYeKFLHG3igj4U2dioIDJ9KQK2o+QM3Lrrj+80prSkdPO964R1gffP4AObcpr22p8wiQwaXTd+vvUT4DaMCO/9oxJZ2TfpdvabDVOkDacV9z8EVVW5Hs3CvGRKXqM7UKCbg3by1511p3DyCgS4Hz0Tuo4VhcnDakBZEL5W05Y7qKxL2ifCqkVqy2bdEmIs1A3zL+0eWJf3OqkJpWpS5QFrt5rksy9KTNDXEWlR+UYJTykxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=oyMAL/8PabMEsLQ2xCT0acovXeDNYN8lz5tHuBx2ozU=; b=gwMFtgwdGtQTO0PIuAfGfFoGqsoj8jRWrYCI5hQ3llIUoIYHSIzMUeA2ncEaaLjmxPrLKgYafKCp08ZwyOzctpihbCxR1YfS4lRp7p5597uPkYN4GgiBUqYqe4EUKOmHmpRoB3wclZChk4H3LuO/ONLHS6gRVlRhtBmn60C9oKDFVgDFf23omgnSUZA+wKOo/a2DvUiZcwUC3U3Ec3xJtfjyQRBUyPeRtj1QBcGmE2t63lkb02khRFc8dctgzfa516fwg1X3VFVj2MnRPL/5l22R622L3EfoGSj/9Oxpw9VApEA13l2/d3VRZ4yDiRu8+XOD0O5aEsmaIgRrjfc00Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=none; dmarc=none; dkim=none; arc=none Received: from PH7PR84MB1885.NAMPRD84.PROD.OUTLOOK.COM (2603:10b6:510:154::18) by PH0PR84MB1955.NAMPRD84.PROD.OUTLOOK.COM (2603:10b6:510:162::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4909.12; Sat, 22 Jan 2022 07:55:27 +0000 Received: from PH7PR84MB1885.NAMPRD84.PROD.OUTLOOK.COM ([fe80::29fe:6cc2:38e0:4b55]) by PH7PR84MB1885.NAMPRD84.PROD.OUTLOOK.COM ([fe80::29fe:6cc2:38e0:4b55%7]) with mapi id 15.20.4867.011; Sat, 22 Jan 2022 07:55:27 +0000 From: "Abner Chang" To: Sunil V L , "devel@edk2.groups.io" CC: "Schaefer, Daniel (ROM Janitor)" Subject: Re: [edk2-devel] [edk2-platforms][PATCH 11/14] RISC-V/ProcessorPkg: Address Core CI Spelling errors. Thread-Topic: [edk2-devel] [edk2-platforms][PATCH 11/14] RISC-V/ProcessorPkg: Address Core CI Spelling errors. Thread-Index: AQHYDqxfYHj7LDsJQE+U75u86qtgW6xtj/MAgAEdZl8= Date: Sat, 22 Jan 2022 07:55:26 +0000 Message-ID: References: <20220121084848.7695-1-abner.chang@hpe.com> <20220121084848.7695-12-abner.chang@hpe.com> <20220121145328.GC66337@sunil-ThinkPad-T490> In-Reply-To: <20220121145328.GC66337@sunil-ThinkPad-T490> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: suggested_attachment_session_id: b44bf07a-0564-e256-829d-077bb4f8fcdc x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 827bccba-a9ba-4364-bfb0-08d9dd7c8da5 x-ms-traffictypediagnostic: PH0PR84MB1955:EE_ x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:5516; x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: V8i0vkx9NBN+B0UtHKInQiruS4146Kn8HzBUMwlDz7qv0nG43XZUOdK+taDRd8pVNEDaRHGGI5kEbEAdHf/Lz8hhYSDH1cW7P/Cw5ehC6WQC7Up5fWtZVJaDr+xHhZFhQcAAtaG57+AcVtC8rv58Jvq2cvaiFnUX8I6edOX32bpOg13RskFE41gBw0IAZEZNPAIc23W2IILaTNKjSYPd5h//JafPtsDKPzl1vDKcWKujRU/SWZma7xMCkKmHoSwz1Fpck4twbRlBlziLpVawuZTyQVRB8fM01EuAHSeF2OdU1Q1Qvknqa3E+X4z6jHMbJ5Pmzi5xwxCAxlFdcnHn9Atl5G6pE060kmHYAWQi/EgbeOthAhv52szjwEO/tZXn9ABTuurhpanFLck6U52Ibft8Dn9nDCfhrm/OULcolOiBzk04mU+V0CT85USrXWjG0Ia4Yl90rpmI3ys91A/Q8FPJNug31TlZckUexPlmPwuh81KTlYF5yCEVqo7iwVQg7elyMr19XJ07fLhG2K9X+LQ6DTGBTyTzCMrJk198mNeLE5dIrt+pg7BVLfcOm9wQYKxyyABvbi/Zti9W+kLRQKvJ/uE7apUfW/j6NrDSh/DwnPKYHOyfeADW/UFiJpCHEQBHBU3RsWfSwLy1eS/f8bnnyg1cVdXZi/nbASTf/mLAT/NIPQATm9NMltf9RCbacCJ+X6cN22PutDIM3tyW7dV2L7HNRfbBt1TPph2YL8Fm4gabkxHpGLzO89Zycsc+h7HfIQ4zrcU+3a7xZs5mT72wKKv5heqKg6MrQ48bqmnMkfGzZsOEYcrwNjW9DT3hbDj+1PHd7ex3hfkFNUkAhg== x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PH7PR84MB1885.NAMPRD84.PROD.OUTLOOK.COM;PTR:;CAT:NONE;SFS:(366004)(38070700005)(86362001)(110136005)(122000001)(64756008)(53546011)(6506007)(66946007)(186003)(5660300002)(316002)(8676002)(38100700002)(52536014)(66446008)(166002)(66476007)(66556008)(508600001)(83380400001)(8936002)(2906002)(26005)(91956017)(966005)(71200400001)(33656002)(76116006)(4326008)(82960400001)(30864003)(19627405001)(7696005)(9686003)(55016003);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?4S29FJ4HhEqcB5DkP03PYmnJLQNGATIEzA1wNuSq3zLX7WG1yeTTjU6Iazi7?= =?us-ascii?Q?DUjVF/909skCGCy9MKPM+l136KV0qqDelJ+6gKCLM/4Q5ZyCEYFNA8zrZH/9?= =?us-ascii?Q?TNB/bIU55w3L+PTj2rxi1My0ph6repvEG0m6SZ1IzliKJpTeTxd1WH2vHWHh?= =?us-ascii?Q?ZENbakEtNdxfRjRIV3z0h1lyHMK6AavRYepXrK6K5sSlosuRrp4Nqn8HPRUh?= =?us-ascii?Q?jX6Su/ZakbKuJPOe7xfb4JyDzl3ZNeWJy74aPNNt/Np/kF6F56HoUqJHYXGv?= =?us-ascii?Q?vyOHfi2c9XKJnWzE28/7MbnX7kavuX+jeKjFj+jePuRt0+FZbCq/EgUe7T4s?= =?us-ascii?Q?EaZLea48QiaY1ZGoC6ggBrQ6urQEso+pnx/uPo1LG8PdDftNKHnbyVlwU/h7?= =?us-ascii?Q?EBrjYkFkw6cL+fLNpmkQkUm/N9cREpm1cFior5vZQ0rhDMVW2yiraPgKHR4+?= =?us-ascii?Q?AvLkOrMyglmXhgSGgW75xojFwYjUpUiWC/zEdislHO2Qnb+KK4uHl5XoGMVG?= =?us-ascii?Q?WQdkhP4IQBy52F00zwMLGZV8kwFBHHpWH4gSQT1vuQcZjb6daf7UVjJiQ3oe?= =?us-ascii?Q?jVrt5JACaWpuW/x1Ncs7Oc6EUZcxkzXlcjhrn7R0ht9JrYnTHTx3ttyQUqtO?= =?us-ascii?Q?/Uw6mWN4WwupVNFkqj8xzCbnwQSwfu/Cl8Jdf6bFJAsRWEHLU2DMZ85b5RzZ?= =?us-ascii?Q?UWq/V0oXdcUlwYs3jmUB+UCWm4D8KQ1ZCoWRx2pSXfJkDrw/4q4tqhVuq4la?= =?us-ascii?Q?22IgAZfqxMNQO4ucbfcpVatosjM2py6yP51Bvf5idlaRnGIN7VmmYgKchlSZ?= =?us-ascii?Q?YOuGLIQdGyQPZRcbAjsOiZy+YpzXFKpC3RphN1jm4Vv+96CBItEqpHPw3VVw?= =?us-ascii?Q?tV0AE2ZuWlnsMR2UjjLDQA8/ODoMbNxIhHSoqRU/JVf2Qmn0yfTPp6Ek+tb/?= =?us-ascii?Q?mexHG7vgdM05QkD4HCDa5BquydRPdU980HdpoKBFGcsyCSXNoLafV1r92mYg?= =?us-ascii?Q?QUMmggYUIVBltkp49LiE84TDLpIPIBPqVHa86Do6tL1W+kMHP3HULtXSsDF5?= =?us-ascii?Q?54RIljviobGrbY0U+KWAdvpW5z5tOTG7SJCEtZmjNx+f3bR59gmwMSQUCqBo?= =?us-ascii?Q?A8Nduhh85bgeLq6pFcKKxO3m3IcX5sI+8K1HfNYUJEuFF8UIoojsbwVr58bh?= =?us-ascii?Q?uUG8G+y74PMj8bfGueOJippXA6qyOVzWpBkgBml/VIKTBkJcheAmVCvilEst?= =?us-ascii?Q?rWqYIFtY7vP91OJKicOxxPuScNNj28dOteQW8xlid69vNOPOn37LXW12EdH7?= =?us-ascii?Q?qOQRmGYMmxdk741trYgYRER1NxuLBG8TlBxHPT04DaLgXTsFsrWP4p9GDPjD?= =?us-ascii?Q?nqmnHX4czBcDudFB+15834r7cPfTCKKRdUqHGoUUr4zKLaHePA0JBcuVJg/Y?= =?us-ascii?Q?kcLDhSq6okzVMHJxOIqMVC4zy9sIIf6jUyNRHiT5itxeE4GGXLlx+HPBjXJc?= =?us-ascii?Q?xxeSXn1cM7WkXtTCEs1QXO0PRRrEaHTGl1n0xy+BDBnHEa8vaYFlNGj2MxUd?= =?us-ascii?Q?lUM8XXmDZPs2ZzZ9ddx1wcj/VGo1jurw1yfR8+4e324bLMG1MsoQHWMHjYMm?= =?us-ascii?Q?FA=3D=3D?= X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH7PR84MB1885.NAMPRD84.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: 827bccba-a9ba-4364-bfb0-08d9dd7c8da5 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Jan 2022 07:55:27.0050 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 105b2061-b669-4b31-92ac-24d304d195dc X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: wSCkGITqPSBqcJ+Vs1SIhemOQZ+OC+uvQ15+Rlv/XFGa7WPtc08Le3Bbl79DprSVyMARkAIORG1WqYQsvhV4cw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR84MB1955 X-OriginatorOrg: hpe.com X-Proofpoint-GUID: vIxLb113wPByo7BKTjAWVzVcmF_wZqBv X-Proofpoint-ORIG-GUID: vIxLb113wPByo7BKTjAWVzVcmF_wZqBv X-Proofpoint-UnRewURL: 12 URL's were un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-22_03,2022-01-21_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 suspectscore=0 impostorscore=0 phishscore=0 bulkscore=0 mlxlogscore=999 adultscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2201220050 Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_PH7PR84MB188586B3EBF5D8F73466B950FF5C9PH7PR84MB1885NAMP_" --_000_PH7PR84MB188586B3EBF5D8F73466B950FF5C9PH7PR84MB1885NAMP_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Sunil, V2 sent. Thanks for the review. Abner ________________________________ From: Sunil V L Sent: Friday, January 21, 2022 10:53 PM To: devel@edk2.groups.io ; Chang, Abner (HPS SW/FW Te= chnologist) Cc: Schaefer, Daniel (ROM Janitor) Subject: Re: [edk2-devel] [edk2-platforms][PATCH 11/14] RISC-V/ProcessorPkg= : Address Core CI Spelling errors. On Fri, Jan 21, 2022 at 04:48:45PM +0800, Abner Chang wrote: > Signed-off-by: Abner Chang > Cc: Daniel Schaefer > Cc: Sunil V L > --- > .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 4 ++-- > .../RiscVFirmwareContextSbiLib.inf | 6 +++--- > .../RiscVFirmwareContextSscratchLib.inf | 4 ++-- > .../Include/Library/RiscVEdk2SbiLib.h | 16 ++++++++-------- > .../RISC-V/ProcessorPkg/Include/OpensbiTypes.h | 4 ++-- > .../Include/ProcessorSpecificHobData.h | 2 +- > .../Include/SmbiosProcessorSpecificData.h | 4 ++-- > .../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 16 ++++++++-------- > .../RiscVFirmwareContextSbiLib.c | 4 ++-- > .../RiscVFirmwareContextStvecLib.c | 4 ++-- > 10 files changed, 32 insertions(+), 32 deletions(-) > > diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silicon/= RISC-V/ProcessorPkg/RiscVProcessorPkg.dec > index 59634f4413..177c1a710d 100644 > --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec > +++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec > @@ -1,7 +1,7 @@ > -## @file RiscVProcesssorPkg.dec > +## @file RiscVProcessorPkg.dec > # This Package provides UEFI RISC-V processor modules and libraries. > # > -# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rig= hts reserved.
> +# Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiL= ib/RiscVFirmwareContextSbiLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/Ris= cVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf > index 0edf781149..1e4f14724b 100644 > --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/Risc= VFirmwareContextSbiLib.inf > +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/Risc= VFirmwareContextSbiLib.inf > @@ -1,9 +1,9 @@ > ## @file > -# Instance of OpebSBI Firmware Conext Library > +# Instance of OpenSBI Firmware Context Library > # > -# This iinstance uses RISC-V OpenSBI Firmware Extension SBI. > +# This instance uses RISC-V OpenSBI Firmware Extension SBI. > # > -# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All ri= ghts reserved.
> +# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscr= atchLib/RiscVFirmwareContextSscratchLib.inf b/Silicon/RISC-V/ProcessorPkg/L= ibrary/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf > index 750c1cf51f..09e635fd1d 100644 > --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib= /RiscVFirmwareContextSscratchLib.inf > +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib= /RiscVFirmwareContextSscratchLib.inf > @@ -1,9 +1,9 @@ > ## @file > -# Instance of OpebSBI Firmware Conext Library > +# Instance of OpenSBI Firmware Context Library > # > # This instance uses RISC-V Supervisor mode SCRATCH CSR > # > -# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All ri= ghts reserved.
> +# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. A= ll rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.= h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h > index 88d957f002..6089137373 100644 > --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h > +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h > @@ -1,7 +1,7 @@ > /** @file > Library to call the RISC-V SBI ecalls > > - Copyright (c) 2021, Hewlett Packard Development LP. All rights reserve= d.
> + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights re= served.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > > @@ -54,7 +54,7 @@ SbiGetSpecVersion ( > /** > Get the SBI implementation ID > > - This ID is used to idenetify a specific SBI implementation in order to= work > + This ID is used to identify a specific SBI implementation in order to = work > around any quirks it might have. > > @param[out] ImplId The ID of the SBI implementation. > @@ -275,7 +275,7 @@ SbiRemoteFenceI ( > /** > Instructs the remote harts to execute one or more SFENCE.VMA instructi= ons. > > - The SFENCE.VMA covers the range of virtual addresses between StartAadd= r and Size. > + The SFENCE.VMA covers the range of virtual addresses between StartAddr= and Size. > > The remote fence function acts as a full tlb flush if * StartAddr and = size > are both 0 * size is equal to 2^XLEN-1 > @@ -305,7 +305,7 @@ SbiRemoteSfenceVma ( > /** > Instructs the remote harts to execute one or more SFENCE.VMA instructi= ons. > > - The SFENCE.VMA covers the range of virtual addresses between StartAadd= r and Size. > + The SFENCE.VMA covers the range of virtual addresses between StartAddr= and Size. > Covers only the given ASID. > > The remote fence function acts as a full tlb flush if * StartAddr and = size > @@ -337,7 +337,7 @@ SbiRemoteSfenceVmaAsid ( > /** > Instructs the remote harts to execute one or more SFENCE.GVMA instruct= ions. > > - The SFENCE.GVMA covers the range of virtual addresses between StartAad= dr and Size. > + The SFENCE.GVMA covers the range of virtual addresses between StartAdd= r and Size. > Covers only the given VMID. > This function call is only valid for harts implementing the hypervisor= extension. > > @@ -373,7 +373,7 @@ SbiRemoteHfenceGvmaVmid ( > /** > Instructs the remote harts to execute one or more SFENCE.GVMA instruct= ions. > > - The SFENCE.GVMA covers the range of virtual addresses between StartAad= dr and Size. > + The SFENCE.GVMA covers the range of virtual addresses between StartAdd= r and Size. > This function call is only valid for harts implementing the hypervisor= extension. > > The remote fence function acts as a full tlb flush if * StartAddr and = size > @@ -407,7 +407,7 @@ SbiRemoteHfenceGvma ( > /** > Instructs the remote harts to execute one or more SFENCE.VVMA instruct= ions. > > - The SFENCE.GVMA covers the range of virtual addresses between StartAad= dr and Size. > + The SFENCE.GVMA covers the range of virtual addresses between StartAdd= r and Size. > Covers only the given ASID. > This function call is only valid for harts implementing the hypervisor= extension. > > @@ -443,7 +443,7 @@ SbiRemoteHfenceVvmaAsid ( > /** > Instructs the remote harts to execute one or more SFENCE.VVMA instruct= ions. > > - The SFENCE.GVMA covers the range of virtual addresses between StartAad= dr and Size. > + The SFENCE.GVMA covers the range of virtual addresses between StartAdd= r and Size. > This function call is only valid for harts implementing the hypervisor= extension. > > The remote fence function acts as a full tlb flush if * StartAddr and = size > diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/Silicon= /RISC-V/ProcessorPkg/Include/OpensbiTypes.h > index 8a6ea97708..ca7fc7a4ac 100644 > --- a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h > +++ b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h > @@ -1,7 +1,7 @@ > /** @file > - RISC-V OpesbSBI header file reference. > + RISC-V OpensbiSBI header file reference. Please change to just OpenSBI. > > - Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rig= hts reserved.
> + Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > > diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData= .h b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h > index 97285289f7..4b2a92e2f2 100644 > --- a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h > +++ b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h > @@ -29,7 +29,7 @@ typedef struct { > EFI_GUID CoreGuid; > VOID *Context; // The additional information of this core w= hich > // built in PEI phase and carried to DXE pha= se. > - // The content is pocessor or platform speci= fic. > + // The content is processor or platform spec= ific. > SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData; > } RISC_V_PROCESSOR_SPECIFIC_HOB_DATA; > > diff --git a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificD= ata.h b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h > index 81e48cd068..85b8dcbe20 100644 > --- a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h > +++ b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h > @@ -1,9 +1,9 @@ > /** @file > Industry Standard Definitions of RISC-V Processor Specific data define= d in > - below link for complaiant with SMBIOS Table Specification v3.3.0. > + below link for compliant with SMBIOS Table Specification v3.3.0. > https://github.com/riscv/riscv-smbios > > - Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rig= hts reserved.
> + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > > diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk= 2SbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2Sb= iLib.c > index 319526ed8f..a51139542d 100644 > --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib= .c > +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib= .c > @@ -15,7 +15,7 @@ > - SbiLegacyRemoteSfenceVmaAsid -> Use SbiRemoteSfenceVmaAsid > - SbiLegacyShutdown -> Wait for new System Reset extension > > - Copyright (c) 2021, Hewlett Packard Development LP. All rights reserve= d.
> + Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights re= served.
> SPDX-License-Identifier: BSD-2-Clause-Patent > > @par Revision Reference: > @@ -173,7 +173,7 @@ SbiGetSpecVersion ( > /** > Get the SBI implementation ID > > - This ID is used to idenetify a specific SBI implementation in order to= work > + This ID is used to identify a specific SBI implementation in order to = work > around any quirks it might have. > > @param[out] ImplId The ID of the SBI implementation. > @@ -441,7 +441,7 @@ SbiRemoteFenceI ( > /** > Instructs the remote harts to execute one or more SFENCE.VMA instructi= ons. > > - The SFENCE.VMA covers the range of virtual addresses between StartAadd= r and Size. > + The SFENCE.VMA covers the range of virtual addresses between StartAddr= and Size. > > The remote fence function acts as a full tlb flush if * StartAddr and = size > are both 0 * size is equal to 2^XLEN-1 > @@ -483,7 +483,7 @@ SbiRemoteSfenceVma ( > /** > Instructs the remote harts to execute one or more SFENCE.VMA instructi= ons. > > - The SFENCE.VMA covers the range of virtual addresses between StartAadd= r and Size. > + The SFENCE.VMA covers the range of virtual addresses between StartAddr= and Size. > Covers only the given ASID. > > The remote fence function acts as a full tlb flush if * StartAddr and = size > @@ -528,7 +528,7 @@ SbiRemoteSfenceVmaAsid ( > /** > Instructs the remote harts to execute one or more SFENCE.GVMA instruct= ions. > > - The SFENCE.GVMA covers the range of virtual addresses between StartAad= dr and Size. > + The SFENCE.GVMA covers the range of virtual addresses between StartAdd= r and Size. > Covers only the given VMID. > This function call is only valid for harts implementing the hypervisor= extension. > > @@ -577,7 +577,7 @@ SbiRemoteHFenceGvmaVmid ( > /** > Instructs the remote harts to execute one or more SFENCE.GVMA instruct= ions. > > - The SFENCE.GVMA covers the range of virtual addresses between StartAad= dr and Size. > + The SFENCE.GVMA covers the range of virtual addresses between StartAdd= r and Size. > This function call is only valid for harts implementing the hypervisor= extension. > > The remote fence function acts as a full tlb flush if * StartAddr and = size > @@ -623,7 +623,7 @@ SbiRemoteHFenceGvma ( > /** > Instructs the remote harts to execute one or more SFENCE.VVMA instruct= ions. > > - The SFENCE.GVMA covers the range of virtual addresses between StartAad= dr and Size. > + The SFENCE.GVMA covers the range of virtual addresses between StartAdd= r and Size. > Covers only the given ASID. > This function call is only valid for harts implementing the hypervisor= extension. > > @@ -672,7 +672,7 @@ SbiRemoteHFenceVvmaAsid ( > /** > Instructs the remote harts to execute one or more SFENCE.VVMA instruct= ions. > > - The SFENCE.GVMA covers the range of virtual addresses between StartAad= dr and Size. > + The SFENCE.GVMA covers the range of virtual addresses between StartAdd= r and Size. > This function call is only valid for harts implementing the hypervisor= extension. > > The remote fence function acts as a full tlb flush if * StartAddr and = size > diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiL= ib/RiscVFirmwareContextSbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscV= FirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c > index 6125618eaf..a2a18d3eb7 100644 > --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/Risc= VFirmwareContextSbiLib.c > +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/Risc= VFirmwareContextSbiLib.c > @@ -1,8 +1,8 @@ > /** @file > - This iinstance uses RISC-V OpenSBI Firmware Extension SBI to > + This instance uses RISC-V OpenSBI Firmware Extension SBI to > get the pointer of firmware context. > > - Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All righ= ts reserved.
> + Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All= rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > **/ > diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStve= cLib/RiscVFirmwareContextStvecLib.c b/Silicon/RISC-V/ProcessorPkg/Library/R= iscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c > index 7d1675355a..d08b51d3d9 100644 > --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/Ri= scVFirmwareContextStvecLib.c > +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/Ri= scVFirmwareContextStvecLib.c > @@ -1,8 +1,8 @@ > /** @file > - This instance uses This iinstance Supervisor mode STVEC CSR to > + This instance uses This instance Supervisor mode STVEC CSR to Please remove extra "This instance" Regards Sunil > get/set the pointer of firmware context. > > - Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All righ= ts reserved.
> + Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All= rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > **/ > -- > 2.31.1 > > > >=20 > > --_000_PH7PR84MB188586B3EBF5D8F73466B950FF5C9PH7PR84MB1885NAMP_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable
Hi Sunil, V2 sent.

Thanks for the review.
Abner
From: Sunil V L <sunilvl= @ventanamicro.com>
Sent: Friday, January 21, 2022 10:53 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>; Chang, Abner = (HPS SW/FW Technologist) <abner.chang@hpe.com>
Cc: Schaefer, Daniel (ROM Janitor) <daniel.schaefer@hpe.com> Subject: Re: [edk2-devel] [edk2-platforms][PATCH 11/14] RISC-V/Proce= ssorPkg: Address Core CI Spelling errors.
 
On Fri, Jan 21, 2022 at 04:48:45PM +0800, Abner Ch= ang wrote:
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
> Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
> Cc: Sunil V L <sunilvl@ventanamicro.com>
> ---
>  .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec    = |  4 ++--
>  .../RiscVFirmwareContextSbiLib.inf     =           |  6 +++---
>  .../RiscVFirmwareContextSscratchLib.inf    &= nbsp;     |  4 ++--
>  .../Include/Library/RiscVEdk2SbiLib.h    &nb= sp;       | 16 ++++++++--------
>  .../RISC-V/ProcessorPkg/Include/OpensbiTypes.h   |&nbs= p; 4 ++--
>  .../Include/ProcessorSpecificHobData.h    &n= bsp;      |  2 +-
>  .../Include/SmbiosProcessorSpecificData.h    = ;    |  4 ++--
>  .../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c    = | 16 ++++++++--------
>  .../RiscVFirmwareContextSbiLib.c     &n= bsp;           |  4 = ++--
>  .../RiscVFirmwareContextStvecLib.c     =           |  4 ++--
>  10 files changed, 32 insertions(+), 32 deletions(-)
>
> diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silic= on/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> index 59634f4413..177c1a710d 100644
> --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> +++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> @@ -1,7 +1,7 @@
> -## @file  RiscVProcesssorPkg.dec
> +## @file  RiscVProcessorPkg.dec
>  # This Package provides UEFI RISC-V processor modules and librar= ies.
>  #
> -# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All = rights reserved.<BR>
> +# Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP.= All rights reserved.<BR>
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent
>  #
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextS= biLib/RiscVFirmwareContextSbiLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/= RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> index 0edf781149..1e4f14724b 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/R= iscVFirmwareContextSbiLib.inf
> +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/R= iscVFirmwareContextSbiLib.inf
> @@ -1,9 +1,9 @@
>  ## @file
> -# Instance of OpebSBI Firmware Conext Library
> +# Instance of OpenSBI Firmware Context Library
>  #
> -# This iinstance uses RISC-V OpenSBI Firmware Extension SBI.
> +# This instance uses RISC-V OpenSBI Firmware Extension SBI.
>  #
> -#  Copyright (c) 2021, Hewlett Packard Enterprise Development LP= . All rights reserved.<BR>
> +#  Copyright (c) 2021-2022, Hewlett Packard Enterprise Developme= nt LP. All rights reserved.<BR>
>  #
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent
>  #
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextS= scratchLib/RiscVFirmwareContextSscratchLib.inf b/Silicon/RISC-V/ProcessorPk= g/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.i= nf
> index 750c1cf51f..09e635fd1d 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratch= Lib/RiscVFirmwareContextSscratchLib.inf
> +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratch= Lib/RiscVFirmwareContextSscratchLib.inf
> @@ -1,9 +1,9 @@
>  ## @file
> -# Instance of OpebSBI Firmware Conext Library
> +# Instance of OpenSBI Firmware Context Library
>  #
>  # This instance uses RISC-V Supervisor mode SCRATCH CSR
>  #
> -#  Copyright (c) 2021, Hewlett Packard Enterprise Development LP= . All rights reserved.<BR>
> +#  Copyright (c) 2021-2022, Hewlett Packard Enterprise Developme= nt LP. All rights reserved.<BR>
>  #
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent
>  #
> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiL= ib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
> index 88d957f002..6089137373 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h > +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h > @@ -1,7 +1,7 @@
>  /** @file
>    Library to call the RISC-V SBI ecalls
> 
> -  Copyright (c) 2021, Hewlett Packard Development LP. All rights= reserved.<BR>
> +  Copyright (c) 2021-2022, Hewlett Packard Development LP. All r= ights reserved.<BR>
> 
>    SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> @@ -54,7 +54,7 @@ SbiGetSpecVersion (
>  /**
>    Get the SBI implementation ID
> 
> -  This ID is used to idenetify a specific SBI implementation in = order to work
> +  This ID is used to identify a specific SBI implementation in o= rder to work
>    around any quirks it might have.
> 
>    @param[out] ImplId     &nbs= p;         The ID of the SBI implem= entation.
> @@ -275,7 +275,7 @@ SbiRemoteFenceI (
>  /**
>    Instructs the remote harts to execute one or more SF= ENCE.VMA instructions.
> 
> -  The SFENCE.VMA covers the range of virtual addresses between S= tartAaddr and Size.
> +  The SFENCE.VMA covers the range of virtual addresses between S= tartAddr and Size.
> 
>    The remote fence function acts as a full tlb flush i= f * StartAddr and size
>    are both 0 * size is equal to 2^XLEN-1
> @@ -305,7 +305,7 @@ SbiRemoteSfenceVma (
>  /**
>    Instructs the remote harts to execute one or more SF= ENCE.VMA instructions.
> 
> -  The SFENCE.VMA covers the range of virtual addresses between S= tartAaddr and Size.
> +  The SFENCE.VMA covers the range of virtual addresses between S= tartAddr and Size.
>    Covers only the given ASID.
> 
>    The remote fence function acts as a full tlb flush i= f * StartAddr and size
> @@ -337,7 +337,7 @@ SbiRemoteSfenceVmaAsid (
>  /**
>    Instructs the remote harts to execute one or more SF= ENCE.GVMA instructions.
> 
> -  The SFENCE.GVMA covers the range of virtual addresses between = StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between = StartAddr and Size.
>    Covers only the given VMID.
>    This function call is only valid for harts implement= ing the hypervisor extension.
> 
> @@ -373,7 +373,7 @@ SbiRemoteHfenceGvmaVmid (
>  /**
>    Instructs the remote harts to execute one or more SF= ENCE.GVMA instructions.
> 
> -  The SFENCE.GVMA covers the range of virtual addresses between = StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between = StartAddr and Size.
>    This function call is only valid for harts implement= ing the hypervisor extension.
> 
>    The remote fence function acts as a full tlb flush i= f * StartAddr and size
> @@ -407,7 +407,7 @@ SbiRemoteHfenceGvma (
>  /**
>    Instructs the remote harts to execute one or more SF= ENCE.VVMA instructions.
> 
> -  The SFENCE.GVMA covers the range of virtual addresses between = StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between = StartAddr and Size.
>    Covers only the given ASID.
>    This function call is only valid for harts implement= ing the hypervisor extension.
> 
> @@ -443,7 +443,7 @@ SbiRemoteHfenceVvmaAsid (
>  /**
>    Instructs the remote harts to execute one or more SF= ENCE.VVMA instructions.
> 
> -  The SFENCE.GVMA covers the range of virtual addresses between = StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between = StartAddr and Size.
>    This function call is only valid for harts implement= ing the hypervisor extension.
> 
>    The remote fence function acts as a full tlb flush i= f * StartAddr and size
> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/Sili= con/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
> index 8a6ea97708..ca7fc7a4ac 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
> +++ b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
> @@ -1,7 +1,7 @@
>  /** @file
> -  RISC-V OpesbSBI header file reference.
> +  RISC-V OpensbiSBI header file reference.

Please change to just OpenSBI.

> 
> -  Copyright (c) 2020, Hewlett Packard Enterprise Development LP.= All rights reserved.<BR>
> +  Copyright (c) 2020-2022, Hewlett Packard Enterprise Developmen= t LP. All rights reserved.<BR>
> 
>    SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobD= ata.h b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
> index 97285289f7..4b2a92e2f2 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h > +++ b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h > @@ -29,7 +29,7 @@ typedef struct {
>    EFI_GUID CoreGuid;
>    VOID     *Context;  &n= bsp;     // The additional information of this core whi= ch
>            = ;            &n= bsp;     // built in PEI phase and carried to DXE phase= .
> -           &nb= sp;            =     // The content is pocessor or platform specific.
> +           &nb= sp;            =     // The content is processor or platform specific.
>    SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpeci= ficData;
>  } RISC_V_PROCESSOR_SPECIFIC_HOB_DATA;
> 
> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecif= icData.h b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.= h
> index 81e48cd068..85b8dcbe20 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.= h
> +++ b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.= h
> @@ -1,9 +1,9 @@
>  /** @file
>    Industry Standard Definitions of RISC-V Processor Sp= ecific data defined in
> -  below link for complaiant with SMBIOS Table Specification v3.3= .0.
> +  below link for compliant with SMBIOS Table Specification v3.3.= 0.
>    ht= tps://github.com/riscv/riscv-smbios
> 
> -  Copyright (c) 2019, Hewlett Packard Enterprise Development LP.= All rights reserved.<BR>
> +  Copyright (c) 2019-2022, Hewlett Packard Enterprise Developmen= t LP. All rights reserved.<BR>
> 
>    SPDX-License-Identifier: BSD-2-Clause-Patent
> 
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscV= Edk2SbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk= 2SbiLib.c
> index 319526ed8f..a51139542d 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2Sbi= Lib.c
> +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2Sbi= Lib.c
> @@ -15,7 +15,7 @@
>    - SbiLegacyRemoteSfenceVmaAsid -> Use SbiRemoteSf= enceVmaAsid
>    - SbiLegacyShutdown     &nb= sp;      -> Wait for new System Reset extension=
> 
> -  Copyright (c) 2021, Hewlett Packard Development LP. All rights= reserved.<BR>
> +  Copyright (c) 2021-2022, Hewlett Packard Development LP. All r= ights reserved.<BR>
>    SPDX-License-Identifier: BSD-2-Clause-Patent
> 
>    @par Revision Reference:
> @@ -173,7 +173,7 @@ SbiGetSpecVersion (
>  /**
>    Get the SBI implementation ID
> 
> -  This ID is used to idenetify a specific SBI implementation in = order to work
> +  This ID is used to identify a specific SBI implementation in o= rder to work
>    around any quirks it might have.
> 
>    @param[out] ImplId     &nbs= p;         The ID of the SBI implem= entation.
> @@ -441,7 +441,7 @@ SbiRemoteFenceI (
>  /**
>    Instructs the remote harts to execute one or more SF= ENCE.VMA instructions.
> 
> -  The SFENCE.VMA covers the range of virtual addresses between S= tartAaddr and Size.
> +  The SFENCE.VMA covers the range of virtual addresses between S= tartAddr and Size.
> 
>    The remote fence function acts as a full tlb flush i= f * StartAddr and size
>    are both 0 * size is equal to 2^XLEN-1
> @@ -483,7 +483,7 @@ SbiRemoteSfenceVma (
>  /**
>    Instructs the remote harts to execute one or more SF= ENCE.VMA instructions.
> 
> -  The SFENCE.VMA covers the range of virtual addresses between S= tartAaddr and Size.
> +  The SFENCE.VMA covers the range of virtual addresses between S= tartAddr and Size.
>    Covers only the given ASID.
> 
>    The remote fence function acts as a full tlb flush i= f * StartAddr and size
> @@ -528,7 +528,7 @@ SbiRemoteSfenceVmaAsid (
>  /**
>    Instructs the remote harts to execute one or more SF= ENCE.GVMA instructions.
> 
> -  The SFENCE.GVMA covers the range of virtual addresses between = StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between = StartAddr and Size.
>    Covers only the given VMID.
>    This function call is only valid for harts implement= ing the hypervisor extension.
> 
> @@ -577,7 +577,7 @@ SbiRemoteHFenceGvmaVmid (
>  /**
>    Instructs the remote harts to execute one or more SF= ENCE.GVMA instructions.
> 
> -  The SFENCE.GVMA covers the range of virtual addresses between = StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between = StartAddr and Size.
>    This function call is only valid for harts implement= ing the hypervisor extension.
> 
>    The remote fence function acts as a full tlb flush i= f * StartAddr and size
> @@ -623,7 +623,7 @@ SbiRemoteHFenceGvma (
>  /**
>    Instructs the remote harts to execute one or more SF= ENCE.VVMA instructions.
> 
> -  The SFENCE.GVMA covers the range of virtual addresses between = StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between = StartAddr and Size.
>    Covers only the given ASID.
>    This function call is only valid for harts implement= ing the hypervisor extension.
> 
> @@ -672,7 +672,7 @@ SbiRemoteHFenceVvmaAsid (
>  /**
>    Instructs the remote harts to execute one or more SF= ENCE.VVMA instructions.
> 
> -  The SFENCE.GVMA covers the range of virtual addresses between = StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between = StartAddr and Size.
>    This function call is only valid for harts implement= ing the hypervisor extension.
> 
>    The remote fence function acts as a full tlb flush i= f * StartAddr and size
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextS= biLib/RiscVFirmwareContextSbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/Ri= scVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
> index 6125618eaf..a2a18d3eb7 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/R= iscVFirmwareContextSbiLib.c
> +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/R= iscVFirmwareContextSbiLib.c
> @@ -1,8 +1,8 @@
>  /** @file
> -  This iinstance uses RISC-V OpenSBI Firmware Extension SBI to > +  This instance uses RISC-V OpenSBI Firmware Extension SBI to >    get the pointer of firmware context.
> 
> -  Copyright (c) 2021 Hewlett Packard Enterprise Development LP. = All rights reserved.<BR>
> +  Copyright (c) 2021-2022 Hewlett Packard Enterprise Development= LP. All rights reserved.<BR>
> 
>    SPDX-License-Identifier: BSD-2-Clause-Patent
>  **/
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextS= tvecLib/RiscVFirmwareContextStvecLib.c b/Silicon/RISC-V/ProcessorPkg/Librar= y/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
> index 7d1675355a..d08b51d3d9 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib= /RiscVFirmwareContextStvecLib.c
> +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib= /RiscVFirmwareContextStvecLib.c
> @@ -1,8 +1,8 @@
>  /** @file
> -  This instance uses This iinstance Supervisor mode STVEC CSR to=
> +  This instance uses This instance Supervisor mode STVEC CSR to<= br>
Please remove extra "This instance"

Regards
Sunil
>    get/set the pointer of firmware context.
> 
> -  Copyright (c) 2021 Hewlett Packard Enterprise Development LP. = All rights reserved.<BR>
> +  Copyright (c) 2021-2022 Hewlett Packard Enterprise Development= LP. All rights reserved.<BR>
> 
>    SPDX-License-Identifier: BSD-2-Clause-Patent
>  **/
> --
> 2.31.1
>
>
>
>
>
>
--_000_PH7PR84MB188586B3EBF5D8F73466B950FF5C9PH7PR84MB1885NAMP_--