* Re: [edk2-devel] [PATCH 3/3] RiscVQemuServerPlatform: create qemu-based server reference board
2024-02-29 15:24 ` [edk2-devel] [PATCH 3/3] RiscVQemuServerPlatform: create qemu-based server reference board Chai, Evan
@ 2024-03-01 23:55 ` Andrei Warkentin
0 siblings, 0 replies; 5+ messages in thread
From: Andrei Warkentin @ 2024-03-01 23:55 UTC (permalink / raw)
To: Chai, Evan, devel@edk2.groups.io; +Cc: Sunil V L, Li, Yong
Evan,
The goal of RiscVQemuServerPlatform has been to create a UEFI implementation that would be (and remain) compliant to the BRS (and eventually - server platform). Another goal is to provide a reference implementation that others could follow in terms of best practices on real hardware. Anything that doesn't serve these two goals is not worth pursuing.
- There's no value to remove/replace any virtio drivers. Real hardware could theoretically have hardware that implements virtio interfaces (e.g. DPUs do that today).
- There's no value to remove FdtLib/FdtClientDxe dependencies. Removing self-configuration just leaves you with a more primitive implementation, that you will have to keep in sync if/when you make any changes to the Qemu virtual platform devices/memory map. Long term, such a reference implementation should adopt https://github.com/intel/FdtBusPkg (https://www.youtube.com/watch?v=9RqKq4wGYZI), so removing existing Fdt dependencies just doesn't make any sense.
- You could maybe argue for removing fw_cfg as a mechanism to sync boot options with qemu, but even here, real server systems frequently sync their boot options (or at least override) with BMC/LOM.
- Moving away from OVMF components towards generic ones is, in general, a good thing. But it's probably not the right time to completely separate RiscVQemuServerPlatform from OVMF - there's no reason to avoid using OVMF libs/drivers when these make sense (and unless you're moving towards an FdtBusPkg-based implementation, I don't see why they wouldn't).
In short, RiscVQemuServerPlatform shouldn't be about busywork of /removing/ things from Ovmf/RiscVVirt. It should be about:
a) Avoiding things that violate the BRS.
b) Implementing things that are BRS requirements or optionals.
A
> -----Original Message-----
> From: Chai, Evan <evan.chai@intel.com>
> Sent: Thursday, February 29, 2024 9:25 AM
> To: devel@edk2.groups.io
> Cc: Warkentin, Andrei <andrei.warkentin@intel.com>; Sunil V L
> <sunilvl@ventanamicro.com>; Li, Yong <yong.li@intel.com>
> Subject: [PATCH 3/3] RiscVQemuServerPlatform: create qemu-based server
> reference board
>
> 1.Reimplemented SecMain to create a Hob for the entire Variable
> region, preventing unauthorized access to this area. As a result,
> VirtNorFlashDxe has been reimplemented without the need for GCD
> mapping of Variable. The change addresses the dependency issue
> between VirtNorFlashDxe and VariableRuntimeDxe.
> 2.Define PcdPciExpressBaseAddress = 0x30000000 by the default dtb
> created by Qemu 'ssoc_ref'(server soc reference model), then
> PciExpressLib can be replaced by the MdePkg version.
> 3.Reconstructed PciHostBridgeLib based on generic ECAM topology,
> removing dependencies on Fdtlib and adopting PCD more extensively
> for configuration parameters. The current PCI configuration
> information for ECAM still relies on the device tree established
> by Qemu.
> 4.Reimplemented VirtNorFlashPlatformLib with static value.
>
> Cc: Andrei Warkentin <andrei.warkentin@intel.com>
> Cc: Sunil V L <sunilvl@ventanamicro.com>
> Cc: Yong Li <yong.li@intel.com>
> Signed-off-by: Evan Chai <evan.chai@intel.com>
> ---
> Platform/Qemu/RiscVQemuServerPlatform/Documents/Media/Hand-Off-Block-
> Hob-List.jpg | Bin 0 -> 16901 bytes
>
> Platform/Qemu/RiscVQemuServerPlatform/Documents/Media/PI_Boot_Phases.j
> pg | Bin 0 -> 196120 bytes
> Platform/Qemu/RiscVQemuServerPlatform/Documents/Media/RISC-
> V_Platform_EDK2_Firmware_Enabling_Philosophy.jpg | Bin 0 -> 329871 bytes
>
> Platform/Qemu/RiscVQemuServerPlatform/Documents/Media/V2_DXE_Foundati
> on-3.jpg | Bin 0 -> 51521 bytes
>
> Platform/Qemu/RiscVQemuServerPlatform/Library/PciHostBridgeLibEcam/PciHos
> tBridgeLibEcam.c | 386
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++
>
> Platform/Qemu/RiscVQemuServerPlatform/Library/PciHostBridgeLibEcam/PciHos
> tBridgeLibEcam.inf | 49
> ++++++++++++++++++++++++++++++++++++++++++++++++
>
> Platform/Qemu/RiscVQemuServerPlatform/Library/VirtNorFlashPlatformLib/Virt
> NorFlashStaticLib.c | 42
> ++++++++++++++++++++++++++++++++++++++++++
>
> Platform/Qemu/RiscVQemuServerPlatform/Library/VirtNorFlashPlatformLib/Virt
> NorFlashStaticLib.inf | 32 ++++++++++++++++++++++++++++++++
> Platform/Qemu/RiscVQemuServerPlatform/Readme.md
> | 327
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.dsc
> | 703
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++
> Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.fdf
> | 284
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++++
> Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.fdf.inc
> | 42 ++++++++++++++++++++++++++++++++++++++++++
> Platform/Qemu/RiscVQemuServerPlatform/Sec/Cpu.c
> | 33 +++++++++++++++++++++++++++++++++
> Platform/Qemu/RiscVQemuServerPlatform/Sec/Memory.c
> | 318
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++
> Platform/Qemu/RiscVQemuServerPlatform/Sec/Platform.c
> | 160
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++
> Platform/Qemu/RiscVQemuServerPlatform/Sec/SecEntry.S
> | 19 +++++++++++++++++++
> Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.c
> | 110
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++
> Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.h
> | 104
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++
> Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.inf
> | 67
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +
> Platform/Qemu/RiscVQemuServerPlatform/VarStore.fdf.inc
> | 72
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++
> Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlash.c
> | 742
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++
> Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlash.h
> | 345
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++
> Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashDxe.c
> | 447
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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> +++++++++++++++++++++++++++++++++++++++++++++++
> Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashDxe.inf
> | 69
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++
> Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashFvb.c
> | 904
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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> +++++++++++++++++++++++++++++++++++++++
> 25 files changed, 5255 insertions(+)
>
> diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Documents/Media/Hand-
> Off-Block-Hob-List.jpg
> b/Platform/Qemu/RiscVQemuServerPlatform/Documents/Media/Hand-Off-
> Block-Hob-List.jpg
> new file mode 100755
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> zYlnl36No{bgQ}f}CIyFnD-q&T$uW+GS7c7XC46Io&G`3`ZGJ~L!>%GdfVhb>Oe*Za
> z>MW)0=`7W6Ox<DLT8Kpd$?j(tW_p1DkEUq)>?L~xVbAFY(Z%{rDSJInZ)C7^+*x<n
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> z#xd@nOmh#CKBh~1n4@EQyIndP?ZEA!U`|xo+2Nn0l7aOt2G`-
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> zJo@932=OqZ4BZxTVWEebe~ae(;@yq64C6gUMy5M4Cv`wc$U1Bvoy;4mfJZhFzSc
> _;
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> zRqr*PRIXPiMX@kjDbcNSU$Tp|Yit==-
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> z8UW#jy4)qPZR80GJsn@~?s7-
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> z=xe}ShXC2?6l;1sLIeuy&=MHg5mw)eC1RJc#;^JKDr63|TRM3>&OONc$>OkGY*!`v
> zbZpie?()MeKI!RLa%!<F0?7CKxIuP&Mb6Sd=p7&^|MwZ;FxeXy37{Z*+6Y4kTBm_7
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> literal 0
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>
> diff --git
> a/Platform/Qemu/RiscVQemuServerPlatform/Documents/Media/PI_Boot_Phase
> s.jpg
> b/Platform/Qemu/RiscVQemuServerPlatform/Documents/Media/PI_Boot_Phase
> s.jpg
> new file mode 100755
> index
> 0000000000000000000000000000000000000000..e5f053c0aa4b7e82dc55e140
> 5bd749a7af555ab4
> GIT binary patch
> literal 196120
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> z0yhC);1=Kq_=7*a0Z%{{5CeV#uLgkUZUBf(Kn8?E!qwm3M?*ou%TNBMqqn`2yo0x
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> zU?d|r^qB9F7gv|q_7@<m=fAP<KQ2oD@jLJz^?|mdDl%yqPu6y~qV@n?zA=nEg?$
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> zXOo0ji<D0M=!L;kce<@cN_U(f4QGJRR2H<wTk18B)X#>oG|d8HD~y$F`0U=+&PAr
> (
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> zi}8NF=A&Y+M9iUZSzX&5Pv|G<)oVau5^*iWmz|ElORJ5<>h3Z4_zW$^(W%74a~+
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> z=-
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> z?)1fZNg<BDbW5QxO0NNqEk0O}+X0XqRR#lcO1uH`U@3C=LDpmh<|TT4Zxwn1It
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> zmt^|eC@wYeO+$YkWQCtMvv?nIFlYhWE_?_3GzXXJE#V06Y1tGV<)U6CPq)mNt4
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> zRmARPmWJHgo7H3z`4D64uFUXENg=;a@85#V<<(!w3;s9Bm=9#QaPpxO>>R3Kr
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> z{Pl#N9TmDnx^a5v1C0r#8=X2<C#wFk8M;Tn;5)i|)je*3sI;7%x4k3P_iHHmZ%EGn
> z(wYC4;N;(phm4tUL)CG<3vZfjrr3QvThvzguM|9NoNnWUl)XB7=mqj!u_+Gaj1s;M
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> z$P1o?1#X7k8l;|I7T)jgHoTJ~$`$nSiv#&mTZI~@U_`2}$oWgk*EKsb2g)o<)m3#r
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> wYjj_F?4Lkc48fwhv5Q
> z0d<qSrdAzM(*1+2#J(l`vARp29s}Lc(iu=Qym|PyVc^`>JOt1^rwc4hwsAl>wXPQ*
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> z|2-h2eu{LVsFe}KuhsbQ;bSc`Em#qQ%gLP#1F7p=cNH&&2TeqAgwWcDSqGAax`6-
> B
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> zb;kyyJq0j?7C=VH+%`e%B2WJM8ydvov>#+`7?Rl7gbA!eVLR2h8T|GdsTVci1DypH
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> zr^D`t&^W$Sc!d1e6WuO&&Fs+|*@g?xng4!*zxV%tS2^I{6~+JR`{MuaEuP~@X+*?
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> z2y?NjA7oBGBJ=um2*NE9Pj;SqABNH{^YVw`BSQo%Gv_&uGN1Us?Hpg#9x3+ZL2
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> zdmYclA?vNwuitp9(eaEHC&fs<*0kVy@HqT7XY!#ex?4vVc^7*^q7!6b@T$_DDQ?T
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> zo(rQB!N~{yAUkIP9XHvdN1-Yq@J2x_hWKIyx~bgPAo0&|H4kvSLIu=&PR~FwKFEx}
> z7N>q)^n!J-0}P$PI14<lzCz=4ufY}7Cg_1eP-YvEV{5B;c^BLmJT+t68-R`{*w+Z9
> z2j`QHN0DmukbBZgOR#|rlA?M5dIj7D%4Q$v6rUbXefylOk*Clr5H~bAoG8`{oj8jf
> z&f4S7`f47`v(o9?7xtNMguPAX?H<awgTGuZSv7T$L9Hm3;@J}AC!q_jw`$(d-F|tD
> z?I~cde3LnYO?l)c{c+&_wbL7>uiamHmNY|Z+o{^djtawB^@nBCRj}Aa(cJnsLyK`E
> z1H}gSqaNvA8c@1N<*ezk(c;bjcqdPv&q^0-Fbt_+FQ3(h$X`k!-OBm{QU8CVc+*|9
> zZf%8n4dMnIc>0{ZIfgVy?fbVETtjWwX6nx7D2|W&c5|fl0@$p&7(BB{0aIuKJCby<
> zpz<QT@iE@|2bsM(kw<yKy18B_ftQ=bhE9Q6`IN7Nks2q7siKX@2xSKqkY(_63&Vf
> A
> zg)$F5#1a$y?b0?QI%*O+VF0Fpj@!5~5^Wn0JSh<PJdt~sd?bNi?Et{)t&5WoSvsVL
> z|A)V<8aa{BbqA-4qreEtFY1IBCf%m!rq2&IYGL$#jM||3l1fNJTB47RcVxx1DdJEe
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> z55Z=y!skEY*Fd{PbAW0j|1{_#|DXJJmJRGqkJR}b{H?{ddJ=ynOCncZej+vTK}z71
> z3-^nAM;wdUa4+3Z_i{KV6@Y023ovbf?pD~`s!-Ba%IEF2tdF<kXalO-0(bKNvF`be
> zr_aAq7noWAhN4BnV2wuBfNw4~?3r7@b}S(4&ODVnz5c}!P#*F@D?C6DAgb>}zP
> Y-h
> zf1&D%=T1TfO#m|@`W>Tb)3;V&THSh}f&Pgsazr%fJa&2SW^i3~^RmE&3}WufoQ;
> Hs
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> znop-uC!Er|Q{2#eAlx2rBkTZhkaR);fLf?Kok_XA3I)N6*W)SunEPw@+v~}O3iBMU
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> z&!Xy2)DCB3SF9k35A7FYr?8Wi7I#J_^*ge$j^3msHiIa~IC9JbvmOrM6S;?fvrYVK
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> z{ojmO@{-hpK@&U;v_ag04cu&kV?;H`?p>hqD}dMV19cdPa--
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> z5dRqPb2A?t0VDsP0|TP#Uk#ZP<X;W~UZaASB)uq|BjN)90Nk;acx6R^a0D{VRzM5?
> z^}t9`V^5JzqFC>{`H~pai-?HtL`=U|#s1Wj{ZYUvF;BDldFZUotC4KwB2$o4gBJQ`
> zVVO)lqeO%~jg_yJP(t{5X~yj(LwuIPDTz}$UDNrqJEnz&3;mxnM0KSve361psHn5z
> zB|r*NLFSz#G~J|dtw~$~avM>@Spn-
> Xp>;}tRU;Wj+>$3oLR&MDE0VgNeB&O0Nj51+
> z2Qt&GoTl=z@ox_RMVY0IzNMUW1s!on;#m`|blwS%1Jk2Fa|Hc!u>T+C7UT*BJrC
> QR
> zPTbZjSK=5`FN^?v><%q|PJMk(@l4eemtNu!!J(k6Fle@`%2*=t*c&CrT#Je5?ht=U
> zrI$yi>5a^5;k(?4e86v&e~$FpqZ#iFqUPor$Tn302)p<+NBq4SGc9Gf(KxlT^xNZY
> zr>;nZrP;eP6h&X0QDXaYqF%_i_1InyY#G7`Z;zi;ConaWn6~+udT6{Y<m8?qZY9c8
> zh+UG)<eWnN`YVj^hrpQl)ffYOJjVo!%C*QOb)u#%iD|D_E2sYCtI7My=r?f7NlDaK
> z{L(&E9c1(3K@X0@fP>-(>6f_#azfEsB%Uvpz_+Y_>0rB%LAS7_RT&A=H=F|TSS1&T
> z9SzYF3fpu+(0NrH59v5aNssR{2SE!mcd51$IZO8uVdyVj8b8Qx!2+RJJpn-O^_@iQ
> zo$^uwiBAc<y0R__vBFD|{m&lnwaUVtf|MXtlbXT$_cWcaH4U110;v<m&2n4G#kN
> I^
> z!Ga{)2i<B!hod}*$soJA(}7-=q#^~ylr#V8GZpIB?>#gfrKK)jNc9kMTp%g*j?tl~
> z-?^ERs<x4P+}6|Vr${&3;Z^8OP7@O^8IV7lO(6Cu2I2G3s5egPyA)u01C^@wP`ep;
> zeQeqy0(zMwxk=R61pU>(-LeDb=Pv}n9^z%)w!$F?5G18lFi$?(1w<EZk>wtY)|5|L
> ztR6mM>yaFz_8BCZmjc*D+9Z1agfV=62bGOBZ`(aD!vShcNaE#~N+mo3U{>mN@
> NL#|
> za1XAT82Gdy*Kc`A13ndWPm7<-L-kLL4i5k05i|K+HP!!)i;cTpZQJe@lN0dO%b+f|
> zV8rieatb<~>jkQtU(-mDsZNDcQ|Q+f(C=GzCN(~Q!=*<)$fWR~5M9y9Q`{*cuv~_r
> zXf9i4h6%h;Zy4qfgtAu12`{gnFkGiD#QRy}Xlts$l=(%JnAfse*+mSty<x*;Gc=ZF
> z*!RF@GFafqkf9|>4Cmy!=T{E5avyD8#s`M=kl#CrIfoS-?RlRGZ>*jNPb-+fZ&~@P
> z-T=$YHiBWKDz75(Rle+3bJN{aS8u!e(vg(teUm$3I&Q_b+dcU%JCn$ln?#A$y)|RM
> z^FW_L&K9y<!fAgqHR=g{1eNkYyO&Bb9;rg=XopRe7d7fWY2a0Os!6UjMoD{A`h-L2
> zC^}nxYAN(o)u390vx?{a>B{cHYv1meb6?n%G410_ph=YMHK}3hPR6AnPU#ykRc>U
> *
> zId|0@6^(LG_MhVknX9y77h4y1-
> s0Del~9ni$2nH@78MnrTEbD5X?BoPX7!&ah`Co{
> zEL%S=6vmfQ*1K88PG1;Yw(qt%6QZ)6eC~R*^ij?n5OS5AMnUl+NtW4IzxxBX3^Y$
> =
> zPcc${rzm|sut+w=E-v#aznpU-onXE%v*6*Rhc++qe;POVfW_lT*i+stNfZorJ47p5
> z!m@CnUnBiSY+T8x8w^7_jr0EAOXBF!Ty@iytT%NVg57<-
> C@5{80IK&Hm6Q<>9zzR)
> zihT~RRV0=5>k*j-d7-1D?mAm+j#U{REP;jBr!EOYSm#}0N}CN7w>?55*Ze21$vPX2
> zNjMqPIu=XWCo+tBX2M?~8J^@`$ph+xk;|96&p!bnQCQ@yG|$veqmP|$z}gx%t>
> Hn5
> z$I5#9l!|dD@<$31^$9tgPd6EC`W=T(v{?=Gl&dFOh{hC^))8DBj8YJEaYr?CLrVBV
> zGoLGH3JsPwsUOGh*FxwXwoe6oyPTqGbLM%?_M3)lXN=U2j*Lmo@${nb#R_3N7
> $mLm
> z*hx7i-2GL#>aW8Q5_bZ`&ONa`GwrybkeBAkGlrF2;jtbno^+8pi`(&+GO`!u;OI#%
> zi({g}ogTe0v`Fz>aSJpWY|}6dBG_UHGGg7r`$YMp1#d6t_&XOSG<2=je5{h9+fnH5
> z8DqNh#>*Nj*UigdIa%(nr}1(=_a)=r^ZUs9luku3hwq|7Lf&5(L*SW?UsEcxv?kqH
> z7QH;$w*;%{UW@j<WF}7eMDIO2tWHL}Z;KB~wRmHX8Ijs*Gu=JfZKz@|=vzX6cB
> WrY
> z&;xr^D%?2K*b!?b=X<Aj^PK@p5o<;DFsI$v^`=~QJ3Bk?Q1cTPX8KE(xarYDK3A}!
> zuQ$t}ELJXiBt)hm^^<PqZi5yZA-d=XEHk`z-h1oU$YYIq%awAx6k@B5S$p|68T0cE
> zN^(YfY`LRy>w6TYV4OTTp4*?iOu}tfyu_1+-Vge%=2P5eC61@RZ`(X`MrNyc5`dU{
> zuwZk45V48s8|Pa2*%b1fIj(a0+xS$*bfTEFoxG|=f>Tt?&H}!_CEfaTMRp&yBy}QQ
> z)d!;<GgiA7U70SS>=pm@;kv#e_UNeZ3=ORU+e6yj?6`?ac5Bevd%I#{jlt+P-1Flw
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> zwFo>3D?kk0gKv0@(Gl*y?ISTF%t2*io{r{MSn>rBdx9JHH!g|)!{GW)GPwBKykO(%
> z^lkxlx*qj@*+Z5Hv(xv1aL6jr^-#^)<+c$i=PmI~-VGRorRo$i(7_F+U0G7xu}PG^
> zs^2@R>OZUSSP)bC{QA~j@8(&}QkSmog&NT_B|O&rPU!JV*uJ{kU6>dJ(nJRw$24
> Xc
> zZY-NJSeHJ`-
> !pkDQ)=<WoiM8JRkTMygQo8U9%~wtLn37`@$sOsl?g6dS%m3zE#zbJ
> zoTYD~v8(~lH&x1dpC($Lem7ED(l2AWwS@2KRco_hFH-C}`95(_(jtNo+Jr^Causxw
> z8IvzBb0mgOI=kJ?a(lTd{zRLqT`<JkCwg^j7EbF#4LRjS2~5G%q}$c<LlEVmbB+F5
> z{k|=XDamTe1~<_6K8mmkX$}-1M>xAK<xtmf@Km-J-
> Y0NQ1s)nBFIMkH&@Ubpqu@#L
> zeJ;DSwKUp$%GWnvJVVQA1W6DB#GE6K497wWq04Q{5d3F&u1rt1!4Mo1JLoe~=
> DH`U
> zKC*_{Yn#AS0B#MwS&Q_Y^bJ^12JD|&(eJ4!Cb)a2tqc{zlbwj81b7yS4Hy#~pcqs&
> zl^|36V<J|^Y4sfs_=HLLw2BLpNNQ>eaagzL#`^HE@{nl|*OgXpGPXGX3de6CxvZwf
> zn(E?GBLud4i2YqzY0gv)hGy>^hY4dlP5Zs~m$hoN)Q+!5YN*(lz`4uVOux6v>`b_Z
> zZmvj;j^J%~A8M2YeQ-$b&WKQ$<PGziIB~mHf}=QNK*jcr#h0u;YQAevbw{2*KXhzY
> zU6WT8I!P7m)S_*5qw;*WPgj}a8C%wyKgibj7*2cA8-b{K=uEln1oXA;OSkhe>zyaN
> z)P^|kzEgTC{d~Ib2;ZrY>PM-%`C(xanak6WrLOavuDdL!>(v@?i#?qLp)70tr>UP8
> zTm<YbQ|r0QqXb_tBy7BN@L5<$j2;>C62!K>7Os$o9&xKER5evCwhrW<&bNq|&|
> 7nV
> zvau|&u5i=wz7I8aa}Vt+^$1Rja(x_Ulj5KRqc|CRGiKND$&(Xlec4Vbf~mZk(W2%o
> zjJwI)wofCv6tXwr({&AN>2)381YXIUshLC`8gcWtvEmox10eE+SrtFx@V(bHEK4!Z
> zzK|<uTJ^L6C*(yEb9W((+%3jP*PB~vs7x|mi~4Q7!@}aVW0*x+^7N-)?`t~^c}R+y
> zKN;<F$wSApaAiBTe9oDw89mzh1p5GI61)|-xpG4#($a=06&-)2lRU!x9N9HEXIIG7
> z;vPplPawbW+TlgPCHv7=C)bLvE9MC?t@m@JJY)+K&z=ZPmWW6@yI)+EUlgA?IO
> q`^
> zJvaxI^Dx6ampYZanEnCpTOWBl>m`G0QJ#Pe>^zD2v8-4dPl#*X1FX3(e>p!cXGjsJ
> zmeO0?t7j+u<|V}i<Ll>8E%oj4;?lGVR?{&y0ox7<wks@LB~Nl<bv|X<==N3Cd5U^+
> z=*W3M>qbOtZjg9;uNI8BcxD@`Dv>%K_nI+WiQx}C_U&8MPK$e;%fxj)CV3G}D<Z
> 4)
> zhBB!_DPqRu_$J*8_`1HZz`h%>LU-
> qDTPnlzIWi&ZMmT22zXWlWxbUWi9WJN<6_$Pn
> zYvc{EcsRqc0D(|4O~awImZ_JPj0CH#N8~3Zt?!>K&sYAY!|2QvH%V{=eRI!N_4dVa
> zIT%{AE?&{+e`lz4C4#&#Xp8*z5%Fy*%Dxu#8K0|*qoTdE@0cp;-+wd^vsg~kMA*qr
> z%s>LDhn8AA=c*C33xfsrZtK9zGN3lD<-4)AEB)05r_FjAdU>B&@^1}P{ZHnw6g?7a
> zWOyAZrg0-7*$0$)26FFaAnTpF-0v&n12IK>$^V^Pyqwz@D1-1C`N)E9@t|>b`mj}{
> z>%c_kO0T)hJ<S2lCJ!+w^N$Ng-tGc*>brdK6F<lfl8_{Zl3eHaG}6kACeflhe6ea$
> z8yc%kGFR|u+KTZCm|{LwG?ZcLUe{b<U}`6soOx&z^ZCYlb+IGqc!SBf`9!*of=o1}
> zTjN~rmzRUO!Aeariakn{U&R`x&gq%Tc~MO6t&xlbDiSf<&!BGs?&jBK1Ck5TP&D=)
> zAcH|C9EafTp;Isdu)Vlid?_7_XC}NYbte}P5iz?VP`u&x*e0jj5Xi_WevkzxlUSsS
> ziAP7l_5KFtlF229AZYL6*v5kQGBn?mP!Azo^@Q!wmxF!0d;z-80mz6taftK^b{0PV
> z0giJn0hU$Hu-(l{;OCu7GNt=zbMrqR-*6IQtF)M~X99Z3^n>1h09N|-_CRfUt_UCm
> zXY0rCmmmZqTMdQ15d)I90I;Qc2LJQZO(xoAgJy`aqc!_Cpx+;X`S~}SgJ4Tm(DU-R
> zV$yLcfc_XnX^@I_e~=+n)*cb#A+rFK{LS!{!Vcp*F&I{zp6&PM-cR_ij<#CBCht!_
> zVAB4=dwOb(yiJ@cDDyu22z08s9=a_u2EVj4+US@*tChfWm_x^#R!W!Yo>H3UJCg
> !9
> z=o=wQ40s4KX3f5rW5DQ1VvbZIx-
> PQz2cPXR8xhWc_N8>U`ALV>mp*P4*R1VcGzQi2
> zFVbnGK>b}Rpu2n{3;_Y*(Z0TaiyGWF`vn&W^Gd_7b!{nhLh>Pm$PpN+W&=orK3fl
> D
> z*2AAdcX>+3hyiop`0n-P>#?hc?j;(TOsez%YV5tIUgS6kNf{Xg=mH|{fG#jvSwuua
> zr(fYcNu%)1Px`w&lTbo5lnE$ct-wYVD!f7ec6j44><$rN1PgZy$QOkF#Af!t&)je3
> zX9S?d3jnYYb=W@AByvwJy0Z@vM!EnfH9|e#;3xLL2^vya9B?&4?I%3>kY^s?W0c
> HU
> zVq#is*sPjoq8}@9nTpT#MoWo2O%#f(t$sin;(n8NJ%+=$YCk{3Tzm&p_)J6RdtFnQ
> zRxO+k<Y`M9OUFK2mC7XLy3;wQ8oAS5ac|HapQhN{X+3fgTl_*8PSx^RDLFoz_<?i
> d
> zRp;6ah1US5ICr2pPvToPJry~q<yB*Yd37#Wi_Kj)jhj_lb>dmyJ6)-XDi)$E?*9~D
> z=b7SRDK+DnCMRyYr^_8qsQ0w~nsdld?&7S?w<vPty8yL-
> zPP2&$%%Run8vgE82*Vi
> zGRsl+p6MQa&}Xb?>tb+&L51#o8<+hYH_LOfHff>0?w$(ZUv3;|mN6(dJ7Tcdr#U=~
> zankuFNF(^1Y}dYjZpong-W*Ta;iK8%b2tJ==lR>#v}KcGn@Jc6WvgfW%BLbZhRrP-
> z+gcJm=HeDm1b)-cZocw8GZ9Wmd4^yo`Lm}LKdLRiR3n?B^bskP6V-
> &daI5h>F<mrf
> z&F_&?O0jljXf2jdh@ZZ2?da%ZKbxwT>J%aL4**HjI}IOT6!5@EMYq%W=)^kfluGHk
> z{{4+N*<fYp;@GXi=*e-5^S>RwuygYW85?fNFb0hsQ|J>xuDrhL%zjqeY=D0?(&=G@
> z4r$3wcBNIQYA$HWBK3?|*~cbc<?l1);#kmOarM*Q$HX6Gx;+n+;TBf07u}<;9ci~C
> zgZR61icNm(tz;Wm92}`nx5-)B6W)>aX)iU}^}A?x_V%@N8wKR`65iIRq|8CJof4VW
> z8-*e86K)1~v59Y=ZN5!#N6e~AwHiN|mNx3&;#uE3RCFonW6{Wf5?9ts-~oB<w-
> ry9
> zty(XTY9rPFtk*x5_Jd3`8w=*%z)<)EfGaK~RX)f5k73boos9lfQUgeS|3S{>SLo>l
> zkBfzqo==K!*TBUI;!mm-k{_3>$M~6X!Opai?TC!(iA;_i!)qB8Sp!3!L2}lW{U?a&
> zJle5xN;c0^LA_B?X0G_N_aa`c4(-BYwZghcbXK3*_C*bFp)K`cUBaFHgWskD-^JSx
> z4@jMAz2=>3oC<?6r55OJcVykGe!&?kf9UgRGEZ`23Re^zjY&2VAeGEkgVXU}go_G
> A
> z?aAjMA#^*kdwr$z#Vp18CqnD9$%-
> mtMmQ#!PSZDNGaILUZ1Wgn$atWvt}p|uTCA(j
> zj{3BUj7HOSm;GGu{OxO9KD_3ZNu>A`;g?Ehms>zhoOzINY*%5tz3>&+%WT3n15
> w)-
> zzD{?St7BKZvK=H53~t^sv&m#FJ$ZY|$a<=sfT@1Hqz+|~D<%4+7nuz8u0;32)|bsK
> z63=ydDLfVsR>8y0OW(C=Ldvsi@6+pxG+0AVY<hz}3;Noztjw8hdr#v?8nB&iyPCd|
> zt&9t>KpBp+Pm8*|^sL@<1(F&a6w;}t35WH#xUta4A7s)&+jdCo%({n<q>qB<U&<-
> X
> zYH%iZUh4SP#*`ugZ0X2F&g$xzlA3d5IS5*XW32Oiw{Mf`afR;#k$S~`y+@f>a(ePf
> zVK*CJLm}m2LkN#R%>>sw%Atx@ldXe6Gv$w_1n{>~3d*~)61_QG)>FUw#ui8Bnys
> dI
> zI9wmQP*h;!co%mhvAC3fSu|#aV1L5}c}v1~**#@~n~BeYN6m`Yr31+f0(X+KULbl|
> zz!|K;aV2~6Qt+SXqwrf3f7cKN^7jMdA>$?!HlMcA*Z`;0jV+tA_gK=cWHxi(_^hSR
> zsyEP1miwSA_Igt%h-%We<tk#DR-t8ARDHw7_YkIarikjcQ>vb#mU8KQE6!t$%i7%L
> zpZDqLmRJ)%39mr!mVGTBDX4mrYbG<r2I#)<6CWdnCdO*}c{C&B9x+HH)}E1N3ir
> n4
> zV|MmD^;J=&d^EyuWZBdd_M1K+YM7cAD!F?$y+yUYbfIW;2eTea)?Uwa&k%YMa
> SY<N
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> za5!<W^|$??e{ZxvkLW+qH)+3m`6s$C{pFBeNGmXCW}(1r=SdYHBP{Nz6oOICZ-
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> z=@Z-
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> zp$LiC1)p?95%wn6UQ%FtfR|Cmq5)5Fewle2!nus~NuDn~PxrGUVvinp(b>c%3iop-
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> zJ8lE^jTZ>P@EZcT#8*=jw8UsNd{P;}X-oZH_I6v{EodV^X#Q<@0>=MU>q4&Fp>x|~
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> B*-
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> zL}?-yXZahWC3In&sKWU=UHUjzmPOje?XhOhjV7vgd*x~28c#D(El0U+6oA?l<e9yu
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> Z
> z-2q2yzR@wdnq5jn+D)4|W)iiuLK>X9<_crwv2(2sw4$o^Bf(p^yd`}=kEAncYGOER
> zyWmX5Azd6#QN!~FIXsg<#8XYVBIA~_Nd%SMaL0I28u3uEtap9x);{yM?k?Jyio$Oe
> zMbW{5Q~m?~Q?Rh-GIpP}vWz}`tqje5qI!#df!bqs(h4<W90}~b#RD$mwVkTXkKP-(
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> z7&a=+QJ~gDKWdqVDsGs{GtJx7(OV`>xR32w$tE~H1OSc9cj<r4S3=62XpF}OyWY+
> 5
> z@NH0EDb6C5UcPhUi{<6V-
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> z=1F_zx_I!Qiwf;Ree%4f`Ntal1FvIsq?I}6TJE$s#h%Rl{N2SGL_0#k%f)!do6CK&
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> b
> zw~Srcq%LL>5U(zxz!mCg1(lv5X{TvqnwX3l85&PH_<kFK>K|gOK05?*%y5U!m#}UI
> zHqwQpoZm(o3Nfg@MqD&HQEIapEs*XP5v3iK>Xn$wS>R$~VhfcgSf=F<i^q`SUxpj
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> zKVLhSPEk<t{JBiHz>)}^2kbsRIZ+TUlWnxLJCom3{bk2ewrGzho<JAk#glxV7z|h8
> zHcekyjvP~yU#sZ}JwE>GJ*|)Pl8L@SuAZi{{1xHH!%8MVAord}+TW2LM!N^Egv;z?
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> z?xMFG2i2lmvAS{sQGgG>L!sdx*6|fu```hQ<S(TgI@9qvN2A3!%kaAD+I-o^v@bzZ
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> z-}iJ*S&z8DU}(9a&sdXLLGuYIQeFCzz^I#hk!G+<WVMdiiwy3(Mgi*cKFvmcO8vt2
> zO}oSPqu-
> OGluw9~pF9od8NJ~6G=@>UBda6fO%*!!H1}nTdzleXTkFy=HE&pHW6qfB
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> z5*<9DtD=vUa%3L6I)|&w#NXzT{5a+L_)9V}^NWQy5+{Um9mYx73OG0WGN&{Q
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> SRn
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> zoU`nh@?0%k60Qav+#tW<y36tU79=;7F24HFq>1-bbgLNss9iE6RA=h+N(ke2r1H4-
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> zBl4&$Kk4R1{6<<>jCi|{HWos~y28mi@1o~cLK!T3c{%`3MrYGJof2%`OUmH>s#v?3
> zY<8Ig-bl&GAMgHlJ4w6T5ZYqVNiDJ|C7+;4<5fzym=71+%2CRcRLZ)jZS?UJ^gBSg
> zH0{N#EQ=gb>#~()YsOaABsDd?olfHXe5>w>20vWTX^bms3+qmxYLe%wdUiMee*
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> z|AXS)m~}M1q%kuwT9yQ4OOHpZhcrW^X}+NQ0^+h2V}cEY6^n~n`66GBMtA7+xr
> V5x
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> zGXo9jIXYl)nZqa!jD^U{g)8GX0@oddFI83X^Sm&wn;Lj{2K!BVkEEJM(ni5-<T>%%
> zY|m0GZMFwPqg!rXKBmO%{_r+$QMDElC~(Bp^GwY3BU5YUDc-
> ryD)oHXT6`z6?oNk2
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> WCP4
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> B
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> zILV+7JViI)nAxY9;hEDa!+Nz`f^5mM`CK`#z)33x6);w)bqk{9y;p=XcUd6z+Dk+V
> z>WqBjY<)AQz+&XS(luk;^%jsjvt^ERvovFTi4YRvo?_Ikn8Cg3P))TpR0^AE_g>_h
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> zG61qgM)EYfekl5uGPPO3*ZMmo4GL97bHkM!{YnX6#$HF)m9%=JYpVCbYqzJAYuqY
> D
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> }
> z_~RA&L<f!wH>7s*4V6NCkR<vFKlPWRT1<tOH$^5~>8aN^yKdLbSFp>h)JRVn+w4
> 6W
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> zb8KL_@K`!2{+_aQqPvqrl!#W;dFVy5um&yx4n`u@DdSx2lXajakzp)@lh(cbi0#39
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> V_Platform_EDK2_Firmware_Enabling_Philosophy.jpg
> b/Platform/Qemu/RiscVQemuServerPlatform/Documents/Media/RISC-
> V_Platform_EDK2_Firmware_Enabling_Philosophy.jpg
> new file mode 100755
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> z*wFqyP~aGS1iLD==NP?9QL4Z44?nC`T%xOR{;{tO7$c?hXwxU}P)~x!*8>3mm`i#4
> z&#HokoBu@RgV}#Uu1m&|A@l6hmD6-(;vf5XsOiW%djP>i$0j`GR4JY&6!B*R?yvrs
> z9-
> PE}fPaxN@U@3bwta{EohAtTCb6szh~QRWq}*Hp9$d{5GrvSX4&MIzV$U^t!>%?x
> zaRT#;izEnEU2+d`^4I_@efpKb5uyY&<O*yOwyU88#7}4J!nTmRdV5op-
> *ox@d(^m`
> zDaReoM@SG?%9{)MK%XZ?iVCB+qUHgxjQ!7S7}VvJvh?^DqPy4ruBSMQ+>4QMYy
> Z<B
> zLo5KPg8l1y<^8)as5T4oEA9+k7=V4%=$6>0ViwS!L3E~=36R~X`J0RY^|4n84!OOw
> zCC^W_G8<J39fhQozA~i2wY|X<<9Q&??}j@{efR_VT;kw@o-IEY@j#kqF|$#pOr(1*
> z`^t+n^o57aRj(Sq9(}CXV1gxR;>q%w+GHppPnC=$_Gt~2al10RmGsqWXP&J}p1AdP
> zx;h|U^J+Ge&~43qvf|G3C5jC{dS1SFIR>c{ED)@K5qju3nGt4joX65Q4H-hWACFCq
> z<NFLYZ88yKK){2_mqm<d(<cWLkY8lhRfYpYEs=#5+44^`;{v%E%Mso3+dJMKyHX@
> @
> zoA`eMdf&_qhHPX;ZK5hlQCaYb$%y*nVfzH7<HveCHv+hM&r8a;@kZ|4A|NO5tx&
> SK
> z>`H&OtyH|@H8Jm11<VOM3r!YiQ>?&|k1hfF;qJ<(Jmk%uP`l(kVL}A~&B*6gaU}uL
> zbg^r;Bi_*Zf$MV7a%sVzwvL^dPZ}OEXRoK{t=8dwf~A%j{9*_JY3xMIu1rq0zYS|}
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> ztkSrXqu1}Q$FS#e-})IIRyq1I?ea~f0)pz~;ZTrAoF(A=6creUHla)lpKW5*yd1>^
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> zY?K5E5+Ub<4T$!a6LtEm-yJvM3X8uT9bMKZ`c76!)=-k-0CI_Mu;Z?%fa~Sag!@g+
> zJV0pbny7U}X@42BM3Iq=a-bru5Z?a8Y*z1a;Z32>GI4PeF4Svo8h-EH08<sYbB38O
> z;%kw#xk=B}K02rb70}68!W~vr{aG5g*e9~ktjqQnDg$vX!zk+c;r@tap)QZp;ddh9
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> zXM(^hp%I1KP{Vy%<o4X3W2R*G$<g)EJ3d!LstYq8<iBiH+o9Ic?LJd79`IXWZGqM;
> zvZyD9;)Q4*7a`l_bn+z)*NVy{!aGbUN+f~$qo3u!SOzjgg-zG_$gf)8VL|H@);DTs
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> zhv8yTniYaclSq#U@2Gt<A=`NJWiBdL#|CMc@C45S?5D411tR#z?iJ*W;jb2c!Yn^(
> zKYdr|@tZ3w6)sZms)qOLZLR$Y-
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> z>|D6fk@Y_6aqfW=r*-aoIWxL5vRqCSDKO;B(8%q$;ckPlukY-dYJDt_IOl3(=@uaC
> zA)W}p1cGts$gRJnwtMwX-_#gb(C6AA<4g%tat?|*pN1A=iB<c02K3azxD;cVJxv)t
> zTcP3vHhunHvu}h_M5va;?d1mI?WU==SIR$R#}8Hqnuf-Nr&okO8-
> v8W<Uoyf$*MTt
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> a
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> eCMHX|C8Lh>PCRJOq0
> z-
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> zrq2#`LkWhcAyuHINk6(xWNvgPO--
> AX7GEEKd)ULbyl?w!=*U%(T1CRawnZhMAQ#r0
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> zJI2|#YAibQ7#lKpV;scm!>Nc4g&A@HF-y0UQUe!FRr__F8a;k}eq{M8xA)f@%7~jI
> zWW3oAIJ4u#PwNzWzOp+x%2qt9cz0sH!Ykfbkpr(`{f<<2N0KRubdB~F!AFH&X#+~
> m
> z3+hVw50L|~o_pJZDFwk#+zxJ(>A&2^uuP6hRxH`C8z8pSjg1Y*w8L@lCKsc-oW2zp
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> zP(AN(`?PbuioTyz!{K^QS_*bg0uZ^JNAy=EZofi+*2N=o$*qn0CSMvh*W8QWmF<@
> B
> z>RgrQh@{5S#--NfuoFji9YTI(gkm(<vhF)b#xBT2Z<*f{v3&j`AxHOU<?^r=M)ez@
> ztIf+Y5gdn`=tofmDbghISz;me0f7%2To!)e$B?OcVU~}jNTX4Gt4yD2?P0<2osp`d
> zup~-1XBn@ui4^JmlPOAOALV<DEyt2-RK9-
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> zCt-&@VxiVHw~rpT&kQTSYqMPv<`kAd5)q+Sy(M9d=Hs9n=J;~T$|s24r{%h!^D}f)
> zQI8S(EyXsHE-
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> zT(dn_)s>Q!Ib$?Ra)hskmv1{7(4UnqG$!d^N{<>6JLwOM;E{oJNwUgP6aDfxX(an|
> zk2Ln5wy{oQrk%eu<OBqYT2*byX;T>L8GDKtRpZB8bunQ(xE3PVTyi0(;A_zVWOdw
> u
> zr!cdN`@F3}C<7tC8t1t4Whr&45S76Rm&e6a838gucMF!Yla+>S$U~OI#vw|yr?f+>
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> zZlU3(Ey&}W6xa!KNiR2h9>YHIIcH~!J4f|nQ0_5igMB{?$nb}@Z1ZWtTw@B{Q&)cE
> zwMCWgy?4ZOTVO?4u{@9T>}{Dsg`Lu=P_rDk%p}q08!bDh<-
> @oPYQcktXdgg_*Vlnh
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> zFas)ERPgY8SnWeXwU}x%La@eXMP=~@QoqbJ9v>Io88|DT+ZJ7>qAs|uj>)@N7^
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> zxpR}Kl<btg=w5HvL`pQCdY*yu=5!m4Xmb8+ndHZMtxQ?2y=BbdlJYg{q7C8YEwG4
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> zd)ew!SQrl!Rm(t_rvM5oYclD~+6ql~>FdVFsH0GiYn`n_A%?K{`?60Sy;ALS)iHf6
> z`7p0DrFJxB(7wVkKIYgpk&`oNoSb!0>aZCO9py(aI9ur7u>VtL)PJ|_72G%NkA04w
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> zDp7qyZ$}ceB>a${alvl(R+H9#*h#J*Zk<m{>f<Pn=@eYBsi%2`)YrVgd6E6w7}u18
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> zWLYH18hE_xxaDJl+%WqWxw@WIIx@k;lGx<iFN@7Y7+Ed#O6#=UubM%CYN6p
> XwnXC9
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> zVm(4e8ASK|kbq12@@0)=2wzYQG0F(_ajA;g|5#mKad7y(PC%<+llHLX+!Xc0<Ik>=
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> z3GiAaY%_^ueVEEHT@p{5Uvo#>e^0tfm3~e$*E37bPoTuN&~dOoci&T(|1R_uoB`
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> zM`Z22I}Yr=)mqebFX8CzXoassv4)QE5wedS?PIi2=Ip#4m6SBMI$lsWa{behMv)T+
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> zcnu!<H*2PpT@xN3rp<RCi(%B0RwNHv_|}NMT@&JnmQ{1P<DBV|(%Ga%LxW|>
> z;M%(
> zcbiVL^4gB3IKd2blwH7~EMlL>2n&zZB+J3Yc>X++Gx^R?zWPI+hNKT<t$gyC)?pZF
> zFrfApk23NpDZZd~OZ}8G{}b^jaXt=e{&lNNWiRZX*Fi5?m~xC9XE302%2O0@>Qv3j
> zO%)c9<q~VP<d}+p5f{afN(bkU5btf<ixDEFHr0}eIzD+d(1#_wpMN~nF?i1&H8f=I
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> z|3TDy^Mw9u-
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> zIy^`M#`F}|=R8VrM7>5V;l0r>SyneoE>g@aDpDZZ;KhjM=@;1y$J7e6ha5?2WFN{Y
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> MZ?=hn|x04b_g#
> zj)xZM`~wB`LupF`dNzXtbSu^QhO5%f7iP}Ii8Mb|6Hq*1ryIhN;Bm9pwhI{A{M8EW
> zAI!>@cSXO`hr6KjRB)OvA>-!(J7EGk-wY*igFYrP=x>tF&?$cW5Cc7!i*9~>5L^j{
> zLz_DPPWHS)Z~KD8y+uw)f`RlLW~hyRlmU?J+M%ajD7p}~C+DdG^h<pL38HrRm6iK
> z
> zoyJzrXZX#wSx<LJ9oL_h=T;o7qk^}WMl~aQU_7;(Wst)>jKP~r;lg@l8y1k#VH~^i
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> zP&Gv<WbxmZp_7Js^~XN+3E*mNMOSU}7N(wnkW{`&1T;e!muDhXBwa9z6_Q(w
> tLm<u
> zBYl~wx9xs8zQz}~HNl3^T6VA?`XK_we>zgJ3Z~KbxFTWF1wF2oSAXBBGs=?_uVXa
> W
> zCHXK;%r+`&BN~|~oA$a%2mT|cRia&JXAe9Ywy5Mr%Z5%w<M%;d;Dggzp=`AbfU
> qhY
> ze5yxbzXz=<dx$=DwT1m@U9(Mt`@F+_uN$I2>zU!F2>|v%C{ZRD`fuWwk;lmH_~
> mL}
> z^srDRMbS&FqAMmrWhTWqxG**3S57EKHz7m5g0tAZwC>c`#*|ZGBG*6r>H3t$;P
> b|S
> zhnv|PfN~6AfyS;MvO=jSZ4tsjWwx6NzjG^KWw}u0lZTbGj>2KdxboPmOEvEb)pWa5
> zWO?W4U3h{f^fjz#pril~mnE3v0#_B)v&!Rg0*HsR+&E`zcvqg!SGtbMHw7H4Nj&Hv
> zzsnS|WJJ}?SmsoBcCV=z^WnuX1iJZ_Wbyxb`u@Xrho{(qmyF&3uPcN84DyrAx<h28
> z9)`}qEkXZ^ME?reRKu==xz5g2)ZbmANWL6M`)801I+DzR?SlRvs`3otAeD)LS;i3(
> zRS2?vuE0%(*%Kif(%88oWwyh#E*+-Wo;>rSrfBEGR@*(MrR>z&ogTgD_sJvu6+hO(
> zthlpVjK$tPgs_txI$JGxen|UjKuT?f3rb@>bR3^-JdV`3zN*XpRQ>e9lRrc1lr`)X
> zQd6p>X0fk<WfE>EjpRVaq>`r_kSxd|xX$E4g0IpxosG|6dU^HhSM4~l&Q`qWm8MI)
> zyMsU8>zH$gJ+xh)!^jGcm4lpthuc<Kpi_lOv{)T+3zVetpAEZVr5;o^Mv@z?p#CzR
> zJU_+Ngd?jd>gBW@GnB=S3@2xOC{ihERjd?elYH}#_hQdgXD>{~^McRhToB4`J4o1
> N
> z_EC@7P5z%)#)b-1lzlpZXR+B;N@N|{ToD;oP%x?}+0jw?bkale^2?9MqSRNl;6#cl
> zKtCX@VZ$R+-GA(hK%9ev!Pp!Bmg`9`TU>l-bveUcp&WL+R-
> Jy60^G_vjbYQm!U?+u
> zA-Qt7Kde_ScDHP6Wo>^f2uw3kjCqt^BMtHe)h7Nk#RSK|QW``nXnEH?#-1-Z-
> *kwY
> zo%Y~u&4*aI2Zz-
> Kw=ZD8C0jmHBV+O$m4F5Lq9E(?62%m5j3wfLrv#et&NE9dg1gWW
> zSy85-E%`XyD$MJpnV{8?TsfVjCo>zcJ7lXScMBH606J~qGYx&ew;-*gEYt@Y!(n@p
> z%Z06tX<xfw%1r;FXlkZNnVL$ndU@L3iQ>|Z3|G9y<Lr`kFsZ^u5TCcmxjyfQoe0I2
> zXg6WQWgsV|k%3q%Vqko3xWmW;uogiNqdRNayi#G83h!CZ&)ewM6-
> 9_HUcZ<YQlNZI
> z!$EOaK?bvA-&oEQZjfwr$<!`=Wx?043K<SP48I0I5|;;RIj31<DOOEN=PM}UpR7s2
> z_Vn-kckDOLKaKQah<Rj}omv!@ar%<-
> P(gfpYI@R>!uSbvu?Ll%b;5C3VOmSG8OjW2
> z1s7#~QJyi<+I$rGVv(!<#hC%EL<iwW)vgfdeTr_acH_TNOAFrSnIL*glhE!XNT2iJ
> zOs-b#8X}^_2C&yN*s`o;Ndks6Pne5Nr|J`O$(c>Jt9)uWt_O@on|5>-z4h_3ddx%;
> zjM(3LGyji$LqLOKjNnLOLtDg6YWrIeO6xBeap^`=G}d=kPeHD<?ypL?{mKi|_=q=b
> zo`Jt#*>F&jDeki#9O$e&Q0(i|eRYG%NYqgDPCjPDm-J0^4m~VIKe9uSrw<@cZ9(|p
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> zCMW}Jv(&w9M!oL{rfQ86z<iW!`H3vsc>RetG_Y3Qw%o)mN@G3LGwvf^K&og_Q|
> c6`
> z_byaxT+9cl_pGpcw*V(c8s`(#C0ZW#u|xp29Pe-Sjef!Njuug<u6)|YnewUb^Rq?E
> z%CP*%dB2<X1+OblNWwT5(FEJ=<>_qO6&FDN7Bgxz^%y!k@FL-
> aRC1M%4BVYEw7mw)
> z&^JVI$+k|WwcpN9tr5-|eK}Q}&wt)*YavI8G`OY&qeX&t5v*iw*|=b2$>JnIQ8wj5
> z=_A6D_vlLY_?M=%yRhw-6|e-sJ2;a?tR0km0oec<No?M|UqaOULL{f@e-
> |_9=$Wvs
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> z=e3|l!q!jJ+sg6qTLbrS`X@Y7KN)VANfy1jOz$%4ezfzTIOlPJm2>{o+meBSwJGcB
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> z^jHx!W&{+B+osSAc@)<uEil4x5Xk&76xPq6&(&1MpWHx51>?_}s(S77U0*-
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> zN7Q-tc&ZRQYSlC6Ium(44u~0_H1cE1*r#B=FLsv~Oh_LqYQzd)r_g6vJx(&9*QtCY
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> zBsvDGOTFBx{Y4)w?7X5<#~)A6tX$aMaB^4k!j9b{k1UfyXj0@T+w=kr`|k>GCF$A9
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> zW`F8ij5-<dyj<T8lv!TQ3t6Ol4}ME`ZPv_RuCaF5Bjv&Tso6ooto*s^QdSxEu_V>U
> zvdAZ7?KX9-$jgTX`j9sg^%ZkMIX5S)??A~ZQYRKNJ!Wwe`{l&Jv>zoQ&FME6_6*gA
> zJRA(ori-Ku6L!>pUes58{HSY3{3=j5v28}Y=M8CwT)8u@AeKuGUel<J-u_mT3>^aZ
> zM#xKDvUw6SBiWgV8xUg+LPq8|8G~<l=}zzTj1TeqRamN?(=8Sli!A1xc)4<V7g>n5
> zMNDb8Bm=lk;nkOIz9#1O)2XiJDw?xHTj4U#&wH?Rj4v}BP?$Ktt<^<K^ukI^+1QfV
> z6!i&>Oy9co@2_$C_a)xtL79$}bb!)~W|@}1mG@}W854_cSs;jXHY*zUx-
> )D}mqapd
> zv$m??!xMixk}XfPD+A0Ryd;3P{I#7j0LQcACMfCiXtz_v0gW*J3l%@~wfl|a1J=20
> z-frcqIptk!JUE^PbVjDMr~bo@{<qc;`JtoCNcCU+Gwc9YNpJJ)mE(=}z~4}8S{WF>
> zwcCJj4^a{ZL=p<i%}p*RTw{0-O9HV;PP=WF#{8}C%2(-AD9J|l%@^C>s#({*N5!W-
> z>(MzjOFBwrN4zd8YLP4#7QWAD9vhLFg7QXHB+lXk*hnsWsCFVCkijK3TG{_7%VFC
> 9
> zvy*o}w_UW8|J+Y}5t5)WL+ogHiT_0oKXRUOZjXE*B$a_NIiZ_GR;>Xe%GLF~ceHD
> M
> zixK)D>~qmTn_xjithR;ugFU9q6YCmEIF7<2&{uZ)s;@X-$If*o)7Ypa(s5)GPX`no
> zR6)Ygwv$I!;Is|jD3jiOy^6@xzV7O~5aJfu;m{5Le3ZiHjRe%={hucH%$q$rXKeS&
> z_>%c~nOn<>Ui3qL=lZ?HNDK=Unw>_5sKHJynR0_M7MhBFaqF&1&ZlK`yQkL{jETA
> p
> z!ov0@$yp~Lp!uAO=acY`!E<pI>pfoN6`0=gblFNooe=NJ__(os&)v-0!L`M|vs?d}
> zJ^SnXbA3v8DIE}6n1pwrrb(MQeQEt@ZfA-c<A`zheU7uM%$l7X)@9yIzx??KG>f|*
> zjNPjm8F1vNNY3UyB#YRC$=__Me3RFjO3xvTH-
> G2jU9^)#wBMlUZ7P3;pD|?6)zdGg
> zmX#5LzC}Uh-U5-L&eFe`El$G^=w$|evM0FP!M@c0Z{ujP2M~+w-vSuJpJ0yI{5_!7
> zS!m<)e@G4fSCxtX?f4Tk<?<j<kp@}<oo)kxUd~U$;eQfOr!0X^t}nqi$F#|}5Z0Il
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> zaR3Bho)2JcmpY^2%ej5<O|mmtmK&JQZ@ReuY(fhBl*<t=fOFJG&O~p0BP0UCL57
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> zM@p&7#8X&1ytx`pr5dbs(YqC^za{VN5Am-
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> z;qYW-)E59Ozq+;(y*_Xib|&>r&bOt7^0Cp_hyXDw*wj~y<@*-?mv5C(n-1tv0v#Sn
> z_&zT}IKnDwv7#O^4VAwS+CR~u6SkaO1emSbgz%+rFd>p1Zaj9Ve0{S-*~Sxb6qfy<
> zFW~D%QsKOk6v242$-qtOdo%Czy2eG94y+pl3>#RWkwk`qxcsRx4Q!+H-
> iWpY<F9i5
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> zwY7T&>E#mY*BW?ryMW*Pdn6HfezL1dqmLcr7a{FwhOK!zerB#BSCQON`*y}aBz
> z|p
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> z^>MVTL-HPwl%YLD(`-nrE8Vmxd;;Z7h=N)Rmfhvkp5Kl*SU30E6T=`P{HcqzU;nZ%
> z?{uh87FQJ#?$P0pl8a)Y1;UyVRh^)=<mWo3_SfwV@FmR}n(Q6L=~=wjzO!wv#f?c!
> ze|?iy<a-=JGQ!fa66Dql_h@}{OC9p2w0<g#>l$~SFH>Q<<UyS__4?Wwp+Fy?S;d9T
> zDSIyd5I5K=<oZ(|4j*4=S~Vyilw)U~&OV`VVR7!UqAmuhu=#9!S`4*wAbl=)D%~*V
> zz+Kl+QP~T^2)6=rbowmiXO|Achny7N3~!A?t(t-dI*v*!DUK~0%%Fe|S7I*}3FNDL
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> z;DVo5IM5VDjMHxZ&feK>%PeG^54KX?BishW9|Cpu4PHCeIvdm4_`<&_EUpz^3W
> *Yv
> z4B%C@%>=d$jVxh{qi~P&y%?eJ_`&}DmFvO$JB^H_w#yq4{LrXZ4UYc9+?HPU{@t
> wB
> zVMAy5k!e{>p!8W7QwHuBD;8A`&X_kLz?KXnZN3fcO)0N^>=7NQaPMmOTMGoga
> b|RI
> zUL4<d*R750{FD_9D?Gb4h$GMS>~x>NUiCD>mY~$JLQPJva~q8yf(`~ke^NB=i<P*|
> zbZf%q3ZRg$#`lPuE-~UDqB4r2ayVjJL>D%HuC}Vm%(nHoHgdc6LVRx7Tu2k$dy^=`
> zLneqJA#oA1m6Cv)2yu4r_hAl*>|^sy;{N)&@EUx;q0fQ<#%d5Ri7x&+3KiL5tW~dy
> z>gGP8W>E-RAovjF3DG81$@|zI2btpD51cLa;?H%(2|5v^&dYSJF2?FwGl?v7TfSUr
> zwgEmlMh;y3qq~yqxnYAksk67UvLA1l$YwQho|nE$I_TOG>Vn;}i_Cl;r~()7wp1H{
> zM@_4i0<J;dbBEud^-
> LxHx&$xGoDKi4%y47e*7H40*p~sW9W1ASPFBa0E8mP4uk8s~
> zq+VA5R=9cYiNTn4q}8yKRb#TvMb5{v3atuD+SE~vR=<)uB)(CA<76yV{AULN1T{oq
> z;&EPuYXF?58OGrth8esWZeYz45P3vRePXz2NV>j;<!mfn0<rpo(b3xm$wz@32Dpe
> D
> zyY%}j=fLw(k78zTA-k_anoo0+u>HCuqgl1Q_0#CdI}M*%MM(3W*hl-ZMAl%s+l>II
> z8~Bc-QcJi%)F3JD0fe8LG88(By{R7+P_)#Yh?`s{Kg?3-9k)o(Z|U6@Q8Xyrdv+x5
> z@7A=c=b}RtgQ#Ya*p;Nn<w|E~VLgaSNOU9Dtjb0s>$okdO7xypm1QGPJF)np9?%J
> u
> z^e~B^BRw?SfRH#fi1$#fi0P1K_>FC7l8Ay!j#QHGq7{4Z?X#sy#m>SH;S)TN`0iUO
> z`91fw83OZ+c81XfLll8Dqg+mlJr4nqxRId^^toLmLGrgH<w_1tp0e~mxv0K|`<#DO
> zX?O7gQ~OQ2x&+vLhAp7T7o2Z+v}B&K_HXXNzel$JcZACYBn~eCCN=KDUowAIfLR
> 5A
> zVvly10^s}K2B3|ZN;Hwx767SD)XBlXwSl$j4kWz;=$CLLe7zQn=7KNA!1tlk3*-m@
> zcvu(7@lm=B?>-
> j>G?p4gzdV2m0YG;H9ZuswDHkx$gu|u3HP3QlAHn+u{$hWqEc~>|
> z9Px(}+p<J{@9-tnw)pV}b#pi8M~yn2t2XQmG<#m9-;`om_ChB8CFj;{ghP`*ZG#V8
> z4Rc@%;C-_=O7j=^Z(YL$tN5Rz)o^-YGihC=VKxERP21uv$|hIG4ZWqHlzcAhzKVug
> z@Eu>(CghYTaZ&p-qP=!y)HkOi&RN1_%1%e^K~&!-
> *DDu<JrmA&9yzXs;T+6BFUT3_
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> zYG=R=Hl|A}ntgOHR59jbK1%Tz1mP|p3g{4X8lNzQ^EL_jREl`qlRuLG+AsO&2L>mb
> z4*3+tbuE&~{C=tlS|ZteKRtQMc-
> %m1?Wu)&1DpMo1ci0UhM7&c<~2AL6xGO18JO-Q
> z@vu36018YQ7G4P!Z;yYckJ>-ev8LMVN^_Y><(>Qo)y{>h3ZT8##meI-
> 1@=6^aBj%m
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> I
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> zf)P9_f;q7tU*>hCWoIW!?!<aI9Zw33dK3=Q=?W+dxN9WL$nRK^r~x<~euczSLx@~
> @
> zWujARX!Y~w3-z8SCq6upeWusXoIE_AiXX-
> ~cL0*7ObV)WAxF_6zAB#_@}G%p?~0tI
> zR<-
> ;z+x59O?n5<0pwH5s+`ahhbSd%&f3Q?4+oO!RP%)lI3HmC@QeB*AZ{(npLo?vS
> z%naTnjA)FwAAOrQH&f-Xk>vZb!wS!gC{=uar^e;mMw01I@8?W+)fw_=)Nv7Ms){?)
> zP7_1CV-Xt$-d<X1cMBh+3@O<hFYG8f4Yu4wm(y*7opa{as~UOA(EEwn(jPP)m-
> S@a
> zS$TGFJ&X3e#3+5Lp$^g0UwH)TkrI6s6?{15Ar$`Xj;3`WIhW~xX7XD9<jFH)>n@j~
> z5z%bp%N%8tLR%GSdEnUoExvQU*R=F9Ea*HOZHnAJ07yk+;4M~a$|pWw){1#Zq
> 791z
> zkNJS4C1X+A*RLfdV~10UV-
> ;@~u9G7#kLGV>C(fr0Z8VA#Wb^&)$?>EMx$B9>(A4oN
> ze4_9~S;bpDld?r71KHkd^OdW3I8GbM^lampZ6TPa(lm)L$|w6S^~)d@P!bc0s0Qy
> &
> zA;|(wios-F-
> ~H&RgQZW$&D!iUbHZ_I*`_iY#D@#QKfHyhH8)4O2p#V<Syy@ZD8pH*
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> z*>6Fa0-XG!L-}wBo3{@Sl-ab^^b++>W=!x(j7yUdwNeUt{%jT6){?nnaLTLA{ESgn
> zv_YweWWoKJ293}cYa{)%d7NjsDjTH3jJEyxUj68QktQc7Z<2spaoV1Pn9Lt5cTNX5
> zxo5}vN2<&xo9rpsm5kuM_LK)dHcENhY>b6fp!STrB;N1!v`A6oED0Y>b4#=4yy1H3
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> zO1V|Sgyv|GJ7MKzjDXsQH;Sn8GZWnB=4<Ju4LkWUsO{+Qn<iDAmQY6<c@5Zl^3
> ymf
> zugU&sU$Rz|-IJ>?S;Iax#I?0+lt+Bc0_zvr{_3Q^>{_VfudqRhT2E)i42C35AGZ}c
> z(>lK0T}2aV-(Q`7Nj<&xyPB7HnW)-qE)t?kXvHGvro<9+3EHZarNQ?u{%Vt#QVMzl
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> zs~+$hrhN~aM0bUxH#9}rdspHt*B5j4^b5ghaxSsalneZDqWirE<~J+s6j%8FP`z)L
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> zz5jTRncM?kUk7E30tz9)u*d&dhWPKle?$0NwULc_Ag1O9lFgexDVnCm@cZ6CAkD
> K5
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> z#kF#OR-(1K{#Y{O>udcD{rGsinF&ls4Yi!qpR~&OQ^p9pNxEkU&oqbr4#ES$RN$Du
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> zu3Kvb&lGpW<@CB>(5$NT31-
> x~)(6%)$I0`L_WQoOK5YFEt9Q+zGwr6HwKZ+gy+^F)
> z4LcW5Vq4+Nt-
> aQSV%(G!ZnXhZ_;FNpX=E^#+43T@&IMvr2<>DO5C0GO1`ZT`v#E)Z
> zwd7ABu{J%=JcHB~LH}J$<TDMc`9$NnVqNJhgw2T`exz_a9~maDChy_mfGi2wK4S
> XI
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> z$2wLn<FDCEe5+{{JL&63#)#tAd+w!rw?Z>_S$QY201%~qB>P{bNiu1N0{9O^??3pT
> zf9s3>S3Vo||D_oMKe-
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> zNY;SJvJ4vkB)PK)#%Un_x-u1ff_;!IQjLTa%V<-cegmH#X#*`qR1|<zH=mRx!06qC
> zuXh7r7UZG-xBq1HXBL5h>Mfk8h;0KyutK*joZ8hOR|YAU!ijQ-Xfz5D;#2~ihJu=0
> z(4k1!3qyBak=oR~zFpSljq4LftN<{k0i>WUDMJXn1_}6>TbN981|$@LbdAk#7$>C@
> zc83rd0E)}^Ch7{<-cfR~w5^rwEbkj3KNdiyVvD@STsPuOx?Pcmf2huG9eaDx97VV@
> zOpETW08m}$!~&Bf;-^WcxKoOSvvAGYs_A7McqXyk07B<alVSIwT-l{~)~D>fukwwx
> zBOAaoJA?EYbqDgU{+1UCorsDBp&aK%BdEYnAUv@7dBw^hupOMvKE_nF$WBgB
> m^tBY
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> zQpRRVQf6u_G4QRmY|0QDGH}a-P`vQ4jA$5Euk6DsKh7!MceZP-
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> zk?E7q{a%n~Cts3i0_k@+PM-l>;IMQWwzN?<LZW#Ys&-
> ^8P+Lr|{?7F3m4&MM7*f!&
> zgYVOVOS+uj@)b|SBH<N)pn?d$W+|?=8{43v>sRQ73OmKBIQZ~O1KpFCnH+*v7m
> >7W
> z5$?#;dJs{WkaW~f?_5cfiwYLGOmjnq=SGdRxLM0NmjmIa`LfIOsn|L|9~Aar7$)XG
> zVXYlG1iYMZ=2Gd~BCbGaS&}jjNfoS8j}J;<JtvTAQ!9YoG)xqpk2;?4t3!A6ZMI<6
> zmEDTRicet1OuKM9?av08d+eBnI6O=1>_zc&XTLlXS^q-
> Agu+B$pC)++L&e&VQi&Yb
> z+r5WogvSpa@tmy|o}`sneVq?>XP7v*RxHt83lBT88o}Vu!R{xLZxV)PP3P2TZ(3L1
> zkdUx=$j_U8PiRz$j<EZjz_19v;T>c$;%=r6sx+DbZE1XTXGfhGcs75<D)7-c#yv*6
> z4(71Y-H06NUjB?jF+jZ`q+V_Dl9Na!q{_~Y9yP{2>XZ|I<AxXY<(yF1^~Db@L3NeB
> z0TWwf+}d;8Y$DrA8*Wz3N8$K-b8)Y~4J!Ez-LBMq=<wqVBSYST*H-QXf7o<#C8}dx
> zOo2b&e%dMVPNJK~vi1t%Rz_*;Q|l}HX+`0YQ?gel$D@PLPIRBy&I}bpkJd9jMStAN
> z)(?{e6pe*PM12=)7PjUCt1We12<{`0`u$A{`<|@&ibh1<%im~F+8sqFa<O}wi+j!Y
> zFO8WfagB@CC=ENl-
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> zWN?gE;mVv8qQ0fJ9xnm3ic5AEuchZZ$+Ma6gv8pBesSK0Oq_wS9yv2Cg0!?~P$uG
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> zNW1t8EnCu^KoRp`Q243Q<y7Q;B8Y0i$r5>MEr_V|BXdg8?IDP^XxYh`!UW0JICb0
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> zVTXjCU%P{p(fP(M_GL)t{4t=OMTKriK|7$VnN|2&wI+g+W&P>a9xZ0ATZxMp)vBN
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> zZJXP<D!5%K>=CE?@{MCx@Xj;gAISz?!uN$rdB`_C6mGH%^TTb3PPY2_VFk$}Q63
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> zi@cb^p~>29mQZh@zv!%2UXp3_^|gZr>K<ZrqpG@Q&H1^i2KLvck*bLMxKdr5hI1
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> zH1Ph*Q8Hh)YmRo4%_v%u)fCo+Lv^Fs6FQKeYORowLI<sHE7b8BVEM>G7IXQA<^d
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> z8U{Q+LlqJ%yQa&VJK|LAzoNZGH>r*GiU_yWd;L)D325D35KVxxePG@K*z}zPr**4
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> z+q*$G39RL6V-Ab-QvrGf3nfflRd(qG5FA|-M-Q?>fN&3!vp2Iu0bM>ohFA(Td{i$C
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> O
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> zT|5+@Ys}O-
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> z4|pDDwy|Jeo53oX6Yd;6Gph!I<-<t@QJV^T^d34Q*pn-E8dF;CD()8h>pNpyjaXym
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> zqFJe%W&~}u1k%|G5Wmvv*M!r(Q4o`GMs|hgHsLT(jBQX`PLh&)W&UymAti?jI^#4
> 5
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> zqHk+M!0d%;23F{JOg^W)^C2VC;42Iexp6B+E>pm6O(Lg%$M>F*@cSG!r1)$r1aQ
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> zf|xmV=`y$Qd4aj-1s7>^AC<3e1=F}9>$96|R&~*oU5w3v8x_RNCEKH|hGd)gzs;T(
> z-7E+Rrdn&1JR>MaC!Bdn-
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> z|E;DopcELesPN{L<X9dOZ>_==pbAm0CE#g#|B&U*>H$L*ll@~-hv{bg<&VtfI#lWQ
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> z+(eGk&8=*D$KRxXo{Eo6Awm=t1K<*8Us{34lT_^>S{3LS(1s;F#eD&mm_kpUp@vT
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> z%SZLCW2Oq-B{K^uEaortH1n!On&vh4*Ao?Ydw*4l_r3ve^Rh;y_bk%ao=;XHy=^)R
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> PX
> zZb&n2xJMgx_aeOkd@MjM7cnwWDlYo1Jlgl=U?vRnrPrL+5Nivp;8@Aot6r8LGV7F
> s
> zMptaX>%xR92OOgi!#da|He0gzkV6h|56FQtzS*kF=LAZN`@no32=QE-z4Cr;tLkOx
> zv+QT3u{V#r>C`p1p?0*)zb{Aja+igrMhqvM>Zw6B#Jp+Nf<!wp#~p7j`P8c)-DG&{
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> zk0>dI5kN8yzkz_nq}nJSC~HEu%AHWXuYp;TP<w5Myri*yMM8oKdq|mSUY5M1&6
> L-%
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> z81!7d-m2a+d><B&goTk_G2#Ky|BQ2|)uq4RB^vQx!@PplPJo6Zu>?@Ar6VsjHa3x0
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> zL+jex3z(%mfV578R85u({Dwil33*;`(GYf|#s8b(NBz*Kt7u|ptgA%9gKVvw%+-~R
> zJ<_d)9Tpts9k@m$x=upP5DmTP-TxidY?IX}d(5-?c>m?MhXVA%!(4QLn3NP=ji}L1
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> zWd1EC7dB5V<T!LCx?*!byr|2M?O8oBZJ~egbWMMY9jFd>Ik8HZ5VscpkxILuMrab
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> zDlAa25nlY}#APX-
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>
> diff --git
> a/Platform/Qemu/RiscVQemuServerPlatform/Documents/Media/V2_DXE_Found
> ation-3.jpg
> b/Platform/Qemu/RiscVQemuServerPlatform/Documents/Media/V2_DXE_Found
> ation-3.jpg
> new file mode 100755
> index
> 0000000000000000000000000000000000000000..61ca5faaeb296f5f8e05ab742
> 028930bce69c367
> GIT binary patch
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> zASzX|gAO74uHCBYSPz#diPsC~ah`7H%`OW+28p}ADD(qekTMa8JRSPY@ot`s;I&@
> 6
> zs<yY?K^l?)yHR@skTyKAA&s_dnzs$6Ase@SrYMGQgrw^A-Q)cIJ`P&<q0PGaOCl7#
> zvn;=bzwtwV=~JU&dA#C|CO|S$emy`~dVoRz&et<vv7(av;tuNhk0_~vRY0!rRTeUM
> zJ~&|*C8oQatJaW3H-
> B*8EeEfVQlhKDiyB`gA}$OHNz2W#(dVo#K&Q=>h|3lm+g<A&
> zuqZ7Hf9Z7c;)R+M(g8)yeM86r(oP(#AZ0^lo~9!HW;-sl>So#ds7T9JJg1TfNuVCd
> zQMsRf*5rX06XKmMyRlnNamQkKh||GW@Z-YAR*v3AZk{%-Y&Iq`E`jJ2Q*?-
> _58@U{
> z()PEOLAUa}Ythl+YDaEI$sM<+z@vm)n8goHJbqo|gQLZRMN(v8dTPQY5KRfq<69`|
> z@||>!dt`V$go!R~g?_|ys?$}`z~?$wY-(50TM@cpTI?4W_T!#GwWfZtuqx)>t>Eet
> z)EnKPV>ERxPB!x>Cd;(dNfd$zEu@fHQa`B%TUpYEo27MbhMu4nZMtth_D#bq_S3
> YP
> z#ad42PKG7=+EQORy~O1r*P!CXoxb8^*0J0s7L`WM)&-OJE2$l6{@W1`qf}F;{Tk{U
> zc~K3YS%uF0WVrRF0R$Hm>%~p@Qy@X-
> J1>65(VIIqV5hhOFGelfQQuTrl)09fohcQ3
> zXn8lc5M5x--3l2Xjje(Zy5;oYrR$e>whiGC#z@>a$`b%yb>sAGALVS?N}!1J_C~y0
> zPtJML#fHuP#+0h5e2IIW(Vv-brl?lyL28R&)|i*05+q0iGGLUSSR9{g6XzCh>uQmu
> z{(b>Buyvg=v8Ud#;9gDh2j{&iUY12ZW;Ae?KG54R7bA_-#agVtO9f#nW=4$O40CS`
> zZwEABk5=Bz_FyIynu-
> w%s9M3A<#E~$btklKg@!ZL1&0*lV^465o_%k(vL@GlZv<C^
> z;~pfZjD=3jI(*b3G(;#?WaK7!NN0NT51T<0w5#Q1ujQ+@MLez#AFr;Xw_>_GcDFhC
> zioMzXh!C%h<t({NGLKMr5_1h5hI}=8fuw`ssmeegz9n%hYUKB!UfG`yo5J2weKvE$
> zz0k}+(yrBMkg*mY<dv9_G`bLzc(Fuc$k2EM0ZJ$dMCLURD@ViI{T-{jwy-EPqvp=c
> z?s-z*bn#6~vhdj8GFA|>Kig5&{tU$eVv<J0+{N~E4+OlZ4+R^ygDPJ$W5K+7DXHNi
> zP2$b~^{iVSO*wr;92Uy!qH|K6Ka=ALdUl!fS_DOrN1pujA3briv{!9BS0&``f8~Ki
> zh?8^-=m`sp*xdsK8OYm-oAVHE)c&p;mW``2#5%`BFSaKa!V1iR1b74_z}KG)2Bd1F
> zXKqm-c9+F+7Ze~M?>@PE`+BGjF{3csldvMx6ve_iZKr*#r8NzS%*HlAj<#<GUsH8^
> z*mg@B_7z{D*y5wN6_Kut>B8+kI_4{cI?@4^D0zV^7IS63N^m%C<dN3CD8{)Rqd!
> C~
> zigc1SS8Ths1l_<t{pM(hx@n`+Yw8P1%Ie6fBgwkPzh(~Koyn7Gp5H}OEXat2L;;i>
> zOxtRA6FYyOx`($F_B<;i^>H4LL{FBB5P}=2n<#dyU(I%$ReZz*F+#HNID9>PyZ5?~
> zLwIV457t@6*=wa18|qAs=+kk|vGqFT%N<s`xx8Q;y0nr*Epm_iYU?+MA`ZWet>Rl
> <
> zSY}-$6R-R(FMGm}82?Yl=ush4@~zT4*t7Haqjb@M1?<ts>voEI0jgc2OB)s?J!V=D
> z3Wi(XL?3_hTxF`fdb|LgpC{v_z*vI`mBk%hr)Y628vIyUAKG71RMfrEU0wRz@&5U8
> z+12d+)rqLmz}tqExE%}7D8^EK-Wpugn(erElGGZttJf4f1HZEXtzkq)lbCPQ;;1qy
> zw$X6`fhZHpPyM4vg!Rtbf=XMf+}_)H!&Obqg1^ZwQ?4pD?F_EAvI8N~YW@YyR)}O
> 9
> zw(;_-&Ld<tiwM@v7_9L|%srL8!B0VmnqQr289HxtXgh8q+h>J_{Zkk!9W~S0d@18j
> z#eF^XKKs!+l&9BsA62i2r0%Z-BXo^xbJe(Uj=Yh}w>A~@R+M_Le&kZ|=j$<h??fFg
> z-aMQJUs3iFsDT|u-6vKDlFnC}`8Z~b3`-@P;IHHweZn_Ns*D_Fng|b3+;fK+vvCLs
> z-#wewK>E)_>gkEK*mP|=h1ku@T;j)?kBjZ6ijndBejm{GCLYNkI-+eGI2Kr`iI*x`
> z3JK5ZuZ(Zs%UYbn?|ym^P<Gu(?Aqj*@m2@J7rHNQm3AyICifO;>xzlki-s=dU)v-G
> zzN=vfX`obv_w~SbuZv1L_~v(-oe#h33-MWzyz@S*-5(`K9GYPDTXGfAsjEvAr1%U3
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> zo0+X08xB2{rrhUuix+<T!1qyZKCU38Nl$B69H!H-Z?8CCYFe4|4jwMbX@5=^H}$9>
> zBxa<N-4^OiFZwx%=IYf214vvrQ!z3F;pzJ@SKhYr%VO|x$*)zKeW}z(WR3CNUa&o`
> z%y1AdvPU8ja~&S;4Wq7~LHx}4MjF3meS~ldY(Z*oUgWZjkKSL(?pm{B$CQoW&c-
> s-
> zYGE2RL&OpAfhZW|I#r!?y7%SdN?2B-pUjozqzJ7H_WL2~Q>BWh_f5jt$nD=F6#9-;
> z?;)2F7PzGrCCHKbRXx1ju)>Ei_0QpXQuCiR?8$KxQz1t6vuvz-3rI7xWuwG5pkbj`
> zWSE7T@Px2$4*jSf?ocjrERlKKAXtfcT+4{Po^z^Us#|U$eb^(aEJDQIXfI+rX3zPb
> z3|9x9rW(jE3pqDp8LKbNvvVHn%%Q4V9;n7zn~4<1jvEOlh3aWm7)hLUXOi>DT|_
> GT
> zMD8wgSJ`y;2JeaGO|hEut=8v!bE*vU)^{HnKEW1AGN|Va2rJ@9CoVNaFpWpdc*)
> eP
> z21(n9@-pYCexy8jdICKKDxxSBS?yX)R-8bRmu61(FRH$I_n@#i<l-fj2Y#o~6zHy$
> uNBO3GzNZ|DgI9J9)+dhOoUodgNsY(%hCL6W@kenqzPr15W1{Tm!2bd}3z`D}
>
> literal 0
> HcmV?d00001
>
> diff --git
> a/Platform/Qemu/RiscVQemuServerPlatform/Library/PciHostBridgeLibEcam/PciH
> ostBridgeLibEcam.c
> b/Platform/Qemu/RiscVQemuServerPlatform/Library/PciHostBridgeLibEcam/PciH
> ostBridgeLibEcam.c
> new file mode 100755
> index 00000000..105c67e6
> --- /dev/null
> +++
> b/Platform/Qemu/RiscVQemuServerPlatform/Library/PciHostBridgeLibEcam/PciH
> ostBridgeLibEcam.c
> @@ -0,0 +1,386 @@
> +/** @file
>
> + PCI Host Bridge Library instance for pci-host-ecam-generic
>
> + compatible RC implementations.
>
> +
>
> + Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +
>
> +**/
>
> +
>
> +#include <PiDxe.h>
>
> +#include <Library/DebugLib.h>
>
> +#include <Library/DevicePathLib.h>
>
> +#include <Library/MemoryAllocationLib.h>
>
> +#include <Library/PcdLib.h>
>
> +#include <Library/PciHostBridgeLib.h>
>
> +#include <Protocol/PciHostBridgeResourceAllocation.h>
>
> +#include <Library/BaseMemoryLib.h>
>
> +#include <Library/DxeServicesTableLib.h>
>
> +
>
> +#pragma pack(1)
>
> +typedef struct {
>
> + ACPI_HID_DEVICE_PATH AcpiDevicePath;
>
> + EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
>
> +} MY_PCI_ROOT_BRIDGE_DEVICE_PATH;
>
> +#pragma pack ()
>
> +
>
> +MY_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = {
>
> + {
>
> + {
>
> + ACPI_DEVICE_PATH,
>
> + ACPI_DP,
>
> + {
>
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
>
> + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
>
> + }
>
> + },
>
> + EISA_PNP_ID (0x0A08), // PCI Express
>
> + 0
>
> + },
>
> + {
>
> + END_DEVICE_PATH_TYPE,
>
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
>
> + {
>
> + END_DEVICE_PATH_LENGTH,
>
> + 0
>
> + }
>
> + }
>
> +};
>
> +
>
> +GLOBAL_REMOVE_IF_UNREFERENCED
>
> +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
>
> + L"Mem", L"I/O", L"Bus"
>
> +};
>
> +
>
> +//
>
> +// They depend on the 'reg' property of the default DT provided by qemu
>
> +//
>
> +#define GENERIC_ECAM_CONFIGURATION_BASE 0x30000000
>
> +#define GENERIC_ECAM_CONFIGURATION_SIZE 0x10000000
>
> +
>
> +/**
>
> + Apply EFI_MEMORY_UC attributees to the range [Base, Base + Size).
>
> +
>
> + @param Base Range base.
>
> + @param Size Range size.
>
> +
>
> + @return EFI_STATUS EFI_SUCCESS or others.
>
> +**/
>
> +STATIC
>
> +EFI_STATUS
>
> +EFIAPI
>
> +MapGcdMmioSpace (
>
> + IN UINT64 Base,
>
> + IN UINT64 Size
>
> + )
>
> +{
>
> + EFI_STATUS Status;
>
> +
>
> + Status = gDS->AddMemorySpace (
>
> + EfiGcdMemoryTypeMemoryMappedIo,
>
> + Base,
>
> + Size,
>
> + EFI_MEMORY_UC
>
> + );
>
> + if (EFI_ERROR (Status)) {
>
> + DEBUG ((
>
> + DEBUG_ERROR,
>
> + "%a: failed to add GCD memory space for region [0x%Lx+0x%Lx)\n",
>
> + __func__,
>
> + Base,
>
> + Size
>
> + ));
>
> + return Status;
>
> + }
>
> +
>
> + Status = gDS->SetMemorySpaceAttributes (Base, Size, EFI_MEMORY_UC);
>
> + if (EFI_ERROR (Status)) {
>
> + DEBUG ((
>
> + DEBUG_ERROR,
>
> + "%a: failed to set memory space attributes for region [0x%Lx+0x%Lx)\n",
>
> + __func__,
>
> + Base,
>
> + Size
>
> + ));
>
> + }
>
> +
>
> + return Status;
>
> +}
>
> +
>
> +/**
>
> + Process a PCI_ROOT_BRIDGE by the default Device Tree.
>
> +
>
> + @param DtIo For a pci-host-ecam-generic node.
>
> + @param Bridge PCI_ROOT_BRIDGE to fill.
>
> +
>
> + @return EFI_STATUS EFI_SUCCESS or others.
>
> +**/
>
> +STATIC
>
> +EFI_STATUS
>
> +EFIAPI
>
> +ProcessPciHost (
>
> + IN PCI_ROOT_BRIDGE *Bridge
>
> + )
>
> +{
>
> + UINT64 ConfigBase;
>
> + UINT64 ConfigSize;
>
> + EFI_STATUS Status;
>
> + UINT32 BusMin;
>
> + UINT32 BusMax;
>
> + PCI_ROOT_BRIDGE_APERTURE Io;
>
> + PCI_ROOT_BRIDGE_APERTURE Mem;
>
> + PCI_ROOT_BRIDGE_APERTURE MemAbove4G;
>
> + PCI_ROOT_BRIDGE_APERTURE PMem;
>
> + PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;
>
> + UINT64 Attributes;
>
> + UINT64 AllocationAttributes;
>
> +
>
> + ZeroMem (&Io, sizeof (Io));
>
> + ZeroMem (&Mem, sizeof (Mem));
>
> + ZeroMem (&MemAbove4G, sizeof (MemAbove4G));
>
> + ZeroMem (&PMem, sizeof (PMem));
>
> + ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G));
>
> +
>
> + PMem.Base = 1;
>
> + PMemAbove4G.Base = MAX_UINT64;
>
> +
>
> + BusMin = PcdGet32 (PcdPciBusMin);
>
> + BusMax = PcdGet32 (PcdPciBusMax);
>
> +
>
> + //
>
> + // IO, MMIO32, MMIO64
>
> + //
>
> + Io.Base = PcdGet64 (PcdPciIoBase);
>
> + Io.Limit = PcdGet64 (PcdPciIoBase) + PcdGet64 (PcdPciIoSize) - 1;
>
> +
>
> + Mem.Base = PcdGet32 (PcdPciMmio32Base);
>
> + Mem.Limit = PcdGet32 (PcdPciMmio32Base)
>
> + + PcdGet32 (PcdPciMmio32Size) - 1;
>
> +
>
> + MemAbove4G.Base = PcdGet64 (PcdPciMmio64Base);
>
> + MemAbove4G.Limit = PcdGet64 (PcdPciMmio64Base)
>
> + + PcdGet64 (PcdPciMmio64Size) - 1;
>
> +
>
> + //
>
> + // Fetch the ECAM window
>
> + //
>
> + ConfigBase = GENERIC_ECAM_CONFIGURATION_BASE;
>
> + ConfigSize = GENERIC_ECAM_CONFIGURATION_SIZE;
>
> +
>
> + DEBUG ((
>
> + DEBUG_INFO,
>
> + "%a: Config[0x%Lx+0x%Lx)\n",
>
> + __func__,
>
> + ConfigBase,
>
> + ConfigSize
>
> + ));
>
> +
>
> + //
>
> + // Map the ECAM space in the GCD memory map
>
> + //
>
> + Status = MapGcdMmioSpace (ConfigBase, ConfigSize);
>
> + if ((Status != EFI_SUCCESS) && (Status != EFI_UNSUPPORTED)) {
>
> + DEBUG ((
>
> + DEBUG_ERROR,
>
> + "%a: MapGcdMmioSpace[0x%Lx-0x%Lx]: %r\n",
>
> + ConfigBase,
>
> + ConfigSize,
>
> + Status
>
> + ));
>
> + }
>
> +
>
> + if (Io.Base <= Io.Limit) {
>
> + //
>
> + // Map the MMIO window that provides I/O access - the PCI host bridge code
>
> + // is not aware of this translation and so it will only map the I/O view
>
> + // in the GCD I/O map.
>
> + //
>
> + Status = MapGcdMmioSpace (Io.Base - Io.Translation, Io.Limit - Io.Base + 1);
>
> + if ((Status != EFI_SUCCESS) && (Status != EFI_UNSUPPORTED)) {
>
> + DEBUG ((
>
> + DEBUG_ERROR,
>
> + "%a: MapGcdMmioSpace[0x%Lx-0x%Lx]: %r\n",
>
> + Status,
>
> + Io.Base - Io.Translation,
>
> + Io.Limit - Io.Base + 1
>
> + ));
>
> + }
>
> + }
>
> +
>
> + Attributes = EFI_PCI_ATTRIBUTE_ISA_IO_16 |
>
> + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO |
>
> + EFI_PCI_ATTRIBUTE_VGA_IO_16 |
>
> + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
>
> +
>
> + AllocationAttributes = 0;
>
> + if ((PMem.Base > PMem.Limit) &&
>
> + (PMemAbove4G.Base > PMemAbove4G.Limit))
>
> + {
>
> + AllocationAttributes |= EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM;
>
> + }
>
> +
>
> + if ((MemAbove4G.Base <= MemAbove4G.Limit) ||
>
> + (PMemAbove4G.Limit <= PMemAbove4G.Limit))
>
> + {
>
> + AllocationAttributes |= EFI_PCI_HOST_BRIDGE_MEM64_DECODE;
>
> + }
>
> +
>
> + Bridge->DmaAbove4G = TRUE;
>
> + Bridge->Supports = Attributes;
>
> + Bridge->Attributes = Attributes;
>
> + Bridge->AllocationAttributes = AllocationAttributes;
>
> + Bridge->Bus.Base = BusMin;
>
> + Bridge->Bus.Limit = BusMax;
>
> + Bridge->NoExtendedConfigSpace = FALSE;
>
> +
>
> + CopyMem (&Bridge->Io, &Io, sizeof (Io));
>
> + CopyMem (&Bridge->Mem, &Mem, sizeof (Mem));
>
> + CopyMem (&Bridge->MemAbove4G, &MemAbove4G, sizeof (MemAbove4G));
>
> + CopyMem (&Bridge->PMem, &PMem, sizeof (PMem));
>
> + CopyMem (&Bridge->PMemAbove4G, &PMemAbove4G, sizeof
> (PMemAbove4G));
>
> +
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +/**
>
> + Populate and return all the root bridge instances in an array.
>
> +
>
> + @param Count Where to store the number of returned PCI_ROOT_BRIDGE
> structs.
>
> +
>
> + @return A Count-sized array of PCI_ROOT_BRIDGE on success. NULL
> otherwise.
>
> +**/
>
> +PCI_ROOT_BRIDGE *
>
> +EFIAPI
>
> +PciHostBridgeGetRootBridges (
>
> + OUT UINTN *Count
>
> + )
>
> +{
>
> + EFI_STATUS Status;
>
> + PCI_ROOT_BRIDGE *Bridges;
>
> + MY_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;
>
> +
>
> + //
>
> + // Only support one RootBridge with single PcdPciExpressBaseAddress
>
> + //
>
> + *Count = 1;
>
> +
>
> + Bridges = AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE) * (*Count));
>
> + if (Bridges == NULL) {
>
> + DEBUG ((DEBUG_ERROR, "%a: %r\n", __func__, EFI_OUT_OF_RESOURCES));
>
> + return NULL;
>
> + }
>
> +
>
> + DevicePath = AllocateCopyPool (
>
> + sizeof mRootBridgeDevicePathTemplate,
>
> + &mRootBridgeDevicePathTemplate
>
> + );
>
> + if (DevicePath == NULL) {
>
> + DEBUG ((DEBUG_ERROR, "%a: %r\n", __func__, EFI_OUT_OF_RESOURCES));
>
> + return NULL;
>
> + }
>
> +
>
> + DevicePath->AcpiDevicePath.UID = 0;
>
> + Bridges[0].Segment = 0;
>
> + Bridges[0].DevicePath = (VOID *)DevicePath;
>
> +
>
> + Status = ProcessPciHost (&Bridges[0]);
>
> + if (EFI_ERROR (Status)) {
>
> + DEBUG ((
>
> + DEBUG_ERROR,
>
> + "%a: ProcessPciHost[0]: %r\n",
>
> + __func__,
>
> + Status
>
> + ));
>
> + FreePool (DevicePath);
>
> + }
>
> +
>
> + return Bridges;
>
> +}
>
> +
>
> +/**
>
> + Free the root bridge instances array returned from
> PciHostBridgeGetRootBridges().
>
> +
>
> + @param Bridges The root bridge instances array.
>
> + @param Count The count of the array.
>
> +**/
>
> +VOID
>
> +EFIAPI
>
> +PciHostBridgeFreeRootBridges (
>
> + PCI_ROOT_BRIDGE *Bridges,
>
> + UINTN Count
>
> + )
>
> +{
>
> + UINTN Index;
>
> +
>
> + for (Index = 0; Index < Count; Index++, Bridges++) {
>
> + FreePool (Bridges->DevicePath);
>
> + }
>
> +
>
> + FreePool (Bridges);
>
> +}
>
> +
>
> +/**
>
> + Inform the platform that a resource conflict happens.
>
> +
>
> + @param HostBridgeHandle Handle of the Host Bridge.
>
> + @param Configuration Pointer to PCI I/O and PCI memory resource
>
> + descriptors. The Configuration contains the resources
>
> + for all the root bridges. The resource for each root
>
> + bridge is terminated with END descriptor and an
>
> + additional END is appended indicating the end of the
>
> + entire resources. The resource descriptor field
>
> + values follow the description in
>
> + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
>
> + .SubmitResources().
>
> +**/
>
> +VOID
>
> +EFIAPI
>
> +PciHostBridgeResourceConflict (
>
> + EFI_HANDLE HostBridgeHandle,
>
> + VOID *Configuration
>
> + )
>
> +{
>
> + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
>
> + UINTN RootBridgeIndex;
>
> +
>
> + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
>
> +
>
> + RootBridgeIndex = 0;
>
> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration;
>
> + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
>
> + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
>
> + for ( ; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR;
> Descriptor++) {
>
> + ASSERT (
>
> + Descriptor->ResType <
>
> + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr)
>
> + );
>
> + DEBUG ((
>
> + DEBUG_ERROR,
>
> + " %s: Length/Alignment = 0x%lx / 0x%lx\n",
>
> + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
>
> + Descriptor->AddrLen,
>
> + Descriptor->AddrRangeMax
>
> + ));
>
> + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
>
> + DEBUG ((
>
> + DEBUG_ERROR,
>
> + " Granularity/SpecificFlag = %ld / %02x%s\n",
>
> + Descriptor->AddrSpaceGranularity,
>
> + Descriptor->SpecificFlag,
>
> + ((Descriptor->SpecificFlag &
>
> +
> EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
>
> + ) != 0) ? L" (Prefetchable)" : L""
>
> + ));
>
> + }
>
> + }
>
> +
>
> + //
>
> + // Skip the END descriptor for root bridge
>
> + //
>
> + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
>
> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
>
> + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor +
> 1
>
> + );
>
> + }
>
> +}
>
> diff --git
> a/Platform/Qemu/RiscVQemuServerPlatform/Library/PciHostBridgeLibEcam/PciH
> ostBridgeLibEcam.inf
> b/Platform/Qemu/RiscVQemuServerPlatform/Library/PciHostBridgeLibEcam/PciH
> ostBridgeLibEcam.inf
> new file mode 100755
> index 00000000..971a1b56
> --- /dev/null
> +++
> b/Platform/Qemu/RiscVQemuServerPlatform/Library/PciHostBridgeLibEcam/PciH
> ostBridgeLibEcam.inf
> @@ -0,0 +1,49 @@
> +## @file
>
> +#
>
> +# PCI Host Bridge Library instance for pci-host-ecam-generic
>
> +# compatible RC implementations.
>
> +#
>
> +# Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +
>
> +[Defines]
>
> + INF_VERSION = 0x00010019
>
> + BASE_NAME = PciHostBridgeLibEcam
>
> + FILE_GUID = E88D8506-4701-45BE-A116-B3260679CDB3
>
> + MODULE_TYPE = DXE_DRIVER
>
> + VERSION_STRING = 1.0
>
> + LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER
>
> +
>
> +#
>
> +# The following information is for reference only and not required by the build
>
> +# tools.
>
> +#
>
> +# VALID_ARCHITECTURES = ARM AARCH64 RISCV64
>
> +#
>
> +
>
> +[Sources]
>
> + PciHostBridgeLibEcam.c
>
> +
>
> +[Packages]
>
> + MdePkg/MdePkg.dec
>
> + MdeModulePkg/MdeModulePkg.dec
>
> + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
>
> +
>
> +[LibraryClasses]
>
> + DebugLib
>
> + DevicePathLib
>
> + MemoryAllocationLib
>
> + PcdLib
>
> +
>
> +[Pcd]
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciBusMin
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciBusMax
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciIoBase
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciIoSize
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio32Base
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio32Size
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio64Base
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio64Size
>
> diff --git
> a/Platform/Qemu/RiscVQemuServerPlatform/Library/VirtNorFlashPlatformLib/Vir
> tNorFlashStaticLib.c
> b/Platform/Qemu/RiscVQemuServerPlatform/Library/VirtNorFlashPlatformLib/Vir
> tNorFlashStaticLib.c
> new file mode 100755
> index 00000000..d86cffae
> --- /dev/null
> +++
> b/Platform/Qemu/RiscVQemuServerPlatform/Library/VirtNorFlashPlatformLib/Vir
> tNorFlashStaticLib.c
> @@ -0,0 +1,42 @@
> +/** @file
>
> +
>
> + Copyright (c) 2019, Linaro Ltd. All rights reserved
>
> + Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +
>
> + **/
>
> +
>
> +#include <Base.h>
>
> +#include <PiDxe.h>
>
> +#include <Library/VirtNorFlashPlatformLib.h>
>
> +
>
> +#define QEMU_NOR_BLOCK_SIZE SIZE_256KB
>
> +
>
> +EFI_STATUS
>
> +VirtNorFlashPlatformInitialization (
>
> + VOID
>
> + )
>
> +{
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +VIRT_NOR_FLASH_DESCRIPTION mNorFlashDevice =
>
> +{
>
> + FixedPcdGet32 (PcdVariableFdBaseAddress),
>
> + FixedPcdGet64 (PcdFlashNvStorageVariableBase),
>
> + FixedPcdGet32 (PcdVariableFdSize) -
>
> + (FixedPcdGet64 (PcdFlashNvStorageVariableBase) - FixedPcdGet32
> (PcdVariableFdBaseAddress)),
>
> + QEMU_NOR_BLOCK_SIZE
>
> +};
>
> +
>
> +EFI_STATUS
>
> +VirtNorFlashPlatformGetDevices (
>
> + OUT VIRT_NOR_FLASH_DESCRIPTION **NorFlashDescriptions,
>
> + OUT UINT32 *Count
>
> + )
>
> +{
>
> + *NorFlashDescriptions = &mNorFlashDevice;
>
> + *Count = 1;
>
> + return EFI_SUCCESS;
>
> +}
>
> diff --git
> a/Platform/Qemu/RiscVQemuServerPlatform/Library/VirtNorFlashPlatformLib/Vir
> tNorFlashStaticLib.inf
> b/Platform/Qemu/RiscVQemuServerPlatform/Library/VirtNorFlashPlatformLib/Vir
> tNorFlashStaticLib.inf
> new file mode 100755
> index 00000000..16eac026
> --- /dev/null
> +++
> b/Platform/Qemu/RiscVQemuServerPlatform/Library/VirtNorFlashPlatformLib/Vir
> tNorFlashStaticLib.inf
> @@ -0,0 +1,32 @@
> +#/** @file
>
> +#
>
> +# Component description file for VirtNorFlashStaticLib module
>
> +#
>
> +# Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>
>
> +# Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +#**/
>
> +
>
> +[Defines]
>
> + INF_VERSION = 0x00010005
>
> + BASE_NAME = VirtNorFlashStaticLib
>
> + FILE_GUID = 9A42D578-7E22-40F8-A587-4759F0DC93BA
>
> + MODULE_TYPE = DXE_DRIVER
>
> + VERSION_STRING = 1.0
>
> + LIBRARY_CLASS = VirtNorFlashPlatformLib
>
> +
>
> +[Sources.common]
>
> + VirtNorFlashStaticLib.c
>
> +
>
> +[Packages]
>
> + MdePkg/MdePkg.dec
>
> + MdeModulePkg/MdeModulePkg.dec
>
> + OvmfPkg/OvmfPkg.dec
>
> + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
>
> +
>
> +[Pcd]
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
>
> diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Readme.md
> b/Platform/Qemu/RiscVQemuServerPlatform/Readme.md
> new file mode 100755
> index 00000000..eaab90e9
> --- /dev/null
> +++ b/Platform/Qemu/RiscVQemuServerPlatform/Readme.md
> @@ -0,0 +1,327 @@
> +# RISC-V UEFI PI Reference Board Port Guide
>
> +The goal of this document is to provide a generic server platform firmware
> solution applicable to systems built on the RISC-V architecture SOC.
>
> +
>
> +## INDEX
>
> +* 1 [Overview](#1-Overview)
>
> +* 2 [Server SOC Reference Model](#2-Server-SOC-Reference-Model)
>
> +* 3 [Boot Flow](#3-Boot-Flow)
>
> +* 4 [Verification](#4-Verification)
>
> +* 5 [Pending Tasks](#5-Pending-Tasks)
>
> +* 6 [Known Issues](#6-Known-Issues)
>
> +* 7 [Appendix](#7-Appendix)
>
> +
>
> +
>
> +## 1 Overview
>
> +### 1.1 References
>
> +* UEFI Specification v2.10:
> https://uefi.org/sites/default/files/resources/UEFI_Spec_2_10_Aug29.pdf
>
> +* UEFI PI Specification v1.8.0:
> https://uefi.org/sites/default/files/resources/UEFI_PI_Spec_1_8_March3.pdf
>
> +* ACPI Specification v6.5:
> https://uefi.org/sites/default/files/resources/ACPI_Spec_6_5_Aug29.pdf
>
> +* OpenSbi Specification: https://github.com/riscv-software-src/opensbi
>
> +* BRS Specification: https://github.com/riscv-non-isa/riscv-brs
>
> +* Device Tree Specification v0.4: https://www.devicetree.org/
>
> +* Smbios Specification v3.7.0:
> https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.7.0.
> pdf
>
> +* Server Soc Specification: https://github.com/riscv-non-isa/server-soc
>
> +
>
> +### 1.2 Target Audience
>
> +This document is intended for the following readers:
>
> +* IHVs and OSVs who actively engaged in the building of the RISC-V ecosystem,
> serving as a vital component in the vertical integration of systems.
>
> +* Bios developers, either those who create general-purpose BIOS and other
> firmware products or those who modify these products for use in various vendor
> architecture-based products.
>
> +* Other stakeholders who are interested in the RISC-V platform and have
> firmware development needs.
>
> +
>
> +### 1.3 Terminology
>
> +
>
> +| Term | Description
>
> +|:-------------------- |:-------------------------
>
> +| UEFI | Unified Extensible Firmware Interface
>
> +| SBI | Supervisor Binary Interface
>
> +| BRS | Boot and Runtime Services
>
> +| BMC | Baseboard Management Component BMC's main function is
> to automatically monitor the system platform management events, the events
> recorded in the system event log.
>
> +| OOB | Out of Band
>
> +| RVI | [RISC-V International](https://riscv.org/)
>
> +| RISE | [RISC-V Software
> Ecosystem](https://wiki.riseproject.dev/display/HOME/About+RISE)
>
> +| BRS | Boot and Runtime Services
>
> +| SCT | UEFI Self Certification Tests
>
> +| FWTS | Firmware Test Suite
>
> +| SPL | U-Boot Second Program Loader
>
> +| SAL | System Abstraction Layer
>
> +
>
> +
>
> +## 2 Server SOC Reference Model
>
> +
>
> +### 2.1 Requirements
>
> +This qemu virtual machine (server soc reference board) is required to be
> compliant with RISC-V [Server SOC Spec](https://github.com/riscv-non-
> isa/server-soc) (the commit id at writing this doc is
> aec20046c35b108f76a11a751f754505aaad7800) as much as possible.
>
> +
>
> +#### <caption>Table 1 Server SOC Requirement
>
> +
>
> +| Items | Requirements | On qemu reference board (1st version)| Future
> Plan
>
> +|:-------------------- |:-------------------------|:-------------------- |:---------------------
> ----
>
> +| 2.1. Clocks and Timers | time CSR | supported
>
> +| 2.2. External Interrupt Controllers | AIA | supported with non-upstream
> patches
>
> +| 2.3. Input-Output Memory Management Unit (IOMMU) | RISC-V IOMMU spec
> | no support (need qemu/linux patches) | Yes
>
> +| 2.4. PCIe Subsystem Integration | PCIe features | supported using existing
> qemu implementation |
>
> +| 2.5. Reliability, Availability, and Serviceability (RAS) | The level of RAS
> implemented by the SoC is UNSPECIFIED | not considered
>
> +| 2.6. Quality of Service | capacity and bandwidth controller register interface
> (CBQRI), etc. | not considered |
>
> +| 2.7. Manageability | BMC | no support | TBD
>
> +| 2.8. Performance Monitoring | HPM counters | supported |
>
> +| 2.9. Security Requirements | On PCIe, off-chip DRAM and TPM | no support
> (follow qemu existing features) | Yes (for TPM)
>
> +| Harts features | (removed from this spec) | support the previous stated hart
> features |
>
> +
>
> +
>
> +### 2.2 High Level Design
>
> +The Implementation Choices
>
> +* Make the configuration as fixed as possible so that this new machine is easy-
> to-go and less confusing.
>
> +* Remove the unnecessary devices as many as possible, e.g. CLINT/PLIC are
> removed.
>
> +* Keep the MemMap entries as similar as RiscVVirt vm for easy adoption at the
> early stage.
>
> +* Keep dtb entries as small as possible.
>
> +#### <caption>Table 2 Devices and Memory Mappings
>
> +
>
> +| Devices | Base Addr | Size | Comment
>
> +|:-------------------- |:-------------------------|:-------------------- |:---------------------
> ----
>
> +| MROM | 0x1000 | 0xf000 |
>
> +| TEST | 0x100000 | 0x1000 | For reset function (name misleading?)
>
> +| RTC | 0x101000 | 0x1000 |
>
> +| ACLINT | 0x2000000 | 0x10000 | aclint mtimer (spec definition missed)
>
> +| PCIE_PIO | 0x3000000 | 0x10000 |
>
> +| APLIC_M | 0xc000000 | APLIC_SIZE(SSOC_CPUS_MAX) | fixed AIA
>
> +| APLIC_S | 0xd000000 | APLIC_SIZE(SSOC_CPUS_MAX) |
>
> +| UART0 | 0x10000000 | 0x100 |
>
> +| FW_CFG | 0x10200000 | 0x18 | depend on ACPI support on firmware
>
> +| FLASH | 0x20000000 | 0x4000000 |
>
> +| IMSIC_M | 0x24000000 | SSOC_IMSIC_MAX_SIZE |
>
> +| IMSIC_S | 0x28000000 | SSOC_IMSIC_MAX_SIZE |
>
> +| PCIE_ECAM | 0x30000000 | 0x10000000 |
>
> +| PCIE_MMIO | 0x40000000 | 0x40000000 |
>
> +| DRAM | 0x80000000 | 0xff80000000ull (max) | still one continuous range
>
> +| VIRT64_HIGH_PCIE_MMIO | 0x10000000000ull | 0x10000000000ull |
> different from RiscVVirt
>
> +| AHCI | Handled as the PCIe device | |
>
> +| EHCI | Handled as the PCIe device | |
>
> +| IOMMU | to be decided | | patch yet to integrate (kernel/qemu/…)
>
> +
>
> +### 2.3 Qemu/Guest FW Interface
>
> +#### Hardcode Addresses
>
> +It's possible qemu and guest have no explicit interface about some information,
> e.g. address of specific devices, but both of them hardcodes the same address to
> access the device.
>
> +
>
> +## 3 Boot Flow
>
> +The following diagram illustrates various platform initialization scenarios. This
> document will not cover the detailed work of initializing on real hardware
> platforms, as it is beyond its scope. Our focus will be on the more general
> firmware initialization tasks performed on the qemu emulator. See the part of the
> diagram indicated by the blue color, which corresponds to QemuServerPlatform
> Boot Flow.
>
> +
>
> +Note: _For specifics on the qemu Server SOC reference model in this document,
> it is essential to consult both the latest developments in the qemu source code
> and the definition in the server platform specifications. Relevant information for
> both can be obtained from Server SOC TG and Server Platform TG of RVI.c_
>
> +
>
> +#### <caption>Figuire 1 RISC-V Platform EDK2 Firmware Enabling Philosophy
>
> +
>
> +
>
> +
>
> +### 3.1 The Traditional Boot Flow
>
> +
>
> +[PI Architecture Firmware
> Phases](https://uefi.org/specs/PI/1.8/V2_Overview.html#pi-architecture-
> firmware-phases) shows the phases that a platform with PI Architecture
> firmware will execute.
>
> +
>
> +#### <caption>Figuire 2 PI Architecture Firmware Phases
>
> +
>
> +
>
> +
>
> +_In a PI Architecture firmware implementation, the phase executed prior to DXE
> is PEI. This specification covers the transition from the PEI to the DXE phase, the
> DXE phase, and the DXE phase’s interaction with the BDS phase. The DXE phase
> does not require a PEI phase to be executed. The only requirement for the DXE
> phase to execute is the presence of a valid HOB list. There are many different
> implementations that can produce a valid HOB list for the DXE phase to execute.
> The PEI phase in a PI Architecture firmware implementation is just one of many
> possible implementations._
>
> +
>
> +Based on the content quoted from the PI specification above, it is evident that
> the PEI phase is merely a traditional and integral part of the UEFI boot flow. In
> actual PI Architecture firmware implementations, it is not mandatory. Currently,
> the primary purpose of the PEI Phase is to perform memory initialization and pass
> necessary HOBs to DXE.
>
> +
>
> +For the former, the alternative solution for the former involves the
> implementation of OOB firmware, which is currently beyond the scope of this
> document. Regarding the latter, we can move more works for building Hand-Off
> Blocks (HOBs) to the SEC phase. All of these considerations collectively contribute
> to providing additional insights and flexibility for the practical initiation of
> hardware.
>
> +
>
> +### 3.2 Alternative Boot Flow
>
> +The boot flow without the PEI phase, also known as the Pei-Less flow, is the
> initialization approach that will be further discussed in this document. Detailed
> standards for Pei-Less can be obtained from RISE's Firmware TG.
>
> +
>
> +#### 3.2.1 SEC Phase
>
> +See [HOB
> Translations](https://uefi.org/specs/PI/1.8/V2_DXE_Foundation.html#hob-
> translations) for more information on HOB types.
>
> +
>
> +#### <caption>Figuire 3 HOB List
>
> +
>
> +
>
> +The HOBs list, as mandated by the PI specification, is illustrated in Figure 2.3. It
> is recommended to refer to the SecMain structure in RiscVVirt for guidance.
>
> +
>
> +Figure 2.3 displays the HOBs list, a prerequisite set by the PI specification for
> readiness before entering the DXE phase. For additional insights, it is
> recommended to refer to the SecMain module in RiscVVirt.
>
> +
>
> +Regarding memory initialization, specific details are intentionally omitted in this
> document. The recommended strategy involves the use of OOB firmware, like
> SPL. This provides input to the System Memory HOB generated by the UEFI
> firmware during the SEC phase, and the input for HOB is extracted from static
> data in the device tree, including entries like 'memory' by
> AddMemoryBaseSizeHob() and 'reserved-memory BuildMemoryAllocationHob().'
>
> +
>
> +The creation of HOBs for IO, MMIO, and other resources provides SOC vendors
> with the flexibility to customize according to their chip specifications. The
> PopulateIoResources() function provides a straightforward approach to achieve
> this customization.
>
> +
>
> +It is essential to emphasize that RiscVVirt adopts a separate Flash Descriptor
> (FD) approach for firmware code and Variables. The advantage is clear as it
> allows for the protection of the firmware code by setting it as read-only, while
> conferring write permissions exclusively to the Variable FD, effectively ensuring
> the security of the firmware. Particularly, this approach provides convenient and
> flexible control, especially when dealing with firmware upgrade actions in the
> future. Of course, in qemu-based firmware development, virtualizing two or even
> more flashes is extremely straightforward. However, it's worth mentioning that in
> many real hardware platforms, the single-flash configuration is more common,
> and further elaboration on this point is not necessary here.
>
> +
>
> +In the upcoming server platform solution, we will continue to adopt a similar
> approach as RiscVVirt. However, there is a slight difference in the treatment of
> the Variable FD. We prefer to establish a corresponding Memory HOB for the
> Variable's scope during the SEC phase,
>
> +
>
> +The advantage of this adjustment is that there is no longer a strong dependency
> between VariableRuntimeDxe and VirtNorFlashDxe. We no longer need to ensure
> that VirtNorFlashDxe is dispatched before VariableRuntimeDxe. To achieve this
> purpose, the following two steps must be taken:
>
> +* Build Memory Hob for variable region by BuildResourceDescriptorHob() in SEC
> phase.
>
> +* Replace the version of Ovfm with a new VirtNorFlashDxe driver or remove its
> GCD mapping related code. To avoid compatibility issues with other platforms, the
> first implementation approach is adopted in this document.
>
> +
>
> +#### 3.2.2 DXE Phase
>
> +The following table supplements the missing implementation details in Table 2.5
> of the PI specification. The DXE Foundation is abstracted from the platform
> through the DXE Architectural Protocols. The DXE Architectural Protocols
> manifest the platform-specific components of the DXE Foundation. DXE drivers
> that are loaded and executed by the DXE Dispatcher component of the DXE
> Foundation must produce these protocols.
>
> +
>
> +For implementations outside of the EmbeddedPkg solutions, please follow the
> guidance outlined in the table.
>
> +
>
> +
>
> +#### <caption>Table 3 DXE Architectural Protocols
>
> +Protocol Name|Driver Path in use|Driver Compatibility __1__|Task required
>
> +|:--------------------|:-------------------------|:--------------------|:--------------------
>
> +|Security
> Architectural|MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf|Pl
> atform independent|no extra work
>
> +|CPU Architectural|UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf|Platform
> dependent|no extra work
>
> +|Metronome Architectural|EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
> (__Note__: Precision in the EmbeddedPkg version is limited to microseconds,
> whereas the MdeModulePkg version offers precision down to
> nanoseconds.)|Platform dependent|no extra work
>
> +|Timer
> Architectural|UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
> (__Note__: In S mode, utilize the TIME CSR for implementing GetTimer, and
> achieve SetTimer by the ‘Set Timer’ interface of SBI Timer Extension 6.1. Please
> note that the Runtime type of timer service isn’t presently supported yet.
> Runtime type of timer service will be produced by RealTimeClock.)|Platform
> dependent|no extra work
>
> +|BDS Architectural|MdeModulePkg/Universal/BdsDxe/BdsDxe.inf|Platform
> independent|no extra work
>
> +|Watchdog Timer
> Architectural|MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
> (__Note__: It depends on TimerLib and ResetLib, the implementation of which is
> typically determined by the different CPU architectures.)|Platform
> independent|no extra work
>
> +|Runtime Architectural|MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> (__Note__: Some functionalities in the RISC-V version of CacheMaintenanceLib
> are still under development.)|Platform independent|need to complete the
> remaining functions of CacheMaintenanceLib.
>
> +|Variable
> Architectural|MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntime
> Dxe.inf (__Note__: The dependency issue on VirtNorFlashDxe in RiscVVirt has
> been clarified in the preceding chapters. Please refer to Section 2.10 for
> details.)|Platform independent|no extra work
>
> +|Variable Write
> ArchitecturalProtocol|MdeModulePkg/Universal/Variable/RuntimeDxe/VariableR
> untimeDxe.inf | Platform independent|no extra work
>
> +|Monotonic Counter
> Architectural|MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/Monoto
> nicCounterRuntimeDxe.inf|Platform independent|no extra work
>
> +|Reset
> Architectural|MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemR
> untimeDxe.inf (__Note__: ResetSystemLib implements warm reset, cold reset,
> and shutdown through the SBI interface.)|Platform independent|no extra work
>
> +|Real Time Clock
> Architectural|EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntime
> Dxe.inf (__Note__: Some features in RealTimeClockLib remain unimplemented,
> including GetWakeUpTime/SetWakeUpTime. The present RealTimeClockLib is
> specifically designed for qemu; future adaptations should implement their own
> RTC timer based on the platform's needs.)|Platform dependent|no extra work
>
> +|Capsule Architectural
> Protocol|MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> (__Note__: It depends on CacheMaintenanceLib and ResetLib.)|Platform
> independent|no extra work
>
> +
>
> +Note:
>
> +_1.The 'Driver Compatibility, task required' column addresses platform
> dependencies exclusively at the DXE driver level. The platform-specificity of the
> consumed libraries does not influence the conclusion._
>
> +
>
> +#### 3.2.3 Network Stack
>
> +The Server SOC model currently in use, 'ssoc_ref,' comes with e1000 as the
> default NIC device. However, as this device lacks an integrated UEFI UNDI driver,
> it cannot provide the foundational services to enable the network. From a testing
> perspective, here are two recommended steps：
>
> +* Build UndiRuntimeDxe to your firmware FD, with the following patch: edk2-
> platforms/Drivers/OptionRomPkg/UndiRuntimeDxe/UndiRuntimeDxe.inf
>
> +* Append NIC ‘i82557b’ to the qemu command line. See the reference command
> in Chapter 4.
>
> +
>
> +From a product implementation perspective, it is not recommended to directly
> use UndiRuntimeDxe as the provider for the UNDI services. It is more appropriate
> to provide the UNDI services based on the NIC device integrated into the
> platform.
>
> +
>
> +### 3.3 Extra work for Fdt-to-OS
>
> +The DXE Foundation produces the UEFI System Table, and the UEFI System Table
> is consumed by every DXE driver and executable image invoked by the DXE
> Dispatcher and BDS. It contains all the information required for these components
> to utilize the services provided by the DXE Foundation and the services provided
> by any previously loaded DXE driver. [UEFI System Table and Related
> Components](https://uefi.org/specs/PI/1.8/V2_DXE_Foundation.html#uefi-
> system-table-and-related-components) shows the various components that are
> available through the UEFI System Table.
>
> +
>
> +#### <caption>Figuire 4 UEFI System Table and Related Components
>
> +
>
> +
>
> +As shown in figure 9.2, the UEFI Configuration Tables are an extensible list of
> tables that describe the configuration of the platform. Today, this includes pointers
> to tables such as DXE Services, the HOB list, ACPI table, SMBIOS table, and the
> SAL System Table. This list may be expanded in the future as new table types are
> defined.
>
> +
>
> +Due to the broad usage of device trees in embedded firmware products, several
> chip manufacturers in the upstream and downstream supply chains use static
> data from the device tree to initialize specific peripherals. For compatibility
> reasons, it is essential to install the device tree pointer into the system
> configuration table. Two DXE drivers are available as references:
>
> +
>
> +#### <caption>Table 4 The Proposal for FdtTabGuid
>
> +|Table Guid |Driver Path in use |Comments
>
> +|:-------------------- |:-------------------------|:--------------------
>
> +|gFdtTableGuid |EmbeddedPkg/Drivers/FdtClientDxe/FdtClientDxe.inf |Using in
> RiscVVirt
>
> +|gFdtTableGuid |Silicon/RISCV/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf
> |Recommend using the streamlined DXE driver if no required for FdtClientProtocl
>
> +
>
> +### 3.4 DT File Decoding
>
> +The DXE driver FdtClientDxe, mentioned in the previous section, supplies a
> limited set of APIs for parsing DT binary, handling fundamental DT data extraction
> tasks.
>
> +
>
> +Users with more advanced demands can turn to another DXE service produced
> by [FdtBusPkg](https://github.com/intel/FdtBusPkg), which offers an extensive
> array of APIs to meet the requirements of more complex scenarios. Detailed
> information is accessible in the firmware TG of RISE community (Project No.
> [EDK2_00_03](https://wiki.riseproject.dev/display/HOME/Firmware+Projects)),
> and the source code is available from
> [FdtBusPkg](https://github.com/intel/FdtBusPkg) repository. It will be
> upstreamed to the [edk2](https://github.com/tianocore/edk2) repository in the
> future, and any suggestions or requirements for improvement are encouraged
> before this transition.
>
> +
>
> +### 3.5 OpenSbi
>
> +It is recommended to align with the version of OpenSBI in the [RISC-V BRS
> Development Suite Repository](https://github.com/intel/rv-brs-test-suite). The
> binary file can be found at the following path: ./rv-brs-test-
> suite/brsi/scripts/opensbi/build/platform/generic/firmware/fw_dynamic.bin
>
> +
>
> +__Or build it by the command example1__:
>
> +```
>
> +cd opensbi
>
> +make ARCH=riscv CROSS_COMPILE=riscv64-linux-gnu- PLATFORM=generic
>
> +```
>
> +### 3.6 OS Image
>
> +Similarly, the BRS Repo offers an OS image based on RISC-V. To validate the boot
> flow, you can make use of the prebuilt images located in the test suite at /rv-brs-
> test-suite/brsi/prebuilt_images/. For those interested in building their own image,
> please refer to the repository guidance for detailed steps.
>
> +
>
> +## 4 Verification
>
> +The tests covered in this document are based on the BRS spec, focusing on two
> primary modules: SCT and FWTS. The relevant test scripts, pre-build image and
> guidance can be obtained from the [RISC-V BRS Development Suite
> Repository](https://github.com/intel/rv-brs-test-suite):
>
> +
>
> +__Command example2__:
>
> +```
>
> + ./qemu-system-riscv64 -nographic -m 8G -smp 2 \
>
> + -machine ssoc_ref,pflash0=pflash0,pflash1=pflash1 \
>
> + -blockdev node-name=pflash0,driver=file,read-
> only=on,filename=$FW_DIR/RISCV_SP_CODE.fd \
>
> + -blockdev node-
> name=pflash1,driver=file,filename==$FW_DIR/RISCV_SP_VARS.fd \
>
> + -bios $Sbi_DIR/fw_dynamic.bin \
>
> + -drive file=$Img_DIR/brs_live_image.img,if=ide,format=raw
>
> +```
>
> +
>
> +__Note__:
>
> +* _‘ssoc_ref’ is a specified qemu-based SOC model, whose source code is still
> under development and will be accessible from the RVI staging repository later._
>
> +* _The Pre-build image ‘brs_live_image.img,if’ can be downloaded in RISC-V BRS
> Development Suite repository, or you can build it by yourself. See 3.6_
>
> +* _‘-bios $Sbi_DIR/fw_dynamic.bin’ the parameter points to the opensbi path.
> See more in 3.5._
>
> +
>
> +In general, a series of modules related to Network are enabled by default.
> However, during SCT test execution, it is noticed that most Network test items fail
> to pass. The most likely reason is the lack of a UNDI driver built in the current
> platform firmware codebase. So, if you intend to enable the edk2 network stack
> with QEMU in the boot flow, it is suggested to use the following command:
>
> +
>
> +__Command example3__:
>
> +```
>
> + Command example2 \
>
> + -device i82557b,netdev=net2 \
>
> + -netdev type=user,id=net2
>
> +```
>
> +
>
> +## 5 Pending Tasks
>
> +The listed items in the table represent ongoing firmware development tasks that
> are still unfinished. Some specifications are in the process of refinement, and a
> few are yet to be drafted. Please refer to subsequent updates from the RISE
> community for more information.
>
> +### 5.1 Bios Requirements
>
> +
>
> +#### <caption>Table 5 Bios Requirements
>
> +ID | Requirement | Comment
>
> +|:-------------------- |:-------------------------|:--------------------
>
> +|1 | ACPI enabling | The establishment of all ACPI tables is currently achieved
> through qemu, leveraging a series of libraries such as QemuFwCfgLib to interact
> with the Linux kernel. The following task is to implement the publishment of all
> ACPI tables solely through firmware.
>
> +|2 | Smbios | The upcoming tasks for SMBIOS should be handled exclusively
> through firmware publishment, replacing the existing qemu method entirely.
>
> +|4 | FWTS test | Upon the completion of tasks 1 and 2, the pass ratio for FWTS
> should be maintained at a specific benchmark.
>
> +|5 | Security | Not started
>
> +|6 | TPM | Not started
>
> +
>
> +## 6 Known Issues
>
> +The following table outlines the current known issues, which will be resolved
> gradually during the subsequent phases of development.
>
> +
>
> +#### <caption>Table 6 Known Issues
>
> +No. | Issue Description | Cause | Comment
>
> +|:--------------------|:-------------------------|:--------------------|:--------------------
>
> +|1 | Graphic device doesn’t work | ‘Ssoc_ref’ doesn’t provide a default GPU yet
> | Will do in next phase
>
> +|2 | ACPI/Smbios don’t work | Not firmware implementation | Will do in next
> phase
>
> +
>
> +## 7 Appendix
>
> +
>
> +
>
> +
>
> +### 7.1 Building and running based on BRS environment
>
> +
>
> +1. Build brs test suit
>
> +```
>
> +git clone https://github.com/intel/rv-brs-test-suite.git
>
> +```
>
> +
>
> +Please refer to detailed build steps from
> [README.md](https://github.com/intel/rv-brs-test-
> suite/blob/main/README.md), then you will get the following stuff:
>
> +```
>
> + QEMU_DIR=$WORKSPACE/rv-brs-test-suite/brsi/scripts/qemu/build
>
> + BRS_IMG_DIR=$WORKSPACE/rv-brs-test-suite/brsi/scripts/output
>
> + OPENSBI_DIR=$WORKSPACE/rv-brs-test-
> suite/brsi/scripts/opensbi/build/platform/generic/firmware
>
> + EDK2_DIR=$WORKSPACE/rv-brs-test-
> suite/brsi/scripts/Build/RiscVQemuServerPlatform/DEBUG_GCC5/FV
>
> +```
>
> +
>
> +2. Boot Execution(See Command example2)
>
> +```
>
> +$QEMU_DIR/qemu-system-riscv64 \
>
> + -machine ssoc_ref,pflash0=pflash0,pflash1=pflash1 \
>
> + -blockdev node-name=pflash0,driver=file,read-
> only=on,filename=$EDK2_DIR/RISCV_SP_CODE.fd \
>
> + -blockdev node-
> name=pflash1,driver=file,filename=$EDK2_DIR/RISCV_SP_VARS.fd \
>
> + -bios $OPENSBI_DIR/fw_dynamic.bin \
>
> + -drive file=$BRS_IMG_DIR/brs_live_image.img,if=ide,format=raw
>
> +```
>
> +### 7.2 Compiling edk2 firmware separately outside of BRS
>
> +1. Building the RISC-V edk2 server platform
>
> +
>
> +```
>
> +git clone https://github.com/tianocore/edk2.git
>
> +cd edk2
>
> +git submodule update --init
>
> +cd ..
>
> +
>
> +git clone https://github.com/tianocore/edk2-platforms.git
>
> +cd edk2-platforms
>
> +git submodule update --init
>
> +cd ..
>
> +
>
> +export WORKSPACE=`pwd`
>
> +export GCC5_RISCV64_PREFIX=riscv64-linux-gnu-
>
> +export PACKAGES_PATH=$WORKSPACE/edk2:$WORKSPACE/edk2-platforms
>
> +
>
> +cd edk2
>
> +make -C BaseTools clean
>
> +make -C BaseTools
>
> +source edksetup.sh
>
> +./edksetup.sh
>
> +
>
> +build -a RISCV64 -t GCC5 -p
> Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.dsc
>
> +```
>
> +2. Convert FD files
>
> +```
>
> + truncate -s 32M
> Build/RiscVQemuServerPlatform/DEBUG_GCC5/FV/RISCV_SP_CODE.fd
>
> + truncate -s 32M
> Build/RiscVQemuServerPlatform/DEBUG_GCC5/FV/RISCV_SP_VARS.fd
>
> +```
>
> +
>
> +## Contributors
>
> +- Evan Chai <evan.chai@intel.com>
>
> diff --git
> a/Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.dsc
> b/Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.dsc
> new file mode 100755
> index 00000000..45501b35
> --- /dev/null
> +++ b/Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.dsc
> @@ -0,0 +1,703 @@
> +## @file
>
> +# RISC-V EFI on Qemu Server Platform
>
> +#
>
> +# Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
>
> +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights
> reserved.<BR>
>
> +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +
>
> +[Defines]
>
> + PLATFORM_NAME = RiscVQemuServerPlatform
>
> + PLATFORM_GUID = A5FAC672-1D51-4461-AB37-B7DB202F34BA
>
> + PLATFORM_VERSION = 0.1
>
> + DSC_SPECIFICATION = 0x0001001c
>
> + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
>
> + SUPPORTED_ARCHITECTURES = RISCV64
>
> + BUILD_TARGETS = DEBUG|RELEASE|NOOPT
>
> + SKUID_IDENTIFIER = DEFAULT
>
> + FLASH_DEFINITION =
> Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.fdf
>
> +
>
> + #
>
> + # Enable below options may cause build error or may not work on
>
> + # the initial version of RISC-V package
>
> + # Defines for default states. These can be changed on the command line.
>
> + # -D FLAG=VALUE
>
> + #
>
> + DEFINE TTY_TERMINAL = FALSE
>
> + DEFINE SECURE_BOOT_ENABLE = FALSE
>
> + DEFINE TPM2_ENABLE = FALSE
>
> + DEFINE TPM2_CONFIG_ENABLE = FALSE
>
> + DEFINE DEBUG_ON_SERIAL_PORT = TRUE
>
> +
>
> + #
>
> + # Network definition
>
> + #
>
> + DEFINE NETWORK_IP6_ENABLE = FALSE
>
> + DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
>
> + DEFINE NETWORK_SNP_ENABLE = FALSE
>
> + DEFINE NETWORK_TLS_ENABLE = FALSE
>
> + DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS = TRUE
>
> + DEFINE NETWORK_ISCSI_ENABLE = FALSE
>
> +
>
> + DEFINE DEBUG_PRINT_ERROR_LEVEL = 0x80000047
>
> +
>
> +!if $(NETWORK_SNP_ENABLE) == TRUE
>
> + !error "NETWORK_SNP_ENABLE is IA32/X64/EBC only"
>
> +!endif
>
> +
>
> +!include MdePkg/MdeLibs.dsc.inc
>
> +!include NetworkPkg/Network.dsc.inc
>
> +
>
> +[BuildOptions]
>
> + GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
>
> +!ifdef $(SOURCE_DEBUG_ENABLE)
>
> + GCC:*_*_RISCV64_GENFW_FLAGS = --keepexceptiontable
>
> +!endif
>
> +
>
> +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
>
> + GCC: *_*_*_DLINK_FLAGS = -z common-page-size=0x1000
>
> + MSFT: *_*_*_DLINK_FLAGS = /ALIGN:4096
>
> +
>
> +################################################################
> ################
>
> +#
>
> +# Library Class section - list of all Library Classes needed by this Platform.
>
> +#
>
> +################################################################
> ################
>
> +!include MdePkg/MdeLibs.dsc.inc
>
> +
>
> +[LibraryClasses.common]
>
> +!ifdef $(SOURCE_DEBUG_ENABLE)
>
> +
> PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug
> /PeCoffExtraActionLibDebug.inf
>
> +
> DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLi
> bSerialPort/DebugCommunicationLibSerialPort.inf
>
> +!else
>
> +
> PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCo
> ffExtraActionLibNull.inf
>
> +
> DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i
> nf
>
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
>
> +!endif
>
> +!if $(DEBUG_ON_SERIAL_PORT) == TRUE
>
> +
> DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
>
> +!else
>
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
>
> +!endif
>
> +
> DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDeb
> ugPrintErrorLevelLib.inf
>
> + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
>
> + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
>
> + SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
>
> +
> BmpSupportLib|MdeModulePkg/Library/BaseBmpSupportLib/BaseBmpSupportLi
> b.inf
>
> +
> SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizatio
> nLib.inf
>
> +
> PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCo
> ffGetEntryPointLib.inf
>
> + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
>
> + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
>
> +
> UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompr
> essLib.inf
>
> + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
>
> +
> CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCache
> MaintenanceLib.inf
>
> + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
>
> + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
>
> +
> UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/Ue
> fiRuntimeServicesTableLib.inf
>
> +
> DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevic
> ePathLibDevicePathProtocol.inf
>
> +
> UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootSe
> rvicesTableLib.inf
>
> +
> DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.i
> nf
>
> + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
>
> +
> UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint
> .inf
>
> +
> UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplic
> ationEntryPoint.inf
>
> + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
>
> +
> UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.
> inf
>
> + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
>
> + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
>
> + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
>
> + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
>
> +
> OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/B
> aseOrderedCollectionRedBlackTreeLib.inf
>
> + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
>
> +
>
> + #
>
> + # Ramdisk Requirements
>
> + #
>
> + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
>
> +
>
> + #
>
> + # Add support for GCC stack protector
>
> + #
>
> + NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
>
> +
>
> + #
>
> + # RISC-V Architectural Libraries
>
> + #
>
> +
> CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerL
> ib/BaseRiscV64CpuExceptionHandlerLib.inf
>
> + RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
>
> + RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
>
> + ResetSystemLib|Platform/RISC-
> V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
>
> +
>
> +
> RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualRealTi
> meClockLib.inf
>
> + TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
>
> +
> SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib
> 16550.inf
>
> +
>
> +
> DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i
> nf
>
> +
> DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAge
> ntTimerLibNull.inf
>
> +
>
> + #
>
> + # Flattened Device Tree (FDT) access library
>
> + #
>
> + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
>
> +
>
> + #
>
> + # PCI Libraries
>
> + #
>
> + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
>
> + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
>
> +
>
> + #
>
> + # USB Libraries
>
> + #
>
> + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
>
> +
>
> + #
>
> + # CryptoPkg libraries needed by multiple firmware features
>
> + #
>
> + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
>
> +!if $(NETWORK_TLS_ENABLE) == TRUE
>
> + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
>
> +!else
>
> + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
>
> +!endif
>
> + RngLib|MdePkg/Library/BaseRngLibTimerLib/BaseRngLibTimerLib.inf
>
> +
>
> + #
>
> + # Secure Boot dependencies
>
> + #
>
> +!if $(SECURE_BOOT_ENABLE) == TRUE
>
> + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
>
> +
> SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBootV
> ariableLib.inf
>
> +
> SecureBootVariableProvisionLib|SecurityPkg/Library/SecureBootVariableProvisio
> nLib/SecureBootVariableProvisionLib.inf
>
> +
> PlatformPKProtectionLib|SecurityPkg/Library/PlatformPKProtectionLibVarPolicy/P
> latformPKProtectionLibVarPolicy.inf
>
> +
>
> + # re-use the UserPhysicalPresent() dummy implementation from the ovmf tree
>
> + PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf
>
> +!else
>
> +
> AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNul
> l.inf
>
> +!endif
>
> + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
>
> +
> VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseVari
> ableFlashInfoLib.inf
>
> +
> VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLib.inf
>
> +
> VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Variabl
> ePolicyHelperLib.inf
>
> +
> UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootMa
> nagerLib.inf
>
> +
> ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepo
> rtStatusCodeLib.inf
>
> +
> PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLi
> b.inf
>
> +
> ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtra
> ctGuidedSectionLib.inf
>
> + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
>
> +
>
> +
> TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLi
> b.inf
>
> +
> VirtNorFlashPlatformLib|Platform/Qemu/RiscVQemuServerPlatform/Library/Virt
> NorFlashPlatformLib/VirtNorFlashStaticLib.inf
>
> +
>
> + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
>
> + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
>
> + PlatformBootManagerLib|Platform/RISC-
> V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
>
> + PlatformMemoryTestLib|Platform/RISC-
> V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.i
> nf
>
> + PlatformUpdateProgressLib|Platform/RISC-
> V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLi
> bNull.inf
>
> +
> CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize
> dDisplayLib.inf
>
> +
> FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib
> .inf
>
> +
> PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
>
> +
> PciHostBridgeLib|Platform/Qemu/RiscVQemuServerPlatform/Library/PciHostBrid
> geLibEcam/PciHostBridgeLibEcam.inf
>
> +
> PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatfor
> mHookLibNull.inf
>
> +
> ImagePropertiesRecordLib|MdeModulePkg/Library/ImagePropertiesRecordLib/I
> magePropertiesRecordLib.inf
>
> +
>
> +!if $(TPM2_ENABLE) == TRUE
>
> +
> Tpm2CommandLib|SecurityPkg/Library/Tpm2CommandLib/Tpm2CommandLib.in
> f
>
> +
> Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeTc
> g2PhysicalPresenceLib.inf
>
> +
> TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMe
> asurementLib.inf
>
> +
> TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/P
> eiDxeTpmPlatformHierarchyLib.inf
>
> +!else
>
> +
> TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMe
> asurementLibNull.inf
>
> +
> TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibN
> ull/PeiDxeTpmPlatformHierarchyLib.inf
>
> +!endif
>
> +
>
> + RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
>
> +
>
> +[LibraryClasses.common.SEC]
>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
>
> + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
>
> +
> PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLib
> Null.inf
>
> +
> ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExt
> ractGuidedSectionLib.inf
>
> + PlatformSecLib|UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.inf
>
> + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
>
> +
> MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMe
> moryAllocationLib.inf
>
> +
>
> +[LibraryClasses.common.DXE_CORE]
>
> +
> PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerfor
> manceLib.inf
>
> + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
>
> +
> MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/Dxe
> CoreMemoryAllocationLib.inf
>
> + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
>
> +
>
> +[LibraryClasses.common.UEFI_APPLICATION]
>
> +
> MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll
> ocationLib.inf
>
> + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
>
> +
>
> +[LibraryClasses.common.DXE_RUNTIME_DRIVER]
>
> +
> MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll
> ocationLib.inf
>
> +!if $(DEBUG_ON_SERIAL_PORT) == TRUE
>
> +
> DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLib
> SerialPort.inf
>
> +!endif
>
> +
> VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLibRun
> timeDxe.inf
>
> +
>
> +!if $(SECURE_BOOT_ENABLE) == TRUE
>
> + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
>
> +!endif
>
> +
>
> +[LibraryClasses.common.DXE_DRIVER]
>
> +
> SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/D
> xeSecurityManagementLib.inf
>
> +
> MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll
> ocationLib.inf
>
> + AcpiPlatformLib|OvmfPkg/Library/AcpiPlatformLib/DxeAcpiPlatformLib.inf
>
> +
> ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepo
> rtStatusCodeLib.inf
>
> + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
>
> +
>
> +!if $(TPM2_ENABLE) == TRUE
>
> +
> Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibTcg2/Tpm2DeviceLibTcg2.inf
>
> +!endif
>
> +
>
> +[LibraryClasses.common.UEFI_DRIVER]
>
> +
> MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll
> ocationLib.inf
>
> + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
>
> + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
>
> +
>
> +################################################################
> ################
>
> +#
>
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
>
> +#
>
> +################################################################
> ################
>
> +[PcdsFeatureFlag.common]
>
> + #
>
> + # Activate AcpiSdtProtocol
>
> + #
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
>
> +
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
>
> +
>
> + #
>
> + # If TRUE, Graphics Output Protocol will be installed on virtual handle created
> by ConsplitterDxe.
>
> + # It could be set FALSE to save size.
>
> + #
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
>
> +
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
>
> +
>
> +[PcdsFixedAtBuild.common]
>
> + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFC
>
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
>
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
>
> + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
>
> + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
>
> + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
>
> +
>
> + # DEBUG_ASSERT_ENABLED 0x01
>
> + # DEBUG_PRINT_ENABLED 0x02
>
> + # DEBUG_CODE_ENABLED 0x04
>
> + # CLEAR_MEMORY_ENABLED 0x08
>
> + # ASSERT_BREAKPOINT_ENABLED 0x10
>
> + # ASSERT_DEADLOOP_ENABLED 0x20
>
> +!if $(DEBUG_ON_SERIAL_PORT) != TRUE
>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
>
> +!else
>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
>
> +!endif
>
> +
>
> + # DEBUG_INIT 0x00000001 // Initialization
>
> + # DEBUG_WARN 0x00000002 // Warnings
>
> + # DEBUG_LOAD 0x00000004 // Load events
>
> + # DEBUG_FS 0x00000008 // EFI File system
>
> + # DEBUG_POOL 0x00000010 // Alloc & Free (pool)
>
> + # DEBUG_PAGE 0x00000020 // Alloc & Free (page)
>
> + # DEBUG_INFO 0x00000040 // Informational debug messages
>
> + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers
>
> + # DEBUG_VARIABLE 0x00000100 // Variable
>
> + # DEBUG_BM 0x00000400 // Boot Manager
>
> + # DEBUG_BLKIO 0x00001000 // BlkIo Driver
>
> + # DEBUG_NET 0x00004000 // SNP Driver
>
> + # DEBUG_UNDI 0x00010000 // UNDI Driver
>
> + # DEBUG_LOADFILE 0x00020000 // LoadFile
>
> + # DEBUG_EVENT 0x00080000 // Event messages
>
> + # DEBUG_GCD 0x00100000 // Global Coherency Database changes
>
> + # DEBUG_CACHE 0x00200000 // Memory range cachability changes
>
> + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may
>
> + # // significantly impact boot performance
>
> + # DEBUG_ERROR 0x80000000 // Error
>
> +!if $(DEBUG_ON_SERIAL_PORT) == TRUE
>
> +
> gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_
> LEVEL)
>
> +!endif
>
> +
>
> + #
>
> + # Optional feature to help prevent EFI memory map fragments
>
> + # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
>
> + # Values are in EFI Pages (4K). DXE Core will make sure that
>
> + # at least this much of each type of memory can be allocated
>
> + # from a single memory range. This way you only end up with
>
> + # maximum of two fragments for each type in the memory map
>
> + # (the memory used, and the free memory that was prereserved
>
> + # but not used).
>
> + #
>
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
>
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
>
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
>
> +!if $(SECURE_BOOT_ENABLE) == TRUE
>
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|600
>
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|400
>
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1500
>
> +!else
>
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|300
>
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|150
>
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|1000
>
> +!endif
>
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|6000
>
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
>
> + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
>
> +
>
> + #
>
> + # Enable strict image permissions for all images. (This applies
>
> + # only to images that were built with >= 4 KB section alignment.)
>
> + #
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdImageProtectionPolicy|0x3
>
> +
>
> + #
>
> + # Enable NX memory protection for all non-code regions, including OEM and OS
>
> + # reserved ones, with the exception of LoaderData regions, of which OS loaders
>
> + # (i.e., GRUB) may assume that its contents are executable.
>
> + #
>
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdDxeNxMemoryProtectionPolicy|0xC0000
> 00000007FD5
>
> +
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800
>
> +!if $(NETWORK_TLS_ENABLE) == TRUE
>
> + #
>
> + # The cumulative and individual VOLATILE variable size limits should be set
>
> + # high enough for accommodating several and/or large CA certificates.
>
> + #
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x80000
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVolatileVariableSize|0x40000
>
> +!endif
>
> +
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"2.7"
>
> +
>
> + #
>
> + # Serial Port
>
> + #
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseMmio|TRUE
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x10000000
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate|9600
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate|3686400
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride|1
>
> +
>
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange
> |FALSE
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa,
> 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23,
> 0x31 }
>
> +
>
> +!if $(SECURE_BOOT_ENABLE) == TRUE
>
> + #
>
> + # override the default values from SecurityPkg to ensure images from all
> sources are verified in secure boot
>
> + #
>
> + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04
>
> + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04
>
> +
> gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x0
> 4
>
> +!endif
>
> +
>
> + gEfiShellPkgTokenSpaceGuid.PcdShellFileOperationSize|0x20000
>
> + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x02
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1
>
> +
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2
>
> +
>
> + #
>
> + # Reference the value in default DT passed from Qemu
>
> + #
>
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x30000000
>
> +
>
> +[PcdsDynamicDefault.common]
>
> + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|3
>
> +
>
> + #
>
> + # If TRUE, OvmfPkg/AcpiPlatformDxe will not wait for PCI
>
> + # enumeration to complete before installing ACPI tables.
>
> + #
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE
>
> +
>
> + gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation|0x0
>
> +
>
> + #
>
> + # Set video resolution for boot options and for text setup.
>
> + # PlatformDxe can set the former at runtime.
>
> + #
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1280
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|800
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0
>
> +
>
> + #
>
> + # SMBIOS entry point version
>
> + #
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0300
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0
>
> +
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0
>
> +
>
> + #
>
> + # TPM2 support
>
> + #
>
> +!if $(TPM2_ENABLE) == TRUE
>
> + gEfiSecurityPkgTokenSpaceGuid.PcdTpmBaseAddress|0x0
>
> + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
>
> + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2HashMask|0
>
> +!endif
>
> +
>
> +[PcdsPatchableInModule]
>
> + #
>
> + # PCI Root Complex - ECAM
>
> + #
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciBusMin|0
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciBusMax|255
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciIoBase|0x0
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciIoSize|0x00010000
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio32Base|0x40000000
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio32Size|0x40000000
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio64Base|0x400000000
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPciMmio64Size|0x400000000
>
> +
>
> +[PcdsDynamicHii]
>
> +!if $(TPM2_CONFIG_ENABLE) == TRUE
>
> +
> gEfiSecurityPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|L"TCG2_VE
> RSION"|gTcg2ConfigFormSetGuid|0x0|"1.3"|NV,BS
>
> +
> gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableRev|L"TCG2_VERSION"|gTcg2
> ConfigFormSetGuid|0x8|3|NV,BS
>
> +!endif
>
> +
>
> +
> gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar
> iableGuid|0x0|5
>
> +
>
> +################################################################
> ################
>
> +#
>
> +# Components Section - list of all EDK II Modules needed by this Platform.
>
> +#
>
> +################################################################
> ################
>
> +[Components.common]
>
> + #
>
> + # SEC Phase modules
>
> + #
>
> + Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.inf {
>
> + <LibraryClasses>
>
> +
> ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/Pr
> ePiExtractGuidedSectionLib.inf
>
> +
> LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/Lzma
> CustomDecompressLib.inf
>
> + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
>
> +
> PrePiHobListPointerLib|OvmfPkg/RiscVVirt/Library/PrePiHobListPointerLib/PrePi
> HobListPointerLib.inf
>
> +
> MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMe
> moryAllocationLib.inf
>
> + }
>
> +
>
> + #
>
> + # DXE
>
> + #
>
> + MdeModulePkg/Core/Dxe/DxeMain.inf {
>
> + <LibraryClasses>
>
> +
> NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32Guid
> edSectionExtractLib.inf
>
> + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
>
> + }
>
> +
>
> + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
>
> + <LibraryClasses>
>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
>
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
>
> + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
>
> + }
>
> +
>
> + #
>
> + # Architectural Protocols
>
> + #
>
> + UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
>
> + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
>
> + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
>
> + <LibraryClasses>
>
> + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
>
> + # do not use unaligned CopyMem () on the UEFI varstore NOR flash region
>
> + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
>
> + }
>
> +
>
> +!if $(SECURE_BOOT_ENABLE) == TRUE
>
> + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {
>
> + <LibraryClasses>
>
> +
> NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf
>
> +!if $(TPM2_ENABLE) == TRUE
>
> +
> NULL|SecurityPkg/Library/DxeTpm2MeasureBootLib/DxeTpm2MeasureBootLib.i
> nf
>
> +!endif
>
> + }
>
> +
> SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.i
> nf
>
> +!else
>
> + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
>
> +!endif
>
> + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
>
> + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
>
> +
> MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu
> ntimeDxe.inf
>
> +
> MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
>
> + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
>
> + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
>
> +
>
> + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
>
> + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
>
> +
> MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
>
> + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
>
> + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
>
> +
>
> + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
>
> +
>
> + UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
>
> +
> Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashDxe.inf
>
> + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
>
> +
>
> + #
>
> + # Status Code Routing
>
> + #
>
> +
> MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCo
> deRouterRuntimeDxe.inf
>
> +
> MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerR
> untimeDxe.inf
>
> +
>
> + #
>
> + # Silicon Driver
>
> + #
>
> + Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf
>
> +
>
> + #
>
> + # FAT filesystem + GPT/MBR partitioning + UDF filesystem + virtio-fs
>
> + #
>
> + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
>
> + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
>
> + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
>
> + FatPkg/EnhancedFatDxe/Fat.inf
>
> + MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf
>
> +
>
> + #
>
> + # Bds
>
> + #
>
> + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf {
>
> + <LibraryClasses>
>
> + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
>
> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
>
> + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
>
> + }
>
> + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
>
> + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
>
> +
> MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.i
> nf
>
> + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
>
> + MdeModulePkg/Logo/LogoDxe.inf
>
> + MdeModulePkg/Application/UiApp/UiApp.inf {
>
> + <LibraryClasses>
>
> +
> NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
>
> + NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
>
> +
> NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanc
> eManagerUiLib.inf
>
> + }
>
> +
>
> + #
>
> + # SCSI Bus and Disk Driver
>
> + #
>
> + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
>
> + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
>
> +
>
> + #
>
> + # SATA
>
> + #
>
> + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
>
> + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
>
> + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
>
> +
>
> + #
>
> + # NVME Driver
>
> + #
>
> + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
>
> +
>
> + #
>
> + # SMBIOS Support
>
> + #
>
> + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
>
> +
>
> + #
>
> + # PCI support
>
> + #
>
> + UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
>
> + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
>
> + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
>
> +
>
> + #
>
> + # Video support
>
> + #
>
> + OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf
>
> +
>
> + #
>
> + # USB Support
>
> + #
>
> + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
>
> + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
>
> + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
>
> + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
>
> + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
>
> + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
>
> +
>
> + #
>
> + # TPM2 support
>
> + #
>
> +!if $(TPM2_ENABLE) == TRUE
>
> + SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf {
>
> + <LibraryClasses>
>
> +
> HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCryptoRout
> erDxe.inf
>
> +
> Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibRoute
> rDxe.inf
>
> + NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf
>
> + NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf
>
> +
> NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf
>
> +
> NULL|SecurityPkg/Library/HashInstanceLibSha384/HashInstanceLibSha384.inf
>
> +
> NULL|SecurityPkg/Library/HashInstanceLibSha512/HashInstanceLibSha512.inf
>
> + NULL|SecurityPkg/Library/HashInstanceLibSm3/HashInstanceLibSm3.inf
>
> + }
>
> +!if $(TPM2_CONFIG_ENABLE) == TRUE
>
> + SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigDxe.inf
>
> +!endif
>
> +!endif
>
> +
>
> + #
>
> + # ACPI Support
>
> + #
>
> +
> MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsRe
> sourceTableDxe.inf
>
> + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf {
>
> + <LibraryClasses>
>
> + NULL|EmbeddedPkg/Library/PlatformHasAcpiLib/PlatformHasAcpiLib.inf
>
> + }
>
> +
>
> + #
>
> + # Ramdisk support
>
> + #
>
> + MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf
>
> +
>
> + #
>
> + # UEFI Shell
>
> + #
>
> + ShellPkg/Application/Shell/Shell.inf {
>
> + <LibraryClasses>
>
> +
> ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib
> .inf
>
> +
> NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Commands
> Lib.inf
>
> +
> NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Commands
> Lib.inf
>
> +
> NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Commands
> Lib.inf
>
> +
> NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Comman
> dsLib.inf
>
> +
> NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comman
> dsLib.inf
>
> +!if $(ACPIVIEW_ENABLE) == TRUE
>
> +
> NULL|ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewComm
> andLib.inf
>
> +!endif
>
> +
> NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1Comman
> dsLib.inf
>
> +
> NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1Com
> mandsLib.inf
>
> +!if $(NETWORK_IP6_ENABLE) == TRUE
>
> +
> NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2Com
> mandsLib.inf
>
> +!endif
>
> +
> HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.i
> nf
>
> + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
>
> +
> BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCom
> mandLib.inf
>
> +
>
> + <PcdsFixedAtBuild>
>
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
>
> + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
>
> + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
>
> + }
>
> diff --git
> a/Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.fdf
> b/Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.fdf
> new file mode 100755
> index 00000000..caa41462
> --- /dev/null
> +++ b/Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.fdf
> @@ -0,0 +1,284 @@
> +## @file
>
> +# RISC-V EFI on Qemu Server Platform
>
> +#
>
> +# Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
>
> +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights
> reserved.<BR>
>
> +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +
>
> +!include RiscVQemuServerPlatform.fdf.inc
>
> +
>
> +################################################################
> ################
>
> +[FD.RISCV_SP_CODE]
>
> +BaseAddress =
> $(CODE_BASE_ADDRESS)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddres
> s
>
> +Size =
> $(CODE_SIZE)|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize
>
> +ErasePolarity = 1
>
> +BlockSize = $(BLOCK_SIZE)
>
> +NumBlocks = $(CODE_BLOCKS)
>
> +
>
> +0x00000000|$(CODE_SIZE)
>
> +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|gUefiRiscVPlatform
> PkgTokenSpaceGuid.PcdRiscVDxeFvSize
>
> +FV = FVMAIN_COMPACT
>
> +
>
> +################################################################
> ################
>
> +[FD.RISCV_SP_VARS]
>
> +BaseAddress = $(VARS_BASE_ADDRESS)
>
> +Size = $(VARS_SIZE)
>
> +ErasePolarity = 1
>
> +BlockSize = $(VARS_BLOCK_SIZE)
>
> +NumBlocks = $(VARS_BLOCKS)
>
> +
>
> +!include VarStore.fdf.inc
>
> +################################################################
> ################
>
> +
>
> +[FV.DXEFV]
>
> +BlockSize = 0x10000
>
> +FvAlignment = 16
>
> +ERASE_POLARITY = 1
>
> +MEMORY_MAPPED = TRUE
>
> +STICKY_WRITE = TRUE
>
> +LOCK_CAP = TRUE
>
> +LOCK_STATUS = TRUE
>
> +WRITE_DISABLED_CAP = TRUE
>
> +WRITE_ENABLED_CAP = TRUE
>
> +WRITE_STATUS = TRUE
>
> +WRITE_LOCK_CAP = TRUE
>
> +WRITE_LOCK_STATUS = TRUE
>
> +READ_DISABLED_CAP = TRUE
>
> +READ_ENABLED_CAP = TRUE
>
> +READ_STATUS = TRUE
>
> +READ_LOCK_CAP = TRUE
>
> +READ_LOCK_STATUS = TRUE
>
> +
>
> +#
>
> +# DXE Phase modules
>
> +#
>
> +INF MdeModulePkg/Core/Dxe/DxeMain.inf
>
> +INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
>
> +INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
>
> +INF Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf
>
> +
>
> +#
>
> +# PI DXE Drivers producing Architectural Protocols (EFI Services)
>
> +#
>
> +INF UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
>
> +INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
>
> +INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
>
> +INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
>
> +INF
> MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
>
> +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
>
> +!if $(SECURE_BOOT_ENABLE) == TRUE
>
> + INF
> SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.i
> nf
>
> +!endif
>
> +INF
> MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRu
> ntimeDxe.inf
>
> +INF
> MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
>
> +INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
>
> +INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
>
> +INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
>
> +
>
> +#
>
> +# Multiple Console IO support
>
> +#
>
> +INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
>
> +INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
>
> +INF
> MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
>
> +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
>
> +INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
>
> +
>
> +# RISC-V Core Drivers
>
> +INF UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
>
> +INF
> Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashDxe.inf
>
> +INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
>
> +
>
> +#
>
> +# FAT filesystem + GPT/MBR partitioning + UDF filesystem + virtio-fs
>
> +#
>
> +INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
>
> +INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
>
> +INF FatPkg/EnhancedFatDxe/Fat.inf
>
> +INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
>
> +INF MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf
>
> +
>
> +#
>
> +# Status Code Routing
>
> +#
>
> +INF
> MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCo
> deRouterRuntimeDxe.inf
>
> +INF
> MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerR
> untimeDxe.inf
>
> +
>
> +#
>
> +# UEFI Shell
>
> +#
>
> +INF ShellPkg/Application/Shell/Shell.inf
>
> +
>
> +#
>
> +# Bds
>
> +#
>
> +INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
>
> +INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
>
> +INF
> MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.i
> nf
>
> +INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
>
> +INF MdeModulePkg/Application/UiApp/UiApp.inf
>
> +
>
> +#
>
> +# Networking stack
>
> +#
>
> +!include NetworkPkg/Network.fdf.inc
>
> +
>
> +#
>
> +# SCSI Bus and Disk Driver
>
> +#
>
> +INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
>
> +INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
>
> +
>
> +#
>
> +# SATA
>
> +#
>
> +INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
>
> +INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
>
> +INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
>
> +
>
> +#
>
> +# NVME Driver
>
> +#
>
> +INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
>
> +
>
> +#
>
> +# SMBIOS Support
>
> +#
>
> +INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
>
> +
>
> +#
>
> +# ACPI Support
>
> +#
>
> +INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
>
> +INF
> MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsRe
> sourceTableDxe.inf
>
> +
>
> +#
>
> +# PCI support
>
> +#
>
> +INF UefiCpuPkg/CpuMmio2Dxe/CpuMmio2Dxe.inf
>
> +INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
>
> +INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
>
> +
>
> +#
>
> +# Video support
>
> +#
>
> +INF OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf
>
> +
>
> +#
>
> +# Usb Support
>
> +#
>
> +INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
>
> +INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
>
> +INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
>
> +INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
>
> +INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
>
> +INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
>
> +
>
> +#
>
> +# TianoCore logo (splash screen)
>
> +#
>
> +INF MdeModulePkg/Logo/LogoDxe.inf
>
> +
>
> +#
>
> +# Ramdisk support
>
> +#
>
> +INF MdeModulePkg/Universal/Disk/RamDiskDxe/RamDiskDxe.inf
>
> +
>
> +################################################################
> ################
>
> +
>
> +[FV.FVMAIN_COMPACT]
>
> +FvAlignment = 16
>
> +ERASE_POLARITY = 1
>
> +MEMORY_MAPPED = TRUE
>
> +STICKY_WRITE = TRUE
>
> +LOCK_CAP = TRUE
>
> +LOCK_STATUS = TRUE
>
> +WRITE_DISABLED_CAP = TRUE
>
> +WRITE_ENABLED_CAP = TRUE
>
> +WRITE_STATUS = TRUE
>
> +WRITE_LOCK_CAP = TRUE
>
> +WRITE_LOCK_STATUS = TRUE
>
> +READ_DISABLED_CAP = TRUE
>
> +READ_ENABLED_CAP = TRUE
>
> +READ_STATUS = TRUE
>
> +READ_LOCK_CAP = TRUE
>
> +READ_LOCK_STATUS = TRUE
>
> +FvNameGuid = 27A72E80-3118-4c0c-8673-AA5B4EFA9613
>
> +
>
> +INF Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.inf
>
> +
>
> +FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
>
> + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
>
> + SECTION FV_IMAGE = DXEFV
>
> + }
>
> + }
>
> +
>
> +[Rule.Common.SEC]
>
> + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
>
> + PE32 PE32 Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
>
> + UI STRING ="$(MODULE_NAME)" Optional
>
> + VERSION STRING ="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
>
> + }
>
> +
>
> +[Rule.Common.DXE_CORE]
>
> + FILE DXE_CORE = $(NAMED_GUID) {
>
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
>
> + UI STRING="$(MODULE_NAME)" Optional
>
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
>
> + }
>
> +
>
> +[Rule.Common.DXE_DRIVER]
>
> + FILE DRIVER = $(NAMED_GUID) {
>
> + DXE_DEPEX DXE_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
>
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
>
> + UI STRING="$(MODULE_NAME)" Optional
>
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
>
> + }
>
> +
>
> +[Rule.Common.DXE_RUNTIME_DRIVER]
>
> + FILE DRIVER = $(NAMED_GUID) {
>
> + DXE_DEPEX DXE_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
>
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
>
> + UI STRING="$(MODULE_NAME)" Optional
>
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
>
> + }
>
> +
>
> +[Rule.Common.UEFI_DRIVER]
>
> + FILE DRIVER = $(NAMED_GUID) {
>
> + DXE_DEPEX DXE_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
>
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
>
> + UI STRING="$(MODULE_NAME)" Optional
>
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
>
> + }
>
> +
>
> +[Rule.Common.UEFI_DRIVER.BINARY]
>
> + FILE DRIVER = $(NAMED_GUID) {
>
> + DXE_DEPEX DXE_DEPEX Optional |.depex
>
> + PE32 PE32 |.efi
>
> + UI STRING="$(MODULE_NAME)" Optional
>
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
>
> + }
>
> +
>
> +[Rule.Common.UEFI_APPLICATION]
>
> + FILE APPLICATION = $(NAMED_GUID) {
>
> + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
>
> + UI STRING="$(MODULE_NAME)" Optional
>
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
>
> + }
>
> +
>
> +[Rule.Common.UEFI_APPLICATION.BINARY]
>
> + FILE APPLICATION = $(NAMED_GUID) {
>
> + PE32 PE32 |.efi
>
> + UI STRING="$(MODULE_NAME)" Optional
>
> + VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
>
> + }
>
> +
>
> +[Rule.Common.USER_DEFINED.ACPITABLE]
>
> + FILE FREEFORM = $(NAMED_GUID) {
>
> + RAW ACPI |.acpi
>
> + RAW ASL |.aml
>
> + UI STRING="$(MODULE_NAME)" Optional
>
> + }
>
> diff --git
> a/Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.fdf.inc
> b/Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.fdf.inc
> new file mode 100755
> index 00000000..63c601d1
> --- /dev/null
> +++
> b/Platform/Qemu/RiscVQemuServerPlatform/RiscVQemuServerPlatform.fdf.inc
> @@ -0,0 +1,42 @@
> +## @file
>
> +# Definitions of Flash definition file on RISC-V Qemu Server Platform
>
> +#
>
> +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights
> reserved.<BR>
>
> +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
>
> +# Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +[Defines]
>
> +DEFINE BLOCK_SIZE = 0x1000
>
> +
>
> +DEFINE PFLASH0_BASE = 0x20000000
>
> +DEFINE PFLASH1_BASE = 0x22000000
>
> +
>
> +DEFINE CODE_BASE_ADDRESS = $(PFLASH0_BASE)
>
> +DEFINE CODE_SIZE = 0x00800000
>
> +DEFINE CODE_BLOCKS = 0x800
>
> +
>
> +DEFINE VARS_BASE_ADDRESS = $(PFLASH1_BASE)
>
> +DEFINE VARS_SIZE = 0x000C0000
>
> +DEFINE VARS_BLOCK_SIZE = 0x40000
>
> +DEFINE VARS_BLOCKS = 0x3
>
> +
>
> +#
>
> +# EFI Variable memory region.
>
> +# The total size of EFI Variable FD must include
>
> +# all of sub regions of EFI Variable
>
> +#
>
> +DEFINE VARS_OFFSET = 0x00000000
>
> +DEFINE VARS_LIVE_SIZE = 0x00040000
>
> +DEFINE VARS_FTW_WORKING_OFFSET = $(VARS_OFFSET) +
> $(VARS_LIVE_SIZE)
>
> +DEFINE VARS_FTW_WORKING_SIZE = 0x00040000
>
> +DEFINE VARS_FTW_SPARE_OFFSET = $(VARS_FTW_WORKING_OFFSET) +
> $(VARS_FTW_WORKING_SIZE)
>
> +DEFINE VARS_FTW_SPARE_SIZE = 0x00040000
>
> +
>
> +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency =
> 10000000
>
> +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvBase =
> 0x83FF0000
>
> +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvSize =
> 0x00010000
>
> +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress =
> $(PFLASH1_BASE)
>
> +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize =
> $(VARS_SIZE)
>
> diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Sec/Cpu.c
> b/Platform/Qemu/RiscVQemuServerPlatform/Sec/Cpu.c
> new file mode 100755
> index 00000000..2c16df69
> --- /dev/null
> +++ b/Platform/Qemu/RiscVQemuServerPlatform/Sec/Cpu.c
> @@ -0,0 +1,33 @@
> +/** @file
>
> +The library call to pass the device tree to DXE via HOB.
>
> +
>
> +Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights
> reserved.<BR>
>
> +
>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +
>
> +**/
>
> +
>
> +//
>
> +//// The package level header files this module uses
>
> +////
>
> +#include <PiPei.h>
>
> +
>
> +#include <Library/DebugLib.h>
>
> +#include <Library/HobLib.h>
>
> +
>
> +/**
>
> + Cpu Peim initialization.
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +CpuPeimInitialization (
>
> + VOID
>
> + )
>
> +{
>
> + //
>
> + // for MMU type >= sv39
>
> + //
>
> + BuildCpuHob (56, 32);
>
> +
>
> + return EFI_SUCCESS;
>
> +}
>
> diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Sec/Memory.c
> b/Platform/Qemu/RiscVQemuServerPlatform/Sec/Memory.c
> new file mode 100755
> index 00000000..7c6d920b
> --- /dev/null
> +++ b/Platform/Qemu/RiscVQemuServerPlatform/Sec/Memory.c
> @@ -0,0 +1,318 @@
> +/** @file
>
> + Memory Detection for Virtual Machines.
>
> +
>
> + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights
> reserved.<BR>
>
> + Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +
>
> +Module Name:
>
> +
>
> + MemDetect.c
>
> +
>
> +**/
>
> +
>
> +//
>
> +// The package level header files this module uses
>
> +//
>
> +#include <PiPei.h>
>
> +
>
> +//
>
> +// The Library classes this module consumes
>
> +//
>
> +#include <Library/BaseMemoryLib.h>
>
> +#include <Library/DebugLib.h>
>
> +#include <Library/HobLib.h>
>
> +#include <Library/IoLib.h>
>
> +#include <Library/PcdLib.h>
>
> +#include <Library/PeimEntryPoint.h>
>
> +#include <Library/ResourcePublicationLib.h>
>
> +#include <Library/BaseRiscVSbiLib.h>
>
> +#include <Register/RiscV64/RiscVEncoding.h>
>
> +#include <Library/PrePiLib.h>
>
> +#include <libfdt.h>
>
> +#include <Guid/FdtHob.h>
>
> +
>
> +VOID
>
> +BuildMemoryTypeInformationHob (
>
> + VOID
>
> + );
>
> +
>
> +/**
>
> + Create memory range resource HOB using the memory base
>
> + address and size.
>
> +
>
> + @param MemoryBase Memory range base address.
>
> + @param MemorySize Memory range size.
>
> +
>
> +**/
>
> +STATIC
>
> +VOID
>
> +AddMemoryBaseSizeHob (
>
> + IN EFI_PHYSICAL_ADDRESS MemoryBase,
>
> + IN UINT64 MemorySize
>
> + )
>
> +{
>
> + BuildResourceDescriptorHob (
>
> + EFI_RESOURCE_SYSTEM_MEMORY,
>
> + EFI_RESOURCE_ATTRIBUTE_PRESENT |
>
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
>
> + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
>
> + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
>
> + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
>
> + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
>
> + EFI_RESOURCE_ATTRIBUTE_TESTED,
>
> + MemoryBase,
>
> + MemorySize
>
> + );
>
> +}
>
> +
>
> +/**
>
> + Create memory range resource HOB using memory base
>
> + address and top address of the memory range.
>
> +
>
> + @param MemoryBase Memory range base address.
>
> + @param MemoryLimit Memory range size.
>
> +
>
> +**/
>
> +STATIC
>
> +VOID
>
> +AddMemoryRangeHob (
>
> + IN EFI_PHYSICAL_ADDRESS MemoryBase,
>
> + IN EFI_PHYSICAL_ADDRESS MemoryLimit
>
> + )
>
> +{
>
> + AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit -
> MemoryBase));
>
> +}
>
> +
>
> +/**
>
> + Publish system RAM and reserve memory regions.
>
> +
>
> +**/
>
> +STATIC
>
> +VOID
>
> +InitializeRamRegions (
>
> + IN EFI_PHYSICAL_ADDRESS SystemMemoryBase,
>
> + IN UINT64 SystemMemorySize
>
> + )
>
> +{
>
> + AddMemoryRangeHob (
>
> + SystemMemoryBase,
>
> + SystemMemoryBase + SystemMemorySize
>
> + );
>
> +}
>
> +
>
> +/** Get the number of cells for a given property
>
> +
>
> + @param[in] Fdt Pointer to Device Tree (DTB)
>
> + @param[in] Node Node
>
> + @param[in] Name Name of the property
>
> +
>
> + @return Number of cells.
>
> +**/
>
> +STATIC
>
> +INT32
>
> +GetNumCells (
>
> + IN VOID *Fdt,
>
> + IN INT32 Node,
>
> + IN CONST CHAR8 *Name
>
> + )
>
> +{
>
> + CONST INT32 *Prop;
>
> + INT32 Len;
>
> + UINT32 Val;
>
> +
>
> + Prop = fdt_getprop (Fdt, Node, Name, &Len);
>
> + if (Prop == NULL) {
>
> + return Len;
>
> + }
>
> +
>
> + if (Len != sizeof (*Prop)) {
>
> + return -FDT_ERR_BADNCELLS;
>
> + }
>
> +
>
> + Val = fdt32_to_cpu (*Prop);
>
> + if (Val > FDT_MAX_NCELLS) {
>
> + return -FDT_ERR_BADNCELLS;
>
> + }
>
> +
>
> + return (INT32)Val;
>
> +}
>
> +
>
> +/** Mark reserved memory ranges in the EFI memory map
>
> +
>
> + * As per DT spec v0.4 Section 3.5.4,
>
> + * "Reserved regions with the no-map property must be listed in the
>
> + * memory map with type EfiReservedMemoryType. All other reserved
>
> + * regions must be listed with type EfiBootServicesData."
>
> +
>
> + @param FdtPointer Pointer to FDT
>
> +
>
> +**/
>
> +STATIC
>
> +VOID
>
> +AddReservedMemoryMap (
>
> + IN VOID *FdtPointer
>
> + )
>
> +{
>
> + CONST INT32 *RegProp;
>
> + INT32 Node;
>
> + INT32 SubNode;
>
> + INT32 Len;
>
> + EFI_PHYSICAL_ADDRESS Addr;
>
> + UINT64 Size;
>
> + INTN NumRsv, i;
>
> + INT32 NumAddrCells, NumSizeCells;
>
> +
>
> + NumRsv = fdt_num_mem_rsv (FdtPointer);
>
> +
>
> + /* Look for an existing entry and add it to the efi mem map. */
>
> + for (i = 0; i < NumRsv; i++) {
>
> + if (fdt_get_mem_rsv (FdtPointer, i, &Addr, &Size) != 0) {
>
> + continue;
>
> + }
>
> +
>
> + BuildMemoryAllocationHob (
>
> + Addr,
>
> + Size,
>
> + EfiReservedMemoryType
>
> + );
>
> + }
>
> +
>
> + /* process reserved-memory */
>
> + Node = fdt_subnode_offset (FdtPointer, 0, "reserved-memory");
>
> + if (Node >= 0) {
>
> + NumAddrCells = GetNumCells (FdtPointer, Node, "#address-cells");
>
> + if (NumAddrCells <= 0) {
>
> + return;
>
> + }
>
> +
>
> + NumSizeCells = GetNumCells (FdtPointer, Node, "#size-cells");
>
> + if (NumSizeCells <= 0) {
>
> + return;
>
> + }
>
> +
>
> + fdt_for_each_subnode (SubNode, FdtPointer, Node) {
>
> + RegProp = fdt_getprop (FdtPointer, SubNode, "reg", &Len);
>
> +
>
> + if ((RegProp != 0) && (Len == ((NumAddrCells + NumSizeCells) * sizeof
> (INT32)))) {
>
> + Addr = fdt32_to_cpu (RegProp[0]);
>
> +
>
> + if (NumAddrCells > 1) {
>
> + Addr = (Addr << 32) | fdt32_to_cpu (RegProp[1]);
>
> + }
>
> +
>
> + RegProp += NumAddrCells;
>
> + Size = fdt32_to_cpu (RegProp[0]);
>
> +
>
> + if (NumSizeCells > 1) {
>
> + Size = (Size << 32) | fdt32_to_cpu (RegProp[1]);
>
> + }
>
> +
>
> + DEBUG ((
>
> + DEBUG_INFO,
>
> + "%a: Adding Reserved Memory Addr = 0x%llx, Size = 0x%llx\n",
>
> + __func__,
>
> + Addr,
>
> + Size
>
> + ));
>
> +
>
> + if (fdt_getprop (FdtPointer, SubNode, "no-map", &Len)) {
>
> + BuildMemoryAllocationHob (
>
> + Addr,
>
> + Size,
>
> + EfiReservedMemoryType
>
> + );
>
> + } else {
>
> + BuildMemoryAllocationHob (
>
> + Addr,
>
> + Size,
>
> + EfiBootServicesData
>
> + );
>
> + }
>
> + }
>
> + }
>
> + }
>
> +}
>
> +
>
> +/**
>
> + Initialize memory hob based on the DTB information.
>
> +
>
> + @return EFI_SUCCESS The memory hob added successfully.
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +MemoryPeimInitialization (
>
> + VOID
>
> + )
>
> +{
>
> + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext;
>
> + CONST UINT64 *RegProp;
>
> + CONST CHAR8 *Type;
>
> + UINT64 CurBase, CurSize;
>
> + INT32 Node, Prev;
>
> + INT32 Len;
>
> + VOID *FdtPointer;
>
> +
>
> + FirmwareContext = NULL;
>
> + GetFirmwareContextPointer (&FirmwareContext);
>
> +
>
> + if (FirmwareContext == NULL) {
>
> + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __func__));
>
> + return EFI_UNSUPPORTED;
>
> + }
>
> +
>
> + FdtPointer = (VOID *)FirmwareContext->FlattenedDeviceTree;
>
> + if (FdtPointer == NULL) {
>
> + DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __func__));
>
> + return EFI_UNSUPPORTED;
>
> + }
>
> +
>
> + // Look for the lowest memory node
>
> + for (Prev = 0; ; Prev = Node) {
>
> + Node = fdt_next_node (FdtPointer, Prev, NULL);
>
> + if (Node < 0) {
>
> + break;
>
> + }
>
> +
>
> + // Check for memory node
>
> + Type = fdt_getprop (FdtPointer, Node, "device_type", &Len);
>
> + if (Type && (AsciiStrnCmp (Type, "memory", Len) == 0)) {
>
> + // Get the 'reg' property of this node. For now, we will assume
>
> + // two 8 byte quantities for base and size, respectively.
>
> + RegProp = fdt_getprop (FdtPointer, Node, "reg", &Len);
>
> + if ((RegProp != 0) && (Len == (2 * sizeof (UINT64)))) {
>
> + CurBase = fdt64_to_cpu (ReadUnaligned64 (RegProp));
>
> + CurSize = fdt64_to_cpu (ReadUnaligned64 (RegProp + 1));
>
> +
>
> + DEBUG ((
>
> + DEBUG_INFO,
>
> + "%a: System RAM @ 0x%lx - 0x%lx\n",
>
> + __func__,
>
> + CurBase,
>
> + CurBase + CurSize - 1
>
> + ));
>
> +
>
> + InitializeRamRegions (
>
> + CurBase,
>
> + CurSize
>
> + );
>
> + } else {
>
> + DEBUG ((
>
> + DEBUG_ERROR,
>
> + "%a: Failed to parse FDT memory node\n",
>
> + __func__
>
> + ));
>
> + }
>
> + }
>
> + }
>
> +
>
> + AddReservedMemoryMap (FdtPointer);
>
> +
>
> + /* Make sure SEC is booting with bare mode */
>
> + ASSERT ((RiscVGetSupervisorAddressTranslationRegister () & SATP64_MODE)
> == (SATP_MODE_OFF << SATP64_MODE_SHIFT));
>
> +
>
> + BuildMemoryTypeInformationHob ();
>
> +
>
> + return EFI_SUCCESS;
>
> +}
>
> diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Sec/Platform.c
> b/Platform/Qemu/RiscVQemuServerPlatform/Sec/Platform.c
> new file mode 100755
> index 00000000..47827ab7
> --- /dev/null
> +++ b/Platform/Qemu/RiscVQemuServerPlatform/Sec/Platform.c
> @@ -0,0 +1,160 @@
> +/** @file
>
> +The library call to pass the device tree to DXE via HOB.
>
> +
>
> +Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights
> reserved.<BR
>
> +Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
>
> +
>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +
>
> +**/
>
> +
>
> +//
>
> +//// The package level header files this module uses
>
> +////
>
> +#include <PiPei.h>
>
> +
>
> +#include <Library/DebugLib.h>
>
> +#include <Library/HobLib.h>
>
> +#include <Library/MemoryAllocationLib.h>
>
> +#include <Library/BaseRiscVSbiLib.h>
>
> +#include <Library/PcdLib.h>
>
> +#include <Include/Library/PrePiLib.h>
>
> +#include <libfdt.h>
>
> +#include <Guid/FdtHob.h>
>
> +
>
> +/**
>
> + Build memory map I/O range resource HOB using the
>
> + base address and size.
>
> +
>
> + @param MemoryBase Memory map I/O base.
>
> + @param MemorySize Memory map I/O size.
>
> +
>
> +**/
>
> +STATIC
>
> +VOID
>
> +AddIoMemoryBaseSizeHob (
>
> + EFI_PHYSICAL_ADDRESS MemoryBase,
>
> + UINT64 MemorySize
>
> + )
>
> +{
>
> + /* Align to EFI_PAGE_SIZE */
>
> + MemorySize = ALIGN_VALUE (MemorySize, EFI_PAGE_SIZE);
>
> + BuildResourceDescriptorHob (
>
> + EFI_RESOURCE_MEMORY_MAPPED_IO,
>
> + EFI_RESOURCE_ATTRIBUTE_PRESENT |
>
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
>
> + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
>
> + EFI_RESOURCE_ATTRIBUTE_TESTED,
>
> + MemoryBase,
>
> + MemorySize
>
> + );
>
> +}
>
> +
>
> +/**
>
> + Populate IO resources from FDT that not added to GCD by its
>
> + driver in the DXE phase.
>
> +
>
> + @param FdtBase Fdt base address
>
> + @param Compatible Compatible string
>
> +
>
> +**/
>
> +STATIC
>
> +VOID
>
> +PopulateIoResources (
>
> + VOID *FdtBase,
>
> + CONST CHAR8 *Compatible
>
> + )
>
> +{
>
> + UINT64 *Reg;
>
> + INT32 Node, LenP;
>
> +
>
> + Node = fdt_node_offset_by_compatible (FdtBase, -1, Compatible);
>
> + while (Node != -FDT_ERR_NOTFOUND) {
>
> + Reg = (UINT64 *)fdt_getprop (FdtBase, Node, "reg", &LenP);
>
> + if (Reg) {
>
> + ASSERT (LenP == (2 * sizeof (UINT64)));
>
> + AddIoMemoryBaseSizeHob (SwapBytes64 (Reg[0]), SwapBytes64 (Reg[1]));
>
> + }
>
> +
>
> + Node = fdt_node_offset_by_compatible (FdtBase, Node, Compatible);
>
> + }
>
> +}
>
> +
>
> +/**
>
> + @retval EFI_SUCCESS The address of FDT is passed in HOB.
>
> + EFI_UNSUPPORTED Can't locate FDT.
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +PlatformPeimInitialization (
>
> + VOID
>
> + )
>
> +{
>
> + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext;
>
> + VOID *FdtPointer;
>
> + VOID *Base;
>
> + VOID *NewBase;
>
> + UINTN FdtSize;
>
> + UINTN FdtPages;
>
> + UINT64 *FdtHobData;
>
> +
>
> + FirmwareContext = NULL;
>
> + GetFirmwareContextPointer (&FirmwareContext);
>
> +
>
> + if (FirmwareContext == NULL) {
>
> + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __func__));
>
> + return EFI_UNSUPPORTED;
>
> + }
>
> +
>
> + FdtPointer = (VOID *)FirmwareContext->FlattenedDeviceTree;
>
> + if (FdtPointer == NULL) {
>
> + DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __func__));
>
> + return EFI_UNSUPPORTED;
>
> + }
>
> +
>
> + DEBUG ((DEBUG_INFO, "%a: Build FDT HOB - FDT at address: 0x%x \n",
> __func__, FdtPointer));
>
> + Base = FdtPointer;
>
> + if (fdt_check_header (Base) != 0) {
>
> + DEBUG ((DEBUG_ERROR, "%a: Corrupted DTB\n", __func__));
>
> + return EFI_UNSUPPORTED;
>
> + }
>
> +
>
> + FdtSize = fdt_totalsize (Base);
>
> + FdtPages = EFI_SIZE_TO_PAGES (FdtSize);
>
> + NewBase = AllocatePages (FdtPages);
>
> + if (NewBase == NULL) {
>
> + DEBUG ((DEBUG_ERROR, "%a: Could not allocate memory for DTB\n",
> __func__));
>
> + return EFI_UNSUPPORTED;
>
> + }
>
> +
>
> + fdt_open_into (Base, NewBase, EFI_PAGES_TO_SIZE (FdtPages));
>
> +
>
> + FdtHobData = BuildGuidHob (&gFdtHobGuid, sizeof *FdtHobData);
>
> + if (FdtHobData == NULL) {
>
> + DEBUG ((DEBUG_ERROR, "%a: Could not build FDT Hob\n", __func__));
>
> + return EFI_UNSUPPORTED;
>
> + }
>
> +
>
> + *FdtHobData = (UINTN)NewBase;
>
> +
>
> + BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize));
>
> +
>
> + //
>
> + // For Variable FD
>
> + //
>
> + BuildResourceDescriptorHob (
>
> + EFI_RESOURCE_MEMORY_MAPPED_IO,
>
> + EFI_RESOURCE_ATTRIBUTE_PRESENT |
>
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
>
> + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
>
> + EFI_RESOURCE_ATTRIBUTE_TESTED,
>
> + PcdGet32 (PcdVariableFdBaseAddress),
>
> + PcdGet32 (PcdVariableFdSize)
>
> + );
>
> +
>
> + PopulateIoResources (Base, "ns16550a");
>
> + PopulateIoResources (Base, "qemu,fw-cfg-mmio");
>
> + PopulateIoResources (Base, "virtio,mmio");
>
> +
>
> + return EFI_SUCCESS;
>
> +}
>
> diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecEntry.S
> b/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecEntry.S
> new file mode 100755
> index 00000000..14f6b4d0
> --- /dev/null
> +++ b/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecEntry.S
> @@ -0,0 +1,19 @@
> +/*
>
> + Copyright (c) 2022 Ventana Micro Systems Inc.
>
> + Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +
>
> + */
>
> +
>
> +#include "SecMain.h"
>
> +
>
> +ASM_FUNC (_ModuleEntryPoint)
>
> + /* Use Temp memory as the stack for calling to C code */
>
> + li a4, FixedPcdGet32 (PcdRiscVSecFvBase)
>
> + li a5, FixedPcdGet32 (PcdRiscVSecFvSize)
>
> +
>
> + /* Use Temp memory as the stack for calling to C code */
>
> + add sp, a4, a5
>
> +
>
> + call SecStartup
>
> diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.c
> b/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.c
> new file mode 100755
> index 00000000..cb53a71a
> --- /dev/null
> +++ b/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.c
> @@ -0,0 +1,110 @@
> +/** @file
>
> + RISC-V SEC phase module for Qemu Virt.
>
> +
>
> + Copyright (c) 2008 - 2024, Intel Corporation. All rights reserved.<BR>
>
> + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +
>
> +**/
>
> +
>
> +#include "SecMain.h"
>
> +
>
> +STATIC
>
> +EFI_STATUS
>
> +EFIAPI
>
> +SecInitializePlatform (
>
> + VOID
>
> + )
>
> +{
>
> + EFI_STATUS Status;
>
> +
>
> + MemoryPeimInitialization ();
>
> +
>
> + CpuPeimInitialization ();
>
> +
>
> + // Set the Boot Mode
>
> + SetBootMode (BOOT_WITH_FULL_CONFIGURATION);
>
> +
>
> + Status = PlatformPeimInitialization ();
>
> + ASSERT_EFI_ERROR (Status);
>
> +
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +/**
>
> +
>
> + Entry point to the C language phase of SEC. After the SEC assembly
>
> + code has initialized some temporary memory and set up the stack,
>
> + the control is transferred to this function.
>
> +
>
> +
>
> + @param[in] BootHartId Hardware thread ID of boot hart.
>
> + @param[in] DeviceTreeAddress Pointer to Device Tree (DTB)
>
> +**/
>
> +VOID
>
> +NORETURN
>
> +EFIAPI
>
> +SecStartup (
>
> + IN UINTN BootHartId,
>
> + IN VOID *DeviceTreeAddress
>
> + )
>
> +{
>
> + EFI_HOB_HANDOFF_INFO_TABLE *HobList;
>
> + EFI_RISCV_FIRMWARE_CONTEXT FirmwareContext;
>
> + EFI_STATUS Status;
>
> + UINT64 UefiMemoryBase;
>
> + UINT64 StackBase;
>
> + UINT32 StackSize;
>
> +
>
> + SerialPortInitialize ();
>
> +
>
> + //
>
> + // Report Status Code to indicate entering SEC core
>
> + //
>
> + DEBUG ((
>
> + DEBUG_INFO,
>
> + "%a() BootHartId: 0x%x, DeviceTreeAddress=0x%x\n",
>
> + __func__,
>
> + BootHartId,
>
> + DeviceTreeAddress
>
> + ));
>
> +
>
> + FirmwareContext.BootHartId = BootHartId;
>
> + FirmwareContext.FlattenedDeviceTree = (UINT64)DeviceTreeAddress;
>
> + SetFirmwareContextPointer (&FirmwareContext);
>
> +
>
> + StackBase = (UINT64)FixedPcdGet32 (PcdRiscVSecFvBase);
>
> + StackSize = FixedPcdGet32 (PcdRiscVSecFvSize);
>
> + UefiMemoryBase = StackBase + StackSize - SIZE_32MB;
>
> +
>
> + // Declare the PI/UEFI memory region
>
> + HobList = HobConstructor (
>
> + (VOID *)UefiMemoryBase,
>
> + SIZE_32MB,
>
> + (VOID *)UefiMemoryBase,
>
> + (VOID *)StackBase // The top of the UEFI Memory is reserved for the
> stacks
>
> + );
>
> + PrePeiSetHobList (HobList);
>
> +
>
> + SecInitializePlatform ();
>
> +
>
> + BuildStackHob (StackBase, StackSize);
>
> +
>
> + //
>
> + // Process all libraries constructor function linked to SecMain.
>
> + //
>
> + ProcessLibraryConstructorList ();
>
> +
>
> + // Assume the FV that contains the SEC (our code) also contains a compressed
> FV.
>
> + Status = DecompressFirstFv ();
>
> + ASSERT_EFI_ERROR (Status);
>
> +
>
> + // Load the DXE Core and transfer control to it
>
> + Status = LoadDxeCoreFromFv (NULL, 0);
>
> + ASSERT_EFI_ERROR (Status);
>
> + //
>
> + // Should not come here.
>
> + //
>
> + UNREACHABLE ();
>
> +}
>
> diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.h
> b/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.h
> new file mode 100755
> index 00000000..29da93c8
> --- /dev/null
> +++ b/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.h
> @@ -0,0 +1,104 @@
> +/** @file
>
> + Master header file for SecCore.
>
> +
>
> + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
>
> + Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +
>
> +**/
>
> +
>
> +#ifndef SEC_MAIN_H_
>
> +#define SEC_MAIN_H_
>
> +
>
> +#include <PiPei.h>
>
> +#include <Library/BaseLib.h>
>
> +#include <Library/BaseMemoryLib.h>
>
> +#include <Library/DebugAgentLib.h>
>
> +#include <Library/DebugLib.h>
>
> +#include <Library/ExtractGuidedSectionLib.h>
>
> +#include <Library/IoLib.h>
>
> +#include <Library/HobLib.h>
>
> +#include <Library/PcdLib.h>
>
> +#include <Library/PeCoffExtraActionLib.h>
>
> +#include <Library/PeCoffGetEntryPointLib.h>
>
> +#include <Library/PeCoffLib.h>
>
> +#include <Library/PeiServicesLib.h>
>
> +#include <Library/PeiServicesTablePointerLib.h>
>
> +#include <Library/DebugPrintErrorLevelLib.h>
>
> +#include <Library/PrintLib.h>
>
> +#include <Library/BaseRiscVSbiLib.h>
>
> +#include <Library/PrePiLib.h>
>
> +#include <Library/PrePiHobListPointerLib.h>
>
> +#include <Library/SerialPortLib.h>
>
> +#include <Register/RiscV64/RiscVImpl.h>
>
> +
>
> +/**
>
> + Entry point to the C language phase of SEC. After the SEC assembly
>
> + code has initialized some temporary memory and set up the stack,
>
> + the control is transferred to this function.
>
> +
>
> + @param SizeOfRam Size of the temporary memory available for use.
>
> + @param TempRamBase Base address of temporary ram
>
> + @param BootFirmwareVolume Base address of the Boot Firmware Volume.
>
> +**/
>
> +VOID
>
> +NORETURN
>
> +EFIAPI
>
> +SecStartup (
>
> + IN UINTN BootHartId,
>
> + IN VOID *DeviceTreeAddress
>
> + );
>
> +
>
> +/**
>
> + Auto-generated function that calls the library constructors for all of the
> module's
>
> + dependent libraries. This function must be called by the SEC Core once a stack
> has
>
> + been established.
>
> +
>
> +**/
>
> +VOID
>
> +EFIAPI
>
> +ProcessLibraryConstructorList (
>
> + VOID
>
> + );
>
> +
>
> +/**
>
> + Perform Platform PEIM initialization.
>
> +
>
> + @return EFI_SUCCESS The platform initialized successfully.
>
> + @retval Others - As the error code indicates
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +PlatformPeimInitialization (
>
> + VOID
>
> + );
>
> +
>
> +/**
>
> + Perform Memory PEIM initialization.
>
> +
>
> + @return EFI_SUCCESS The platform initialized successfully.
>
> + @retval Others - As the error code indicates
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +MemoryPeimInitialization (
>
> + VOID
>
> + );
>
> +
>
> +/**
>
> + Perform CPU PEIM initialization.
>
> +
>
> + @return EFI_SUCCESS The platform initialized successfully.
>
> + @retval Others - As the error code indicates
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +CpuPeimInitialization (
>
> + VOID
>
> + );
>
> +
>
> +#endif
>
> diff --git a/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.inf
> b/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.inf
> new file mode 100755
> index 00000000..b40a095a
> --- /dev/null
> +++ b/Platform/Qemu/RiscVQemuServerPlatform/Sec/SecMain.inf
> @@ -0,0 +1,67 @@
> +## @file
>
> +# SEC Driver for RISC-V
>
> +#
>
> +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR
>
> +# Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +
>
> +[Defines]
>
> + INF_VERSION = 0x0001001B
>
> + BASE_NAME = SecMainRiscV64
>
> + FILE_GUID = 80D22D3C-81EC-44B2-A55C-242C21BF9539
>
> + MODULE_TYPE = SEC
>
> + VERSION_STRING = 1.0
>
> + ENTRY_POINT = SecMain
>
> +
>
> +#
>
> +# The following information is for reference only and not required by the build
> tools.
>
> +#
>
> +# VALID_ARCHITECTURES = RISCV64
>
> +#
>
> +
>
> +[Sources]
>
> + SecEntry.S
>
> + SecMain.c
>
> + SecMain.h
>
> + Cpu.c
>
> + Memory.c
>
> + Platform.c
>
> +
>
> +[Packages]
>
> + MdePkg/MdePkg.dec
>
> + MdeModulePkg/MdeModulePkg.dec
>
> + UefiCpuPkg/UefiCpuPkg.dec
>
> + EmbeddedPkg/EmbeddedPkg.dec
>
> + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
>
> +
>
> +[LibraryClasses]
>
> + BaseLib
>
> + DebugLib
>
> + PcdLib
>
> + IoLib
>
> + PeCoffLib
>
> + LzmaDecompressLib
>
> + RiscVSbiLib
>
> + PrePiLib
>
> + FdtLib
>
> + MemoryAllocationLib
>
> + HobLib
>
> + SerialPortLib
>
> +
>
> +[Ppis]
>
> + gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED
>
> + gEfiTemporaryRamDonePpiGuid ## PRODUCES
>
> +
>
> +[Pcd]
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvBase
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvSize
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress
>
> + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize
>
> +
>
> +[Guids]
>
> + gFdtHobGuid
>
> diff --git a/Platform/Qemu/RiscVQemuServerPlatform/VarStore.fdf.inc
> b/Platform/Qemu/RiscVQemuServerPlatform/VarStore.fdf.inc
> new file mode 100755
> index 00000000..07fe3caf
> --- /dev/null
> +++ b/Platform/Qemu/RiscVQemuServerPlatform/VarStore.fdf.inc
> @@ -0,0 +1,72 @@
> +## @file
>
> +# FDF include file with Layout Regions that define an empty variable store.
>
> +#
>
> +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
>
> +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights
> reserved.<BR>
>
> +# Copyright (C) 2014, Red Hat, Inc.
>
> +# Copyright (c) 2006 - 2024, Intel Corporation. All rights reserved.<BR>
>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +##
>
> +
>
> +$(VARS_OFFSET)|$(VARS_LIVE_SIZE)
>
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeM
> odulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
>
> +#
>
> +# NV_VARIABLE_STORE
>
> +#
>
> +DATA = {
>
> + ## This is the EFI_FIRMWARE_VOLUME_HEADER
>
> + # ZeroVector []
>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>
> + # FileSystemGuid: gEfiSystemNvDataFvGuid =
>
> + # { 0xFFF12B8D, 0x7696, 0x4C8B,
>
> + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
>
> + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
>
> + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
>
> + # FvLength: 0xC0000
>
> + 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00,
>
> + # Signature "_FVH" # Attributes
>
> + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
>
> + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
>
> + 0x48, 0x00, 0x28, 0x09, 0x00, 0x00, 0x00, 0x02,
>
> + # Blockmap[0]: 0x3 Blocks * 0x40000 Bytes / Block
>
> + 0x3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00,
>
> + # Blockmap[1]: End
>
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>
> + ## This is the VARIABLE_STORE_HEADER
>
> + # It is compatible with SECURE_BOOT_ENABLE == FALSE as well.
>
> + # Signature: gEfiAuthenticatedVariableGuid =
>
> + # { 0xaaf32c78, 0x947b, 0x439a,
>
> + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
>
> + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
>
> + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
>
> + # Size: 0x40000
> (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
>
> + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x3FFB8
>
> + # This can speed up the Variable Dispatch a bit.
>
> + 0xB8, 0xFF, 0x03, 0x00,
>
> + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
>
> + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
>
> +}
>
> +
>
> +$(VARS_FTW_WORKING_OFFSET)|$(VARS_FTW_WORKING_SIZE)
>
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMd
> eModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
>
> +#
>
> +#NV_FTW_WORK
>
> +#
>
> +DATA = {
>
> + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =
> gEdkiiWorkingBlockSignatureGuid =
>
> + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b,
> 0x95 }}
>
> + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
>
> + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
>
> + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
>
> + 0x5b, 0xe7, 0xc6, 0x86, 0xFE, 0xFF, 0xFF, 0xFF,
>
> + # WriteQueueSize: UINT64
>
> + 0xE0, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00
>
> +}
>
> +
>
> +$(VARS_FTW_SPARE_OFFSET)|$(VARS_FTW_SPARE_SIZE)
>
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMde
> ModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
>
> +#
>
> +#NV_FTW_SPARE
>
> diff --git
> a/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlash.c
> b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlash.c
> new file mode 100755
> index 00000000..e6aaed27
> --- /dev/null
> +++
> b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlash.c
> @@ -0,0 +1,742 @@
> +/** @file NorFlash.c
>
> +
>
> + Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.<BR>
>
> + Copyright (c) 2020, Linaro, Ltd. All rights reserved.<BR>
>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +
>
> +**/
>
> +
>
> +#include <Library/BaseMemoryLib.h>
>
> +
>
> +#include "VirtNorFlash.h"
>
> +
>
> +//
>
> +// Global variable declarations
>
> +//
>
> +extern NOR_FLASH_INSTANCE **mNorFlashInstances;
>
> +extern UINT32 mNorFlashDeviceCount;
>
> +
>
> +UINT32
>
> +NorFlashReadStatusRegister (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN UINTN SR_Address
>
> + )
>
> +{
>
> + // Prepare to read the status register
>
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0,
> P30_CMD_READ_STATUS_REGISTER);
>
> + return MmioRead32 (Instance->DeviceBaseAddress);
>
> +}
>
> +
>
> +STATIC
>
> +BOOLEAN
>
> +NorFlashBlockIsLocked (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN UINTN BlockAddress
>
> + )
>
> +{
>
> + UINT32 LockStatus;
>
> +
>
> + // Send command for reading device id
>
> + SEND_NOR_COMMAND (BlockAddress, 2, P30_CMD_READ_DEVICE_ID);
>
> +
>
> + // Read block lock status
>
> + LockStatus = MmioRead32 (CREATE_NOR_ADDRESS (BlockAddress, 2));
>
> +
>
> + // Decode block lock status
>
> + LockStatus = FOLD_32BIT_INTO_16BIT (LockStatus);
>
> +
>
> + if ((LockStatus & 0x2) != 0) {
>
> + DEBUG ((DEBUG_ERROR, "NorFlashBlockIsLocked: WARNING: Block LOCKED
> DOWN\n"));
>
> + }
>
> +
>
> + return ((LockStatus & 0x1) != 0);
>
> +}
>
> +
>
> +STATIC
>
> +EFI_STATUS
>
> +NorFlashUnlockSingleBlock (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN UINTN BlockAddress
>
> + )
>
> +{
>
> + UINT32 LockStatus;
>
> +
>
> + // Raise the Task Priority Level to TPL_NOTIFY to serialise all its operations
>
> + // and to protect shared data structures.
>
> +
>
> + // Request a lock setup
>
> + SEND_NOR_COMMAND (BlockAddress, 0, P30_CMD_LOCK_BLOCK_SETUP);
>
> +
>
> + // Request an unlock
>
> + SEND_NOR_COMMAND (BlockAddress, 0, P30_CMD_UNLOCK_BLOCK);
>
> +
>
> + // Wait until the status register gives us the all clear
>
> + do {
>
> + LockStatus = NorFlashReadStatusRegister (Instance, BlockAddress);
>
> + } while ((LockStatus & P30_SR_BIT_WRITE) != P30_SR_BIT_WRITE);
>
> +
>
> + // Put device back into Read Array mode
>
> + SEND_NOR_COMMAND (BlockAddress, 0, P30_CMD_READ_ARRAY);
>
> +
>
> + DEBUG ((DEBUG_BLKIO, "UnlockSingleBlock: BlockAddress=0x%08x\n",
> BlockAddress));
>
> +
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +EFI_STATUS
>
> +NorFlashUnlockSingleBlockIfNecessary (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN UINTN BlockAddress
>
> + )
>
> +{
>
> + EFI_STATUS Status;
>
> +
>
> + Status = EFI_SUCCESS;
>
> +
>
> + if (NorFlashBlockIsLocked (Instance, BlockAddress)) {
>
> + Status = NorFlashUnlockSingleBlock (Instance, BlockAddress);
>
> + }
>
> +
>
> + return Status;
>
> +}
>
> +
>
> +/**
>
> + * The following function presumes that the block has already been unlocked.
>
> + **/
>
> +EFI_STATUS
>
> +NorFlashEraseSingleBlock (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN UINTN BlockAddress
>
> + )
>
> +{
>
> + EFI_STATUS Status;
>
> + UINT32 StatusRegister;
>
> +
>
> + Status = EFI_SUCCESS;
>
> +
>
> + // Request a block erase and then confirm it
>
> + SEND_NOR_COMMAND (BlockAddress, 0, P30_CMD_BLOCK_ERASE_SETUP);
>
> + SEND_NOR_COMMAND (BlockAddress, 0,
> P30_CMD_BLOCK_ERASE_CONFIRM);
>
> +
>
> + // Wait until the status register gives us the all clear
>
> + do {
>
> + StatusRegister = NorFlashReadStatusRegister (Instance, BlockAddress);
>
> + } while ((StatusRegister & P30_SR_BIT_WRITE) != P30_SR_BIT_WRITE);
>
> +
>
> + if (StatusRegister & P30_SR_BIT_VPP) {
>
> + DEBUG ((DEBUG_ERROR, "EraseSingleBlock(BlockAddress=0x%08x: VPP
> Range Error\n", BlockAddress));
>
> + Status = EFI_DEVICE_ERROR;
>
> + }
>
> +
>
> + if ((StatusRegister & (P30_SR_BIT_ERASE | P30_SR_BIT_PROGRAM)) ==
> (P30_SR_BIT_ERASE | P30_SR_BIT_PROGRAM)) {
>
> + DEBUG ((DEBUG_ERROR, "EraseSingleBlock(BlockAddress=0x%08x:
> Command Sequence Error\n", BlockAddress));
>
> + Status = EFI_DEVICE_ERROR;
>
> + }
>
> +
>
> + if (StatusRegister & P30_SR_BIT_ERASE) {
>
> + DEBUG ((DEBUG_ERROR, "EraseSingleBlock(BlockAddress=0x%08x: Block
> Erase Error StatusRegister:0x%X\n", BlockAddress, StatusRegister));
>
> + Status = EFI_DEVICE_ERROR;
>
> + }
>
> +
>
> + if (StatusRegister & P30_SR_BIT_BLOCK_LOCKED) {
>
> + // The debug level message has been reduced because a device lock might
> happen. In this case we just retry it ...
>
> + DEBUG ((DEBUG_INFO, "EraseSingleBlock(BlockAddress=0x%08x: Block
> Locked Error\n", BlockAddress));
>
> + Status = EFI_WRITE_PROTECTED;
>
> + }
>
> +
>
> + if (EFI_ERROR (Status)) {
>
> + // Clear the Status Register
>
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0,
> P30_CMD_CLEAR_STATUS_REGISTER);
>
> + }
>
> +
>
> + // Put device back into Read Array mode
>
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0,
> P30_CMD_READ_ARRAY);
>
> +
>
> + return Status;
>
> +}
>
> +
>
> +EFI_STATUS
>
> +NorFlashWriteSingleWord (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN UINTN WordAddress,
>
> + IN UINT32 WriteData
>
> + )
>
> +{
>
> + EFI_STATUS Status;
>
> + UINT32 StatusRegister;
>
> +
>
> + Status = EFI_SUCCESS;
>
> +
>
> + // Request a write single word command
>
> + SEND_NOR_COMMAND (WordAddress, 0,
> P30_CMD_WORD_PROGRAM_SETUP);
>
> +
>
> + // Store the word into NOR Flash;
>
> + MmioWrite32 (WordAddress, WriteData);
>
> +
>
> + // Wait for the write to complete and then check for any errors; i.e. check the
> Status Register
>
> + do {
>
> + // Prepare to read the status register
>
> + StatusRegister = NorFlashReadStatusRegister (Instance, WordAddress);
>
> + // The chip is busy while the WRITE bit is not asserted
>
> + } while ((StatusRegister & P30_SR_BIT_WRITE) != P30_SR_BIT_WRITE);
>
> +
>
> + // Perform a full status check:
>
> + // Mask the relevant bits of Status Register.
>
> + // Everything should be zero, if not, we have a problem
>
> +
>
> + if (StatusRegister & P30_SR_BIT_VPP) {
>
> + DEBUG ((DEBUG_ERROR, "NorFlashWriteSingleWord(WordAddress:0x%X):
> VPP Range Error\n", WordAddress));
>
> + Status = EFI_DEVICE_ERROR;
>
> + }
>
> +
>
> + if (StatusRegister & P30_SR_BIT_PROGRAM) {
>
> + DEBUG ((DEBUG_ERROR, "NorFlashWriteSingleWord(WordAddress:0x%X):
> Program Error\n", WordAddress));
>
> + Status = EFI_DEVICE_ERROR;
>
> + }
>
> +
>
> + if (StatusRegister & P30_SR_BIT_BLOCK_LOCKED) {
>
> + DEBUG ((DEBUG_ERROR, "NorFlashWriteSingleWord(WordAddress:0x%X):
> Device Protect Error\n", WordAddress));
>
> + Status = EFI_DEVICE_ERROR;
>
> + }
>
> +
>
> + if (!EFI_ERROR (Status)) {
>
> + // Clear the Status Register
>
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0,
> P30_CMD_CLEAR_STATUS_REGISTER);
>
> + }
>
> +
>
> + return Status;
>
> +}
>
> +
>
> +/*
>
> + * Writes data to the NOR Flash using the Buffered Programming method.
>
> + *
>
> + * The maximum size of the on-chip buffer is 32-words, because of hardware
> restrictions.
>
> + * Therefore this function will only handle buffers up to 32 words or 128 bytes.
>
> + * To deal with larger buffers, call this function again.
>
> + *
>
> + * This function presumes that both the TargetAddress and the
> TargetAddress+BufferSize
>
> + * exist entirely within the NOR Flash. Therefore these conditions will not be
> checked here.
>
> + *
>
> + * In buffered programming, if the target address not at the beginning of a 32-bit
> word boundary,
>
> + * then programming time is doubled and power consumption is increased.
>
> + * Therefore, it is a requirement to align buffer writes to 32-bit word boundaries.
>
> + * i.e. the last 4 bits of the target start address must be zero: 0x......00
>
> + */
>
> +EFI_STATUS
>
> +NorFlashWriteBuffer (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN UINTN TargetAddress,
>
> + IN UINTN BufferSizeInBytes,
>
> + IN UINT32 *Buffer
>
> + )
>
> +{
>
> + EFI_STATUS Status;
>
> + UINTN BufferSizeInWords;
>
> + UINTN Count;
>
> + volatile UINT32 *Data;
>
> + UINTN WaitForBuffer;
>
> + BOOLEAN BufferAvailable;
>
> + UINT32 StatusRegister;
>
> +
>
> + WaitForBuffer = MAX_BUFFERED_PROG_ITERATIONS;
>
> + BufferAvailable = FALSE;
>
> +
>
> + // Check that the target address does not cross a 32-word boundary.
>
> + if ((TargetAddress & BOUNDARY_OF_32_WORDS) != 0) {
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> +
>
> + // Check there are some data to program
>
> + if (BufferSizeInBytes == 0) {
>
> + return EFI_BUFFER_TOO_SMALL;
>
> + }
>
> +
>
> + // Check that the buffer size does not exceed the maximum hardware buffer
> size on chip.
>
> + if (BufferSizeInBytes > P30_MAX_BUFFER_SIZE_IN_BYTES) {
>
> + return EFI_BAD_BUFFER_SIZE;
>
> + }
>
> +
>
> + // Check that the buffer size is a multiple of 32-bit words
>
> + if ((BufferSizeInBytes % 4) != 0) {
>
> + return EFI_BAD_BUFFER_SIZE;
>
> + }
>
> +
>
> + // Pre-programming conditions checked, now start the algorithm.
>
> +
>
> + // Prepare the data destination address
>
> + Data = (UINT32 *)TargetAddress;
>
> +
>
> + // Check the availability of the buffer
>
> + do {
>
> + // Issue the Buffered Program Setup command
>
> + SEND_NOR_COMMAND (TargetAddress, 0,
> P30_CMD_BUFFERED_PROGRAM_SETUP);
>
> +
>
> + // Read back the status register bit#7 from the same address
>
> + if (((*Data) & P30_SR_BIT_WRITE) == P30_SR_BIT_WRITE) {
>
> + BufferAvailable = TRUE;
>
> + }
>
> +
>
> + // Update the loop counter
>
> + WaitForBuffer--;
>
> + } while ((WaitForBuffer > 0) && (BufferAvailable == FALSE));
>
> +
>
> + // The buffer was not available for writing
>
> + if (WaitForBuffer == 0) {
>
> + return EFI_DEVICE_ERROR;
>
> + }
>
> +
>
> + // From now on we work in 32-bit words
>
> + BufferSizeInWords = BufferSizeInBytes / (UINTN)4;
>
> +
>
> + // Write the word count, which is (buffer_size_in_words - 1),
>
> + // because word count 0 means one word.
>
> + SEND_NOR_COMMAND (TargetAddress, 0, (BufferSizeInWords - 1));
>
> +
>
> + // Write the data to the NOR Flash, advancing each address by 4 bytes
>
> + for (Count = 0; Count < BufferSizeInWords; Count++, Data++, Buffer++) {
>
> + MmioWrite32 ((UINTN)Data, *Buffer);
>
> + }
>
> +
>
> + // Issue the Buffered Program Confirm command, to start the programming
> operation
>
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0,
> P30_CMD_BUFFERED_PROGRAM_CONFIRM);
>
> +
>
> + // Wait for the write to complete and then check for any errors; i.e. check the
> Status Register
>
> + do {
>
> + StatusRegister = NorFlashReadStatusRegister (Instance, TargetAddress);
>
> + // The chip is busy while the WRITE bit is not asserted
>
> + } while ((StatusRegister & P30_SR_BIT_WRITE) != P30_SR_BIT_WRITE);
>
> +
>
> + // Perform a full status check:
>
> + // Mask the relevant bits of Status Register.
>
> + // Everything should be zero, if not, we have a problem
>
> +
>
> + Status = EFI_SUCCESS;
>
> +
>
> + if (StatusRegister & P30_SR_BIT_VPP) {
>
> + DEBUG ((DEBUG_ERROR, "NorFlashWriteBuffer(TargetAddress:0x%X): VPP
> Range Error\n", TargetAddress));
>
> + Status = EFI_DEVICE_ERROR;
>
> + }
>
> +
>
> + if (StatusRegister & P30_SR_BIT_PROGRAM) {
>
> + DEBUG ((DEBUG_ERROR, "NorFlashWriteBuffer(TargetAddress:0x%X):
> Program Error\n", TargetAddress));
>
> + Status = EFI_DEVICE_ERROR;
>
> + }
>
> +
>
> + if (StatusRegister & P30_SR_BIT_BLOCK_LOCKED) {
>
> + DEBUG ((DEBUG_ERROR, "NorFlashWriteBuffer(TargetAddress:0x%X): Device
> Protect Error\n", TargetAddress));
>
> + Status = EFI_DEVICE_ERROR;
>
> + }
>
> +
>
> + if (!EFI_ERROR (Status)) {
>
> + // Clear the Status Register
>
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0,
> P30_CMD_CLEAR_STATUS_REGISTER);
>
> + }
>
> +
>
> + return Status;
>
> +}
>
> +
>
> +EFI_STATUS
>
> +NorFlashWriteBlocks (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN EFI_LBA Lba,
>
> + IN UINTN BufferSizeInBytes,
>
> + IN VOID *Buffer
>
> + )
>
> +{
>
> + UINT32 *pWriteBuffer;
>
> + EFI_STATUS Status;
>
> + EFI_LBA CurrentBlock;
>
> + UINT32 BlockSizeInWords;
>
> + UINT32 NumBlocks;
>
> + UINT32 BlockCount;
>
> +
>
> + Status = EFI_SUCCESS;
>
> +
>
> + // The buffer must be valid
>
> + if (Buffer == NULL) {
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> +
>
> + // We must have some bytes to read
>
> + DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: BufferSizeInBytes=0x%x\n",
> BufferSizeInBytes));
>
> + if (BufferSizeInBytes == 0) {
>
> + return EFI_BAD_BUFFER_SIZE;
>
> + }
>
> +
>
> + // The size of the buffer must be a multiple of the block size
>
> + DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: BlockSize in bytes =0x%x\n",
> Instance->BlockSize));
>
> + if ((BufferSizeInBytes % Instance->BlockSize) != 0) {
>
> + return EFI_BAD_BUFFER_SIZE;
>
> + }
>
> +
>
> + // All blocks must be within the device
>
> + NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->BlockSize;
>
> +
>
> + DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: NumBlocks=%d,
> LastBlock=%ld, Lba=%ld.\n", NumBlocks, Instance->LastBlock, Lba));
>
> +
>
> + if ((Lba + NumBlocks) > (Instance->LastBlock + 1)) {
>
> + DEBUG ((DEBUG_ERROR, "NorFlashWriteBlocks: ERROR - Write will exceed
> last block.\n"));
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> +
>
> + BlockSizeInWords = Instance->BlockSize / 4;
>
> +
>
> + // Because the target *Buffer is a pointer to VOID, we must put all the data into
> a pointer
>
> + // to a proper data type, so use *ReadBuffer
>
> + pWriteBuffer = (UINT32 *)Buffer;
>
> +
>
> + CurrentBlock = Lba;
>
> + for (BlockCount = 0; BlockCount < NumBlocks; BlockCount++, CurrentBlock++,
> pWriteBuffer = pWriteBuffer + BlockSizeInWords) {
>
> + DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: Writing block #%d\n",
> (UINTN)CurrentBlock));
>
> +
>
> + Status = NorFlashWriteFullBlock (Instance, CurrentBlock, pWriteBuffer,
> BlockSizeInWords);
>
> +
>
> + if (EFI_ERROR (Status)) {
>
> + break;
>
> + }
>
> + }
>
> +
>
> + DEBUG ((DEBUG_BLKIO, "NorFlashWriteBlocks: Exit Status = \"%r\".\n",
> Status));
>
> + return Status;
>
> +}
>
> +
>
> +EFI_STATUS
>
> +NorFlashReadBlocks (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN EFI_LBA Lba,
>
> + IN UINTN BufferSizeInBytes,
>
> + OUT VOID *Buffer
>
> + )
>
> +{
>
> + UINT32 NumBlocks;
>
> + UINTN StartAddress;
>
> +
>
> + DEBUG ((
>
> + DEBUG_BLKIO,
>
> + "NorFlashReadBlocks: BufferSize=0x%xB BlockSize=0x%xB LastBlock=%ld,
> Lba=%ld.\n",
>
> + BufferSizeInBytes,
>
> + Instance->BlockSize,
>
> + Instance->LastBlock,
>
> + Lba
>
> + ));
>
> +
>
> + // The buffer must be valid
>
> + if (Buffer == NULL) {
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> +
>
> + // Return if we have not any byte to read
>
> + if (BufferSizeInBytes == 0) {
>
> + return EFI_SUCCESS;
>
> + }
>
> +
>
> + // The size of the buffer must be a multiple of the block size
>
> + if ((BufferSizeInBytes % Instance->BlockSize) != 0) {
>
> + return EFI_BAD_BUFFER_SIZE;
>
> + }
>
> +
>
> + // All blocks must be within the device
>
> + NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->BlockSize;
>
> +
>
> + if ((Lba + NumBlocks) > (Instance->LastBlock + 1)) {
>
> + DEBUG ((DEBUG_ERROR, "NorFlashReadBlocks: ERROR - Read will exceed
> last block\n"));
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> +
>
> + // Get the address to start reading from
>
> + StartAddress = GET_NOR_BLOCK_ADDRESS (
>
> + Instance->RegionBaseAddress,
>
> + Lba,
>
> + Instance->BlockSize
>
> + );
>
> +
>
> + // Put the device into Read Array mode
>
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0,
> P30_CMD_READ_ARRAY);
>
> +
>
> + // Readout the data
>
> + CopyMem (Buffer, (VOID *)StartAddress, BufferSizeInBytes);
>
> +
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +EFI_STATUS
>
> +NorFlashRead (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN EFI_LBA Lba,
>
> + IN UINTN Offset,
>
> + IN UINTN BufferSizeInBytes,
>
> + OUT VOID *Buffer
>
> + )
>
> +{
>
> + UINTN StartAddress;
>
> +
>
> + // The buffer must be valid
>
> + if (Buffer == NULL) {
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> +
>
> + // Return if we have not any byte to read
>
> + if (BufferSizeInBytes == 0) {
>
> + return EFI_SUCCESS;
>
> + }
>
> +
>
> + if (((Lba * Instance->BlockSize) + Offset + BufferSizeInBytes) > Instance->Size) {
>
> + DEBUG ((DEBUG_ERROR, "NorFlashRead: ERROR - Read will exceed device
> size.\n"));
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> +
>
> + // Get the address to start reading from
>
> + StartAddress = GET_NOR_BLOCK_ADDRESS (
>
> + Instance->RegionBaseAddress,
>
> + Lba,
>
> + Instance->BlockSize
>
> + );
>
> +
>
> + // Put the device into Read Array mode
>
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0,
> P30_CMD_READ_ARRAY);
>
> +
>
> + // Readout the data
>
> + CopyMem (Buffer, (VOID *)(StartAddress + Offset), BufferSizeInBytes);
>
> +
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +STATIC
>
> +EFI_STATUS
>
> +NorFlashWriteSingleBlockWithErase (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN EFI_LBA Lba,
>
> + IN UINTN Offset,
>
> + IN OUT UINTN *NumBytes,
>
> + IN UINT8 *Buffer
>
> + )
>
> +{
>
> + EFI_STATUS Status;
>
> +
>
> + // Read NOR Flash data into shadow buffer
>
> + Status = NorFlashReadBlocks (Instance, Lba, Instance->BlockSize, Instance-
> >ShadowBuffer);
>
> + if (EFI_ERROR (Status)) {
>
> + // Return one of the pre-approved error statuses
>
> + return EFI_DEVICE_ERROR;
>
> + }
>
> +
>
> + // Put the data at the appropriate location inside the buffer area
>
> + CopyMem ((VOID *)((UINTN)Instance->ShadowBuffer + Offset), Buffer,
> *NumBytes);
>
> +
>
> + // Write the modified buffer back to the NorFlash
>
> + Status = NorFlashWriteBlocks (Instance, Lba, Instance->BlockSize, Instance-
> >ShadowBuffer);
>
> + if (EFI_ERROR (Status)) {
>
> + // Return one of the pre-approved error statuses
>
> + return EFI_DEVICE_ERROR;
>
> + }
>
> +
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +/*
>
> + Write a full or portion of a block. It must not span block boundaries; that is,
>
> + Offset + *NumBytes <= Instance->BlockSize.
>
> +*/
>
> +EFI_STATUS
>
> +NorFlashWriteSingleBlock (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN EFI_LBA Lba,
>
> + IN UINTN Offset,
>
> + IN OUT UINTN *NumBytes,
>
> + IN UINT8 *Buffer
>
> + )
>
> +{
>
> + EFI_STATUS Status;
>
> + UINTN CurOffset;
>
> + UINTN BlockSize;
>
> + UINTN BlockAddress;
>
> + UINT8 *OrigData;
>
> + UINTN Start, End;
>
> + UINT32 Index, Count;
>
> +
>
> + DEBUG ((DEBUG_BLKIO, "NorFlashWriteSingleBlock(Parameters: Lba=%ld,
> Offset=0x%x, *NumBytes=0x%x, Buffer @ 0x%08x)\n", Lba, Offset, *NumBytes,
> Buffer));
>
> +
>
> + // Check we did get some memory. Buffer is BlockSize.
>
> + if (Instance->ShadowBuffer == NULL) {
>
> + DEBUG ((DEBUG_ERROR, "FvbWrite: ERROR - Buffer not ready\n"));
>
> + return EFI_DEVICE_ERROR;
>
> + }
>
> +
>
> + // Cache the block size to avoid de-referencing pointers all the time
>
> + BlockSize = Instance->BlockSize;
>
> +
>
> + // The write must not span block boundaries.
>
> + // We need to check each variable individually because adding two large values
> together overflows.
>
> + if ((Offset >= BlockSize) ||
>
> + (*NumBytes > BlockSize) ||
>
> + ((Offset + *NumBytes) > BlockSize))
>
> + {
>
> + DEBUG ((DEBUG_ERROR, "NorFlashWriteSingleBlock: ERROR -
> EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n",
> Offset, *NumBytes, BlockSize));
>
> + return EFI_BAD_BUFFER_SIZE;
>
> + }
>
> +
>
> + // We must have some bytes to write
>
> + if (*NumBytes == 0) {
>
> + DEBUG ((DEBUG_ERROR, "NorFlashWriteSingleBlock: ERROR -
> EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n",
> Offset, *NumBytes, BlockSize));
>
> + return EFI_BAD_BUFFER_SIZE;
>
> + }
>
> +
>
> + // Pick 4 * P30_MAX_BUFFER_SIZE_IN_BYTES (== 512 bytes) as a good
>
> + // start for word operations as opposed to erasing the block and
>
> + // writing the data regardless if an erase is really needed.
>
> + //
>
> + // Many NV variable updates are small enough for a a single
>
> + // P30_MAX_BUFFER_SIZE_IN_BYTES block write. In case the update is
>
> + // larger than a single block, or the update crosses a
>
> + // P30_MAX_BUFFER_SIZE_IN_BYTES boundary (as shown in the diagram
>
> + // below), or both, we might have to write two or more blocks.
>
> + //
>
> + // 0 128 256
>
> + // [----------------|----------------]
>
> + // ^ ^ ^ ^
>
> + // | | | |
>
> + // | | | End, the next "word" boundary beyond
>
> + // | | | the (logical) update
>
> + // | | |
>
> + // | | (Offset & BOUNDARY_OF_32_WORDS) + NumBytes;
>
> + // | | i.e., the relative offset inside (or just past)
>
> + // | | the *double-word* such that it is the
>
> + // | | *exclusive* end of the (logical) update.
>
> + // | |
>
> + // | Offset & BOUNDARY_OF_32_WORDS; i.e., Offset within the "word";
>
> + // | this is where the (logical) update is supposed to start
>
> + // |
>
> + // Start = Offset & ~BOUNDARY_OF_32_WORDS; i.e., Offset truncated to
> "word" boundary
>
> +
>
> + Start = Offset & ~BOUNDARY_OF_32_WORDS;
>
> + End = ALIGN_VALUE (Offset + *NumBytes,
> P30_MAX_BUFFER_SIZE_IN_BYTES);
>
> +
>
> + if ((End - Start) <= (4 * P30_MAX_BUFFER_SIZE_IN_BYTES)) {
>
> + // Check to see if we need to erase before programming the data into NOR.
>
> + // If the destination bits are only changing from 1s to 0s we can just write.
>
> + // After a block is erased all bits in the block is set to 1.
>
> + // If any byte requires us to erase we just give up and rewrite all of it.
>
> +
>
> + // Read the old version of the data into the shadow buffer
>
> + Status = NorFlashRead (
>
> + Instance,
>
> + Lba,
>
> + Start,
>
> + End - Start,
>
> + Instance->ShadowBuffer
>
> + );
>
> + if (EFI_ERROR (Status)) {
>
> + return EFI_DEVICE_ERROR;
>
> + }
>
> +
>
> + // Make OrigData point to the start of the old version of the data inside
>
> + // the word aligned buffer
>
> + OrigData = Instance->ShadowBuffer + (Offset & BOUNDARY_OF_32_WORDS);
>
> +
>
> + // Update the buffer containing the old version of the data with the new
>
> + // contents, while checking whether the old version had any bits cleared
>
> + // that we want to set. In that case, we will need to erase the block first.
>
> + for (CurOffset = 0; CurOffset < *NumBytes; CurOffset++) {
>
> + if (~(UINT32)OrigData[CurOffset] & (UINT32)Buffer[CurOffset]) {
>
> + Status = NorFlashWriteSingleBlockWithErase (
>
> + Instance,
>
> + Lba,
>
> + Offset,
>
> + NumBytes,
>
> + Buffer
>
> + );
>
> + return Status;
>
> + }
>
> +
>
> + OrigData[CurOffset] = Buffer[CurOffset];
>
> + }
>
> +
>
> + //
>
> + // Write the updated buffer to NOR.
>
> + //
>
> + BlockAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress,
> Lba, BlockSize);
>
> +
>
> + // Unlock the block if we have to
>
> + Status = NorFlashUnlockSingleBlockIfNecessary (Instance, BlockAddress);
>
> + if (EFI_ERROR (Status)) {
>
> + goto Exit;
>
> + }
>
> +
>
> + Count = (End - Start) / P30_MAX_BUFFER_SIZE_IN_BYTES;
>
> + for (Index = 0; Index < Count; Index++) {
>
> + Status = NorFlashWriteBuffer (
>
> + Instance,
>
> + BlockAddress + Start + Index * P30_MAX_BUFFER_SIZE_IN_BYTES,
>
> + P30_MAX_BUFFER_SIZE_IN_BYTES,
>
> + Instance->ShadowBuffer + Index * P30_MAX_BUFFER_SIZE_IN_BYTES
>
> + );
>
> + if (EFI_ERROR (Status)) {
>
> + goto Exit;
>
> + }
>
> + }
>
> + } else {
>
> + Status = NorFlashWriteSingleBlockWithErase (
>
> + Instance,
>
> + Lba,
>
> + Offset,
>
> + NumBytes,
>
> + Buffer
>
> + );
>
> + return Status;
>
> + }
>
> +
>
> +Exit:
>
> + // Put device back into Read Array mode
>
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0,
> P30_CMD_READ_ARRAY);
>
> +
>
> + return Status;
>
> +}
>
> +
>
> +EFI_STATUS
>
> +NorFlashReset (
>
> + IN NOR_FLASH_INSTANCE *Instance
>
> + )
>
> +{
>
> + // As there is no specific RESET to perform, ensure that the devices is in the
> default Read Array mode
>
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0,
> P30_CMD_READ_ARRAY);
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +/**
>
> + Fixup internal data so that EFI can be call in virtual mode.
>
> + Call the passed in Child Notify event and convert any pointers in
>
> + lib to virtual mode.
>
> +
>
> + @param[in] Event The Event that is being processed
>
> + @param[in] Context Event Context
>
> +**/
>
> +VOID
>
> +EFIAPI
>
> +NorFlashVirtualNotifyEvent (
>
> + IN EFI_EVENT Event,
>
> + IN VOID *Context
>
> + )
>
> +{
>
> + UINTN Index;
>
> +
>
> + for (Index = 0; Index < mNorFlashDeviceCount; Index++) {
>
> + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]-
> >DeviceBaseAddress);
>
> + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]-
> >RegionBaseAddress);
>
> +
>
> + // Convert Fvb
>
> + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]-
> >FvbProtocol.EraseBlocks);
>
> + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]-
> >FvbProtocol.GetAttributes);
>
> + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]-
> >FvbProtocol.GetBlockSize);
>
> + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]-
> >FvbProtocol.GetPhysicalAddress);
>
> + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]-
> >FvbProtocol.Read);
>
> + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]-
> >FvbProtocol.SetAttributes);
>
> + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]-
> >FvbProtocol.Write);
>
> +
>
> + if (mNorFlashInstances[Index]->ShadowBuffer != NULL) {
>
> + EfiConvertPointer (0x0, (VOID **)&mNorFlashInstances[Index]-
> >ShadowBuffer);
>
> + }
>
> + }
>
> +
>
> + return;
>
> +}
>
> diff --git
> a/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlash.h
> b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlash.h
> new file mode 100755
> index 00000000..455eafac
> --- /dev/null
> +++
> b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlash.h
> @@ -0,0 +1,345 @@
> +/** @file NorFlash.h
>
> +
>
> + Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +
>
> +**/
>
> +
>
> +#ifndef __VIRT_NOR_FLASH__
>
> +#define __VIRT_NOR_FLASH__
>
> +
>
> +#include <Base.h>
>
> +#include <PiDxe.h>
>
> +
>
> +#include <Guid/EventGroup.h>
>
> +
>
> +#include <Protocol/FirmwareVolumeBlock.h>
>
> +
>
> +#include <Library/DebugLib.h>
>
> +#include <Library/IoLib.h>
>
> +#include <Library/UefiLib.h>
>
> +#include <Library/UefiRuntimeLib.h>
>
> +#include <Library/VirtNorFlashPlatformLib.h>
>
> +
>
> +#define NOR_FLASH_ERASE_RETRY 10
>
> +
>
> +// Device access macros
>
> +// These are necessary because we use 2 x 16bit parts to make up 32bit data
>
> +
>
> +#define HIGH_16_BITS 0xFFFF0000
>
> +#define LOW_16_BITS 0x0000FFFF
>
> +#define LOW_8_BITS 0x000000FF
>
> +
>
> +#define FOLD_32BIT_INTO_16BIT(value) ( ( value >> 16 ) | ( value &
> LOW_16_BITS ) )
>
> +
>
> +#define GET_LOW_BYTE(value) ( value & LOW_8_BITS )
>
> +#define GET_HIGH_BYTE(value) ( GET_LOW_BYTE( value >> 16 ) )
>
> +
>
> +// Each command must be sent simultaneously to both chips,
>
> +// i.e. at the lower 16 bits AND at the higher 16 bits
>
> +#define CREATE_NOR_ADDRESS(BaseAddr, OffsetAddr) ((BaseAddr) +
> ((OffsetAddr) << 2))
>
> +#define CREATE_DUAL_CMD(Cmd) ( ( Cmd << 16) | ( Cmd &
> LOW_16_BITS) )
>
> +#define SEND_NOR_COMMAND(BaseAddr, Offset, Cmd) MmioWrite32
> (CREATE_NOR_ADDRESS(BaseAddr,Offset), CREATE_DUAL_CMD(Cmd))
>
> +#define GET_NOR_BLOCK_ADDRESS(BaseAddr, Lba, LbaSize) ( BaseAddr +
> (UINTN)((Lba) * LbaSize) )
>
> +
>
> +// Status Register Bits
>
> +#define P30_SR_BIT_WRITE (BIT7 << 16 | BIT7)
>
> +#define P30_SR_BIT_ERASE_SUSPEND (BIT6 << 16 | BIT6)
>
> +#define P30_SR_BIT_ERASE (BIT5 << 16 | BIT5)
>
> +#define P30_SR_BIT_PROGRAM (BIT4 << 16 | BIT4)
>
> +#define P30_SR_BIT_VPP (BIT3 << 16 | BIT3)
>
> +#define P30_SR_BIT_PROGRAM_SUSPEND (BIT2 << 16 | BIT2)
>
> +#define P30_SR_BIT_BLOCK_LOCKED (BIT1 << 16 | BIT1)
>
> +#define P30_SR_BIT_BEFP (BIT0 << 16 | BIT0)
>
> +
>
> +// Device Commands for Intel StrataFlash(R) Embedded Memory (P30) Family
>
> +
>
> +// On chip buffer size for buffered programming operations
>
> +// There are 2 chips, each chip can buffer up to 32 (16-bit)words, and each word
> is 2 bytes.
>
> +// Therefore the total size of the buffer is 2 x 32 x 2 = 128 bytes
>
> +#define P30_MAX_BUFFER_SIZE_IN_BYTES ((UINTN)128)
>
> +#define P30_MAX_BUFFER_SIZE_IN_WORDS
> (P30_MAX_BUFFER_SIZE_IN_BYTES/((UINTN)4))
>
> +#define MAX_BUFFERED_PROG_ITERATIONS 10000000
>
> +#define BOUNDARY_OF_32_WORDS ((UINTN)0x7F)
>
> +
>
> +// CFI Addresses
>
> +#define P30_CFI_ADDR_QUERY_UNIQUE_QRY 0x10
>
> +#define P30_CFI_ADDR_VENDOR_ID 0x13
>
> +
>
> +// CFI Data
>
> +#define CFI_QRY 0x00595251
>
> +
>
> +// READ Commands
>
> +#define P30_CMD_READ_DEVICE_ID 0x0090
>
> +#define P30_CMD_READ_STATUS_REGISTER 0x0070
>
> +#define P30_CMD_CLEAR_STATUS_REGISTER 0x0050
>
> +#define P30_CMD_READ_ARRAY 0x00FF
>
> +#define P30_CMD_READ_CFI_QUERY 0x0098
>
> +
>
> +// WRITE Commands
>
> +#define P30_CMD_WORD_PROGRAM_SETUP 0x0040
>
> +#define P30_CMD_ALTERNATE_WORD_PROGRAM_SETUP 0x0010
>
> +#define P30_CMD_BUFFERED_PROGRAM_SETUP 0x00E8
>
> +#define P30_CMD_BUFFERED_PROGRAM_CONFIRM 0x00D0
>
> +#define P30_CMD_BEFP_SETUP 0x0080
>
> +#define P30_CMD_BEFP_CONFIRM 0x00D0
>
> +
>
> +// ERASE Commands
>
> +#define P30_CMD_BLOCK_ERASE_SETUP 0x0020
>
> +#define P30_CMD_BLOCK_ERASE_CONFIRM 0x00D0
>
> +
>
> +// SUSPEND Commands
>
> +#define P30_CMD_PROGRAM_OR_ERASE_SUSPEND 0x00B0
>
> +#define P30_CMD_SUSPEND_RESUME 0x00D0
>
> +
>
> +// BLOCK LOCKING / UNLOCKING Commands
>
> +#define P30_CMD_LOCK_BLOCK_SETUP 0x0060
>
> +#define P30_CMD_LOCK_BLOCK 0x0001
>
> +#define P30_CMD_UNLOCK_BLOCK 0x00D0
>
> +#define P30_CMD_LOCK_DOWN_BLOCK 0x002F
>
> +
>
> +// PROTECTION Commands
>
> +#define P30_CMD_PROGRAM_PROTECTION_REGISTER_SETUP 0x00C0
>
> +
>
> +// CONFIGURATION Commands
>
> +#define P30_CMD_READ_CONFIGURATION_REGISTER_SETUP 0x0060
>
> +#define P30_CMD_READ_CONFIGURATION_REGISTER 0x0003
>
> +
>
> +#define NOR_FLASH_SIGNATURE SIGNATURE_32('n', 'o', 'r', '0')
>
> +#define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE,
> FvbProtocol, NOR_FLASH_SIGNATURE)
>
> +
>
> +typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE;
>
> +
>
> +#pragma pack (1)
>
> +typedef struct {
>
> + VENDOR_DEVICE_PATH Vendor;
>
> + UINT8 Index;
>
> + EFI_DEVICE_PATH_PROTOCOL End;
>
> +} NOR_FLASH_DEVICE_PATH;
>
> +#pragma pack ()
>
> +
>
> +struct _NOR_FLASH_INSTANCE {
>
> + UINT32 Signature;
>
> + EFI_HANDLE Handle;
>
> +
>
> + UINTN DeviceBaseAddress;
>
> + UINTN RegionBaseAddress;
>
> + UINTN Size;
>
> + EFI_LBA StartLba;
>
> + EFI_LBA LastBlock;
>
> + UINT32 BlockSize;
>
> +
>
> + EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;
>
> + VOID *ShadowBuffer;
>
> +
>
> + NOR_FLASH_DEVICE_PATH DevicePath;
>
> +};
>
> +
>
> +EFI_STATUS
>
> +NorFlashReadCfiData (
>
> + IN UINTN DeviceBaseAddress,
>
> + IN UINTN CFI_Offset,
>
> + IN UINT32 NumberOfBytes,
>
> + OUT UINT32 *Data
>
> + );
>
> +
>
> +EFI_STATUS
>
> +NorFlashWriteBuffer (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN UINTN TargetAddress,
>
> + IN UINTN BufferSizeInBytes,
>
> + IN UINT32 *Buffer
>
> + );
>
> +
>
> +//
>
> +// NorFlashFvbDxe.c
>
> +//
>
> +
>
> +EFI_STATUS
>
> +EFIAPI
>
> +FvbGetAttributes (
>
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
>
> + OUT EFI_FVB_ATTRIBUTES_2 *Attributes
>
> + );
>
> +
>
> +EFI_STATUS
>
> +EFIAPI
>
> +FvbSetAttributes (
>
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
>
> + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
>
> + );
>
> +
>
> +EFI_STATUS
>
> +EFIAPI
>
> +FvbGetPhysicalAddress (
>
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
>
> + OUT EFI_PHYSICAL_ADDRESS *Address
>
> + );
>
> +
>
> +EFI_STATUS
>
> +EFIAPI
>
> +FvbGetBlockSize (
>
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
>
> + IN EFI_LBA Lba,
>
> + OUT UINTN *BlockSize,
>
> + OUT UINTN *NumberOfBlocks
>
> + );
>
> +
>
> +EFI_STATUS
>
> +EFIAPI
>
> +FvbRead (
>
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
>
> + IN EFI_LBA Lba,
>
> + IN UINTN Offset,
>
> + IN OUT UINTN *NumBytes,
>
> + IN OUT UINT8 *Buffer
>
> + );
>
> +
>
> +EFI_STATUS
>
> +EFIAPI
>
> +FvbWrite (
>
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
>
> + IN EFI_LBA Lba,
>
> + IN UINTN Offset,
>
> + IN OUT UINTN *NumBytes,
>
> + IN UINT8 *Buffer
>
> + );
>
> +
>
> +EFI_STATUS
>
> +EFIAPI
>
> +FvbEraseBlocks (
>
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
>
> + ...
>
> + );
>
> +
>
> +EFI_STATUS
>
> +ValidateFvHeader (
>
> + IN NOR_FLASH_INSTANCE *Instance
>
> + );
>
> +
>
> +EFI_STATUS
>
> +InitializeFvAndVariableStoreHeaders (
>
> + IN NOR_FLASH_INSTANCE *Instance
>
> + );
>
> +
>
> +VOID
>
> +EFIAPI
>
> +FvbVirtualNotifyEvent (
>
> + IN EFI_EVENT Event,
>
> + IN VOID *Context
>
> + );
>
> +
>
> +//
>
> +// NorFlashDxe.c
>
> +//
>
> +
>
> +EFI_STATUS
>
> +NorFlashWriteFullBlock (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN EFI_LBA Lba,
>
> + IN UINT32 *DataBuffer,
>
> + IN UINT32 BlockSizeInWords
>
> + );
>
> +
>
> +EFI_STATUS
>
> +NorFlashUnlockAndEraseSingleBlock (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN UINTN BlockAddress
>
> + );
>
> +
>
> +EFI_STATUS
>
> +NorFlashCreateInstance (
>
> + IN UINTN NorFlashDeviceBase,
>
> + IN UINTN NorFlashRegionBase,
>
> + IN UINTN NorFlashSize,
>
> + IN UINT32 Index,
>
> + IN UINT32 BlockSize,
>
> + IN BOOLEAN SupportFvb,
>
> + OUT NOR_FLASH_INSTANCE **NorFlashInstance
>
> + );
>
> +
>
> +EFI_STATUS
>
> +EFIAPI
>
> +NorFlashFvbInitialize (
>
> + IN NOR_FLASH_INSTANCE *Instance
>
> + );
>
> +
>
> +//
>
> +// NorFlash.c
>
> +//
>
> +EFI_STATUS
>
> +NorFlashWriteSingleBlock (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN EFI_LBA Lba,
>
> + IN UINTN Offset,
>
> + IN OUT UINTN *NumBytes,
>
> + IN UINT8 *Buffer
>
> + );
>
> +
>
> +EFI_STATUS
>
> +NorFlashWriteBlocks (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN EFI_LBA Lba,
>
> + IN UINTN BufferSizeInBytes,
>
> + IN VOID *Buffer
>
> + );
>
> +
>
> +EFI_STATUS
>
> +NorFlashReadBlocks (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN EFI_LBA Lba,
>
> + IN UINTN BufferSizeInBytes,
>
> + OUT VOID *Buffer
>
> + );
>
> +
>
> +EFI_STATUS
>
> +NorFlashRead (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN EFI_LBA Lba,
>
> + IN UINTN Offset,
>
> + IN UINTN BufferSizeInBytes,
>
> + OUT VOID *Buffer
>
> + );
>
> +
>
> +EFI_STATUS
>
> +NorFlashWrite (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN EFI_LBA Lba,
>
> + IN UINTN Offset,
>
> + IN OUT UINTN *NumBytes,
>
> + IN UINT8 *Buffer
>
> + );
>
> +
>
> +EFI_STATUS
>
> +NorFlashReset (
>
> + IN NOR_FLASH_INSTANCE *Instance
>
> + );
>
> +
>
> +EFI_STATUS
>
> +NorFlashEraseSingleBlock (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN UINTN BlockAddress
>
> + );
>
> +
>
> +EFI_STATUS
>
> +NorFlashUnlockSingleBlockIfNecessary (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN UINTN BlockAddress
>
> + );
>
> +
>
> +EFI_STATUS
>
> +NorFlashWriteSingleWord (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN UINTN WordAddress,
>
> + IN UINT32 WriteData
>
> + );
>
> +
>
> +VOID
>
> +EFIAPI
>
> +NorFlashVirtualNotifyEvent (
>
> + IN EFI_EVENT Event,
>
> + IN VOID *Context
>
> + );
>
> +
>
> +#endif /* __VIRT_NOR_FLASH__ */
>
> diff --git
> a/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashDxe.c
> b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashDxe.c
> new file mode 100755
> index 00000000..a7620702
> --- /dev/null
> +++
> b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashDxe.c
> @@ -0,0 +1,447 @@
> +/** @file NorFlashDxe.c
>
> +
>
> + Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
>
> + Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +
>
> +**/
>
> +
>
> +#include <Library/BaseMemoryLib.h>
>
> +#include <Library/HobLib.h>
>
> +#include <Library/MemoryAllocationLib.h>
>
> +#include <Library/PcdLib.h>
>
> +#include <Library/UefiBootServicesTableLib.h>
>
> +#include <Library/UefiLib.h>
>
> +
>
> +#include "VirtNorFlash.h"
>
> +
>
> +STATIC EFI_EVENT mNorFlashVirtualAddrChangeEvent;
>
> +
>
> +//
>
> +// Global variable declarations
>
> +//
>
> +NOR_FLASH_INSTANCE **mNorFlashInstances;
>
> +UINT32 mNorFlashDeviceCount;
>
> +UINTN mFlashNvStorageVariableBase;
>
> +EFI_EVENT mFvbVirtualAddrChangeEvent;
>
> +
>
> +NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = {
>
> + NOR_FLASH_SIGNATURE, // Signature
>
> + NULL, // Handle ... NEED TO BE FILLED
>
> +
>
> + 0, // DeviceBaseAddress ... NEED TO BE FILLED
>
> + 0, // RegionBaseAddress ... NEED TO BE FILLED
>
> + 0, // Size ... NEED TO BE FILLED
>
> + 0, // StartLba
>
> + 0, // LastBlock
>
> + 0, // BlockSize
>
> +
>
> + {
>
> + FvbGetAttributes, // GetAttributes
>
> + FvbSetAttributes, // SetAttributes
>
> + FvbGetPhysicalAddress, // GetPhysicalAddress
>
> + FvbGetBlockSize, // GetBlockSize
>
> + FvbRead, // Read
>
> + FvbWrite, // Write
>
> + FvbEraseBlocks, // EraseBlocks
>
> + NULL, // ParentHandle
>
> + }, // FvbProtoccol;
>
> + NULL, // ShadowBuffer
>
> + {
>
> + {
>
> + {
>
> + HARDWARE_DEVICE_PATH,
>
> + HW_VENDOR_DP,
>
> + {
>
> + (UINT8)(OFFSET_OF (NOR_FLASH_DEVICE_PATH, End)),
>
> + (UINT8)(OFFSET_OF (NOR_FLASH_DEVICE_PATH, End) >> 8)
>
> + }
>
> + },
>
> + { 0x0, 0x0, 0x0, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
>
> + }, // GUID ... NEED TO BE FILLED
>
> + },
>
> + 0, // Index
>
> + {
>
> + END_DEVICE_PATH_TYPE,
>
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
>
> + { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 }
>
> + }
>
> + } // DevicePath
>
> +};
>
> +
>
> +EFI_STATUS
>
> +NorFlashCreateInstance (
>
> + IN UINTN NorFlashDeviceBase,
>
> + IN UINTN NorFlashRegionBase,
>
> + IN UINTN NorFlashSize,
>
> + IN UINT32 Index,
>
> + IN UINT32 BlockSize,
>
> + IN BOOLEAN SupportFvb,
>
> + OUT NOR_FLASH_INSTANCE **NorFlashInstance
>
> + )
>
> +{
>
> + EFI_STATUS Status;
>
> + NOR_FLASH_INSTANCE *Instance;
>
> +
>
> + ASSERT (NorFlashInstance != NULL);
>
> +
>
> + Instance = AllocateRuntimeCopyPool (sizeof (NOR_FLASH_INSTANCE),
> &mNorFlashInstanceTemplate);
>
> + if (Instance == NULL) {
>
> + return EFI_OUT_OF_RESOURCES;
>
> + }
>
> +
>
> + Instance->DeviceBaseAddress = NorFlashDeviceBase;
>
> + Instance->RegionBaseAddress = NorFlashRegionBase;
>
> + Instance->Size = NorFlashSize;
>
> + Instance->BlockSize = BlockSize;
>
> + Instance->LastBlock = (NorFlashSize / BlockSize) - 1;
>
> +
>
> + CopyGuid (&Instance->DevicePath.Vendor.Guid, &gEfiCallerIdGuid);
>
> + Instance->DevicePath.Index = (UINT8)Index;
>
> +
>
> + Instance->ShadowBuffer = AllocateRuntimePool (BlockSize);
>
> + if (Instance->ShadowBuffer == NULL) {
>
> + return EFI_OUT_OF_RESOURCES;
>
> + }
>
> +
>
> + if (SupportFvb) {
>
> + NorFlashFvbInitialize (Instance);
>
> +
>
> + Status = gBS->InstallMultipleProtocolInterfaces (
>
> + &Instance->Handle,
>
> + &gEfiDevicePathProtocolGuid,
>
> + &Instance->DevicePath,
>
> + &gEfiFirmwareVolumeBlockProtocolGuid,
>
> + &Instance->FvbProtocol,
>
> + NULL
>
> + );
>
> + if (EFI_ERROR (Status)) {
>
> + FreePool (Instance);
>
> + return Status;
>
> + }
>
> + } else {
>
> + Status = gBS->InstallMultipleProtocolInterfaces (
>
> + &Instance->Handle,
>
> + &gEfiDevicePathProtocolGuid,
>
> + &Instance->DevicePath,
>
> + NULL
>
> + );
>
> + if (EFI_ERROR (Status)) {
>
> + FreePool (Instance);
>
> + return Status;
>
> + }
>
> + }
>
> +
>
> + *NorFlashInstance = Instance;
>
> + return Status;
>
> +}
>
> +
>
> +/**
>
> + * This function unlock and erase an entire NOR Flash block.
>
> + **/
>
> +EFI_STATUS
>
> +NorFlashUnlockAndEraseSingleBlock (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN UINTN BlockAddress
>
> + )
>
> +{
>
> + EFI_STATUS Status;
>
> + UINTN Index;
>
> + EFI_TPL OriginalTPL;
>
> +
>
> + if (!EfiAtRuntime ()) {
>
> + // Raise TPL to TPL_HIGH to stop anyone from interrupting us.
>
> + OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
>
> + } else {
>
> + // This initialization is only to prevent the compiler to complain about the
>
> + // use of uninitialized variables
>
> + OriginalTPL = TPL_HIGH_LEVEL;
>
> + }
>
> +
>
> + Index = 0;
>
> + // The block erase might fail a first time (SW bug ?). Retry it ...
>
> + do {
>
> + // Unlock the block if we have to
>
> + Status = NorFlashUnlockSingleBlockIfNecessary (Instance, BlockAddress);
>
> + if (EFI_ERROR (Status)) {
>
> + break;
>
> + }
>
> +
>
> + Status = NorFlashEraseSingleBlock (Instance, BlockAddress);
>
> + Index++;
>
> + } while ((Index < NOR_FLASH_ERASE_RETRY) && (Status ==
> EFI_WRITE_PROTECTED));
>
> +
>
> + if (Index == NOR_FLASH_ERASE_RETRY) {
>
> + DEBUG ((DEBUG_ERROR, "EraseSingleBlock(BlockAddress=0x%08x: Block
> Locked Error (try to erase %d times)\n", BlockAddress, Index));
>
> + }
>
> +
>
> + if (!EfiAtRuntime ()) {
>
> + // Interruptions can resume.
>
> + gBS->RestoreTPL (OriginalTPL);
>
> + }
>
> +
>
> + return Status;
>
> +}
>
> +
>
> +EFI_STATUS
>
> +NorFlashWriteFullBlock (
>
> + IN NOR_FLASH_INSTANCE *Instance,
>
> + IN EFI_LBA Lba,
>
> + IN UINT32 *DataBuffer,
>
> + IN UINT32 BlockSizeInWords
>
> + )
>
> +{
>
> + EFI_STATUS Status;
>
> + UINTN WordAddress;
>
> + UINT32 WordIndex;
>
> + UINTN BufferIndex;
>
> + UINTN BlockAddress;
>
> + UINTN BuffersInBlock;
>
> + UINTN RemainingWords;
>
> + EFI_TPL OriginalTPL;
>
> + UINTN Cnt;
>
> +
>
> + Status = EFI_SUCCESS;
>
> +
>
> + // Get the physical address of the block
>
> + BlockAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress,
> Lba, BlockSizeInWords * 4);
>
> +
>
> + // Start writing from the first address at the start of the block
>
> + WordAddress = BlockAddress;
>
> +
>
> + if (!EfiAtRuntime ()) {
>
> + // Raise TPL to TPL_HIGH to stop anyone from interrupting us.
>
> + OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
>
> + } else {
>
> + // This initialization is only to prevent the compiler to complain about the
>
> + // use of uninitialized variables
>
> + OriginalTPL = TPL_HIGH_LEVEL;
>
> + }
>
> +
>
> + Status = NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress);
>
> + if (EFI_ERROR (Status)) {
>
> + DEBUG ((DEBUG_ERROR, "WriteSingleBlock: ERROR - Failed to Unlock and
> Erase the single block at 0x%X\n", BlockAddress));
>
> + goto EXIT;
>
> + }
>
> +
>
> + // To speed up the programming operation, NOR Flash is programmed using the
> Buffered Programming method.
>
> +
>
> + // Check that the address starts at a 32-word boundary, i.e. last 7 bits must be
> zero
>
> + if ((WordAddress & BOUNDARY_OF_32_WORDS) == 0x00) {
>
> + // First, break the entire block into buffer-sized chunks.
>
> + BuffersInBlock = (UINTN)(BlockSizeInWords * 4) /
> P30_MAX_BUFFER_SIZE_IN_BYTES;
>
> +
>
> + // Then feed each buffer chunk to the NOR Flash
>
> + // If a buffer does not contain any data, don't write it.
>
> + for (BufferIndex = 0;
>
> + BufferIndex < BuffersInBlock;
>
> + BufferIndex++, WordAddress += P30_MAX_BUFFER_SIZE_IN_BYTES,
> DataBuffer += P30_MAX_BUFFER_SIZE_IN_WORDS
>
> + )
>
> + {
>
> + // Check the buffer to see if it contains any data (not set all 1s).
>
> + for (Cnt = 0; Cnt < P30_MAX_BUFFER_SIZE_IN_WORDS; Cnt++) {
>
> + if (~DataBuffer[Cnt] != 0 ) {
>
> + // Some data found, write the buffer.
>
> + Status = NorFlashWriteBuffer (
>
> + Instance,
>
> + WordAddress,
>
> + P30_MAX_BUFFER_SIZE_IN_BYTES,
>
> + DataBuffer
>
> + );
>
> + if (EFI_ERROR (Status)) {
>
> + goto EXIT;
>
> + }
>
> +
>
> + break;
>
> + }
>
> + }
>
> + }
>
> +
>
> + // Finally, finish off any remaining words that are less than the maximum size
> of the buffer
>
> + RemainingWords = BlockSizeInWords % P30_MAX_BUFFER_SIZE_IN_WORDS;
>
> +
>
> + if (RemainingWords != 0) {
>
> + Status = NorFlashWriteBuffer (Instance, WordAddress, (RemainingWords * 4),
> DataBuffer);
>
> + if (EFI_ERROR (Status)) {
>
> + goto EXIT;
>
> + }
>
> + }
>
> + } else {
>
> + // For now, use the single word programming algorithm
>
> + // It is unlikely that the NOR Flash will exist in an address which falls within a
> 32 word boundary range,
>
> + // i.e. which ends in the range 0x......01 - 0x......7F.
>
> + for (WordIndex = 0; WordIndex < BlockSizeInWords; WordIndex++,
> DataBuffer++, WordAddress = WordAddress + 4) {
>
> + Status = NorFlashWriteSingleWord (Instance, WordAddress, *DataBuffer);
>
> + if (EFI_ERROR (Status)) {
>
> + goto EXIT;
>
> + }
>
> + }
>
> + }
>
> +
>
> +EXIT:
>
> + // Put device back into Read Array mode
>
> + SEND_NOR_COMMAND (Instance->DeviceBaseAddress, 0,
> P30_CMD_READ_ARRAY);
>
> +
>
> + if (!EfiAtRuntime ()) {
>
> + // Interruptions can resume.
>
> + gBS->RestoreTPL (OriginalTPL);
>
> + }
>
> +
>
> + if (EFI_ERROR (Status)) {
>
> + DEBUG ((DEBUG_ERROR, "NOR FLASH Programming [WriteSingleBlock] failed
> at address 0x%08x. Exit Status = \"%r\".\n", WordAddress, Status));
>
> + }
>
> +
>
> + return Status;
>
> +}
>
> +
>
> +EFI_STATUS
>
> +EFIAPI
>
> +NorFlashInitialise (
>
> + IN EFI_HANDLE ImageHandle,
>
> + IN EFI_SYSTEM_TABLE *SystemTable
>
> + )
>
> +{
>
> + EFI_STATUS Status;
>
> + UINT32 Index;
>
> + VIRT_NOR_FLASH_DESCRIPTION *NorFlashDevices;
>
> + BOOLEAN ContainVariableStorage;
>
> +
>
> + Status = VirtNorFlashPlatformInitialization ();
>
> + if (EFI_ERROR (Status)) {
>
> + DEBUG ((DEBUG_ERROR, "NorFlashInitialise: Fail to initialize Nor Flash
> devices\n"));
>
> + return Status;
>
> + }
>
> +
>
> + Status = VirtNorFlashPlatformGetDevices (&NorFlashDevices,
> &mNorFlashDeviceCount);
>
> + if (EFI_ERROR (Status)) {
>
> + DEBUG ((DEBUG_ERROR, "NorFlashInitialise: Fail to get Nor Flash
> devices\n"));
>
> + return Status;
>
> + }
>
> +
>
> + mNorFlashInstances = AllocateRuntimePool (sizeof (NOR_FLASH_INSTANCE *)
> * mNorFlashDeviceCount);
>
> +
>
> + for (Index = 0; Index < mNorFlashDeviceCount; Index++) {
>
> + // Check if this NOR Flash device contain the variable storage region
>
> +
>
> + if (PcdGet64 (PcdFlashNvStorageVariableBase64) != 0) {
>
> + ContainVariableStorage =
>
> + (NorFlashDevices[Index].RegionBaseAddress <= PcdGet64
> (PcdFlashNvStorageVariableBase64)) &&
>
> + (PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32
> (PcdFlashNvStorageVariableSize) <=
>
> + NorFlashDevices[Index].RegionBaseAddress +
> NorFlashDevices[Index].Size);
>
> + } else {
>
> + ContainVariableStorage =
>
> + (NorFlashDevices[Index].RegionBaseAddress <= PcdGet32
> (PcdFlashNvStorageVariableBase)) &&
>
> + (PcdGet32 (PcdFlashNvStorageVariableBase) + PcdGet32
> (PcdFlashNvStorageVariableSize) <=
>
> + NorFlashDevices[Index].RegionBaseAddress +
> NorFlashDevices[Index].Size);
>
> + }
>
> +
>
> + Status = NorFlashCreateInstance (
>
> + NorFlashDevices[Index].DeviceBaseAddress,
>
> + NorFlashDevices[Index].RegionBaseAddress,
>
> + NorFlashDevices[Index].Size,
>
> + Index,
>
> + NorFlashDevices[Index].BlockSize,
>
> + ContainVariableStorage,
>
> + &mNorFlashInstances[Index]
>
> + );
>
> + if (EFI_ERROR (Status)) {
>
> + DEBUG ((DEBUG_ERROR, "NorFlashInitialise: Fail to create instance for
> NorFlash[%d]\n", Index));
>
> + }
>
> + }
>
> +
>
> + //
>
> + // Register for the virtual address change event
>
> + //
>
> + Status = gBS->CreateEventEx (
>
> + EVT_NOTIFY_SIGNAL,
>
> + TPL_NOTIFY,
>
> + NorFlashVirtualNotifyEvent,
>
> + NULL,
>
> + &gEfiEventVirtualAddressChangeGuid,
>
> + &mNorFlashVirtualAddrChangeEvent
>
> + );
>
> + ASSERT_EFI_ERROR (Status);
>
> +
>
> + return Status;
>
> +}
>
> +
>
> +EFI_STATUS
>
> +EFIAPI
>
> +NorFlashFvbInitialize (
>
> + IN NOR_FLASH_INSTANCE *Instance
>
> + )
>
> +{
>
> + EFI_STATUS Status;
>
> + UINT32 FvbNumLba;
>
> + EFI_BOOT_MODE BootMode;
>
> +
>
> + DEBUG ((DEBUG_BLKIO, "NorFlashFvbInitialize\n"));
>
> + ASSERT ((Instance != NULL));
>
> +
>
> + mFlashNvStorageVariableBase = (PcdGet64
> (PcdFlashNvStorageVariableBase64) != 0) ?
>
> + PcdGet64 (PcdFlashNvStorageVariableBase64) : PcdGet32
> (PcdFlashNvStorageVariableBase);
>
> +
>
> + // Set the index of the first LBA for the FVB
>
> + Instance->StartLba = (mFlashNvStorageVariableBase - Instance-
> >RegionBaseAddress) / Instance->BlockSize;
>
> +
>
> + BootMode = GetBootModeHob ();
>
> + if (BootMode == BOOT_WITH_DEFAULT_SETTINGS) {
>
> + Status = EFI_INVALID_PARAMETER;
>
> + } else {
>
> + // Determine if there is a valid header at the beginning of the NorFlash
>
> + Status = ValidateFvHeader (Instance);
>
> + }
>
> +
>
> + // Install the Default FVB header if required
>
> + if (EFI_ERROR (Status)) {
>
> + // There is no valid header, so time to install one.
>
> + DEBUG ((DEBUG_INFO, "%a: The FVB Header is not valid.\n", __func__));
>
> + DEBUG ((
>
> + DEBUG_INFO,
>
> + "%a: Installing a correct one for this volume.\n",
>
> + __func__
>
> + ));
>
> +
>
> + // Erase all the NorFlash that is reserved for variable storage
>
> + FvbNumLba = (PcdGet32 (PcdFlashNvStorageVariableSize) + PcdGet32
> (PcdFlashNvStorageFtwWorkingSize) + PcdGet32
> (PcdFlashNvStorageFtwSpareSize)) / Instance->BlockSize;
>
> +
>
> + Status = FvbEraseBlocks (&Instance->FvbProtocol, (EFI_LBA)0, FvbNumLba,
> EFI_LBA_LIST_TERMINATOR);
>
> + if (EFI_ERROR (Status)) {
>
> + return Status;
>
> + }
>
> +
>
> + // Install all appropriate headers
>
> + Status = InitializeFvAndVariableStoreHeaders (Instance);
>
> + if (EFI_ERROR (Status)) {
>
> + return Status;
>
> + }
>
> + }
>
> +
>
> + //
>
> + // The driver implementing the variable read service can now be dispatched;
>
> + // the varstore headers are in place.
>
> + //
>
> + Status = gBS->InstallProtocolInterface (
>
> + &gImageHandle,
>
> + &gEdkiiNvVarStoreFormattedGuid,
>
> + EFI_NATIVE_INTERFACE,
>
> + NULL
>
> + );
>
> + ASSERT_EFI_ERROR (Status);
>
> +
>
> + //
>
> + // Register for the virtual address change event
>
> + //
>
> + Status = gBS->CreateEventEx (
>
> + EVT_NOTIFY_SIGNAL,
>
> + TPL_NOTIFY,
>
> + FvbVirtualNotifyEvent,
>
> + NULL,
>
> + &gEfiEventVirtualAddressChangeGuid,
>
> + &mFvbVirtualAddrChangeEvent
>
> + );
>
> + ASSERT_EFI_ERROR (Status);
>
> +
>
> + return Status;
>
> +}
>
> diff --git
> a/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashDxe.i
> nf
> b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashDxe.i
> nf
> new file mode 100755
> index 00000000..8975bdb1
> --- /dev/null
> +++
> b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashDxe.i
> nf
> @@ -0,0 +1,69 @@
> +#/** @file
>
> +#
>
> +# Component description file for NorFlashDxe module
>
> +#
>
> +# Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
>
> +# Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
>
> +#
>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +#
>
> +#**/
>
> +
>
> +[Defines]
>
> + INF_VERSION = 1.29
>
> + BASE_NAME = VirtNorFlashDxe
>
> + FILE_GUID = ADA0DB67-7C55-4950-8BA3-FC6D19CEA52F
>
> + MODULE_TYPE = DXE_RUNTIME_DRIVER
>
> + VERSION_STRING = 1.0
>
> + ENTRY_POINT = NorFlashInitialise
>
> +
>
> +[Sources.common]
>
> + VirtNorFlash.c
>
> + VirtNorFlash.h
>
> + VirtNorFlashDxe.c
>
> + VirtNorFlashFvb.c
>
> +
>
> +[Packages]
>
> + EmbeddedPkg/EmbeddedPkg.dec
>
> + MdePkg/MdePkg.dec
>
> + MdeModulePkg/MdeModulePkg.dec
>
> + OvmfPkg/OvmfPkg.dec
>
> +
>
> +[LibraryClasses]
>
> + BaseLib
>
> + DebugLib
>
> + HobLib
>
> + IoLib
>
> + SafeIntLib
>
> + UefiBootServicesTableLib
>
> + UefiDriverEntryPoint
>
> + UefiLib
>
> + UefiRuntimeLib
>
> + VirtNorFlashPlatformLib
>
> +
>
> +[Guids]
>
> + gEdkiiNvVarStoreFormattedGuid ## PRODUCES ## PROTOCOL
>
> + gEfiAuthenticatedVariableGuid
>
> + gEfiEventVirtualAddressChangeGuid
>
> + gEfiSystemNvDataFvGuid
>
> + gEfiVariableGuid
>
> +
>
> +[Protocols]
>
> + gEfiBlockIoProtocolGuid
>
> + gEfiDevicePathProtocolGuid
>
> + gEfiDiskIoProtocolGuid
>
> + gEfiFirmwareVolumeBlockProtocolGuid
>
> +
>
> +[Pcd.common]
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
>
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
>
> +
>
> +[Depex]
>
> + gEfiCpuArchProtocolGuid
>
> diff --git
> a/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashFvb.c
> b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashFvb.c
> new file mode 100755
> index 00000000..c8b5e0be
> --- /dev/null
> +++
> b/Platform/Qemu/RiscVQemuServerPlatform/VirtNorFlashDxe/VirtNorFlashFvb.c
> @@ -0,0 +1,904 @@
> +/*++ @file NorFlashFvbDxe.c
>
> +
>
> + Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +
>
> + --*/
>
> +
>
> +#include <PiDxe.h>
>
> +
>
> +#include <Library/BaseLib.h>
>
> +#include <Library/BaseMemoryLib.h>
>
> +#include <Library/MemoryAllocationLib.h>
>
> +#include <Library/PcdLib.h>
>
> +#include <Library/SafeIntLib.h>
>
> +#include <Library/UefiLib.h>
>
> +
>
> +#include <Guid/NvVarStoreFormatted.h>
>
> +#include <Guid/SystemNvDataGuid.h>
>
> +#include <Guid/VariableFormat.h>
>
> +
>
> +#include "VirtNorFlash.h"
>
> +
>
> +extern UINTN mFlashNvStorageVariableBase;
>
> +///
>
> +/// The Firmware Volume Block Protocol is the low-level interface
>
> +/// to a firmware volume. File-level access to a firmware volume
>
> +/// should not be done using the Firmware Volume Block Protocol.
>
> +/// Normal access to a firmware volume must use the Firmware
>
> +/// Volume Protocol. Typically, only the file system driver that
>
> +/// produces the Firmware Volume Protocol will bind to the
>
> +/// Firmware Volume Block Protocol.
>
> +///
>
> +
>
> +/**
>
> + Initialises the FV Header and Variable Store Header
>
> + to support variable operations.
>
> +
>
> + @param[in] Ptr - Location to initialise the headers
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +InitializeFvAndVariableStoreHeaders (
>
> + IN NOR_FLASH_INSTANCE *Instance
>
> + )
>
> +{
>
> + EFI_STATUS Status;
>
> + VOID *Headers;
>
> + UINTN HeadersLength;
>
> + EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader;
>
> + VARIABLE_STORE_HEADER *VariableStoreHeader;
>
> + UINT32 NvStorageFtwSpareSize;
>
> + UINT32 NvStorageFtwWorkingSize;
>
> + UINT32 NvStorageVariableSize;
>
> + UINT64 NvStorageFtwSpareBase;
>
> + UINT64 NvStorageFtwWorkingBase;
>
> + UINT64 NvStorageVariableBase;
>
> +
>
> + HeadersLength = sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof
> (EFI_FV_BLOCK_MAP_ENTRY) + sizeof (VARIABLE_STORE_HEADER);
>
> + Headers = AllocateZeroPool (HeadersLength);
>
> +
>
> + NvStorageFtwWorkingSize = PcdGet32 (PcdFlashNvStorageFtwWorkingSize);
>
> + NvStorageFtwSpareSize = PcdGet32 (PcdFlashNvStorageFtwSpareSize);
>
> + NvStorageVariableSize = PcdGet32 (PcdFlashNvStorageVariableSize);
>
> +
>
> + NvStorageFtwSpareBase = (PcdGet64 (PcdFlashNvStorageFtwSpareBase64) !=
> 0) ?
>
> + PcdGet64 (PcdFlashNvStorageFtwSpareBase64) : PcdGet32
> (PcdFlashNvStorageFtwSpareBase);
>
> + NvStorageFtwWorkingBase = (PcdGet64
> (PcdFlashNvStorageFtwWorkingBase64) != 0) ?
>
> + PcdGet64 (PcdFlashNvStorageFtwWorkingBase64) : PcdGet32
> (PcdFlashNvStorageFtwWorkingBase);
>
> + NvStorageVariableBase = (PcdGet64 (PcdFlashNvStorageVariableBase64) != 0)
> ?
>
> + PcdGet64 (PcdFlashNvStorageVariableBase64) : PcdGet32
> (PcdFlashNvStorageVariableBase);
>
> +
>
> + // FirmwareVolumeHeader->FvLength is declared to have the Variable area
> AND the FTW working area AND the FTW Spare contiguous.
>
> + if ((NvStorageVariableBase + NvStorageVariableSize) !=
> NvStorageFtwWorkingBase) {
>
> + DEBUG ((
>
> + DEBUG_ERROR,
>
> + "%a: NvStorageFtwWorkingBase is not contiguous with
> NvStorageVariableBase region\n",
>
> + __func__
>
> + ));
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> +
>
> + if ((NvStorageFtwWorkingBase + NvStorageFtwWorkingSize) !=
> NvStorageFtwSpareBase) {
>
> + DEBUG ((
>
> + DEBUG_ERROR,
>
> + "%a: NvStorageFtwSpareBase is not contiguous with
> NvStorageFtwWorkingBase region\n",
>
> + __func__
>
> + ));
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> +
>
> + // Check if the size of the area is at least one block size
>
> + if ((NvStorageVariableSize <= 0) || (NvStorageVariableSize / Instance-
> >BlockSize <= 0)) {
>
> + DEBUG ((
>
> + DEBUG_ERROR,
>
> + "%a: NvStorageVariableSize is 0x%x, should be atleast one block size\n",
>
> + __func__,
>
> + NvStorageVariableSize
>
> + ));
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> +
>
> + if ((NvStorageFtwWorkingSize <= 0) || (NvStorageFtwWorkingSize / Instance-
> >BlockSize <= 0)) {
>
> + DEBUG ((
>
> + DEBUG_ERROR,
>
> + "%a: NvStorageFtwWorkingSize is 0x%x, should be atleast one block size\n",
>
> + __func__,
>
> + NvStorageFtwWorkingSize
>
> + ));
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> +
>
> + if ((NvStorageFtwSpareSize <= 0) || (NvStorageFtwSpareSize / Instance-
> >BlockSize <= 0)) {
>
> + DEBUG ((
>
> + DEBUG_ERROR,
>
> + "%a: NvStorageFtwSpareSize is 0x%x, should be atleast one block size\n",
>
> + __func__,
>
> + NvStorageFtwSpareSize
>
> + ));
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> +
>
> + // Ensure the Variable area Base Addresses are aligned on a block size
> boundaries
>
> + if ((NvStorageVariableBase % Instance->BlockSize != 0) ||
>
> + (NvStorageFtwWorkingBase % Instance->BlockSize != 0) ||
>
> + (NvStorageFtwSpareBase % Instance->BlockSize != 0))
>
> + {
>
> + DEBUG ((DEBUG_ERROR, "%a: NvStorage Base addresses must be aligned to
> block size boundaries", __func__));
>
> + return EFI_INVALID_PARAMETER;
>
> + }
>
> +
>
> + //
>
> + // EFI_FIRMWARE_VOLUME_HEADER
>
> + //
>
> + FirmwareVolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER *)Headers;
>
> + CopyGuid (&FirmwareVolumeHeader->FileSystemGuid,
> &gEfiSystemNvDataFvGuid);
>
> + FirmwareVolumeHeader->FvLength =
>
> + PcdGet32 (PcdFlashNvStorageVariableSize) +
>
> + PcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
>
> + PcdGet32 (PcdFlashNvStorageFtwSpareSize);
>
> + FirmwareVolumeHeader->Signature = EFI_FVH_SIGNATURE;
>
> + FirmwareVolumeHeader->Attributes = (EFI_FVB_ATTRIBUTES_2)(
>
> + EFI_FVB2_READ_ENABLED_CAP | // Reads
> may be enabled
>
> + EFI_FVB2_READ_STATUS | // Reads are
> currently enabled
>
> + EFI_FVB2_STICKY_WRITE | // A block erase
> is required to flip bits into EFI_FVB2_ERASE_POLARITY
>
> + EFI_FVB2_MEMORY_MAPPED | // It is
> memory mapped
>
> + EFI_FVB2_ERASE_POLARITY | // After
> erasure all bits take this value (i.e. '1')
>
> + EFI_FVB2_WRITE_STATUS | // Writes are
> currently enabled
>
> + EFI_FVB2_WRITE_ENABLED_CAP // Writes
> may be enabled
>
> + );
>
> + FirmwareVolumeHeader->HeaderLength = sizeof
> (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY);
>
> + FirmwareVolumeHeader->Revision = EFI_FVH_REVISION;
>
> + FirmwareVolumeHeader->BlockMap[0].NumBlocks = Instance->LastBlock + 1;
>
> + FirmwareVolumeHeader->BlockMap[0].Length = Instance->BlockSize;
>
> + FirmwareVolumeHeader->BlockMap[1].NumBlocks = 0;
>
> + FirmwareVolumeHeader->BlockMap[1].Length = 0;
>
> + FirmwareVolumeHeader->Checksum = CalculateCheckSum16 ((UINT16
> *)FirmwareVolumeHeader, FirmwareVolumeHeader->HeaderLength);
>
> +
>
> + //
>
> + // VARIABLE_STORE_HEADER
>
> + //
>
> + VariableStoreHeader = (VARIABLE_STORE_HEADER *)((UINTN)Headers +
> FirmwareVolumeHeader->HeaderLength);
>
> + CopyGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGuid);
>
> + VariableStoreHeader->Size = PcdGet32 (PcdFlashNvStorageVariableSize) -
> FirmwareVolumeHeader->HeaderLength;
>
> + VariableStoreHeader->Format = VARIABLE_STORE_FORMATTED;
>
> + VariableStoreHeader->State = VARIABLE_STORE_HEALTHY;
>
> +
>
> + // Install the combined super-header in the NorFlash
>
> + Status = FvbWrite (&Instance->FvbProtocol, 0, 0, &HeadersLength, Headers);
>
> +
>
> + FreePool (Headers);
>
> + return Status;
>
> +}
>
> +
>
> +/**
>
> + Check the integrity of firmware volume header.
>
> +
>
> + @param[in] FwVolHeader - A pointer to a firmware volume header
>
> +
>
> + @retval EFI_SUCCESS - The firmware volume is consistent
>
> + @retval EFI_NOT_FOUND - The firmware volume has been corrupted.
>
> +
>
> +**/
>
> +EFI_STATUS
>
> +ValidateFvHeader (
>
> + IN NOR_FLASH_INSTANCE *Instance
>
> + )
>
> +{
>
> + UINT16 Checksum;
>
> + CONST EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader;
>
> + CONST VARIABLE_STORE_HEADER *VariableStoreHeader;
>
> + UINTN VarOffset;
>
> + UINTN VariableStoreLength;
>
> + UINTN FvLength;
>
> +
>
> + FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER *)Instance-
> >RegionBaseAddress;
>
> +
>
> + FvLength = PcdGet32 (PcdFlashNvStorageVariableSize) + PcdGet32
> (PcdFlashNvStorageFtwWorkingSize) +
>
> + PcdGet32 (PcdFlashNvStorageFtwSpareSize);
>
> +
>
> + //
>
> + // Verify the header revision, header signature, length
>
> + // Length of FvBlock cannot be 2**64-1
>
> + // HeaderLength cannot be an odd number
>
> + //
>
> + if ( (FwVolHeader->Revision != EFI_FVH_REVISION)
>
> + || (FwVolHeader->Signature != EFI_FVH_SIGNATURE)
>
> + || (FwVolHeader->FvLength != FvLength)
>
> + )
>
> + {
>
> + DEBUG ((
>
> + DEBUG_INFO,
>
> + "%a: No Firmware Volume header present\n",
>
> + __func__
>
> + ));
>
> + return EFI_NOT_FOUND;
>
> + }
>
> +
>
> + // Check the Firmware Volume Guid
>
> + if ( CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid)
> == FALSE ) {
>
> + DEBUG ((
>
> + DEBUG_INFO,
>
> + "%a: Firmware Volume Guid non-compatible\n",
>
> + __func__
>
> + ));
>
> + return EFI_NOT_FOUND;
>
> + }
>
> +
>
> + // Verify the header checksum
>
> + Checksum = CalculateSum16 ((UINT16 *)FwVolHeader, FwVolHeader-
> >HeaderLength);
>
> + if (Checksum != 0) {
>
> + DEBUG ((
>
> + DEBUG_INFO,
>
> + "%a: FV checksum is invalid (Checksum:0x%X)\n",
>
> + __func__,
>
> + Checksum
>
> + ));
>
> + return EFI_NOT_FOUND;
>
> + }
>
> +
>
> + VariableStoreHeader = (VARIABLE_STORE_HEADER *)((UINTN)FwVolHeader +
> FwVolHeader->HeaderLength);
>
> +
>
> + // Check the Variable Store Guid
>
> + if (!CompareGuid (&VariableStoreHeader->Signature,
> &gEfiAuthenticatedVariableGuid)) {
>
> + DEBUG ((
>
> + DEBUG_INFO,
>
> + "%a: Variable Store Guid non-compatible\n",
>
> + __func__
>
> + ));
>
> + return EFI_NOT_FOUND;
>
> + }
>
> +
>
> + VariableStoreLength = PcdGet32 (PcdFlashNvStorageVariableSize) -
> FwVolHeader->HeaderLength;
>
> + if (VariableStoreHeader->Size != VariableStoreLength) {
>
> + DEBUG ((
>
> + DEBUG_INFO,
>
> + "%a: Variable Store Length does not match\n",
>
> + __func__
>
> + ));
>
> + return EFI_NOT_FOUND;
>
> + }
>
> +
>
> + //
>
> + // check variables
>
> + //
>
> + DEBUG ((DEBUG_INFO, "%a: checking variables\n", __func__));
>
> + VarOffset = sizeof (*VariableStoreHeader);
>
> + for ( ; ;) {
>
> + UINTN VarHeaderEnd;
>
> + UINTN VarNameEnd;
>
> + UINTN VarEnd;
>
> + UINTN VarPadding;
>
> + CONST AUTHENTICATED_VARIABLE_HEADER *VarHeader;
>
> + CONST CHAR16 *VarName;
>
> + CONST CHAR8 *VarState;
>
> + RETURN_STATUS Status;
>
> +
>
> + Status = SafeUintnAdd (VarOffset, sizeof (*VarHeader), &VarHeaderEnd);
>
> + if (RETURN_ERROR (Status)) {
>
> + DEBUG ((DEBUG_ERROR, "%a: integer overflow\n", __func__));
>
> + return EFI_NOT_FOUND;
>
> + }
>
> +
>
> + if (VarHeaderEnd >= VariableStoreHeader->Size) {
>
> + if (VarOffset <= VariableStoreHeader->Size - sizeof (UINT16)) {
>
> + CONST UINT16 *StartId;
>
> +
>
> + StartId = (VOID *)((UINTN)VariableStoreHeader + VarOffset);
>
> + if (*StartId == 0x55aa) {
>
> + DEBUG ((DEBUG_ERROR, "%a: startid at invalid location\n", __func__));
>
> + return EFI_NOT_FOUND;
>
> + }
>
> + }
>
> +
>
> + DEBUG ((DEBUG_INFO, "%a: end of var list (no space left)\n", __func__));
>
> + break;
>
> + }
>
> +
>
> + VarHeader = (VOID *)((UINTN)VariableStoreHeader + VarOffset);
>
> + if (VarHeader->StartId != 0x55aa) {
>
> + DEBUG ((DEBUG_INFO, "%a: end of var list (no startid)\n", __func__));
>
> + break;
>
> + }
>
> +
>
> + if (VarHeader->State == 0xff) {
>
> + DEBUG ((DEBUG_INFO, "%a: end of var list (unwritten state)\n", __func__));
>
> + break;
>
> + }
>
> +
>
> + VarName = NULL;
>
> + switch (VarHeader->State) {
>
> + // usage: State = VAR_HEADER_VALID_ONLY
>
> + case VAR_HEADER_VALID_ONLY:
>
> + VarState = "header-ok";
>
> + VarName = L"<unknown>";
>
> + break;
>
> +
>
> + // usage: State = VAR_ADDED
>
> + case VAR_ADDED:
>
> + VarState = "ok";
>
> + break;
>
> +
>
> + // usage: State &= VAR_IN_DELETED_TRANSITION
>
> + case VAR_ADDED &VAR_IN_DELETED_TRANSITION:
>
> + VarState = "del-in-transition";
>
> + break;
>
> +
>
> + // usage: State &= VAR_DELETED
>
> + case VAR_ADDED &VAR_DELETED:
>
> + case VAR_ADDED &VAR_DELETED &VAR_IN_DELETED_TRANSITION:
>
> + VarState = "deleted";
>
> + break;
>
> +
>
> + default:
>
> + DEBUG ((
>
> + DEBUG_ERROR,
>
> + "%a: invalid variable state: 0x%x\n",
>
> + __func__,
>
> + VarHeader->State
>
> + ));
>
> + return EFI_NOT_FOUND;
>
> + }
>
> +
>
> + Status = SafeUintnAdd (VarHeaderEnd, VarHeader->NameSize,
> &VarNameEnd);
>
> + if (RETURN_ERROR (Status)) {
>
> + DEBUG ((DEBUG_ERROR, "%a: integer overflow\n", __func__));
>
> + return EFI_NOT_FOUND;
>
> + }
>
> +
>
> + Status = SafeUintnAdd (VarNameEnd, VarHeader->DataSize, &VarEnd);
>
> + if (RETURN_ERROR (Status)) {
>
> + DEBUG ((DEBUG_ERROR, "%a: integer overflow\n", __func__));
>
> + return EFI_NOT_FOUND;
>
> + }
>
> +
>
> + if (VarEnd > VariableStoreHeader->Size) {
>
> + DEBUG ((
>
> + DEBUG_ERROR,
>
> + "%a: invalid variable size: 0x%Lx + 0x%Lx + 0x%x + 0x%x > 0x%x\n",
>
> + __func__,
>
> + (UINT64)VarOffset,
>
> + (UINT64)(sizeof (*VarHeader)),
>
> + VarHeader->NameSize,
>
> + VarHeader->DataSize,
>
> + VariableStoreHeader->Size
>
> + ));
>
> + return EFI_NOT_FOUND;
>
> + }
>
> +
>
> + if (((VarHeader->NameSize & 1) != 0) ||
>
> + (VarHeader->NameSize < 4))
>
> + {
>
> + DEBUG ((DEBUG_ERROR, "%a: invalid name size\n", __func__));
>
> + return EFI_NOT_FOUND;
>
> + }
>
> +
>
> + if (VarName == NULL) {
>
> + VarName = (VOID *)((UINTN)VariableStoreHeader + VarHeaderEnd);
>
> + if (VarName[VarHeader->NameSize / 2 - 1] != L'\0') {
>
> + DEBUG ((DEBUG_ERROR, "%a: name is not null terminated\n", __func__));
>
> + return EFI_NOT_FOUND;
>
> + }
>
> + }
>
> +
>
> + DEBUG ((
>
> + DEBUG_VERBOSE,
>
> + "%a: +0x%04Lx: name=0x%x data=0x%x guid=%g '%s' (%a)\n",
>
> + __func__,
>
> + (UINT64)VarOffset,
>
> + VarHeader->NameSize,
>
> + VarHeader->DataSize,
>
> + &VarHeader->VendorGuid,
>
> + VarName,
>
> + VarState
>
> + ));
>
> +
>
> + VarPadding = (4 - (VarEnd & 3)) & 3;
>
> + Status = SafeUintnAdd (VarEnd, VarPadding, &VarOffset);
>
> + if (RETURN_ERROR (Status)) {
>
> + DEBUG ((DEBUG_ERROR, "%a: integer overflow\n", __func__));
>
> + return EFI_NOT_FOUND;
>
> + }
>
> + }
>
> +
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +/**
>
> + The GetAttributes() function retrieves the attributes and
>
> + current settings of the block.
>
> +
>
> + @param This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
> instance.
>
> +
>
> + @param Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes
> and
>
> + current settings are returned.
>
> + Type EFI_FVB_ATTRIBUTES_2 is defined in
> EFI_FIRMWARE_VOLUME_HEADER.
>
> +
>
> + @retval EFI_SUCCESS The firmware volume attributes were returned.
>
> +
>
> + **/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +FvbGetAttributes (
>
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
>
> + OUT EFI_FVB_ATTRIBUTES_2 *Attributes
>
> + )
>
> +{
>
> + EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes;
>
> +
>
> + FlashFvbAttributes = (EFI_FVB_ATTRIBUTES_2)(
>
> +
>
> + EFI_FVB2_READ_ENABLED_CAP | // Reads may be
> enabled
>
> + EFI_FVB2_READ_STATUS | // Reads are currently
> enabled
>
> + EFI_FVB2_STICKY_WRITE | // A block erase is
> required to flip bits into EFI_FVB2_ERASE_POLARITY
>
> + EFI_FVB2_MEMORY_MAPPED | // It is memory
> mapped
>
> + EFI_FVB2_ERASE_POLARITY | // After erasure all bits
> take this value (i.e. '1')
>
> + EFI_FVB2_WRITE_STATUS | // Writes are currently
> enabled
>
> + EFI_FVB2_WRITE_ENABLED_CAP // Writes may be
> enabled
>
> +
>
> + );
>
> +
>
> + *Attributes = FlashFvbAttributes;
>
> +
>
> + DEBUG ((DEBUG_BLKIO, "FvbGetAttributes(0x%X)\n", *Attributes));
>
> +
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +/**
>
> + The SetAttributes() function sets configurable firmware volume attributes
>
> + and returns the new settings of the firmware volume.
>
> +
>
> +
>
> + @param This Indicates the
> EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
>
> +
>
> + @param Attributes On input, Attributes is a pointer to
> EFI_FVB_ATTRIBUTES_2
>
> + that contains the desired firmware volume settings.
>
> + On successful return, it contains the new settings of
>
> + the firmware volume.
>
> + Type EFI_FVB_ATTRIBUTES_2 is defined in
> EFI_FIRMWARE_VOLUME_HEADER.
>
> +
>
> + @retval EFI_SUCCESS The firmware volume attributes were returned.
>
> +
>
> + @retval EFI_INVALID_PARAMETER The attributes requested are in conflict
> with the capabilities
>
> + as declared in the firmware volume header.
>
> +
>
> + **/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +FvbSetAttributes (
>
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
>
> + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
>
> + )
>
> +{
>
> + DEBUG ((DEBUG_BLKIO, "FvbSetAttributes(0x%X) is not supported\n",
> *Attributes));
>
> + return EFI_UNSUPPORTED;
>
> +}
>
> +
>
> +/**
>
> + The GetPhysicalAddress() function retrieves the base address of
>
> + a memory-mapped firmware volume. This function should be called
>
> + only for memory-mapped firmware volumes.
>
> +
>
> + @param This Indicates the
> EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
>
> +
>
> + @param Address Pointer to a caller-allocated
>
> + EFI_PHYSICAL_ADDRESS that, on successful
>
> + return from GetPhysicalAddress(), contains the
>
> + base address of the firmware volume.
>
> +
>
> + @retval EFI_SUCCESS The firmware volume base address was returned.
>
> +
>
> + @retval EFI_NOT_SUPPORTED The firmware volume is not memory mapped.
>
> +
>
> + **/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +FvbGetPhysicalAddress (
>
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
>
> + OUT EFI_PHYSICAL_ADDRESS *Address
>
> + )
>
> +{
>
> + NOR_FLASH_INSTANCE *Instance;
>
> +
>
> + Instance = INSTANCE_FROM_FVB_THIS (This);
>
> +
>
> + DEBUG ((DEBUG_BLKIO, "FvbGetPhysicalAddress(BaseAddress=0x%08x)\n",
> Instance->RegionBaseAddress));
>
> +
>
> + ASSERT (Address != NULL);
>
> +
>
> + *Address = mFlashNvStorageVariableBase;
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +/**
>
> + The GetBlockSize() function retrieves the size of the requested
>
> + block. It also returns the number of additional blocks with
>
> + the identical size. The GetBlockSize() function is used to
>
> + retrieve the block map (see EFI_FIRMWARE_VOLUME_HEADER).
>
> +
>
> +
>
> + @param This Indicates the
> EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
>
> +
>
> + @param Lba Indicates the block for which to return the size.
>
> +
>
> + @param BlockSize Pointer to a caller-allocated UINTN in which
>
> + the size of the block is returned.
>
> +
>
> + @param NumberOfBlocks Pointer to a caller-allocated UINTN in
>
> + which the number of consecutive blocks,
>
> + starting with Lba, is returned. All
>
> + blocks in this range have a size of
>
> + BlockSize.
>
> +
>
> +
>
> + @retval EFI_SUCCESS The firmware volume base address was returned.
>
> +
>
> + @retval EFI_INVALID_PARAMETER The requested LBA is out of range.
>
> +
>
> + **/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +FvbGetBlockSize (
>
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
>
> + IN EFI_LBA Lba,
>
> + OUT UINTN *BlockSize,
>
> + OUT UINTN *NumberOfBlocks
>
> + )
>
> +{
>
> + EFI_STATUS Status;
>
> + NOR_FLASH_INSTANCE *Instance;
>
> +
>
> + Instance = INSTANCE_FROM_FVB_THIS (This);
>
> +
>
> + DEBUG ((DEBUG_BLKIO, "FvbGetBlockSize(Lba=%ld, BlockSize=0x%x,
> LastBlock=%ld)\n", Lba, Instance->BlockSize, Instance->LastBlock));
>
> +
>
> + if (Lba > Instance->LastBlock) {
>
> + DEBUG ((DEBUG_ERROR, "FvbGetBlockSize: ERROR - Parameter LBA %ld is
> beyond the last Lba (%ld).\n", Lba, Instance->LastBlock));
>
> + Status = EFI_INVALID_PARAMETER;
>
> + } else {
>
> + // This is easy because in this platform each NorFlash device has equal sized
> blocks.
>
> + *BlockSize = (UINTN)Instance->BlockSize;
>
> + *NumberOfBlocks = (UINTN)(Instance->LastBlock - Lba + 1);
>
> +
>
> + DEBUG ((DEBUG_BLKIO, "FvbGetBlockSize: *BlockSize=0x%x,
> *NumberOfBlocks=0x%x.\n", *BlockSize, *NumberOfBlocks));
>
> +
>
> + Status = EFI_SUCCESS;
>
> + }
>
> +
>
> + return Status;
>
> +}
>
> +
>
> +/**
>
> + Reads the specified number of bytes into a buffer from the specified block.
>
> +
>
> + The Read() function reads the requested number of bytes from the
>
> + requested block and stores them in the provided buffer.
>
> + Implementations should be mindful that the firmware volume
>
> + might be in the ReadDisabled state. If it is in this state,
>
> + the Read() function must return the status code
>
> + EFI_ACCESS_DENIED without modifying the contents of the
>
> + buffer. The Read() function must also prevent spanning block
>
> + boundaries. If a read is requested that would span a block
>
> + boundary, the read must read up to the boundary but not
>
> + beyond. The output parameter NumBytes must be set to correctly
>
> + indicate the number of bytes actually read. The caller must be
>
> + aware that a read may be partially completed.
>
> +
>
> + @param This Indicates the
> EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
>
> +
>
> + @param Lba The starting logical block index from which to read.
>
> +
>
> + @param Offset Offset into the block at which to begin reading.
>
> +
>
> + @param NumBytes Pointer to a UINTN.
>
> + At entry, *NumBytes contains the total size of the buffer.
>
> + At exit, *NumBytes contains the total number of bytes read.
>
> +
>
> + @param Buffer Pointer to a caller-allocated buffer that will be used
>
> + to hold the data that is read.
>
> +
>
> + @retval EFI_SUCCESS The firmware volume was read successfully, and
> contents are
>
> + in Buffer.
>
> +
>
> + @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary.
>
> + On output, NumBytes contains the total number of bytes
>
> + returned in Buffer.
>
> +
>
> + @retval EFI_ACCESS_DENIED The firmware volume is in the ReadDisabled
> state.
>
> +
>
> + @retval EFI_DEVICE_ERROR The block device is not functioning correctly and
> could not be read.
>
> +
>
> + **/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +FvbRead (
>
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
>
> + IN EFI_LBA Lba,
>
> + IN UINTN Offset,
>
> + IN OUT UINTN *NumBytes,
>
> + IN OUT UINT8 *Buffer
>
> + )
>
> +{
>
> + EFI_STATUS TempStatus;
>
> + UINTN BlockSize;
>
> + NOR_FLASH_INSTANCE *Instance;
>
> +
>
> + Instance = INSTANCE_FROM_FVB_THIS (This);
>
> +
>
> + DEBUG ((DEBUG_BLKIO, "FvbRead(Parameters: Lba=%ld, Offset=0x%x,
> *NumBytes=0x%x, Buffer @ 0x%08x)\n", Instance->StartLba + Lba, Offset,
> *NumBytes, Buffer));
>
> +
>
> + TempStatus = EFI_SUCCESS;
>
> +
>
> + // Cache the block size to avoid de-referencing pointers all the time
>
> + BlockSize = Instance->BlockSize;
>
> +
>
> + DEBUG ((DEBUG_BLKIO, "FvbRead: Check if (Offset=0x%x + NumBytes=0x%x)
> <= BlockSize=0x%x\n", Offset, *NumBytes, BlockSize));
>
> +
>
> + // The read must not span block boundaries.
>
> + // We need to check each variable individually because adding two large values
> together overflows.
>
> + if ((Offset >= BlockSize) ||
>
> + (*NumBytes > BlockSize) ||
>
> + ((Offset + *NumBytes) > BlockSize))
>
> + {
>
> + DEBUG ((DEBUG_ERROR, "FvbRead: ERROR - EFI_BAD_BUFFER_SIZE:
> (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", Offset, *NumBytes,
> BlockSize));
>
> + return EFI_BAD_BUFFER_SIZE;
>
> + }
>
> +
>
> + // We must have some bytes to read
>
> + if (*NumBytes == 0) {
>
> + return EFI_BAD_BUFFER_SIZE;
>
> + }
>
> +
>
> + // Decide if we are doing full block reads or not.
>
> + if (*NumBytes % BlockSize != 0) {
>
> + TempStatus = NorFlashRead (Instance, Instance->StartLba + Lba, Offset,
> *NumBytes, Buffer);
>
> + if (EFI_ERROR (TempStatus)) {
>
> + return EFI_DEVICE_ERROR;
>
> + }
>
> + } else {
>
> + // Read NOR Flash data into shadow buffer
>
> + TempStatus = NorFlashReadBlocks (Instance, Instance->StartLba + Lba,
> BlockSize, Buffer);
>
> + if (EFI_ERROR (TempStatus)) {
>
> + // Return one of the pre-approved error statuses
>
> + return EFI_DEVICE_ERROR;
>
> + }
>
> + }
>
> +
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
> +/**
>
> + Writes the specified number of bytes from the input buffer to the block.
>
> +
>
> + The Write() function writes the specified number of bytes from
>
> + the provided buffer to the specified block and offset. If the
>
> + firmware volume is sticky write, the caller must ensure that
>
> + all the bits of the specified range to write are in the
>
> + EFI_FVB_ERASE_POLARITY state before calling the Write()
>
> + function, or else the result will be unpredictable. This
>
> + unpredictability arises because, for a sticky-write firmware
>
> + volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY
>
> + state but cannot flip it back again. Before calling the
>
> + Write() function, it is recommended for the caller to first call
>
> + the EraseBlocks() function to erase the specified block to
>
> + write. A block erase cycle will transition bits from the
>
> + (NOT)EFI_FVB_ERASE_POLARITY state back to the
>
> + EFI_FVB_ERASE_POLARITY state. Implementations should be
>
> + mindful that the firmware volume might be in the WriteDisabled
>
> + state. If it is in this state, the Write() function must
>
> + return the status code EFI_ACCESS_DENIED without modifying the
>
> + contents of the firmware volume. The Write() function must
>
> + also prevent spanning block boundaries. If a write is
>
> + requested that spans a block boundary, the write must store up
>
> + to the boundary but not beyond. The output parameter NumBytes
>
> + must be set to correctly indicate the number of bytes actually
>
> + written. The caller must be aware that a write may be
>
> + partially completed. All writes, partial or otherwise, must be
>
> + fully flushed to the hardware before the Write() service
>
> + returns.
>
> +
>
> + @param This Indicates the
> EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
>
> +
>
> + @param Lba The starting logical block index to write to.
>
> +
>
> + @param Offset Offset into the block at which to begin writing.
>
> +
>
> + @param NumBytes The pointer to a UINTN.
>
> + At entry, *NumBytes contains the total size of the buffer.
>
> + At exit, *NumBytes contains the total number of bytes actually
> written.
>
> +
>
> + @param Buffer The pointer to a caller-allocated buffer that contains the
> source for the write.
>
> +
>
> + @retval EFI_SUCCESS The firmware volume was written successfully.
>
> +
>
> + @retval EFI_BAD_BUFFER_SIZE The write was attempted across an LBA
> boundary.
>
> + On output, NumBytes contains the total number of bytes
>
> + actually written.
>
> +
>
> + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled
> state.
>
> +
>
> + @retval EFI_DEVICE_ERROR The block device is malfunctioning and could not
> be written.
>
> +
>
> +
>
> + **/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +FvbWrite (
>
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
>
> + IN EFI_LBA Lba,
>
> + IN UINTN Offset,
>
> + IN OUT UINTN *NumBytes,
>
> + IN UINT8 *Buffer
>
> + )
>
> +{
>
> + NOR_FLASH_INSTANCE *Instance;
>
> +
>
> + Instance = INSTANCE_FROM_FVB_THIS (This);
>
> +
>
> + return NorFlashWriteSingleBlock (Instance, Instance->StartLba + Lba, Offset,
> NumBytes, Buffer);
>
> +}
>
> +
>
> +/**
>
> + Erases and initialises a firmware volume block.
>
> +
>
> + The EraseBlocks() function erases one or more blocks as denoted
>
> + by the variable argument list. The entire parameter list of
>
> + blocks must be verified before erasing any blocks. If a block is
>
> + requested that does not exist within the associated firmware
>
> + volume (it has a larger index than the last block of the
>
> + firmware volume), the EraseBlocks() function must return the
>
> + status code EFI_INVALID_PARAMETER without modifying the contents
>
> + of the firmware volume. Implementations should be mindful that
>
> + the firmware volume might be in the WriteDisabled state. If it
>
> + is in this state, the EraseBlocks() function must return the
>
> + status code EFI_ACCESS_DENIED without modifying the contents of
>
> + the firmware volume. All calls to EraseBlocks() must be fully
>
> + flushed to the hardware before the EraseBlocks() service
>
> + returns.
>
> +
>
> + @param This Indicates the
> EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
>
> + instance.
>
> +
>
> + @param ... The variable argument list is a list of tuples.
>
> + Each tuple describes a range of LBAs to erase
>
> + and consists of the following:
>
> + - An EFI_LBA that indicates the starting LBA
>
> + - A UINTN that indicates the number of blocks to erase.
>
> +
>
> + The list is terminated with an EFI_LBA_LIST_TERMINATOR.
>
> + For example, the following indicates that two ranges of blocks
>
> + (5-7 and 10-11) are to be erased:
>
> + EraseBlocks (This, 5, 3, 10, 2, EFI_LBA_LIST_TERMINATOR);
>
> +
>
> + @retval EFI_SUCCESS The erase request successfully completed.
>
> +
>
> + @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled
> state.
>
> +
>
> + @retval EFI_DEVICE_ERROR The block device is not functioning correctly
> and could not be written.
>
> + The firmware device may have been partially erased.
>
> +
>
> + @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the
> variable argument list do
>
> + not exist in the firmware volume.
>
> +
>
> + **/
>
> +EFI_STATUS
>
> +EFIAPI
>
> +FvbEraseBlocks (
>
> + IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
>
> + ...
>
> + )
>
> +{
>
> + EFI_STATUS Status;
>
> + VA_LIST Args;
>
> + UINTN BlockAddress; // Physical address of Lba to erase
>
> + EFI_LBA StartingLba; // Lba from which we start erasing
>
> + UINTN NumOfLba; // Number of Lba blocks to erase
>
> + NOR_FLASH_INSTANCE *Instance;
>
> +
>
> + Instance = INSTANCE_FROM_FVB_THIS (This);
>
> +
>
> + DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks()\n"));
>
> +
>
> + Status = EFI_SUCCESS;
>
> +
>
> + // Before erasing, check the entire list of parameters to ensure all specified
> blocks are valid
>
> +
>
> + VA_START (Args, This);
>
> + do {
>
> + // Get the Lba from which we start erasing
>
> + StartingLba = VA_ARG (Args, EFI_LBA);
>
> +
>
> + // Have we reached the end of the list?
>
> + if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
>
> + // Exit the while loop
>
> + break;
>
> + }
>
> +
>
> + // How many Lba blocks are we requested to erase?
>
> + NumOfLba = VA_ARG (Args, UINTN);
>
> +
>
> + // All blocks must be within range
>
> + DEBUG ((
>
> + DEBUG_BLKIO,
>
> + "FvbEraseBlocks: Check if: ( StartingLba=%ld + NumOfLba=%Lu - 1 ) >
> LastBlock=%ld.\n",
>
> + Instance->StartLba + StartingLba,
>
> + (UINT64)NumOfLba,
>
> + Instance->LastBlock
>
> + ));
>
> + if ((NumOfLba == 0) || ((Instance->StartLba + StartingLba + NumOfLba - 1) >
> Instance->LastBlock)) {
>
> + VA_END (Args);
>
> + DEBUG ((DEBUG_ERROR, "FvbEraseBlocks: ERROR - Lba range goes past the
> last Lba.\n"));
>
> + Status = EFI_INVALID_PARAMETER;
>
> + goto EXIT;
>
> + }
>
> + } while (TRUE);
>
> +
>
> + VA_END (Args);
>
> +
>
> + //
>
> + // To get here, all must be ok, so start erasing
>
> + //
>
> + VA_START (Args, This);
>
> + do {
>
> + // Get the Lba from which we start erasing
>
> + StartingLba = VA_ARG (Args, EFI_LBA);
>
> +
>
> + // Have we reached the end of the list?
>
> + if (StartingLba == EFI_LBA_LIST_TERMINATOR) {
>
> + // Exit the while loop
>
> + break;
>
> + }
>
> +
>
> + // How many Lba blocks are we requested to erase?
>
> + NumOfLba = VA_ARG (Args, UINTN);
>
> +
>
> + // Go through each one and erase it
>
> + while (NumOfLba > 0) {
>
> + // Get the physical address of Lba to erase
>
> + BlockAddress = GET_NOR_BLOCK_ADDRESS (
>
> + Instance->RegionBaseAddress,
>
> + Instance->StartLba + StartingLba,
>
> + Instance->BlockSize
>
> + );
>
> +
>
> + // Erase it
>
> + DEBUG ((DEBUG_BLKIO, "FvbEraseBlocks: Erasing Lba=%ld @ 0x%08x.\n",
> Instance->StartLba + StartingLba, BlockAddress));
>
> + Status = NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress);
>
> + if (EFI_ERROR (Status)) {
>
> + VA_END (Args);
>
> + Status = EFI_DEVICE_ERROR;
>
> + goto EXIT;
>
> + }
>
> +
>
> + // Move to the next Lba
>
> + StartingLba++;
>
> + NumOfLba--;
>
> + }
>
> + } while (TRUE);
>
> +
>
> + VA_END (Args);
>
> +
>
> +EXIT:
>
> + return Status;
>
> +}
>
> +
>
> +/**
>
> + Fixup internal data so that EFI can be call in virtual mode.
>
> + Call the passed in Child Notify event and convert any pointers in
>
> + lib to virtual mode.
>
> +
>
> + @param[in] Event The Event that is being processed
>
> + @param[in] Context Event Context
>
> +**/
>
> +VOID
>
> +EFIAPI
>
> +FvbVirtualNotifyEvent (
>
> + IN EFI_EVENT Event,
>
> + IN VOID *Context
>
> + )
>
> +{
>
> + EfiConvertPointer (0x0, (VOID **)&mFlashNvStorageVariableBase);
>
> + return;
>
> +}
>
> --
> 2.34.1
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