From: "Andrei Warkentin" <andrei.warkentin@intel.com>
To: Tuan Phan <tphan@ventanamicro.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Kinney, Michael D" <michael.d.kinney@intel.com>,
"Gao, Liming" <gaoliming@byosoft.com.cn>,
"Liu, Zhiguang" <zhiguang.liu@intel.com>,
"sunilvl@ventanamicro.com" <sunilvl@ventanamicro.com>,
"git@danielschaefer.me" <git@danielschaefer.me>,
"ardb+tianocore@kernel.org" <ardb+tianocore@kernel.org>
Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
Date: Wed, 4 Oct 2023 18:48:10 +0000 [thread overview]
Message-ID: <PH8PR11MB6856276AF9E803EFE78E85A283CBA@PH8PR11MB6856.namprd11.prod.outlook.com> (raw)
In-Reply-To: <PH7PR10MB6335595206FF79241444004BA7CBA@PH7PR10MB6335.namprd10.prod.outlook.com>
[-- Attachment #1: Type: text/plain, Size: 5773 bytes --]
Looks good to me.
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
From: Tuan Phan <tphan@ventanamicro.com>
Sent: Wednesday, October 4, 2023 1:44 PM
To: devel@edk2.groups.io; Warkentin, Andrei <andrei.warkentin@intel.com>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>; sunilvl@ventanamicro.com; git@danielschaefer.me; ardb+tianocore@kernel.org
Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
https://github.com/pttuan/edk2.git
branch: tphan/riscv_mmu_new_pcd
From: devel@edk2.groups.io<mailto:devel@edk2.groups.io> <devel@edk2.groups.io<mailto:devel@edk2.groups.io>> on behalf of Andrei Warkentin <andrei.warkentin@intel.com<mailto:andrei.warkentin@intel.com>>
Date: Wednesday, October 4, 2023 at 11:42 AM
To: Tuan Phan <tphan@ventanamicro.com<mailto:tphan@ventanamicro.com>>, devel@edk2.groups.io<mailto:devel@edk2.groups.io> <devel@edk2.groups.io<mailto:devel@edk2.groups.io>>
Cc: Kinney, Michael D <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>, Gao, Liming <gaoliming@byosoft.com.cn<mailto:gaoliming@byosoft.com.cn>>, Liu, Zhiguang <zhiguang.liu@intel.com<mailto:zhiguang.liu@intel.com>>, sunilvl@ventanamicro.com<mailto:sunilvl@ventanamicro.com> <sunilvl@ventanamicro.com<mailto:sunilvl@ventanamicro.com>>, git@danielschaefer.me<mailto:git@danielschaefer.me> <git@danielschaefer.me<mailto:git@danielschaefer.me>>, ardb+tianocore@kernel.org<mailto:ardb+tianocore@kernel.org> <ardb+tianocore@kernel.org<mailto:ardb+tianocore@kernel.org>>
Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
Do you happen to have a link to a Github tree?
A
> -----Original Message-----
> From: Tuan Phan <tphan@ventanamicro.com<mailto:tphan@ventanamicro.com>>
> Sent: Tuesday, October 3, 2023 4:00 PM
> To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>
> Cc: Kinney, Michael D <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>; Gao, Liming
> <gaoliming@byosoft.com.cn<mailto:gaoliming@byosoft.com.cn>>; Liu, Zhiguang <zhiguang.liu@intel.com<mailto:zhiguang.liu@intel.com>>;
> sunilvl@ventanamicro.com<mailto:sunilvl@ventanamicro.com>; git@danielschaefer.me<mailto:git@danielschaefer.me>; Warkentin, Andrei
> <andrei.warkentin@intel.com<mailto:andrei.warkentin@intel.com>>; ardb+tianocore@kernel.org<mailto:ardb+tianocore@kernel.org>; Tuan Phan
> <tphan@ventanamicro.com<mailto:tphan@ventanamicro.com>>
> Subject: [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
>
> Introduce a PCD to control the maximum SATP mode that MMU allowed to
> use. This PCD helps RISC-V platform set bare or minimum SATA mode during
> bring up to debug memory map issue.
>
> Signed-off-by: Tuan Phan <tphan@ventanamicro.com<mailto:tphan@ventanamicro.com>>
> ---
> UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 +++++-
> UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++
> UefiCpuPkg/UefiCpuPkg.dec | 8 ++++++++
> 3 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> index 9cca5fc128af..826a1d32a1d4 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> @@ -36,7 +36,7 @@
> #define PTE_PPN_SHIFT 10 #define RISCV_MMU_PAGE_SHIFT 12 -
> STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48,
> SATP_MODE_SV39 };+STATIC UINTN mModeSupport[] = { SATP_MODE_SV57,
> SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF }; STATIC UINTN
> mMaxRootTableLevel; STATIC UINTN mBitPerLevel; STATIC UINTN
> mTableEntryCount;@@ -590,6 +590,10 @@ RiscVMmuSetSatpMode (
> UINTN Index; EFI_STATUS Status; + if
> (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {+ return
> EFI_DEVICE_ERROR;+ }+ switch (SatpMode) { case SATP_MODE_OFF:
> return EFI_SUCCESS;diff --git
> a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> index 9b28a98cb346..51ebe1750e97 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> @@ -25,3 +25,6 @@
> [LibraryClasses] BaseLib++[Pcd]+
> gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ##
> CONSUMESdiff --git a/UefiCpuPkg/UefiCpuPkg.dec
> b/UefiCpuPkg/UefiCpuPkg.dec
> index 68473fc640e6..79191af18a05 100644
> --- a/UefiCpuPkg/UefiCpuPkg.dec
> +++ b/UefiCpuPkg/UefiCpuPkg.dec
> @@ -396,6 +396,14 @@
> # @Prompt Access to non-SMRAM memory is restricted to reserved,
> runtime and ACPI NVS type after SmmReadyToLock.
> gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|B
> OOLEAN|0x3213210F +[PcdsFixedAtBuild.RISCV64]+ ## Indicate the
> maximum SATP mode allowed.+ # 0 - Bare mode.+ # 8 - 39bit mode.+ # 9 -
> 48bit mode.+ # 10 - 57bit mode.+
> gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0|UINT32|0x6
> 0000021+ [PcdsDynamic, PcdsDynamicEx] ## Contains the pointer to a CPU
> S3 data buffer of structure ACPI_CPU_DATA. # @Prompt The pointer to a CPU
> S3 data buffer.--
> 2.25.1
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prev parent reply other threads:[~2023-10-04 18:48 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-03 21:00 [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode Tuan Phan
2023-10-04 4:24 ` Dhaval Sharma
2023-10-04 11:36 ` Sunil V L
2023-10-04 15:27 ` Tuan Phan
2023-10-04 18:41 ` Andrei Warkentin
2023-10-04 18:43 ` Tuan Phan
2023-10-04 18:48 ` Andrei Warkentin [this message]
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