Looks good to me. Reviewed-by: Andrei Warkentin From: Tuan Phan Sent: Wednesday, October 4, 2023 1:44 PM To: devel@edk2.groups.io; Warkentin, Andrei Cc: Kinney, Michael D ; Gao, Liming ; Liu, Zhiguang ; sunilvl@ventanamicro.com; git@danielschaefer.me; ardb+tianocore@kernel.org Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode https://github.com/pttuan/edk2.git branch: tphan/riscv_mmu_new_pcd From: devel@edk2.groups.io > on behalf of Andrei Warkentin > Date: Wednesday, October 4, 2023 at 11:42 AM To: Tuan Phan >, devel@edk2.groups.io > Cc: Kinney, Michael D >, Gao, Liming >, Liu, Zhiguang >, sunilvl@ventanamicro.com >, git@danielschaefer.me >, ardb+tianocore@kernel.org > Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode Do you happen to have a link to a Github tree? A > -----Original Message----- > From: Tuan Phan > > Sent: Tuesday, October 3, 2023 4:00 PM > To: devel@edk2.groups.io > Cc: Kinney, Michael D >; Gao, Liming > >; Liu, Zhiguang >; > sunilvl@ventanamicro.com; git@danielschaefer.me; Warkentin, Andrei > >; ardb+tianocore@kernel.org; Tuan Phan > > > Subject: [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode > > Introduce a PCD to control the maximum SATP mode that MMU allowed to > use. This PCD helps RISC-V platform set bare or minimum SATA mode during > bring up to debug memory map issue. > > Signed-off-by: Tuan Phan > > --- > UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 +++++- > UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++ > UefiCpuPkg/UefiCpuPkg.dec | 8 ++++++++ > 3 files changed, 16 insertions(+), 1 deletion(-) > > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > index 9cca5fc128af..826a1d32a1d4 100644 > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > @@ -36,7 +36,7 @@ > #define PTE_PPN_SHIFT 10 #define RISCV_MMU_PAGE_SHIFT 12 - > STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, > SATP_MODE_SV39 };+STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, > SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF }; STATIC UINTN > mMaxRootTableLevel; STATIC UINTN mBitPerLevel; STATIC UINTN > mTableEntryCount;@@ -590,6 +590,10 @@ RiscVMmuSetSatpMode ( > UINTN Index; EFI_STATUS Status; + if > (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {+ return > EFI_DEVICE_ERROR;+ }+ switch (SatpMode) { case SATP_MODE_OFF: > return EFI_SUCCESS;diff --git > a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > index 9b28a98cb346..51ebe1750e97 100644 > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > @@ -25,3 +25,6 @@ > [LibraryClasses] BaseLib++[Pcd]+ > gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ## > CONSUMESdiff --git a/UefiCpuPkg/UefiCpuPkg.dec > b/UefiCpuPkg/UefiCpuPkg.dec > index 68473fc640e6..79191af18a05 100644 > --- a/UefiCpuPkg/UefiCpuPkg.dec > +++ b/UefiCpuPkg/UefiCpuPkg.dec > @@ -396,6 +396,14 @@ > # @Prompt Access to non-SMRAM memory is restricted to reserved, > runtime and ACPI NVS type after SmmReadyToLock. > gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|B > OOLEAN|0x3213210F +[PcdsFixedAtBuild.RISCV64]+ ## Indicate the > maximum SATP mode allowed.+ # 0 - Bare mode.+ # 8 - 39bit mode.+ # 9 - > 48bit mode.+ # 10 - 57bit mode.+ > gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0|UINT32|0x6 > 0000021+ [PcdsDynamic, PcdsDynamicEx] ## Contains the pointer to a CPU > S3 data buffer of structure ACPI_CPU_DATA. # @Prompt The pointer to a CPU > S3 data buffer.-- > 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109334): https://edk2.groups.io/g/devel/message/109334 Mute This Topic: https://groups.io/mt/101742937/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-