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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,andrei.warkentin@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: BD3ZsWVRcf07x6jY4h5EBi5Qx7686176AA= Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_PH8PR11MB6856276AF9E803EFE78E85A283CBAPH8PR11MB6856namp_" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=HDLI8s3A; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") --_000_PH8PR11MB6856276AF9E803EFE78E85A283CBAPH8PR11MB6856namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Looks good to me. Reviewed-by: Andrei Warkentin From: Tuan Phan Sent: Wednesday, October 4, 2023 1:44 PM To: devel@edk2.groups.io; Warkentin, Andrei Cc: Kinney, Michael D ; Gao, Liming ; Liu, Zhiguang ; sunilvl@ventanamic= ro.com; git@danielschaefer.me; ardb+tianocore@kernel.org Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD = for SATP mode https://github.com/pttuan/edk2.git branch: tphan/riscv_mmu_new_pcd From: devel@edk2.groups.io > on behalf of Andrei Warkentin > Date: Wednesday, October 4, 2023 at 11:42 AM To: Tuan Phan >, deve= l@edk2.groups.io > Cc: Kinney, Michael D >, Gao, Liming >, Liu, Zhiguang >, sunilvl@ventanamicro.com >, git@danielschaefer.me >, ardb+tianocore@kernel.org > Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD = for SATP mode Do you happen to have a link to a Github tree? A > -----Original Message----- > From: Tuan Phan > > Sent: Tuesday, October 3, 2023 4:00 PM > To: devel@edk2.groups.io > Cc: Kinney, Michael D >; Gao, Liming > >; Liu, Zhiguan= g >; > sunilvl@ventanamicro.com; git@danielscha= efer.me; Warkentin, Andrei > >; ardb+tia= nocore@kernel.org; Tuan Phan > > > Subject: [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode > > Introduce a PCD to control the maximum SATP mode that MMU allowed to > use. This PCD helps RISC-V platform set bare or minimum SATA mode during > bring up to debug memory map issue. > > Signed-off-by: Tuan Phan > > --- > UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 +++++- > UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++ > UefiCpuPkg/UefiCpuPkg.dec | 8 ++++++++ > 3 files changed, 16 insertions(+), 1 deletion(-) > > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > index 9cca5fc128af..826a1d32a1d4 100644 > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > @@ -36,7 +36,7 @@ > #define PTE_PPN_SHIFT 10 #define RISCV_MMU_PAGE_SHIFT 12 - > STATIC UINTN mModeSupport[] =3D { SATP_MODE_SV57, SATP_MODE_SV48, > SATP_MODE_SV39 };+STATIC UINTN mModeSupport[] =3D { SATP_MODE_SV57, > SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF }; STATIC UINTN > mMaxRootTableLevel; STATIC UINTN mBitPerLevel; STATIC UINTN > mTableEntryCount;@@ -590,6 +590,10 @@ RiscVMmuSetSatpMode ( > UINTN Index; EFI_STATUS = Status; + if > (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {+ return > EFI_DEVICE_ERROR;+ }+ switch (SatpMode) { case SATP_MODE_OFF: > return EFI_SUCCESS;diff --git > a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > index 9b28a98cb346..51ebe1750e97 100644 > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > @@ -25,3 +25,6 @@ > [LibraryClasses] BaseLib++[Pcd]+ > gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ## > CONSUMESdiff --git a/UefiCpuPkg/UefiCpuPkg.dec > b/UefiCpuPkg/UefiCpuPkg.dec > index 68473fc640e6..79191af18a05 100644 > --- a/UefiCpuPkg/UefiCpuPkg.dec > +++ b/UefiCpuPkg/UefiCpuPkg.dec > @@ -396,6 +396,14 @@ > # @Prompt Access to non-SMRAM memory is restricted to reserved, > runtime and ACPI NVS type after SmmReadyToLock. > gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|B > OOLEAN|0x3213210F +[PcdsFixedAtBuild.RISCV64]+ ## Indicate the > maximum SATP mode allowed.+ # 0 - Bare mode.+ # 8 - 39bit mode.+ # = 9 - > 48bit mode.+ # 10 - 57bit mode.+ > gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0|UINT32|0x6 > 0000021+ [PcdsDynamic, PcdsDynamicEx] ## Contains the pointer to a CPU > S3 data buffer of structure ACPI_CPU_DATA. # @Prompt The pointer to a C= PU > S3 data buffer.-- > 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109334): https://edk2.groups.io/g/devel/message/109334 Mute This Topic: https://groups.io/mt/101742937/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --_000_PH8PR11MB6856276AF9E803EFE78E85A283CBAPH8PR11MB6856namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Looks good to me.

 

Reviewed-by: Andrei= Warkentin <andrei.warkentin@intel.com>

 

 

From:= Tuan Phan <tphan@ventanamicro.com>
Sent: Wednesday, October 4, 2023 1:44 PM
To: devel@edk2.groups.io; Warkentin, Andrei <andrei.warkentin@int= el.com>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Limin= g <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.co= m>; sunilvl@ventanamicro.com; git@danielschaefer.me; ardb+tianocore@kern= el.org
Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce= a PCD for SATP mode

 

https://github.com/pttuan/edk2.git

branch: tphan/riscv= _mmu_new_pcd

 

Do you happen to have a link to a Github tree?

A

> -----Original Message-----
> From: Tuan Phan <tphan@ve= ntanamicro.com>
> Sent: Tuesday, October 3, 2023 4:00 PM
> To: devel@edk2.groups.io > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> <gaoliming@byosoft.com.= cn>; Liu, Zhiguang <zhi= guang.liu@intel.com>;
> sunilvl@ventanamicro.com; git@danielschaefer.me; Warkentin, Andrei
> <andrei.warkentin@int= el.com>; ardb+tianocore@kernel.org; Tuan Phan
> <tphan@ventanamicro.com>
> Subject: [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mod= e
>
> Introduce a PCD to control the maximum SATP mode that MMU allowed to > use. This PCD helps RISC-V platform set bare or minimum SATA mode duri= ng
> bring up to debug memory map issue.
>
> Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> ---
>  UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c  = | 6 +++++-
>  UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++ >  UefiCpuPkg/UefiCpuPkg.dec      &nb= sp;            =            | 8 ++++++++ >  3 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> index 9cca5fc128af..826a1d32a1d4 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> @@ -36,7 +36,7 @@
>  #define PTE_PPN_SHIFT       &= nbsp; 10 #define RISCV_MMU_PAGE_SHIFT  12 -
> STATIC UINTN  mModeSupport[] =3D { SATP_MODE_SV57, SATP_MODE_SV48= ,
> SATP_MODE_SV39 };+STATIC UINTN  mModeSupport[] =3D { SATP_MODE_SV= 57,
> SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF }; STATIC UINTN
> mMaxRootTableLevel; STATIC UINTN  mBitPerLevel; STATIC UINTN
> mTableEntryCount;@@ -590,6 +590,10 @@ RiscVMmuSetSatpMode  (
>    UINTN        = ;            &n= bsp;       Index;   EFI_STATUS = ;            &n= bsp;         Status; +  if
> (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {+  &nb= sp; return
> EFI_DEVICE_ERROR;+  }+   switch (SatpMode) {  = ;   case SATP_MODE_OFF:
> return EFI_SUCCESS;diff --git
> a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> index 9b28a98cb346..51ebe1750e97 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> @@ -25,3 +25,6 @@
>   [LibraryClasses]   BaseLib++[Pcd]+
> gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode  ##
> CONSUMESdiff --git a/UefiCpuPkg/UefiCpuPkg.dec
> b/UefiCpuPkg/UefiCpuPkg.dec
> index 68473fc640e6..79191af18a05 100644
> --- a/UefiCpuPkg/UefiCpuPkg.dec
> +++ b/UefiCpuPkg/UefiCpuPkg.dec
> @@ -396,6 +396,14 @@
>    # @Prompt Access to non-SMRAM memory is restricted t= o reserved,
> runtime and ACPI NVS type after SmmReadyToLock.
> gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|B
> OOLEAN|0x3213210F +[PcdsFixedAtBuild.RISCV64]+  ## Indicate the > maximum SATP mode allowed.+  #  0 - Bare mode.+  # = ; 8 - 39bit mode.+  #  9 -
> 48bit mode.+  #  10 - 57bit mode.+
> gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0|UINT32|0x6
> 0000021+ [PcdsDynamic, PcdsDynamicEx]   ## Contains the poin= ter to a CPU
> S3 data buffer of structure ACPI_CPU_DATA.   # @Prompt The p= ointer to a CPU
> S3 data buffer.--
> 2.25.1



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