Re: [edk2-devel] [PATCH v2 1/4] MdePkg.dec: RISC-V: Define override bit for Sstc extension

["Andrei Warkentin" <andrei.warkentin@intel.com>]

Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>

> -----Original Message-----
> From: Sunil V L <sunilvl@ventanamicro.com>
> Sent: Monday, January 8, 2024 5:37 AM
> To: devel@edk2.groups.io
> Cc: Sunil V L <sunilvl@ventanamicro.com>; Gao, Liming
> <gaoliming@byosoft.com.cn>; Kinney, Michael D
> <michael.d.kinney@intel.com>; Liu, Zhiguang <zhiguang.liu@intel.com>;
> Warkentin, Andrei <andrei.warkentin@intel.com>
> Subject: [PATCH v2 1/4] MdePkg.dec: RISC-V: Define override bit for Sstc
> extension
> 
> Define the BIT 1 as the override bit for Sstc extension. This will be used by the
> timer driver to decide whether to use SBI calls or direct CSR access to configure
> the timer.
> 
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> Cc: Andrei Warkentin <andrei.warkentin@intel.com>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
>  MdePkg/MdePkg.dec | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index
> 2ee112cc087a..0459418906f8 100644
> --- a/MdePkg/MdePkg.dec
> +++ b/MdePkg/MdePkg.dec
> @@ -2405,6 +2405,8 @@ [PcdsFixedAtBuild.RISCV64,
> PcdsPatchableInModule.RISCV64]
>    # Configurability to override RISC-V CPU Features
>    # BIT 0 = Cache Management Operations. This bit is relevant only if
>    # previous stage has feature enabled and user wants to disable it.
> +  # BIT 1 = Supervisor Time Compare (Sstc). This bit is relevant only
> + if  # previous stage has feature enabled and user wants to disable it.
>    #
> 
> gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|
> UINT64|0x69
> 
> --
> 2.34.1



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