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From: "Andrei Warkentin" <andrei.warkentin@intel.com>
To: "devel@edk2.groups.io" <devel@edk2.groups.io>,
	"tphan@ventanamicro.com" <tphan@ventanamicro.com>
Cc: "Kinney, Michael D" <michael.d.kinney@intel.com>,
	"Gao, Liming" <gaoliming@byosoft.com.cn>,
	"Liu, Zhiguang" <zhiguang.liu@intel.com>,
	"sunilvl@ventanamicro.com" <sunilvl@ventanamicro.com>,
	"git@danielschaefer.me" <git@danielschaefer.me>
Subject: Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support
Date: Mon, 8 May 2023 17:19:04 +0000	[thread overview]
Message-ID: <PH8PR11MB685680A563FAD40E3B6D306783719@PH8PR11MB6856.namprd11.prod.outlook.com> (raw)
In-Reply-To: <MN2PR13MB30222EA8A4CC9AA908B6BE38A7629@MN2PR13MB3022.namprd13.prod.outlook.com>

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Apologies for the late review. I added my comments on GH. Aside from a request for more context for https://github.com/tianocore/edk2/commit/b7387dae40cc3a72562c6461d007d20087ab7414#comments, I think this patch set from a functionality standpoint looks good enough to be submitted.

Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Tuan Phan
Sent: Wednesday, April 19, 2023 5:37 PM
To: devel@edk2.groups.io; Warkentin, Andrei <andrei.warkentin@intel.com>
Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>; sunilvl@ventanamicro.com; git@danielschaefer.me
Subject: Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support

Hi Andrei,
Here you go: https://github.com/pttuan/edk2/tree/tphan/riscv_mmu
Will put the link in the cover letter next round.

From: devel@edk2.groups.io<mailto:devel@edk2.groups.io> <devel@edk2.groups.io<mailto:devel@edk2.groups.io>> on behalf of Andrei Warkentin <andrei.warkentin@intel.com<mailto:andrei.warkentin@intel.com>>
Date: Tuesday, April 18, 2023 at 9:04 AM
To: Tuan Phan <tphan@ventanamicro.com<mailto:tphan@ventanamicro.com>>, devel@edk2.groups.io<mailto:devel@edk2.groups.io> <devel@edk2.groups.io<mailto:devel@edk2.groups.io>>
Cc: Kinney, Michael D <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>, Gao, Liming <gaoliming@byosoft.com.cn<mailto:gaoliming@byosoft.com.cn>>, Liu, Zhiguang <zhiguang.liu@intel.com<mailto:zhiguang.liu@intel.com>>, sunilvl@ventanamicro.com<mailto:sunilvl@ventanamicro.com> <sunilvl@ventanamicro.com<mailto:sunilvl@ventanamicro.com>>, git@danielschaefer.me<mailto:git@danielschaefer.me> <git@danielschaefer.me<mailto:git@danielschaefer.me>>
Subject: Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support
Hi Tuan,

Do you mind sharing the GitHub branch as well? It would help with the review immensely.

A

> -----Original Message-----
> From: Tuan Phan <tphan@ventanamicro.com<mailto:tphan@ventanamicro.com>>
> Sent: Friday, April 14, 2023 1:58 PM
> To: devel@edk2.groups.io<mailto:devel@edk2.groups.io>
> Cc: Kinney, Michael D <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>; Gao, Liming
> <gaoliming@byosoft.com.cn<mailto:gaoliming@byosoft.com.cn>>; Liu, Zhiguang <zhiguang.liu@intel.com<mailto:zhiguang.liu@intel.com>>;
> sunilvl@ventanamicro.com<mailto:sunilvl@ventanamicro.com>; git@danielschaefer.me<mailto:git@danielschaefer.me>; Warkentin, Andrei
> <andrei.warkentin@intel.com<mailto:andrei.warkentin@intel.com>>; Tuan Phan <tphan@ventanamicro.com<mailto:tphan@ventanamicro.com>>
> Subject: [PATCH v2 0/6] RISC-V MMU support
>
> RISC-V: Add MMU support
>
> This series adds MMU support for RISC-V. Only SV39/48/57 modes are
> supported and tested. The MMU is required to support setting page
> attribute which is the first basic step to support security booting on RISC-V.
>
> There are three parts:
> 1. Add MMU base library. MMU will be enabled during CpuDxe initialization.
> 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base address to GCD
> if already done.
> 3. Fix all resources should be populated in HOB or added to GCD by driver
> before accessing when MMU enabled.
>
> Changes in v2:
>   - Move MMU core to a library.
>   - Setup SATP mode as highest possible that HW supports.
>
> Tuan Phan (6):
>   MdePkg/BaseLib: RISC-V: Support getting satp register value
>   MdePkg/Register: RISC-V: Add satp mode bits shift definition
>   UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
>   OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size
>   OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists
>   OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform
>     devices
>
>  MdePkg/Include/Library/BaseLib.h              |   5 +
>  MdePkg/Include/Library/BaseRiscVMmuLib.h      |  39 ++
>  .../Include/Register/RiscV64/RiscVEncoding.h  |   7 +-
>  MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S     |   8 +
>  .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569
> ++++++++++++++++++
>  .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  25 +
>  MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S |  31 +
>  .../VirtNorFlashStaticLib.c                   |   3 +-
>  OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |   1 +
>  OvmfPkg/RiscVVirt/Sec/Memory.c                |  18 +-
>  OvmfPkg/RiscVVirt/Sec/Platform.c              |  62 ++
>  OvmfPkg/RiscVVirt/Sec/SecMain.inf             |   1 +
>  OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c     |  25 +-
>  UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c             |   9 +-
>  UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h             |   2 +
>  UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf    |   2 +
>  16 files changed, 776 insertions(+), 31 deletions(-)  create mode 100644
> MdePkg/Include/Library/BaseRiscVMmuLib.h
>  create mode 100644
> MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
>  create mode 100644
> MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
>  create mode 100644 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S
>
> --
> 2.25.1






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  reply	other threads:[~2023-05-08 17:19 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-14 18:58 [PATCH v2 0/6] RISC-V MMU support Tuan Phan
2023-04-14 18:58 ` [PATCH v2 1/6] MdePkg/BaseLib: RISC-V: Support getting satp register value Tuan Phan
2023-04-18 16:02   ` Andrei Warkentin
2023-04-14 18:58 ` [PATCH v2 2/6] MdePkg/Register: RISC-V: Add satp mode bits shift definition Tuan Phan
2023-04-18 16:05   ` Andrei Warkentin
2023-04-14 18:58 ` [PATCH v2 3/6] UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode Tuan Phan
2023-05-24  2:10   ` [edk2-devel] " Chao Li
2023-05-24  9:51     ` Ni, Ray
2023-05-24 18:16       ` Tuan Phan
2023-04-14 18:58 ` [PATCH v2 4/6] OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size Tuan Phan
2023-04-14 18:58 ` [PATCH v2 5/6] OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists Tuan Phan
2023-04-14 18:58 ` [PATCH v2 6/6] OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform devices Tuan Phan
2023-04-18 16:03 ` [PATCH v2 0/6] RISC-V MMU support Andrei Warkentin
2023-04-19 22:37   ` [edk2-devel] " Tuan Phan
2023-05-08 17:19     ` Andrei Warkentin [this message]
2023-05-23 21:59       ` Tuan Phan
2023-05-24  4:17         ` Sunil V L

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