From: "Andrei Warkentin" <andrei.warkentin@intel.com>
To: "devel@edk2.groups.io" <devel@edk2.groups.io>,
"sunilvl@ventanamicro.com" <sunilvl@ventanamicro.com>
Subject: Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V7 02/20] MdePkg/BaseLib: RISC-V: Add few more helper functions
Date: Mon, 6 Feb 2023 15:46:51 +0000 [thread overview]
Message-ID: <PH8PR11MB68569D8968195BF8F304773E83DA9@PH8PR11MB6856.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20230128191807.2080547-3-sunilvl@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Sunil V L
Sent: Saturday, January 28, 2023 1:18 PM
To: devel@edk2.groups.io
Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>; Daniel Schaefer <git@danielschaefer.me>; Abner Chang <abner.chang@amd.com>
Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V7 02/20] MdePkg/BaseLib: RISC-V: Add few more helper functions
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076
Few of the basic helper functions required for any RISC-V CPU were added in edk2-platforms. To support qemu virt, they need to be added in BaseLib.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
---
MdePkg/Library/BaseLib/BaseLib.inf | 3 ++
MdePkg/Include/Library/BaseLib.h | 50 ++++++++++++++++++
MdePkg/Library/BaseLib/RiscV64/CpuScratch.S | 31 ++++++++++++
MdePkg/Library/BaseLib/RiscV64/ReadTimer.S | 23 +++++++++
MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 53 ++++++++++++++++++--
MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 23 +++++++++
6 files changed, 179 insertions(+), 4 deletions(-)
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 9ed46a584a14..3a48492b1a01 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -401,6 +401,9 @@ [Sources.RISCV64]
RiscV64/RiscVCpuPause.S | GCC
RiscV64/RiscVInterrupt.S | GCC
RiscV64/FlushCache.S | GCC
+ RiscV64/CpuScratch.S | GCC
+ RiscV64/ReadTimer.S | GCC
+ RiscV64/RiscVMmu.S | GCC
[Sources.LOONGARCH64]
Math64.c
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index f3f59f21c2ea..b4f4e45a1486 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -151,6 +151,56 @@ typedef struct {
#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+VOID
+ RiscVSetSupervisorScratch (
+ UINT64
+ );
+
+UINT64
+RiscVGetSupervisorScratch (
+ VOID
+ );
+
+VOID
+ RiscVSetSupervisorStvec (
+ UINT64
+ );
+
+UINT64
+RiscVGetSupervisorStvec (
+ VOID
+ );
+
+UINT64
+RiscVGetSupervisorTrapCause (
+ VOID
+ );
+
+VOID
+ RiscVSetSupervisorAddressTranslationRegister (
+ UINT64
+ );
+
+UINT64
+RiscVReadTimer (
+ VOID
+ );
+
+VOID
+RiscVEnableTimerInterrupt (
+ VOID
+ );
+
+VOID
+RiscVDisableTimerInterrupt (
+ VOID
+ );
+
+VOID
+RiscVClearPendingTimerInterrupt (
+ VOID
+ );
+
#endif // defined (MDE_CPU_RISCV64)
#if defined (MDE_CPU_LOONGARCH64)
diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S
new file mode 100644
index 000000000000..5492a500eb5e
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S
@@ -0,0 +1,31 @@
+//---------------------------------------------------------------------
+---------
+//
+// CPU scratch register related functions for RISC-V // // Copyright
+(c) 2020, Hewlett Packard Enterprise Development LP. All rights
+reserved.<BR> // // SPDX-License-Identifier: BSD-2-Clause-Patent //
+//---------------------------------------------------------------------
+---------
+
+#include <Register/RiscV64/RiscVImpl.h>
+
+.data
+.align 3
+.section .text
+
+//
+// Set Supervisor mode scratch.
+// @param a0 : Value set to Supervisor mode scratch // ASM_FUNC
+(RiscVSetSupervisorScratch)
+ csrw CSR_SSCRATCH, a0
+ ret
+
+//
+// Get Supervisor mode scratch.
+// @retval a0 : Value in Supervisor mode scratch // ASM_FUNC
+(RiscVGetSupervisorScratch)
+ csrr a0, CSR_SSCRATCH
+ ret
diff --git a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
new file mode 100644
index 000000000000..39a06efa51ef
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
@@ -0,0 +1,23 @@
+//---------------------------------------------------------------------
+---------
+//
+// Read CPU timer
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All
+rights reserved.<BR> // // SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//---------------------------------------------------------------------
+---------
+
+#include <Register/RiscV64/RiscVImpl.h>
+
+.data
+.align 3
+.section .text
+
+//
+// Read TIME CSR.
+// @retval a0 : 64-bit timer.
+//
+ASM_FUNC (RiscVReadTimer)
+ csrr a0, CSR_TIME
+ ret
diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
index 87b3468fc7fd..6a1b90a7e45c 100644
--- a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
@@ -8,13 +8,13 @@
//
//------------------------------------------------------------------------------
+#include <Register/RiscV64/RiscVImpl.h>
+
ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts)
ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt)
ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts)
-#define SSTATUS_SIE 0x00000002
-#define CSR_SSTATUS 0x100
- #define SSTATUS_SPP_BIT_POSITION 8
+#define SSTATUS_SPP_BIT_POSITION 8
//
// This routine disables supervisor mode interrupt @@ -53,11 +53,56 @@ InTrap:
ret
//
+// Set Supervisor mode trap vector.
+// @param a0 : Value set to Supervisor mode trap vector // ASM_FUNC
+(RiscVSetSupervisorStvec)
+ csrrw a1, CSR_STVEC, a0
+ ret
+
+//
+// Get Supervisor mode trap vector.
+// @retval a0 : Value in Supervisor mode trap vector // ASM_FUNC
+(RiscVGetSupervisorStvec)
+ csrr a0, CSR_STVEC
+ ret
+
+//
+// Get Supervisor trap cause CSR.
+//
+ASM_FUNC (RiscVGetSupervisorTrapCause)
+ csrrs a0, CSR_SCAUSE, 0
+ ret
+//
// This routine returns supervisor mode interrupt // status.
//
-ASM_PFX(RiscVGetSupervisorModeInterrupts):
+ASM_FUNC (RiscVGetSupervisorModeInterrupts)
csrr a0, CSR_SSTATUS
andi a0, a0, SSTATUS_SIE
ret
+//
+// This routine disables supervisor mode timer interrupt // ASM_FUNC
+(RiscVDisableTimerInterrupt)
+ li a0, SIP_STIP
+ csrc CSR_SIE, a0
+ ret
+
+//
+// This routine enables supervisor mode timer interrupt // ASM_FUNC
+(RiscVEnableTimerInterrupt)
+ li a0, SIP_STIP
+ csrs CSR_SIE, a0
+ ret
+
+//
+// This routine clears pending supervisor mode timer interrupt //
+ASM_FUNC (RiscVClearPendingTimerInterrupt)
+ li a0, SIP_STIP
+ csrc CSR_SIP, a0
+ ret
diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S
new file mode 100644
index 000000000000..ac8f92f38aed
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S
@@ -0,0 +1,23 @@
+//---------------------------------------------------------------------
+---------
+//
+// CPU scratch register related functions for RISC-V // // Copyright
+(c) 2020, Hewlett Packard Enterprise Development LP. All rights
+reserved.<BR> // // SPDX-License-Identifier: BSD-2-Clause-Patent //
+//---------------------------------------------------------------------
+---------
+
+#include <Register/RiscV64/RiscVImpl.h>
+
+.data
+.align 3
+.section .text
+
+//
+// Set Supervisor Address Translation and // Protection Register.
+//
+ASM_FUNC (RiscVSetSupervisorAddressTranslationRegister)
+ csrw CSR_SATP, a0
+ ret
--
2.38.0
next prev parent reply other threads:[~2023-02-06 15:48 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-28 19:17 [edk2-staging/RiscV64QemuVirt PATCH V7 00/20] Add support for RISC-V virt machine Sunil V L
2023-01-28 19:17 ` [edk2-staging/RiscV64QemuVirt PATCH V7 01/20] MdePkg/Register: Add register definition header files for RISC-V Sunil V L
2023-02-06 15:44 ` [edk2-devel] " Andrei Warkentin
2023-02-09 1:44 ` Michael D Kinney
2023-01-28 19:17 ` [edk2-staging/RiscV64QemuVirt PATCH V7 02/20] MdePkg/BaseLib: RISC-V: Add few more helper functions Sunil V L
2023-02-06 15:46 ` Andrei Warkentin [this message]
2023-02-09 1:43 ` Michael D Kinney
2023-02-09 7:21 ` Sunil V L
2023-01-28 19:17 ` [edk2-staging/RiscV64QemuVirt PATCH V7 03/20] MdePkg: Add BaseRiscVSbiLib Library for RISC-V Sunil V L
2023-02-06 15:47 ` [edk2-devel] " Andrei Warkentin
2023-02-09 1:45 ` Michael D Kinney
2023-02-09 7:18 ` [edk2-devel] " Sunil V L
2023-02-09 15:47 ` Michael D Kinney
2023-01-28 19:17 ` [edk2-staging/RiscV64QemuVirt PATCH V7 04/20] UefiCpuPkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions Sunil V L
2023-02-06 15:47 ` [edk2-devel] " Andrei Warkentin
2023-02-09 5:16 ` Ni, Ray
2023-01-28 19:17 ` [edk2-staging/RiscV64QemuVirt PATCH V7 05/20] UefiCpuPkg: Add CpuTimerDxe module Sunil V L
2023-02-08 18:02 ` [edk2-devel] " Michael D Kinney
2023-02-08 18:12 ` Sunil V L
2023-02-09 5:21 ` Ni, Ray
2023-02-09 10:17 ` Michael Brown
2023-02-09 10:28 ` Sunil V L
2023-02-09 10:30 ` Michael Brown
2023-02-09 10:37 ` Sunil V L
2023-01-28 19:17 ` [edk2-staging/RiscV64QemuVirt PATCH V7 06/20] UefiCpuPkg/CpuExceptionHandlerLib: Add RISC-V instance Sunil V L
2023-02-09 5:24 ` [edk2-devel] " Ni, Ray
2023-01-28 19:17 ` [edk2-staging/RiscV64QemuVirt PATCH V7 07/20] UefiCpuPkg/CpuDxe: " Sunil V L
2023-02-06 15:58 ` [edk2-devel] " Andrei Warkentin
2023-02-08 5:05 ` Sunil V L
2023-02-09 5:43 ` Ni, Ray
2023-02-09 5:49 ` Sunil V L
2023-01-28 19:17 ` [edk2-staging/RiscV64QemuVirt PATCH V7 08/20] UefiCpuPkg/CpuTimerLib: " Sunil V L
2023-01-30 11:07 ` [edk2-devel] " dhaval
2023-01-30 13:08 ` Sunil V L
2023-02-06 16:00 ` Andrei Warkentin
2023-02-09 5:37 ` Ni, Ray
2023-01-28 19:17 ` [edk2-staging/RiscV64QemuVirt PATCH V7 09/20] UefiCpuPkg/UefiCpuPkg.ci.yaml: Ignore RISC-V file Sunil V L
2023-02-06 16:00 ` [edk2-devel] " Andrei Warkentin
2023-02-09 1:50 ` Michael D Kinney
2023-02-09 5:38 ` Ni, Ray
2023-01-28 19:17 ` [edk2-staging/RiscV64QemuVirt PATCH V7 10/20] EmbeddedPkg: Enable PcdPrePiCpuIoSize for RISC-V Sunil V L
2023-02-06 16:00 ` [edk2-devel] " Andrei Warkentin
2023-02-09 1:51 ` Michael D Kinney
2023-01-28 19:17 ` [edk2-staging/RiscV64QemuVirt PATCH V7 11/20] ArmVirtPkg/PlatformHasAcpiDtDxe: Move to OvmfPkg Sunil V L
2023-02-06 16:01 ` [edk2-devel] " Andrei Warkentin
2023-01-28 19:17 ` [edk2-staging/RiscV64QemuVirt PATCH V7 12/20] ArmVirtPkg: Fix up the location of PlatformHasAcpiDtDxe Sunil V L
2023-02-06 16:01 ` [edk2-devel] " Andrei Warkentin
2023-01-28 19:18 ` [edk2-staging/RiscV64QemuVirt PATCH V7 13/20] OvmfPkg/RiscVVirt: Add PlatformBootManagerLib library Sunil V L
2023-02-06 16:01 ` [edk2-devel] " Andrei Warkentin
2023-01-28 19:18 ` [edk2-staging/RiscV64QemuVirt PATCH V7 14/20] OvmfPkg/RiscVVirt: Add PrePiHobListPointerLib library Sunil V L
2023-02-06 16:01 ` [edk2-devel] " Andrei Warkentin
2023-01-28 19:18 ` [edk2-staging/RiscV64QemuVirt PATCH V7 15/20] OvmfPkg/RiscVVirt: Add ResetSystemLib library Sunil V L
2023-02-06 16:01 ` [edk2-devel] " Andrei Warkentin
2023-01-28 19:18 ` [edk2-staging/RiscV64QemuVirt PATCH V7 16/20] OvmfPkg/RiscVVirt: Add VirtNorFlashPlatformLib library Sunil V L
2023-02-06 16:02 ` [edk2-devel] " Andrei Warkentin
2023-01-28 19:18 ` [edk2-staging/RiscV64QemuVirt PATCH V7 17/20] OvmfPkg/RiscVVirt: Add PciCpuIo2Dxe module Sunil V L
2023-01-30 10:12 ` [edk2-devel] " dhaval
2023-01-30 13:05 ` Sunil V L
2023-01-30 14:33 ` dhaval
2023-02-06 16:02 ` Andrei Warkentin
2023-01-28 19:18 ` [edk2-staging/RiscV64QemuVirt PATCH V7 18/20] OvmfPkg/RiscVVirt: Add SEC module Sunil V L
2023-01-30 5:17 ` [edk2-devel] " dhaval
2023-01-30 6:00 ` Sunil V L
2023-02-06 16:03 ` Andrei Warkentin
2023-01-28 19:18 ` [edk2-staging/RiscV64QemuVirt PATCH V7 19/20] OvmfPkg/RiscVVirt: Add build files for Qemu Virt platform Sunil V L
2023-02-06 16:03 ` [edk2-devel] " Andrei Warkentin
2023-01-28 19:18 ` [edk2-staging/RiscV64QemuVirt PATCH V7 20/20] Maintainers.txt: Add entry for OvmfPkg/RiscVVirt Sunil V L
2023-02-06 16:04 ` [edk2-devel] " Andrei Warkentin
2023-02-09 1:51 ` Michael D Kinney
2023-02-09 3:32 ` [edk2-devel] " Yao, Jiewen
2023-02-09 4:34 ` Sunil V L
2023-02-09 5:07 ` Yao, Jiewen
2023-02-09 5:15 ` Chang, Abner
2023-02-09 14:05 ` Yao, Jiewen
2023-02-09 15:19 ` Sunil V L
2023-02-09 15:21 ` Yao, Jiewen
[not found] ` <173E8F29CD0D02D8.27165@groups.io>
2023-01-30 13:43 ` [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V7 11/20] ArmVirtPkg/PlatformHasAcpiDtDxe: Move to OvmfPkg Sunil V L
2023-02-03 12:29 ` Ard Biesheuvel
[not found] ` <173E8F254E9BED62.27165@groups.io>
2023-02-02 14:35 ` [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V7 03/20] MdePkg: Add BaseRiscVSbiLib Library for RISC-V Sunil V L
[not found] ` <173E8F293E682CB4.27165@groups.io>
2023-02-03 9:46 ` [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V7 10/20] EmbeddedPkg: Enable PcdPrePiCpuIoSize " Sunil V L
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