From: "Andrei Warkentin" <andrei.warkentin@intel.com>
To: Sunil V L <sunilvl@ventanamicro.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: Gerd Hoffmann <kraxel@redhat.com>,
"Kumar, Rahul R" <rahul.r.kumar@intel.com>,
Laszlo Ersek <lersek@redhat.com>, "Ni, Ray" <ray.ni@intel.com>
Subject: Re: [edk2-devel] [PATCH v2 3/4] UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc
Date: Tue, 9 Jan 2024 16:22:25 +0000 [thread overview]
Message-ID: <PH8PR11MB6856AF9079F454F64C4BDB88836A2@PH8PR11MB6856.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20240108113650.454940-4-sunilvl@ventanamicro.com>
Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>
> -----Original Message-----
> From: Sunil V L <sunilvl@ventanamicro.com>
> Sent: Monday, January 8, 2024 5:37 AM
> To: devel@edk2.groups.io
> Cc: Sunil V L <sunilvl@ventanamicro.com>; Gerd Hoffmann
> <kraxel@redhat.com>; Kumar, Rahul R <rahul.r.kumar@intel.com>; Laszlo
> Ersek <lersek@redhat.com>; Ni, Ray <ray.ni@intel.com>; Warkentin, Andrei
> <andrei.warkentin@intel.com>
> Subject: [PATCH v2 3/4] UefiCpuPkg/CpuTimerDxeRiscV64: Add support for
> Sstc
>
> Sstc extension allows to program the timer and receive the interrupt without
> using an SBI call. This reduces the latency to generate the timer interrupt. So,
> detect whether Sstc extension is supported and use the stimecmp register
> directly to program the timer interrupt.
>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Andrei Warkentin <andrei.warkentin@intel.com>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
> .../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 1 +
> UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h | 2 +
> UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 49 +++++++++++++++++--
> 3 files changed, 49 insertions(+), 3 deletions(-)
>
> diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
> b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
> index aba660186dc0..f2a2cf12caef 100644
> --- a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
> +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
> @@ -41,6 +41,7 @@ [Sources.RISCV64]
> Timer.c
>
> [Pcd]
> + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES
> gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ##
> CONSUMES
>
> [Protocols]
> diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
> b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
> index 9b3542230cb5..067bbd29f377 100644
> --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
> +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h
> @@ -26,6 +26,8 @@
> //
> #define DEFAULT_TIMER_TICK_DURATION 100000
>
> +#define RISCV_CPU_FEATURE_SSTC_BITMASK BIT1
> +
> extern VOID
> RiscvSetTimerPeriod (
> UINT32 TimerPeriod
> diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
> b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
> index 30e48061cd06..216f48a52931 100644
> --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
> +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c
> @@ -44,6 +44,45 @@ STATIC EFI_TIMER_NOTIFY mTimerNotifyFunction;
> STATIC UINT64 mTimerPeriod = 0;
> STATIC UINT64 mLastPeriodStart = 0;
>
> +//
> +// Sstc support
> +//
> +STATIC BOOLEAN mSstcEnabled = FALSE;
> +
> +/**
> + Program the timer.
> +
> + Program either using stimecmp (when Sstc extension is enabled) or
> + using SBI TIME call.
> +
> + @param NextValue Core tick value the timer should expire.
> +**/
> +STATIC
> +VOID
> +RiscVProgramTimer (
> + UINT64 NextValue
> + )
> +{
> + if (mSstcEnabled) {
> + RiscVSetSupervisorTimeCompareRegister (NextValue);
> + } else {
> + SbiSetTimer (NextValue);
> + }
> +}
> +
> +/**
> + Check whether Sstc is enabled in PCD.
> +
> +**/
> +STATIC
> +BOOLEAN
> +RiscVIsSstcEnabled (
> + VOID
> + )
> +{
> + return ((PcdGet64 (PcdRiscVFeatureOverride) &
> +RISCV_CPU_FEATURE_SSTC_BITMASK) != 0); }
> +
> /**
> Timer Interrupt Handler.
>
> @@ -94,7 +133,7 @@ TimerInterruptHandler (
> ),
> 1000000u
> ); // convert to tick
> - SbiSetTimer (PeriodStart);
> + RiscVProgramTimer (PeriodStart);
> RiscVEnableTimerInterrupt (); // enable SMode timer int
> gBS->RestoreTPL (OriginalTPL);
> }
> @@ -197,8 +236,7 @@ TimerDriverSetTimerPeriod (
> ),
> 1000000u
> ); // convert to tick
> - SbiSetTimer (PeriodStart);
> -
> + RiscVProgramTimer (PeriodStart);
> mCpu->EnableInterrupt (mCpu);
> RiscVEnableTimerInterrupt (); // enable SMode timer int
> return EFI_SUCCESS;
> @@ -282,6 +320,11 @@ TimerDriverInitialize (
> //
> mTimerNotifyFunction = NULL;
>
> + if (RiscVIsSstcEnabled ()) {
> + mSstcEnabled = TRUE;
> + DEBUG ((DEBUG_INFO, "TimerDriverInitialize: Timer interrupt is via
> + Sstc extension\n")); }
> +
> //
> // Make sure the Timer Architectural Protocol is not already installed in the
> system
> //
> --
> 2.34.1
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next prev parent reply other threads:[~2024-01-09 16:22 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-08 11:36 [edk2-devel] [PATCH v2 0/4] RISC-V: Add support for Sstc extension Sunil V L
2024-01-08 11:36 ` [edk2-devel] [PATCH v2 1/4] MdePkg.dec: RISC-V: Define override bit " Sunil V L
2024-01-09 16:21 ` Andrei Warkentin
2024-01-08 11:36 ` [edk2-devel] [PATCH v2 2/4] MdePkg/BaseLib: RISC-V: Add function to update stimecmp register Sunil V L
2024-01-09 16:21 ` Andrei Warkentin
2024-01-08 11:36 ` [edk2-devel] [PATCH v2 3/4] UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc Sunil V L
2024-01-08 13:00 ` Laszlo Ersek
2024-01-08 15:25 ` Dhaval Sharma
2024-01-09 16:22 ` Andrei Warkentin [this message]
2024-01-08 11:36 ` [edk2-devel] [PATCH v2 4/4] OvmfPkg/RiscVVirt: Override Sstc extension Sunil V L
2024-01-09 16:22 ` Andrei Warkentin
2024-01-11 12:57 ` [edk2-devel] [PATCH v2 0/4] RISC-V: Add support for " Sunil V L
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