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devel@edk2.groups.io,andrei.warkentin@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: QA4OU9disjxRNCKrGscG4rEHx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=eHpqF+FF; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") Reviewed-by: Andrei Warkentin > -----Original Message----- > From: Sunil V L > Sent: Monday, January 8, 2024 5:37 AM > To: devel@edk2.groups.io > Cc: Sunil V L ; Gerd Hoffmann > ; Kumar, Rahul R ; Laszlo > Ersek ; Ni, Ray ; Warkentin, Andrei > > Subject: [PATCH v2 3/4] UefiCpuPkg/CpuTimerDxeRiscV64: Add support for > Sstc >=20 > Sstc extension allows to program the timer and receive the interrupt with= out > using an SBI call. This reduces the latency to generate the timer interru= pt. So, > detect whether Sstc extension is supported and use the stimecmp register > directly to program the timer interrupt. >=20 > Cc: Gerd Hoffmann > Cc: Rahul Kumar > Cc: Laszlo Ersek > Cc: Ray Ni > Cc: Andrei Warkentin > Signed-off-by: Sunil V L > --- > .../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 1 + > UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h | 2 + > UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 49 +++++++++++++++++-- > 3 files changed, 49 insertions(+), 3 deletions(-) >=20 > diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf > b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf > index aba660186dc0..f2a2cf12caef 100644 > --- a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf > +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf > @@ -41,6 +41,7 @@ [Sources.RISCV64] > Timer.c >=20 > [Pcd] > + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES > gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## > CONSUMES >=20 > [Protocols] > diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h > b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h > index 9b3542230cb5..067bbd29f377 100644 > --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h > +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h > @@ -26,6 +26,8 @@ > // > #define DEFAULT_TIMER_TICK_DURATION 100000 >=20 > +#define RISCV_CPU_FEATURE_SSTC_BITMASK BIT1 > + > extern VOID > RiscvSetTimerPeriod ( > UINT32 TimerPeriod > diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c > b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c > index 30e48061cd06..216f48a52931 100644 > --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c > +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c > @@ -44,6 +44,45 @@ STATIC EFI_TIMER_NOTIFY mTimerNotifyFunction; > STATIC UINT64 mTimerPeriod =3D 0; > STATIC UINT64 mLastPeriodStart =3D 0; >=20 > +// > +// Sstc support > +// > +STATIC BOOLEAN mSstcEnabled =3D FALSE; > + > +/** > + Program the timer. > + > + Program either using stimecmp (when Sstc extension is enabled) or > + using SBI TIME call. > + > + @param NextValue Core tick value the timer should expire. > +**/ > +STATIC > +VOID > +RiscVProgramTimer ( > + UINT64 NextValue > + ) > +{ > + if (mSstcEnabled) { > + RiscVSetSupervisorTimeCompareRegister (NextValue); > + } else { > + SbiSetTimer (NextValue); > + } > +} > + > +/** > + Check whether Sstc is enabled in PCD. > + > +**/ > +STATIC > +BOOLEAN > +RiscVIsSstcEnabled ( > + VOID > + ) > +{ > + return ((PcdGet64 (PcdRiscVFeatureOverride) & > +RISCV_CPU_FEATURE_SSTC_BITMASK) !=3D 0); } > + > /** > Timer Interrupt Handler. >=20 > @@ -94,7 +133,7 @@ TimerInterruptHandler ( > ), > 1000000u > ); // convert to tick > - SbiSetTimer (PeriodStart); > + RiscVProgramTimer (PeriodStart); > RiscVEnableTimerInterrupt (); // enable SMode timer int > gBS->RestoreTPL (OriginalTPL); > } > @@ -197,8 +236,7 @@ TimerDriverSetTimerPeriod ( > ), > 1000000u > ); // convert to tick > - SbiSetTimer (PeriodStart); > - > + RiscVProgramTimer (PeriodStart); > mCpu->EnableInterrupt (mCpu); > RiscVEnableTimerInterrupt (); // enable SMode timer int > return EFI_SUCCESS; > @@ -282,6 +320,11 @@ TimerDriverInitialize ( > // > mTimerNotifyFunction =3D NULL; >=20 > + if (RiscVIsSstcEnabled ()) { > + mSstcEnabled =3D TRUE; > + DEBUG ((DEBUG_INFO, "TimerDriverInitialize: Timer interrupt is via > + Sstc extension\n")); } > + > // > // Make sure the Timer Architectural Protocol is not already installed= in the > system > // > -- > 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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