Re: [edk2-devel] [PATCH v2 2/4] MdePkg/BaseLib: RISC-V: Add function to update stimecmp register

["Andrei Warkentin" <andrei.warkentin@intel.com>]

Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>

> -----Original Message-----
> From: Sunil V L <sunilvl@ventanamicro.com>
> Sent: Monday, January 8, 2024 5:37 AM
> To: devel@edk2.groups.io
> Cc: Sunil V L <sunilvl@ventanamicro.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>;
> Liu, Zhiguang <zhiguang.liu@intel.com>; Warkentin, Andrei
> <andrei.warkentin@intel.com>
> Subject: [PATCH v2 2/4] MdePkg/BaseLib: RISC-V: Add function to update
> stimecmp register
> 
> stimecmp is a CSR supported only when Sstc extension is supported by the
> platform. This register can be used to set the timer interrupt directly in S-mode
> instead of going via SBI call. Add a function to update this register.
> 
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> Cc: Andrei Warkentin <andrei.warkentin@intel.com>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> ---
>  MdePkg/Include/Library/BaseLib.h                | 5 +++++
>  MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 3 +++
>  MdePkg/Library/BaseLib/RiscV64/ReadTimer.S      | 7 +++++++
>  3 files changed, 15 insertions(+)
> 
> diff --git a/MdePkg/Include/Library/BaseLib.h
> b/MdePkg/Include/Library/BaseLib.h
> index b71e47f41b7f..ca0d06c7f335 100644
> --- a/MdePkg/Include/Library/BaseLib.h
> +++ b/MdePkg/Include/Library/BaseLib.h
> @@ -191,6 +191,11 @@ RiscVReadTimer (
>    VOID
>    );
> 
> +VOID
> +RiscVSetSupervisorTimeCompareRegister (
> +  IN UINT64
> +  );
> +
>  VOID
>  RiscVEnableTimerInterrupt (
>    VOID
> diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> index 2bde8db478ff..8ccdea2f4fcd 100644
> --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
> @@ -96,6 +96,9 @@
>  /* Supervisor Protection and Translation */  #define CSR_SATP  0x180
> 
> +/* Sstc extension */
> +#define CSR_STIMECMP  0x14D
> +
>  /* Trap/Exception Causes */
>  #define CAUSE_MISALIGNED_FETCH          0x0
>  #define CAUSE_FETCH_ACCESS              0x1
> diff --git a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
> b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
> index 39a06efa51ef..36781c29c0b9 100644
> --- a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
> +++ b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S
> @@ -21,3 +21,10 @@
>  ASM_FUNC (RiscVReadTimer)
>      csrr a0, CSR_TIME
>      ret
> +
> +//
> +// Set Supervisor Time Compare Register // ASM_FUNC
> +(RiscVSetSupervisorTimeCompareRegister)
> +    csrw  CSR_STIMECMP, a0
> +    ret
> --
> 2.34.1



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