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devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,andrei.warkentin@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: wXzs3sOj9ow2uY16RRykETivx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=eeJbGMGA; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") Reviewed-by: Andrei Warkentin > -----Original Message----- > From: Sunil V L > Sent: Monday, January 8, 2024 5:37 AM > To: devel@edk2.groups.io > Cc: Sunil V L ; Kinney, Michael D > ; Gao, Liming ; > Liu, Zhiguang ; Warkentin, Andrei > > Subject: [PATCH v2 2/4] MdePkg/BaseLib: RISC-V: Add function to update > stimecmp register >=20 > stimecmp is a CSR supported only when Sstc extension is supported by the > platform. This register can be used to set the timer interrupt directly i= n S-mode > instead of going via SBI call. Add a function to update this register. >=20 > Cc: Michael D Kinney > Cc: Liming Gao > Cc: Zhiguang Liu > Cc: Andrei Warkentin > Signed-off-by: Sunil V L > --- > MdePkg/Include/Library/BaseLib.h | 5 +++++ > MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 3 +++ > MdePkg/Library/BaseLib/RiscV64/ReadTimer.S | 7 +++++++ > 3 files changed, 15 insertions(+) >=20 > diff --git a/MdePkg/Include/Library/BaseLib.h > b/MdePkg/Include/Library/BaseLib.h > index b71e47f41b7f..ca0d06c7f335 100644 > --- a/MdePkg/Include/Library/BaseLib.h > +++ b/MdePkg/Include/Library/BaseLib.h > @@ -191,6 +191,11 @@ RiscVReadTimer ( > VOID > ); >=20 > +VOID > +RiscVSetSupervisorTimeCompareRegister ( > + IN UINT64 > + ); > + > VOID > RiscVEnableTimerInterrupt ( > VOID > diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h > b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h > index 2bde8db478ff..8ccdea2f4fcd 100644 > --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h > +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h > @@ -96,6 +96,9 @@ > /* Supervisor Protection and Translation */ #define CSR_SATP 0x180 >=20 > +/* Sstc extension */ > +#define CSR_STIMECMP 0x14D > + > /* Trap/Exception Causes */ > #define CAUSE_MISALIGNED_FETCH 0x0 > #define CAUSE_FETCH_ACCESS 0x1 > diff --git a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S > b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S > index 39a06efa51ef..36781c29c0b9 100644 > --- a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S > +++ b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S > @@ -21,3 +21,10 @@ > ASM_FUNC (RiscVReadTimer) > csrr a0, CSR_TIME > ret > + > +// > +// Set Supervisor Time Compare Register // ASM_FUNC > +(RiscVSetSupervisorTimeCompareRegister) > + csrw CSR_STIMECMP, a0 > + ret > -- > 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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