Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V7 01/20] MdePkg/Register: Add register definition header files for RISC-V

["Andrei Warkentin" <andrei.warkentin@intel.com>]

Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Sunil V L
Sent: Saturday, January 28, 2023 1:18 PM
To: devel@edk2.groups.io
Cc: Daniel Schaefer <git@danielschaefer.me>; Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>; Liu, Zhiguang <zhiguang.liu@intel.com>; Abner Chang <abner.chang@amd.com>
Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V7 01/20] MdePkg/Register: Add register definition header files for RISC-V

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

Add register definitions and access routines for RISC-V. These headers are leveraged from opensbi repo.

Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
---
 MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 119 ++++++++++++++++++++
 MdePkg/Include/Register/RiscV64/RiscVImpl.h     |  25 ++++
 2 files changed, 144 insertions(+)

diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
new file mode 100644
index 000000000000..5c2989b797bf
--- /dev/null
+++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
@@ -0,0 +1,119 @@
+/** @file
+  RISC-V CSR encodings
+
+  Copyright (c) 2019, Western Digital Corporation or its affiliates. 
+ All rights reserved.<BR>  Copyright (c) 2022, Ventana Micro Systems 
+ Inc. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_ENCODING_H_
+#define RISCV_ENCODING_H_
+
+#define MSTATUS_SIE         0x00000002UL
+#define MSTATUS_MIE         0x00000008UL
+#define MSTATUS_SPIE_SHIFT  5
+#define MSTATUS_SPIE        (1UL << MSTATUS_SPIE_SHIFT)
+#define MSTATUS_UBE         0x00000040UL
+#define MSTATUS_MPIE        0x00000080UL
+#define MSTATUS_SPP_SHIFT   8
+#define MSTATUS_SPP         (1UL << MSTATUS_SPP_SHIFT)
+#define MSTATUS_MPP_SHIFT   11
+#define MSTATUS_MPP         (3UL << MSTATUS_MPP_SHIFT)
+
+#define SSTATUS_SIE         MSTATUS_SIE
+#define SSTATUS_SPIE_SHIFT  MSTATUS_SPIE_SHIFT
+#define SSTATUS_SPIE        MSTATUS_SPIE
+#define SSTATUS_SPP_SHIFT   MSTATUS_SPP_SHIFT
+#define SSTATUS_SPP         MSTATUS_SPP
+
+#define IRQ_S_SOFT    1
+#define IRQ_VS_SOFT   2
+#define IRQ_M_SOFT    3
+#define IRQ_S_TIMER   5
+#define IRQ_VS_TIMER  6
+#define IRQ_M_TIMER   7
+#define IRQ_S_EXT     9
+#define IRQ_VS_EXT    10
+#define IRQ_M_EXT     11
+#define IRQ_S_GEXT    12
+#define IRQ_PMU_OVF   13
+
+#define MIP_SSIP    (1UL << IRQ_S_SOFT)
+#define MIP_VSSIP   (1UL << IRQ_VS_SOFT)
+#define MIP_MSIP    (1UL << IRQ_M_SOFT)
+#define MIP_STIP    (1UL << IRQ_S_TIMER)
+#define MIP_VSTIP   (1UL << IRQ_VS_TIMER)
+#define MIP_MTIP    (1UL << IRQ_M_TIMER)
+#define MIP_SEIP    (1UL << IRQ_S_EXT)
+#define MIP_VSEIP   (1UL << IRQ_VS_EXT)
+#define MIP_MEIP    (1UL << IRQ_M_EXT)
+#define MIP_SGEIP   (1UL << IRQ_S_GEXT)
+#define MIP_LCOFIP  (1UL << IRQ_PMU_OVF)
+
+#define SIP_SSIP  MIP_SSIP
+#define SIP_STIP  MIP_STIP
+
+#define PRV_U  0UL
+#define PRV_S  1UL
+#define PRV_M  3UL
+
+#define SATP64_MODE  0xF000000000000000ULL #define SATP64_ASID  
+0x0FFFF00000000000ULL
+#define SATP64_PPN   0x00000FFFFFFFFFFFULL
+
+#define SATP_MODE_OFF   0UL
+#define SATP_MODE_SV32  1UL
+#define SATP_MODE_SV39  8UL
+#define SATP_MODE_SV48  9UL
+#define SATP_MODE_SV57  10UL
+#define SATP_MODE_SV64  11UL
+
+#define SATP_MODE  SATP64_MODE
+
+/* User Counters/Timers */
+#define CSR_CYCLE  0xc00
+#define CSR_TIME   0xc01
+
+/* Supervisor Trap Setup */
+#define CSR_SSTATUS  0x100
+#define CSR_SEDELEG  0x102
+#define CSR_SIDELEG  0x103
+#define CSR_SIE      0x104
+#define CSR_STVEC    0x105
+
+/* Supervisor Configuration */
+#define CSR_SENVCFG  0x10a
+
+/* Supervisor Trap Handling */
+#define CSR_SSCRATCH  0x140
+#define CSR_SEPC      0x141
+#define CSR_SCAUSE    0x142
+#define CSR_STVAL     0x143
+#define CSR_SIP       0x144
+
+/* Supervisor Protection and Translation */ #define CSR_SATP  0x180
+
+/* Trap/Exception Causes */
+#define CAUSE_MISALIGNED_FETCH          0x0
+#define CAUSE_FETCH_ACCESS              0x1
+#define CAUSE_ILLEGAL_INSTRUCTION       0x2
+#define CAUSE_BREAKPOINT                0x3
+#define CAUSE_MISALIGNED_LOAD           0x4
+#define CAUSE_LOAD_ACCESS               0x5
+#define CAUSE_MISALIGNED_STORE          0x6
+#define CAUSE_STORE_ACCESS              0x7
+#define CAUSE_USER_ECALL                0x8
+#define CAUSE_SUPERVISOR_ECALL          0x9
+#define CAUSE_VIRTUAL_SUPERVISOR_ECALL  0xa
+#define CAUSE_MACHINE_ECALL             0xb
+#define CAUSE_FETCH_PAGE_FAULT          0xc
+#define CAUSE_LOAD_PAGE_FAULT           0xd
+#define CAUSE_STORE_PAGE_FAULT          0xf
+#define CAUSE_FETCH_GUEST_PAGE_FAULT    0x14
+#define CAUSE_LOAD_GUEST_PAGE_FAULT     0x15
+#define CAUSE_VIRTUAL_INST_FAULT        0x16
+#define CAUSE_STORE_GUEST_PAGE_FAULT    0x17
+
+#endif
diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
new file mode 100644
index 000000000000..ee5c2ba60377
--- /dev/null
+++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
@@ -0,0 +1,25 @@
+/** @file
+  RISC-V package definitions.
+
+  Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. 
+ All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_IMPL_H_
+#define RISCV_IMPL_H_
+
+#include <Register/RiscV64/RiscVEncoding.h>
+
+#define _ASM_FUNC(Name, Section)    \
+  .global   Name                  ; \
+  .section  #Section, "ax"        ; \
+  .type     Name, %function       ; \
+  .p2align  2                     ; \
+  Name:
+
+#define ASM_FUNC(Name)  _ASM_FUNC(ASM_PFX(Name), .text. ## Name) 
+#define RISCV_TIMER_COMPARE_BITS  32
+
+#endif
--
2.38.0