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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Andrei Warkentin -----Original Message----- From: devel@edk2.groups.io On Behalf Of Sunil V L Sent: Saturday, January 28, 2023 1:18 PM To: devel@edk2.groups.io Cc: Dong, Eric ; Ni, Ray ; Kumar, Ra= hul R ; Daniel Schaefer ; G= erd Hoffmann ; Abner Chang ; Heinri= ch Schuchardt Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V7 04/20] UefiCpu= Pkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4076 RISC-V UEFI based platforms need to support RISCV_EFI_BOOT_PROTOCOL. Add this protocol GUID definition and the header file required. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Cc: Gerd Hoffmann Signed-off-by: Sunil V L Acked-by: Abner Chang Reviewed-by: Heinrich Schuchardt --- UefiCpuPkg/UefiCpuPkg.dec | 7 ++++ UefiCpuPkg/Include/Protocol/RiscVBootProtocol.h | 34 ++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index cf= f239d5283e..903ad52da91b 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -86,6 +86,13 @@ [Protocols] ## Include/Protocol/SmMonitorInit.h gEfiSmMonitorInitProtocolGuid =3D { 0x228f344d, 0xb3de, 0x43bb, { 0xa4,= 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }} =20 +[Protocols.RISCV64] + # + # Protocols defined for RISC-V systems + # + ## Include/Protocol/RiscVBootProtocol.h + gRiscVEfiBootProtocolGuid =3D { 0xccd15fec, 0x6f73, 0x4eec, { 0x83,=20 +0x95, 0x3e, 0x69, 0xe4, 0xb9, 0x40, 0xbf }} + # # [Error.gUefiCpuPkgTokenSpaceGuid] # 0x80000001 | Invalid value provided. diff --git a/UefiCpuPkg/Include/Protocol/RiscVBootProtocol.h b/UefiCpuPkg/I= nclude/Protocol/RiscVBootProtocol.h new file mode 100644 index 000000000000..ed223b852d34 --- /dev/null +++ b/UefiCpuPkg/Include/Protocol/RiscVBootProtocol.h @@ -0,0 +1,34 @@ +/** @file + RISC-V Boot Protocol mandatory for RISC-V UEFI platforms. + + @par Revision Reference: + The protocol specification can be found at =20 + https://github.com/riscv-non-isa/riscv-uefi + + Copyright (c) 2022, Ventana Micro Systems Inc. All rights=20 + reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_BOOT_PROTOCOL_H_ +#define RISCV_BOOT_PROTOCOL_H_ + +typedef struct _RISCV_EFI_BOOT_PROTOCOL RISCV_EFI_BOOT_PROTOCOL; + +#define RISCV_EFI_BOOT_PROTOCOL_REVISION 0x00010000 #define=20 +RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION \ + RISCV_EFI_BOOT_PROTOCOL_REVISION + +typedef +EFI_STATUS +(EFIAPI *EFI_GET_BOOT_HARTID)( + IN RISCV_EFI_BOOT_PROTOCOL *This, + OUT UINTN *BootHartId + ); + +typedef struct _RISCV_EFI_BOOT_PROTOCOL { + UINT64 Revision; + EFI_GET_BOOT_HARTID GetBootHartId; +} RISCV_EFI_BOOT_PROTOCOL; + +#endif -- 2.38.0