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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Pushed as b013adb40e..1b02220269 -----Original Message----- From: devel@edk2.groups.io On Behalf Of Isaac Oram Sent: Wednesday, September 7, 2022 4:51 PM To: Benjamin Doron ; devel@edk2.groups.io Cc: Desimone, Nathaniel L ; Sinha, Ankit ; Ni, Ray ; Chaganty, Rangasai V Subject: Re: [edk2-devel][edk2-platforms][PATCH v2 3/6] IntelSiliconPkg/Fea= ture/SmmControl: Implement PPI with chipset support Reviewed-by: Isaac Oram -----Original Message----- From: Benjamin Doron =20 Sent: Tuesday, September 6, 2022 10:02 AM To: devel@edk2.groups.io Cc: Desimone, Nathaniel L ; Sinha, Ankit ; Ni, Ray ; Chaganty, Rangasai V ; Oram, Isaac W Subject: [edk2-devel][edk2-platforms][PATCH v2 3/6] IntelSiliconPkg/Feature= /SmmControl: Implement PPI with chipset support S3 resume may require communication with SMM, for which we need the SmmCont= rol PPI. Therefore, port the DXE drivers to a library, like there is for SM= M Access. Tested, working on Kabylake. Further testing required after the refactor fo= r compatibility. Cc: Nate DeSimone Cc: Ankit Sinha Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Isaac Oram Signed-off-by: Benjamin Doron --- .../PeiSmmControlLib/PeiSmmControlLib.c | 309 ++++++++++++++++++ .../PeiSmmControlLib/PeiSmmControlLib.inf | 34 ++ .../Include/Library/SmmControlLib.h | 26 ++ .../Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 4 + 4 files changed, 373 insertions(+) create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Librar= y/PeiSmmControlLib/PeiSmmControlLib.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Librar= y/PeiSmmControlLib/PeiSmmControlLib.inf create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Library/SmmContro= lLib.h diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSm= mControlLib/PeiSmmControlLib.c b/Silicon/Intel/IntelSiliconPkg/Feature/SmmC= ontrol/Library/PeiSmmControlLib/PeiSmmControlLib.c new file mode 100644 index 000000000000..cc6c7f8fe672 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmCon +++ trolLib/PeiSmmControlLib.c @@ -0,0 +1,309 @@ +/** @file+ This is to publish the SMM Control Ppi instance.++ Copyright = (c) 2019 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License= -Identifier: BSD-2-Clause-Patent++**/+#include +#inclu= de +#include +#include +#include +#include ++#include +#include ++#def= ine SMM_CONTROL_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('i', '4', 's', 'c')++= typedef struct {+ UINTN Signature;+ EFI_HANDLE = Handle;+ EFI_PEI_MM_CONTROL_PPI SmmControl;+= } SMM_CONTROL_PRIVATE_DATA;++#define SMM_CONTROL_PRIVATE_DATA_FROM_THIS(a) = \+ CR (a, \+ SMM_CONTROL_PRIVATE_DATA, \+ SmmContr= ol, \+ SMM_CONTROL_DEV_SIGNATURE \+ )++//+// Common registers= :+//+//+// APM Registers+//+#define R_PCH_APM_CNT = 0xB2+//+// ACPI and legacy I/O register offsets from ACPIBASE+//+#define= R_PCH_ACPI_PM1_STS 0x00+#define B_PCH_ACPI_PM1_STS_= PRBTNOR BIT11++#define R_PCH_SMI_EN = 0x30++#define R_PCH_SMI_STS 0x34+#define B= _PCH_SMI_STS_APM BIT5+#define B_PCH_SMI_EN_APMC = BIT5+#define B_PCH_SMI_EN_EOS = BIT1+#define B_PCH_SMI_EN_GBL_SMI BIT0++/**+ Trigger= the software SMI++ @param[in] Data The value to be set on= the software SMI data port++ @retval EFI_SUCCESS Function com= pletes successfully+**/+EFI_STATUS+EFIAPI+SmmTrigger (+ UINT8 Data+ )+{= + UINT16 ABase;+ UINT32 OutputData;+ UINT32 OutputPort;++ ABase =3D = FixedPcdGet16 (PcdAcpiBaseAddress);++ ///+ /// Enable the APMC SMI+ ///+= OutputPort =3D ABase + R_PCH_SMI_EN;+ OutputData =3D IoRead32 ((UINTN)= OutputPort);+ OutputData |=3D (B_PCH_SMI_EN_APMC | B_PCH_SMI_EN_GBL_SMI);= + DEBUG (+ (DEBUG_EVENT,+ "The SMI Control Port at address %x will = be written to %x.\n",+ OutputPort,+ OutputData)+ );+ IoWrite32 = (+ (UINTN) OutputPort,+ (UINT32) (OutputData)+ );++ OutputPort = =3D R_PCH_APM_CNT;+ OutputData =3D Data;++ ///+ /// Generate the APMC S= MI+ ///+ IoWrite8 (+ (UINTN) OutputPort,+ (UINT8) (OutputData)+ = );++ return EFI_SUCCESS;+}++/**+ Clear the SMI status+++ @retval EFI_SUC= CESS The function completes successfully+ @retval EFI_DEVICE_E= RROR Something error occurred+**/+EFI_STATUS+EFIAPI+SmmClear (+ VOI= D+ )+{+ UINT16 ABase;+ UINT32 OutputData;+ UINT32 OutputPort;++ ABa= se =3D FixedPcdGet16 (PcdAcpiBaseAddress);++ ///+ /// Clear the Power But= ton Override Status Bit, it gates EOS from being set.+ ///+ OutputPort = =3D ABase + R_PCH_ACPI_PM1_STS;+ OutputData =3D B_PCH_ACPI_PM1_STS_PRBTNO= R;+ DEBUG (+ (DEBUG_EVENT,+ "The PM1 Status Port at address %x will= be written to %x.\n",+ OutputPort,+ OutputData)+ );+ IoWrite16= (+ (UINTN) OutputPort,+ (UINT16) (OutputData)+ );++ ///+ /// Cl= ear the APM SMI Status Bit+ ///+ OutputPort =3D ABase + R_PCH_SMI_STS;+ = OutputData =3D B_PCH_SMI_STS_APM;+ DEBUG (+ (DEBUG_EVENT,+ "The S= MI Status Port at address %x will be written to %x.\n",+ OutputPort,+ = OutputData)+ );+ IoWrite32 (+ (UINTN) OutputPort,+ (UINT32) (O= utputData)+ );++ ///+ /// Set the EOS Bit+ ///+ OutputPort =3D ABas= e + R_PCH_SMI_EN;+ OutputData =3D IoRead32 ((UINTN) OutputPort);+ Output= Data |=3D B_PCH_SMI_EN_EOS;+ DEBUG (+ (DEBUG_EVENT,+ "The SMI Contr= ol Port at address %x will be written to %x.\n",+ OutputPort,+ Outp= utData)+ );+ IoWrite32 (+ (UINTN) OutputPort,+ (UINT32) (OutputDa= ta)+ );++ ///+ /// There is no need to read EOS back and check if it i= s set.+ /// This can lead to a reading of zero if an SMI occurs right afte= r the SMI_EN port read+ /// but before the data is returned to the CPU.+ = /// SMM Dispatcher should make sure that EOS is set after all SMI sources a= re processed.+ ///+ return EFI_SUCCESS;+}++/**+ This routine generates a= n SMI++ @param[in] This The EFI SMM Control protocol= instance+ @param[in, out] ArgumentBuffer The buffer of argument+ = @param[in, out] ArgumentBufferSize The size of the argument buffer+ @pa= ram[in] Periodic Periodic or not+ @param[in] ActivationI= nterval Interval of periodic SMI++ @retval EFI Status = Describing the result of the operation+ @retval EFI_INVALID_PARAMET= ER Some parameter value passed is not supported+**/+EFI_STATUS+EFIA= PI+Activate (+ IN EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_C= ONTROL_PPI * This,+ IN OUT INT8 *ArgumentBuffer OPTIONAL,+= IN OUT UINTN *ArgumentBufferSize OPTIONAL,+ IN BOOLEAN = Periodic OPTIONAL,+ IN UINTN ActivationInte= rval OPTIONAL+ )+{+ EFI_STATUS Status;+ UINT8 Data;++ if (Period= ic) {+ DEBUG ((DEBUG_WARN, "Invalid parameter\n"));+ return EFI_INVAL= ID_PARAMETER;+ }++ // NOTE: Copied from Quark. Matches the usage in PiSmm= CommunicationPei+ if (ArgumentBuffer =3D=3D NULL) {+ Data =3D 0xFF;+ }= else {+ if (ArgumentBufferSize =3D=3D NULL || *ArgumentBufferSize !=3D = 1) {+ return EFI_INVALID_PARAMETER;+ }++ Data =3D *ArgumentBuffe= r;+ }+ ///+ /// Clear any pending the APM SMI+ ///+ Status =3D SmmClea= r ();+ if (EFI_ERROR (Status)) {+ return Status;+ }++ return SmmTrigg= er (Data);+}++/**+ This routine clears an SMI++ @param[in] This = The EFI SMM Control protocol instance+ @param[in] Periodic = Periodic or not++ @retval EFI Status Describing the resul= t of the operation+ @retval EFI_INVALID_PARAMETER Some parameter value p= assed is not supported+**/+EFI_STATUS+EFIAPI+Deactivate (+ IN EFI_PEI_SERV= ICES **PeiServices,+ IN EFI_PEI_MM_CONTROL_PPI * This,+ IN BOOLEA= N Periodic OPTIONAL+ )+{+ if (Periodic) {+ return EFI_= INVALID_PARAMETER;+ }++ return SmmClear ();+}++/**+ This function is to = install an SMM Control PPI+ - Introduction \n+ An API to install= an instance of EFI_PEI_MM_CONTROL_PPI. This PPI provides a standard+ wa= y for other modules to trigger software SMIs.++ @retval EFI_SUCCESS = - Ppi successfully started and installed.+ @retval EFI_NOT_FOUND = - Ppi can't be found.+ @retval EFI_OUT_OF_RESOURCES - Ppi does n= ot have enough resources to initialize the driver.+**/+EFI_STATUS+EFIAPI+Pe= iInstallSmmControlPpi (+ VOID+ )+{+ EFI_STATUS Stat= us;+ EFI_PEI_PPI_DESCRIPTOR *PpiList;+ SMM_CONTROL_PRIVATE_DATA = *SmmControlPrivate;++ //+ // Initialize private data+ //+ SmmCon= trolPrivate =3D AllocateZeroPool (sizeof (*SmmControlPrivate));+ ASSERT (= SmmControlPrivate !=3D NULL);+ if (SmmControlPrivate =3D=3D NULL) {+ re= turn EFI_OUT_OF_RESOURCES;+ }+ PpiList =3D AllocateZeroPool (si= zeof (*PpiList));+ ASSERT (PpiList !=3D NULL);+ if (PpiList =3D=3D NULL) = {+ return EFI_OUT_OF_RESOURCES;+ }++ SmmControlPrivate->Signature =3D = SMM_CONTROL_PRIVATE_DATA_SIGNATURE;+ SmmControlPrivate->Handle =3D NULL= ;++ SmmControlPrivate->SmmControl.Trigger =3D Activate;+ SmmControlPriva= te->SmmControl.Clear =3D Deactivate;++ //+ // Install PPI+ //+ PpiLi= st->Flags =3D (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST);+ PpiList->Guid =3D &gEfiPeiMmControlPpiGuid;+ PpiList->Ppi = =3D &SmmControlPrivate->SmmControl;++ Status =3D PeiServicesInst= allPpi (PpiList);+ ASSERT_EFI_ERROR (Status);++ // Unlike driver, do not = disable SMIs as S3 resume continues+ return EFI_SUCCESS;+}diff --git a/Sil= icon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiS= mmControlLib.inf b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library= /PeiSmmControlLib/PeiSmmControlLib.inf new file mode 100644 index 000000000000..91c761366446 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmCon +++ trolLib/PeiSmmControlLib.inf @@ -0,0 +1,34 @@ +## @file+# Library description file for the SmmControl PPI+#+# Copyright (= c) 2019, Intel Corporation. All rights reserved.
+# SPDX-License-Identif= ier: BSD-2-Clause-Patent+#+##++[Defines]+ INF_VERSION = =3D 0x00010017+ BASE_NAME =3D PeiSmmControlLib+ FILE= _GUID =3D F45D521A-C0DF-4283-A3CA-65AD01B479E7+ VERSI= ON_STRING =3D 1.0+ MODULE_TYPE =3D PEIM= + LIBRARY_CLASS =3D SmmControlLib++[LibraryClasses]+ IoL= ib+ DebugLib+ MemoryAllocationLib+ PeiServicesLib++[Packages]+ MdePkg/M= dePkg.dec+ IntelSiliconPkg/IntelSiliconPkg.dec++[Sources]+ PeiSmmControlL= ib.c++[Pcd]+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUME= S++[Ppis]+ gEfiPeiMmControlPpiGuid ## PRODUCESd= iff --git a/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h b= /Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h new file mode 100644 index 000000000000..b532dd13f373 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h @@ -0,0 +1,26 @@ +/** @file+ This is to publish the SMM Control Ppi instance.++ Copyright = (c) 2019 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License= -Identifier: BSD-2-Clause-Patent++**/+#ifndef _SMM_CONTROL_LIB_H_+#define _= SMM_CONTROL_LIB_H_++/**+ This function is to install an SMM Control PPI+ = - Introduction \n+ An API to install an instance of EFI_PEI_MM_CO= NTROL_PPI. This PPI provides a standard+ way for other modules to trigge= r software SMIs.++ @retval EFI_SUCCESS - Ppi successfully star= ted and installed.+ @retval EFI_NOT_FOUND - Ppi can't be found.+= @retval EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to i= nitialize the driver.+**/+EFI_STATUS+EFIAPI+PeiInstallSmmControlPpi (+ VOI= D+ );+#endifdiff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec= b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec index deefdc55b5d6..440c7d0255ce 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -35,6 +35,10 @@ # SmmAccessLib|Include/Library/SmmAccessLib.h + ## @libraryclass Prov= ides services to trigger SMI+ #+ SmmControlLib|Include/Library/SmmControl= Lib.h+ ## @libraryclass Provides services to access config block # Co= nfigBlockLib|Include/Library/ConfigBlockLib.h--=20 2.37.2