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Thread-Topic: [PATCH] FIX MinPlatformPkg PCIE Base Addess avoid thunking operation. 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Ali, I don't understand what "thunking the address" means. The old code was typ= ecasting the address which could truncate it. In my experience, when peopl= e say thunk, they refer to a processor environment switch, eg from 64b to 3= 2b. Other uses should probably be avoided or at least clearly defined. Pl= ease provide a clearer description for this change in patch V2. The prior code behavior was to make the limit 4GB if the PCIE base address = is over 4GB. I suspect that this was intended. Your change would make the limit just under the PCIE base address. The dif= ference is to make the limit above 4GB if the PCIE base is above 4GB. I am not an expert on this, but the data structure seems to be trying to de= fine a range below 4GB and there are different ranges for above 4GB. And t= hat matches my understanding of the way devices request and we allocate PCI= resources. If this range is intended to be allowed to span above 4GB, we = probably should comment the data structure definitions to better explain th= at. I further note that the original design seems hacky and confusing. It is e= ssentially "if the board didn't specify the end, just hack it to PCIE Base = or 4GB, whichever is lower." I say hack because there is nothing to guaran= tee that none of that space is in use and comments aren't clear that the tr= uncation is functionally important. =20 1. I don't think that matches the MinPlatform intent to have simple code th= at is easy to understand. 2. I don't think it is good to have two mechanisms for the same thing. Let= 's just always tell people they must set the base and limit. 3. I don't see a reason to allow people to explicitly tie the PCIE resource= window to the PCIE base address. 4. I don't think it is good for the range limit to be 4GB or above, as ther= e are almost always other items near 4GB. APIC and flash, etc. Please change the code to something like: if (PcdGet32(PcdPciReservedMemLimit) <=3D PcdGet32 (PcdPciReservedMemBase= )) { DEBUG ((DEBUG_ERROR, "PciHostBridge: PCIE below 4GB memory range invali= d limit\n")); ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); *Count =3D 0; return RootBridge; } mRootBridgeTemplate.Mem.Base =3D PcdGet32 (PcdPciReservedMemBase); mRootBridgeTemplate.Mem.Limit =3D PcdGet32 (PcdPciReservedMemLimit);=20 (note this code is not tested and is intended to be pseudo-code, also note = that some error checking on the other ranges would be good too.) And update the PCD definitions to remove the comments indicating the limit = is optional and PcdPciExpressBaseAddress will be used if 0. Thanks, Isaac -----Original Message----- From: S, Ashraf Ali =20 Sent: Sunday, September 18, 2022 10:53 PM To: devel@edk2.groups.io Cc: S, Ashraf Ali ; Ni, Ray ; Cha= ganty, Rangasai V ; Oram, Isaac W ; Chiu, Chasel ; Desimone, Nathaniel L= ; Gao, Liming ; = Dong, Eric Subject: [PATCH] FIX MinPlatformPkg PCIE Base Addess avoid thunking operati= on. thunking the PCIE base address will cause the distruption in the execution = flow when the PCIE base address is 64bit bit. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4068 Signed-off-by: Ashraf Ali S Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Isaac Oram Cc: Chasel Chiu Cc: Nate DeSimone Cc: Isaac Oram Cc: Liming Gao Cc: Eric Dong --- .../Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimp= le/PciHostBridgeLibSimple.c b/Platform/Intel/MinPlatformPkg/Pci/Library/Pci= HostBridgeLibSimple/PciHostBridgeLibSimple.c index 0e3fee28b5..e38975eee5 100644 --- a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciH= ostBridgeLibSimple.c +++ b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/P +++ ciHostBridgeLibSimple.c @@ -90,7 +90,7 @@ PciHostBridgeGetRootBridges ( if (PcdGet32(PcdPciReservedMemLimit) !=3D 0) { mRootBridgeTemplate.Mem.Limit =3D PcdGet32 (PcdPciReservedMemLimit); } else { - mRootBridgeTemplate.Mem.Limit =3D (UINT32) PcdGet64 (PcdPciExpressBase= Address) - 1; + mRootBridgeTemplate.Mem.Limit =3D PcdGet64 (PcdPciExpressBaseAddress)= =20 + - 1; } =20 mRootBridgeTemplate.MemAbove4G.Base =3D PcdGet64 (PcdPciReservedMemAbove= 4GBBase); -- 2.30.2.windows.1