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charset="us-ascii" Content-Transfer-Encoding: quoted-printable I think that the shim lib might be overkill. PmcGetAcpiBase just resolves = to PcdGet16 (PcdAcpiBaseAddress); I think that you should be able to use that PCD for any Intel chipset/silic= on for the foreseeable future. I would prefer to see contents of sections in INF files indented, but it is= a nit. Regards, Isaac -----Original Message----- From: devel@edk2.groups.io On Behalf Of Benjamin Dor= on Sent: Monday, August 29, 2022 1:36 PM To: devel@edk2.groups.io Cc: Desimone, Nathaniel L ; Sinha, Ankit ; Ni, Ray ; Chaganty, Rangasai V ; Oram, Isaac W Subject: [edk2-devel][edk2-platforms][PATCH v1 2/5] Silicon/Intel: Port Smm= Control protocol to PPI for S3 S3 resume may require communication with SMM, for which we need the SmmCont= rol PPI. Therefore, port the DXE drivers to a library, like there is for SM= M Access. As the registers are common across Intel platforms in the tree, while a hel= per function definition is not, implement a new library as a compatibility = shim. Tested, working on Kabylake. Further testing required after the refactor fo= r compatibility. Cc: Nate DeSimone Cc: Ankit Sinha Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Isaac Oram Signed-off-by: Benjamin Doron --- .../BaseIntelCompatShimLibCfl.c | 24 ++ .../BaseIntelCompatShimLibCfl.inf | 24 ++ .../PeiSmmControlLib/PeiSmmControlLib.c | 309 ++++++++++++++++++ .../PeiSmmControlLib/PeiSmmControlLib.inf | 36 ++ .../Include/Library/IntelCompatShimLib.h | 20 ++ .../Include/Library/SmmControlLib.h | 26 ++ .../Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 4 + .../BaseIntelCompatShimLibKbl.c | 29 ++ .../BaseIntelCompatShimLibKbl.inf | 24 ++ 9 files changed, 496 insertions(+) create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCom= patShimLibCfl/BaseIntelCompatShimLibCfl.c create mode 100644 Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCom= patShimLibCfl/BaseIntelCompatShimLibCfl.inf create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Librar= y/PeiSmmControlLib/PeiSmmControlLib.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Librar= y/PeiSmmControlLib/PeiSmmControlLib.inf create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Library/IntelComp= atShimLib.h create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Library/SmmContro= lLib.h create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompa= tShimLibKbl/BaseIntelCompatShimLibKbl.c create mode 100644 Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompa= tShimLibKbl/BaseIntelCompatShimLibKbl.inf diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShim= LibCfl/BaseIntelCompatShimLibCfl.c b/Silicon/Intel/CoffeelakeSiliconPkg/Lib= rary/BaseIntelCompatShimLibCfl/BaseIntelCompatShimLibCfl.c new file mode 100644 index 000000000000..5353126267e6 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShimLibC +++ fl/BaseIntelCompatShimLibCfl.c @@ -0,0 +1,24 @@ +/** @file + A Coffeelake+ compatibility shim + + Copyright (c) 2022, Baruch Binyamin Doron
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +/** + Get PCH ACPI base address. + + @retval Address Address of PWRM base address. +**/ +UINT16 +EFIAPI +CompatShimGetAcpiBase ( + VOID + ) +{ + return PmcGetAcpiBase (); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShim= LibCfl/BaseIntelCompatShimLibCfl.inf b/Silicon/Intel/CoffeelakeSiliconPkg/L= ibrary/BaseIntelCompatShimLibCfl/BaseIntelCompatShimLibCfl.inf new file mode 100644 index 000000000000..48b071ed05ae --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseIntelCompatShimLibC +++ fl/BaseIntelCompatShimLibCfl.inf @@ -0,0 +1,24 @@ +## @file +# Library description file for the Coffeelake+ compatibility shim # #=20 +Copyright (c) 2022, Baruch Binyamin Doron
#=20 +SPDX-License-Identifier: BSD-2-Clause-Patent # ## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D BaseIntelCompatShimLibCfl +FILE_GUID =3D 3D0BB32E-D328-4615-ADFC-782CECC68D53 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D IntelCompatShimLib + +[LibraryClasses] +PmcLib + +[Packages] +CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] +BaseIntelCompatShimLibCfl.c diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSm= mControlLib/PeiSmmControlLib.c b/Silicon/Intel/IntelSiliconPkg/Feature/SmmC= ontrol/Library/PeiSmmControlLib/PeiSmmControlLib.c new file mode 100644 index 000000000000..80c2c1be90b1 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmCon +++ trolLib/PeiSmmControlLib.c @@ -0,0 +1,309 @@ +/** @file+ This is to publish the SMM Control Ppi instance.++ Copyright = (c) 2019 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License= -Identifier: BSD-2-Clause-Patent++**/+#include +#inclu= de +#include +#include +#include +#include ++#include +#include ++#define SMM_CONTROL_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('i', '4',= 's', 'c')++typedef struct {+ UINTN Signature;+ = EFI_HANDLE Handle;+ EFI_PEI_MM_CONTROL_PPI = SmmControl;+} SMM_CONTROL_PRIVATE_DATA;++#define SMM_CONTROL_PRIVATE_DATA_F= ROM_THIS(a) \+ CR (a, \+ SMM_CONTROL_PRIVATE_DATA, \+ = SmmControl, \+ SMM_CONTROL_DEV_SIGNATURE \+ )++//+// Comm= on registers:+//+//+// APM Registers+//+#define R_PCH_APM_CNT = 0xB2+//+// ACPI and legacy I/O register offsets from ACPIBAS= E+//+#define R_PCH_ACPI_PM1_STS 0x00+#define B_PCH_A= CPI_PM1_STS_PRBTNOR BIT11++#define R_PCH_SMI_EN = 0x30++#define R_PCH_SMI_STS 0x= 34+#define B_PCH_SMI_STS_APM BIT5+#define B_PCH_SMI= _EN_APMC BIT5+#define B_PCH_SMI_EN_EOS = BIT1+#define B_PCH_SMI_EN_GBL_SMI BIT0++/= **+ Trigger the software SMI++ @param[in] Data The value = to be set on the software SMI data port++ @retval EFI_SUCCESS = Function completes successfully+**/+EFI_STATUS+EFIAPI+SmmTrigger (+ UINT8 = Data+ )+{+ UINT16 ABase;+ UINT32 OutputData;+ UINT32 OutputPort;++= ABase =3D CompatShimGetAcpiBase ();++ ///+ /// Enable the APMC SMI+ //= /+ OutputPort =3D ABase + R_PCH_SMI_EN;+ OutputData =3D IoRead32 ((UINT= N) OutputPort);+ OutputData |=3D (B_PCH_SMI_EN_APMC | B_PCH_SMI_EN_GBL_SMI= );+ DEBUG (+ (DEBUG_EVENT,+ "The SMI Control Port at address %x wil= l be written to %x.\n",+ OutputPort,+ OutputData)+ );+ IoWrite3= 2 (+ (UINTN) OutputPort,+ (UINT32) (OutputData)+ );++ OutputPort = =3D R_PCH_APM_CNT;+ OutputData =3D Data;++ ///+ /// Generate the APMC = SMI+ ///+ IoWrite8 (+ (UINTN) OutputPort,+ (UINT8) (OutputData)+ = );++ return EFI_SUCCESS;+}++/**+ Clear the SMI status+++ @retval EFI_SU= CCESS The function completes successfully+ @retval EFI_DEVICE_= ERROR Something error occurred+**/+EFI_STATUS+EFIAPI+SmmClear (+ VO= ID+ )+{+ UINT16 ABase;+ UINT32 OutputData;+ UINT32 OutputPort;++ AB= ase =3D CompatShimGetAcpiBase ();++ ///+ /// Clear the Power Button Overr= ide Status Bit, it gates EOS from being set.+ ///+ OutputPort =3D ABase = + R_PCH_ACPI_PM1_STS;+ OutputData =3D B_PCH_ACPI_PM1_STS_PRBTNOR;+ DEBUG= (+ (DEBUG_EVENT,+ "The PM1 Status Port at address %x will be writte= n to %x.\n",+ OutputPort,+ OutputData)+ );+ IoWrite16 (+ (UI= NTN) OutputPort,+ (UINT16) (OutputData)+ );++ ///+ /// Clear the AP= M SMI Status Bit+ ///+ OutputPort =3D ABase + R_PCH_SMI_STS;+ OutputDat= a =3D B_PCH_SMI_STS_APM;+ DEBUG (+ (DEBUG_EVENT,+ "The SMI Status = Port at address %x will be written to %x.\n",+ OutputPort,+ OutputD= ata)+ );+ IoWrite32 (+ (UINTN) OutputPort,+ (UINT32) (OutputData)= + );++ ///+ /// Set the EOS Bit+ ///+ OutputPort =3D ABase + R_PCH_= SMI_EN;+ OutputData =3D IoRead32 ((UINTN) OutputPort);+ OutputData |=3D = B_PCH_SMI_EN_EOS;+ DEBUG (+ (DEBUG_EVENT,+ "The SMI Control Port at= address %x will be written to %x.\n",+ OutputPort,+ OutputData)+ = );+ IoWrite32 (+ (UINTN) OutputPort,+ (UINT32) (OutputData)+ );= ++ ///+ /// There is no need to read EOS back and check if it is set.+ /= // This can lead to a reading of zero if an SMI occurs right after the SMI_= EN port read+ /// but before the data is returned to the CPU.+ /// SMM Di= spatcher should make sure that EOS is set after all SMI sources are process= ed.+ ///+ return EFI_SUCCESS;+}++/**+ This routine generates an SMI++ @= param[in] This The EFI SMM Control protocol instance+= @param[in, out] ArgumentBuffer The buffer of argument+ @param[in,= out] ArgumentBufferSize The size of the argument buffer+ @param[in] Pe= riodic Periodic or not+ @param[in] ActivationInterval = Interval of periodic SMI++ @retval EFI Status Des= cribing the result of the operation+ @retval EFI_INVALID_PARAMETER = Some parameter value passed is not supported+**/+EFI_STATUS+EFIAPI+Activat= e (+ IN EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_CONTROL_PPI= * This,+ IN OUT INT8 *ArgumentBuffer OPTIONAL,+ IN OUT U= INTN *ArgumentBufferSize OPTIONAL,+ IN BOOLEAN = Periodic OPTIONAL,+ IN UINTN ActivationInterval OPTIO= NAL+ )+{+ EFI_STATUS Status;+ UINT8 Data;++ if (Periodic) {+ = DEBUG ((DEBUG_WARN, "Invalid parameter\n"));+ return EFI_INVALID_PARAMET= ER;+ }++ // NOTE: Copied from Quark. Matches the usage in PiSmmCommunicat= ionPei+ if (ArgumentBuffer =3D=3D NULL) {+ Data =3D 0xFF;+ } else {+ = if (ArgumentBufferSize =3D=3D NULL || *ArgumentBufferSize !=3D 1) {+ = return EFI_INVALID_PARAMETER;+ }++ Data =3D *ArgumentBuffer;+ }+ /= //+ /// Clear any pending the APM SMI+ ///+ Status =3D SmmClear ();+ if= (EFI_ERROR (Status)) {+ return Status;+ }++ return SmmTrigger (Data);= +}++/**+ This routine clears an SMI++ @param[in] This The= EFI SMM Control protocol instance+ @param[in] Periodic Period= ic or not++ @retval EFI Status Describing the result of the o= peration+ @retval EFI_INVALID_PARAMETER Some parameter value passed is n= ot supported+**/+EFI_STATUS+EFIAPI+Deactivate (+ IN EFI_PEI_SERVICES = **PeiServices,+ IN EFI_PEI_MM_CONTROL_PPI * This,+ IN BOOLEAN = Periodic OPTIONAL+ )+{+ if (Periodic) {+ return EFI_INVALID_PA= RAMETER;+ }++ return SmmClear ();+}++/**+ This function is to install an= SMM Control PPI+ - Introduction \n+ An API to install an instan= ce of EFI_PEI_MM_CONTROL_PPI. This PPI provides a standard+ way for othe= r modules to trigger software SMIs.++ @retval EFI_SUCCESS - Pp= i successfully started and installed.+ @retval EFI_NOT_FOUND - P= pi can't be found.+ @retval EFI_OUT_OF_RESOURCES - Ppi does not have en= ough resources to initialize the driver.+**/+EFI_STATUS+EFIAPI+PeiInstallSm= mControlPpi (+ VOID+ )+{+ EFI_STATUS Status;+ EFI_= PEI_PPI_DESCRIPTOR *PpiList;+ SMM_CONTROL_PRIVATE_DATA *Sm= mControlPrivate;++ //+ // Initialize private data+ //+ SmmControlPrivat= e =3D AllocateZeroPool (sizeof (*SmmControlPrivate));+ ASSERT (SmmControl= Private !=3D NULL);+ if (SmmControlPrivate =3D=3D NULL) {+ return EFI_O= UT_OF_RESOURCES;+ }+ PpiList =3D AllocateZeroPool (sizeof (*Ppi= List));+ ASSERT (PpiList !=3D NULL);+ if (PpiList =3D=3D NULL) {+ retu= rn EFI_OUT_OF_RESOURCES;+ }++ SmmControlPrivate->Signature =3D SMM_CONTRO= L_PRIVATE_DATA_SIGNATURE;+ SmmControlPrivate->Handle =3D NULL;++ SmmCo= ntrolPrivate->SmmControl.Trigger =3D Activate;+ SmmControlPrivate->SmmCon= trol.Clear =3D Deactivate;++ //+ // Install PPI+ //+ PpiList->Flags = =3D (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);+= PpiList->Guid =3D &gEfiPeiMmControlPpiGuid;+ PpiList->Ppi =3D &SmmC= ontrolPrivate->SmmControl;++ Status =3D PeiServicesInstallPpi (Pp= iList);+ ASSERT_EFI_ERROR (Status);++ // Unlike driver, do not disable SM= Is as S3 resume continues+ return EFI_SUCCESS;+}diff --git a/Silicon/Intel= /IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlL= ib.inf b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmCon= trolLib/PeiSmmControlLib.inf new file mode 100644 index 000000000000..92f2879d82ab --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmCon +++ trolLib/PeiSmmControlLib.inf @@ -0,0 +1,36 @@ +## @file+# Library description file for the SmmControl PPI+#+#=20 +Copyright (c) 2019, Intel Corporation. All rights reserved.
+#=20 +SPDX-License-Identifier:=20 +BSD-2-Clause-Patent+#+##++[Defines]+INF_VERSION =3D 0x00010017+BASE_NAME=20 +=3D PeiSmmControlLib+FILE_GUID =3D=20 +F45D521A-C0DF-4283-A3CA-65AD01B479E7+VERSION_STRING =3D 1.0+MODULE_TYPE = =3D=20 +PEIM+LIBRARY_CLASS =3D=20 +SmmControlLib+++[LibraryClasses]+IntelCompatShimLib+IoLib+DebugLib+Memo +ryAllocationLib+PeiServicesLib+++[Packages]+MdePkg/MdePkg.dec+IntelSili +conPkg/IntelSiliconPkg.dec+++[Sources]+PeiSmmControlLib.c+++[Ppis]+gEfi +PeiMmControlPpiGuid ## PRODUCESdiff --git=20 +a/Silicon/Intel/IntelSiliconPkg/Include/Library/IntelCompatShimLib.h=20 +b/Silicon/Intel/IntelSiliconPkg/Include/Library/IntelCompatShimLib.h new file mode 100644 index 000000000000..f8621d92e41a --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/IntelCompatShimLib.h @@ -0,0 +1,20 @@ +/** @file + Library description file for compatibility shim + + Copyright (c) 2022, Baruch Binyamin Doron
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +/** + Get PCH ACPI base address. + + @retval Address Address of PWRM base address. +**/ +UINT16 +EFIAPI +CompatShimGetAcpiBase ( + VOID + ); diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h = b/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h new file mode 100644 index 000000000000..b532dd13f373 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h @@ -0,0 +1,26 @@ +/** @file+ This is to publish the SMM Control Ppi instance.++ Copyright = (c) 2019 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License= -Identifier: BSD-2-Clause-Patent++**/+#ifndef _SMM_CONTROL_LIB_H_+#define _= SMM_CONTROL_LIB_H_++/**+ This function is to install an SMM Control PPI+ = - Introduction \n+ An API to install an instance of EFI_PEI_MM_CO= NTROL_PPI. This PPI provides a standard+ way for other modules to trigge= r software SMIs.++ @retval EFI_SUCCESS - Ppi successfully star= ted and installed.+ @retval EFI_NOT_FOUND - Ppi can't be found.+= @retval EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to i= nitialize the driver.+**/+EFI_STATUS+EFIAPI+PeiInstallSmmControlPpi (+ VOI= D+ );+#endifdiff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec= b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec index c36d130a0197..fc27b394d267 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -35,6 +35,10 @@ # SmmAccessLib|Include/Library/SmmAccessLib.h + ## @libraryclass Prov= ides services to trigger SMI+ #+ SmmControlLib|Include/Library/SmmControl= Lib.h+ ## @libraryclass Provides services to access config block # Co= nfigBlockLib|Include/Library/ConfigBlockLib.hdiff --git a/Silicon/Intel/Kab= ylakeSiliconPkg/Library/BaseIntelCompatShimLibKbl/BaseIntelCompatShimLibKbl= .c b/Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLibKbl/Bas= eIntelCompatShimLibKbl.c new file mode 100644 index 000000000000..573f67555aa3 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLibKbl +++ /BaseIntelCompatShimLibKbl.c @@ -0,0 +1,29 @@ +/** @file + A Kabylake compatibility shim + + Copyright (c) 2022, Baruch Binyamin Doron
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +/** + Get PCH ACPI base address. + + @retval Address Address of PWRM base address. +**/ +UINT16 +EFIAPI +CompatShimGetAcpiBase ( + VOID + ) +{ + UINT16 Address; + + Address =3D 0; + PchAcpiBaseGet (&Address); + + return Address; +} diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLi= bKbl/BaseIntelCompatShimLibKbl.inf b/Silicon/Intel/KabylakeSiliconPkg/Libra= ry/BaseIntelCompatShimLibKbl/BaseIntelCompatShimLibKbl.inf new file mode 100644 index 000000000000..af3e5a4726e6 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/BaseIntelCompatShimLibKbl +++ /BaseIntelCompatShimLibKbl.inf @@ -0,0 +1,24 @@ +## @file +# Library description file for the Kabylake compatibility shim # #=20 +Copyright (c) 2022, Baruch Binyamin Doron
#=20 +SPDX-License-Identifier: BSD-2-Clause-Patent # ## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D BaseIntelCompatShimLibKbl +FILE_GUID =3D B4A2193E-CF3E-46E6-8617-49E48143B5AB +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D IntelCompatShimLib + +[LibraryClasses] +PchCycleDecodingLib + +[Packages] +KabylakeSiliconPkg/SiPkg.dec + +[Sources] +BaseIntelCompatShimLibKbl.c -- 2.37.2 -=3D-=3D-=3D-=3D-=3D-=3D Groups.io Links: You receive all messages sent to this group. View/Reply Online (#92921): https://edk2.groups.io/g/devel/message/92921 Mute This Topic: https://groups.io/mt/93335519/1492418 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [isaac.w.oram@intel.com] -=3D-=3D-=3D-=3D-=3D-=3D