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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Pushed as 3b896d1a32..e9c5be65fe -----Original Message----- From: devel@edk2.groups.io On Behalf Of Oram, Isaac = W Sent: Friday, June 3, 2022 1:01 PM To: Ponnusamy, Suresh ; devel@edk2.groups.io Cc: Desimone, Nathaniel L ; KARPAGAVINAYAGA= M, MANICKAVASAKAM ; DOPPALAPUDI, HARIKRISHNA ; Bobroff, Zachary Subject: Re: [edk2-devel] [edk2-platfoms][PATCH V1] WhitleyOpenBoardPkg : S= upport for Aowanda Platform Reviewed-by: Isaac Oram Note that if you start a board port from the WhitleyOpenBoardPkg/BoardPortT= emplate, there is not as much function renaming required inside UBA DXE. B= y no means required, but it would reduce noise if you are making similar bo= ard ports and want to be able to diff with less noise. -----Original Message----- From: Sureshkumar Ponnusamy =20 Sent: Friday, June 3, 2022 11:13 AM To: devel@edk2.groups.io Cc: Desimone, Nathaniel L ; Oram, Isaac W <= isaac.w.oram@intel.com>; KARPAGAVINAYAGAM, MANICKAVASAKAM ; DOPPALAPUDI, HARIKRISHNA ; Bobroff, Zachary= Subject: [edk2-platfoms][PATCH V1] WhitleyOpenBoardPkg : Support for Aowand= a Platform - Created UBA for Aowanda platform - Disabled Intel ME IDE-R devices, KT devices to reduce BIOS POST time - Modified build configuration file to support Aowanda platform build Cc: Nate DeSimone Cc: Isaac Oram Cc: Manickavasakam Karpagavinayagam Cc: Harikrishna Doppalapudi Cc: Sureshkumar Ponnusamy Cc: Zachary Bobroff Signed-off-by: Sureshkumar Ponnusamy --- Platform/Intel/Readme.md = | 908 +++++----- Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/IpmiPlatformHookLib/Ipm= iPlatformHookLib.c | 47 + Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/IpmiPlatformHookLib/Ipm= iPlatformHookLib.inf | 32 + Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/PeiPlatformHookLib/PeiP= latformHooklib.c | 93 + Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/PeiPlatformHookLib/PeiP= latformHooklib.inf | 35 + Platform/Intel/WhitleyOpenBoardPkg/Aowanda/PlatformPkg.dsc = | 82 + Platform/Intel/WhitleyOpenBoardPkg/Aowanda/PlatformPkg.fdf = | 827 +++++++++ Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/IioCfgUpdat= eDxe/IioCfgUpdateDxe.c | 99 ++ Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/IioCfgUpdat= eDxe/IioCfgUpdateDxe.h | 99 ++ Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/IioCfgUpdat= eDxe/IioCfgUpdateDxe.inf | 49 + Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/SlotDataUpd= ateDxe/SlotDataUpdateDxe.c | 112 ++ Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/SlotDataUpd= ateDxe/SlotDataUpdateDxe.h | 57 + Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/SlotDataUpd= ateDxe/SlotDataUpdateDxe.inf | 49 + Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/UsbOcUpdate= Dxe/UsbOcUpdateDxe.c | 128 ++ Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/UsbOcUpdate= Dxe/UsbOcUpdateDxe.h | 24 + Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/UsbOcUpdate= Dxe/UsbOcUpdateDxe.inf | 45 + Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/AcpiTablePc= ds.c | 54 + Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/GpioTable.c= | 329 ++++ Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/IioBifurIni= t.c | 186 ++ Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/KtiEparam.c= | 86 + Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PcdData.c = | 382 +++++ Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PchEarlyUpd= ate.c | 82 + Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PeiBoardIni= t.h | 77 + Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PeiBoardIni= tLib.c | 154 ++ Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PeiBoardIni= tLib.inf | 167 ++ Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/SlotTable.c= | 167 ++ Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/SoftStrapFi= xup.c | 73 + Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/UsbOC.c = | 124 ++ Platform/Intel/WhitleyOpenBoardPkg/Aowanda/build_board.py = | 195 +++ Platform/Intel/WhitleyOpenBoardPkg/Aowanda/build_config.cfg = | 52 + Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec = | 1813 ++++++++++---------- Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c = | 226 +-- Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf = | 145 +- Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuD= ataDxe.inf | 120 +- Platform/Intel/build.cfg = | 141 +- Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h = | 229 +-- 36 files changed, 5713 insertions(+), 1775 deletions(-) diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index 6f055f2524..bfd784fe49 100644 --- a/Platform/Intel/Readme.md +++ b/Platform/Intel/Readme.md @@ -1,446 +1,462 @@ -# **EDK II Minimum Platform Firmware for Intel® Platforms** - -The Minimum Platform is a software architecture that guides uniform delive= ry of Intel platforms enabling firmware -solutions for basic boot functionality with extensibility built-in. Please= see the -[EDK II Minimum Platform Draft Specification](https://edk2-docs.gitbooks.i= o/edk-ii-minimum-platform-specification/) -for more details. - -Package maintainers for the Minimum Platform projects are listed in Mainta= iners.txt. - -## Overview -The key elements of the architecture are organized into a staged boot appr= oach where each stage has requirements and -functionality for specific use cases. The generic control flow through the= boot process is implemented in the -[`MinPlatformPkg`](https://github.com/tianocore/edk2-platforms/tree/master= /Platform/Intel/MinPlatformPkg). -The generic nature of the tasks performed in MinPlatformPkg lends to reuse= across all Intel platforms with no -source modification. Details for any particular board are made accessible = to the MinPlatformPkg through a well-defined -statically linked board API. A complete platform solution then consists of= the MinPlatformPkg and a compatible board -package. - -## Board Naming Convention -The board packages supported by Intel follow the naming convention \= OpenBoardPkg where xxx refers to the -encompassing platform name for a particular platform generation. For examp= le, the [`KabylakeOpenBoardPkg`](https://github.com/tianocore/edk2-platform= s/tree/master/Platform/Intel/KabylakeOpenBoardPkg) contains the -board code for Intel KabyLake reference systems. Intel uses the moniker "O= penBoardPkg" to indicate that this package -is the open source board code. A closed source counterpart may exist which= simply uses "BoardPkg". Both directly use -the MinPlatformPkg from edk2-platforms. - -## Stage Selection -Stage selection is controlled via the PCD `gMinPlatformPkgTokenSpaceGuid.P= cdBootStage` in [`MinPlatformPkg.dec`](https://github.com/tianocore/edk2-pl= atforms/tree/master/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec). -The stage should be configured in the board package DSC file to the approp= riate value. For example, a board may disable -all advanced features by setting this value to 4 instead of 6. This may be= used to improve boot time for a particular -use case. Decrementing the stage can also be used for debug since only the= actions required for that stage objective -should be executed. As an example, ACPI initialization is not required for= a Stage 3 boot. - -The stages are defined as follows: - -| Stage | Functional Objective | Example Capabilities = | -| -------|------------------------------|---------------------------------= -------------------------------------------------------------------| -| I | Minimal Debug | Serial port output, source debug= enabled, hardware debugger enabled | -| II | Memory Functional | Basic hardware initialization ne= cessary to reach memory initialization, permanent memory available | -| III | Boot to UI | Simple console input and output = to a UI, UEFI shell | -| IV | Boot to OS | Boot an operating system with th= e minimally required features | -| V | Security Enable | UEFI Secure Boot, TCG measured b= oot, DMA protections | -| VI | Advanced Feature Enable | Firmware update, power managemen= t, non-essential I/O | - -## Minimum Platform Firmware Solution Stack -A UEFI firmware implementation using MinPlatformPkg is constructed using t= he following pieces. - -| | -|------------------------------------| -| [EDK II](https://github.com/tianocore/edk2) = | -| [Intel(r) FSP](https://github.com/IntelFsp/FSP) = | -| [Minimum Platform (`MinPlatformPkg`)](https://github.com/tianocore/edk2-= platforms/tree/master/Platform/Intel/MinPlatformPkg) = | -| [Board Support (\OpenBoardPkg)](https://github.com/tianocore/edk2-= platforms/tree/master/Platform/Intel) | - - -## Board Support -* The `KabylakeOpenBoardPkg` contains board implementations for KabyLake s= ystems. -* The `PurleyOpenBoardPkg` contains board implementations for Purley syste= ms. -* The `SimicsOpenBoardPkg` contains board implementations for the Simics h= ardware simulator. -* The `WhiskeylakeOpenBoardPkg` contains board implementations for Whiskey= Lake systems. -* The `CometlakeOpenBoardPkg` contains board implementations for CometLake= systems. -* The `TigerlakeOpenBoardPkg` contains board implementations for TigerLake= systems. -* The `WhitleyOpenBoardPkg` contains board implementations for Ice Lake-SP= and Cooper Lake systems. - -### **Supported Hardware** - -#### AAEON - -| Machine Name | Supported Chipsets = | BoardPkg | Board Name | -----------------------------------------|---------------------------------= -----------|------------------------------|--------------------| -| UP Xtreme | Whiskey Lake = | WhiskeylakeOpenBoardPkg | UpXtreme | - -#### Acer - -***Aspire VN7-572G Laptop*** - -| Machine Name | Supported Chipsets = | BoardPkg | Board Name | -----------------------------------------|---------------------------------= -----------|------------------------------|--------------------| -| Aspire VN7-572G | SkyLake = | KabylakeOpenBoardPkg | AspireVn7Dash572G | - -#### Intel - -***Intel Reference and Validation Platform*** - -| Machine Name | Supported Chipsets = | BoardPkg | Board Name | -----------------------------------------|---------------------------------= -----------|------------------------------|--------------------| -| RVP 3 | SkyLake, KabyLake, KabyLake Refr= esh | KabylakeOpenBoardPkg | KabylakeRvp3 | -| WHL-U DDR4 RVP | WhiskeyLake = | WhiskeylakeOpenBoardPkg | WhiskeylakeURvp | -| CML-U LPDDR3 RVP | CometLake V1 = | CometlakeOpenBoardPkg | CometlakeURvp | -| TGL-U DDR4 RVP | TigerLake = | TigerlakeOpenBoardPkg | TigerlakeURvp | -| Wilson City RVP | IceLake-SP (Xeon Scalable) = | WhitleyOpenBoardPkg | WilsonCityRvp | -| Cooper City RVP | Copper Lake = | WhitleyOpenBoardPkg | CooperCityRvp | - -*Note: RVP =3D Reference and Validation Platform* - -#### Open Compute Project (OCP) - -| Machine Name | Supported Chipsets = | BoardPkg | Board Name | -----------------------------------------|---------------------------------= -----------|------------------------------|--------------------| -| Junction City | IceLake-SP (Xeon Scalable) = | WhitleyOpenBoardPkg | JunctionCity | -| Mt. Olympus | Purley = | PurleyOpenBoardPkg | BoardMtOlympus | -| TiogaPass | Purley = | PurleyOpenBoardPkg | BoardTiogaPass | - - -#### Simics - -| Machine Name | Supported Chipsets = | BoardPkg | Board Name | -----------------------------------------|---------------------------------= -----------|------------------------------|--------------------| -| Simics Quick Start Package | Nehalem = | SimicsOpenBoardPkg | BoardX58Ich10 | - -#### System 76 - -***Galago Pro Laptop*** - -| Machine Name | Supported Chipsets = | BoardPkg | Board Name | -----------------------------------------|---------------------------------= -----------|------------------------------|--------------------| -| galp2 | KabyLake = | KabylakeOpenBoardPkg | GalagoPro3 | -| galp3 & galp3-b | KabyLake Refresh = | KabylakeOpenBoardPkg | GalagoPro3 | - -## Board Package Organization -The board package follows the standard EDK II package structure with the f= ollowing additional elements and guidelines: -* Only code usable across more than one board at the root level. -* Board-specific code in a directory. The directory name should match that= of the board supported. -* Features not essential to achieve stage 5 or earlier boots are maintaine= d in edk2-platforms/Features/Intel. - -Shared resources in the package root directory can include interfaces desc= ribed in header files, library instances, -firmware modules, binaries, etc. The UEFI firmware implementation is built= using the process described below from the -board-specific directory. - -A board package must implement the board APIs defined in the MinPlatformPk= g even if a "NULL" implementation is used to -return back to the minimum platform caller. - -## **Windows Build Instructions** - -### Pre-requisites - -* GIT client: Available from https://git-scm.com/downloads -* Microsoft Visual Studio. - - Visual Studio 2015 recommended and is used in the examples below. -* ASL compiler: Available from http://www.acpica.org - - Install into ```C:\ASL``` to match default tools_def.txt configuration= . -* NASM assembler: Available from: http://www.nasm.us/ - - Install into ```C:\NASM``` to match default tools_def.txt configuratio= n. -* Python 3.7.3: Available from: https://www.python.org/downloads/release/= python-373/ - - Other versions of Python 3.x should be compatible. - - It is recommended to use the Python launcher to ensure the Python buil= d script is launched using Python 3. - - E.g. "py -3.7 build_bios.py -l" - -## **Linux Build Instructions** - -### Pre-requisites - - * Set up a EDK II build environment for Linux following the instructions = in - [Using EDK II with Native GCC](https://github.com/tianocore/tianocore.g= ithub.io/wiki/Using-EDK-II-with-Native-GCC). - * Proceed to the [Common EDK II build instructions for Linux](https://git= hub.com/tianocore/tianocore.github.io/wiki/Common-instructions) - to verify your basic EDK II build environment is set up properly. - -### Download the required components - -1. Create a new directory for the EDK II WORKSPACE. - -2. Download below repository to this WORKSPACE: - -* edk2 repository - * ``git clone https://github.com/tianocore/edk2.git`` - -* edk2-platforms repository - * ``git clone https://github.com/tianocore/edk2-platforms.git`` - -* edk2-non-osi repository - * ``git clone https://github.com/tianocore/edk2-non-osi.git`` - -* FSP repository - * ``git clone https://github.com/IntelFsp/FSP.git`` - -### Board Builds - -**Building with the python script** - -1. Open command window, go to the workspace directory, e.g. c:\Edk2Workspa= ce or ~/Edk2Workspace in the case of a linux OS -2. If using a linux OS - * Type "cd edk2" - * Type "source edksetup.sh" - * Type "cd ../" to go back to the workspace directory -3. Type "cd edk2-platforms/Platform/Intel -4. Type "python build_bios.py -p REPLACE_WITH_BOARD_NAME" - -* build_bios.py arguments: - - | Argument | Function | - | ----------------------|-------------------------------------| - | -h, --help | show this help message and exit | - | --platform, -p | the platform to build | - | --toolchain, -t | tool Chain to use in build process | - | --DEBUG, -d | debug flag | - | --RELEASE, -r | release flag | - | --TEST_RELEASE, -tr | test Release flag | - | --RELEASE_PDB, -rp | release flag | - | --list, -l | lists available platforms | - | --cleanall | cleans all | - | --clean | cleans specified platform | - | --capsule | capsule build enabled | - | --silent | silent build enabled | - | --performance | performance build enabled | - | --fsp | fsp wrapper build enabled | - | --fspapi | API mode fsp wrapper build enabled | - | --hash | Enable hash-based caching | - | --binary-destination | create cache in specified directory | - | --binary-source | Consume cache from directory | - | | - -* For more information on build options - * Type "python build_bios.py -h" - -* Note - * The Python build scripts were compatible with Python 2.7.16. But Pytho= n 2.x support is no longer maintained or recommended. - - * This python build script has been tested on Windows 10 and Ubuntu 18.0= 4.1 LTS. - - * Unless otherwise noted, all boards build with the following components= and versions: - * Linux build: Ubuntu 18.04.1 LTS with GCC version 5.4.0 - * Windows build: Windows 10 with the Microsoft Visual Studio 2015 comp= iler - * iASL version: 20190816 - * NASM version: 2.12.02 - - * Unless otherwise noted all boards have been tested for boot to Windows= 10 x64 RS3. - - * See [known limitations](#Known-limitations) - -* Configuration Files - * The edk2-platforms\Platform\Intel\build.cfg file contains the default = settings used by build_bios.py - * The default settings are under the DEFAULT_CONFIG section - * Each board can have a settings file that will override the edk2-platfo= rms\Platform\Intel\build.cfg settings - * An example of a board specific settings: - * edk2-platforms\Platform\Intel\KabylakeOpenBoardPkg\KabylakeRvp3\buil= d_config.cfg - -* Workspace view of the build scripts - * 

-    WORKSPACE

-          |------edk2

-          |------edk2-non-osi

-          |------edk2-platforms

-          |       |---Platform

-          |       |    |--Intel

-          |       |        |------build.cfg: Default build settings. These=
 are overridden by

-          |       |        |                 platform specific settings (b=
uild_config.cfg) and

-          |       |        |                 then command-line settings.

-          |       |        |

-          |       |        |------build_bios.py: Main build script. Generi=
c pre-build, build,

-          |       |        |                     post-build, and clean fun=
ctions.

-          |       |        |

-          |       |        |------KabylakeOpenBoardPkg

-          |       |        |       |------GalagoPro3

-          |       |        |       |       |---build_config.cfg: System 76=
 Galago Pro 3 specific build

-          |       |        |       |                             settings =
environment variables.

-          |       |        |       |------KabylakeRvp3

-          |       |        |               |---build_config.cfg: KabylakeR=
vp3 specific

-          |       |        |               |                     build set=
tings, environment variables.

-          |       |        |               |---build_board.py: Optional bo=
ard-specific pre-build, build

-          |       |        |                                   and clean p=
ost-build functions.

-          |       |        |

-          |       |        |------PurleyOpenBoardPkg

-          |       |        |       |------BoardMtOlympus

-          |       |        |       |       |---build_config.cfg: BoardMtOl=
ympus specific

-          |       |        |       |       |                     build set=
tings, environment variables.

-          |       |        |       |       |---build_board.py: Optional bo=
ard-specific pre-build,

-          |       |        |       |                           build, post=
-build and clean functions.

-          |       |        |       |------BoardTiogaPass

-          |       |        |               |---build_config.cfg: BoardTiog=
aPass specific

-          |       |        |               |                     build set=
tings, environment variables.

-          |       |        |               |---build_board.py: Optional bo=
ard-specific pre-build,

-          |       |        |                                   build, post=
-build and clean functions.

-          |       |        |

-          |       |        |------SimicsOpenBoardPkg

-          |       |        |       |------BoardX58Ich10

-          |       |        |               |---build_config.cfg: BoardX58I=
ch10 specific

-          |       |        |                                     build set=
tings, environment variables.

-          |       |        |

-          |       |        |------WhitleyOpenBoardPkg

-          |       |        |       |------CooperCityRvp

-          |       |        |       |       |---build_config.cfg: CooperCit=
yRvp specific build

-          |       |        |       |       |                     settings =
environment variables.

-          |       |        |       |       |---build_board.py: Board-speci=
fic pre-build,

-          |       |        |       |                           build, post=
-build and clean functions.

-          |       |        |       |------JunctionCity

-          |       |        |       |       |---build_config.cfg: CooperCit=
yRvp specific build

-          |       |        |       |       |                     settings =
environment variables.

-          |       |        |       |       |---build_board.py: Board-speci=
fic pre-build,

-          |       |        |       |                           build, post=
-build and clean functions.

-          |       |        |       |------WilsonCityRvp

-          |       |        |               |---build_config.cfg: WilsonCit=
yRvp specific build

-          |       |        |               |                     settings =
environment variables.

-          |       |        |               |---build_board.py: Board-speci=
fic pre-build,

-          |       |        |                                   build, post=
-build and clean functions.

-          |       |        |

-          |       |        |------WhiskeylakeOpenBoardPkg

-          |       |        |       |------UpXtreme

-          |       |        |       |       |---build_config.cfg: UpXtreme =
specific build

-          |       |        |       |                             settings =
environment variables.

-          |       |        |       |------WhiskeylakeURvp

-          |       |        |               |---build_config.cfg: Whiskeyla=
keURvp specific build

-          |       |        |                                     settings =
environment variables.

-          |       |        |

-          |       |        |------CometlakeOpenBoardPkg

-          |       |        |       |------CometlakeURvp

-          |       |        |               |---build_config.cfg: Cometlake=
URvp specific build

-          |       |        |                                     settings =
environment variables.

-          |       |        |

-          |       |        |------TigerlakeOpenBoardPkg

-          |       |        |       |------TigerlakeURvp

-          |       |        |               |---build_config.cfg: Tigerlake=
URvp specific build

-          |       |        |                                     settings =
environment variables.

-          |       |        |

-          |------FSP

-
- -**Building with the batch scripts** - -Only PurleyOpenBoardPkg still supports batch script build (in addition to = Python build). Batch scripts are deprecated -and will be removed from PurleyOpenBoardPkg in the future. All other board= packages must only use the Python build -infrastructure. - -For PurleyOpenBoardPkg -1. Open command window, go to the workspace directory, e.g. c:\Edk2Workspa= ce. -2. Type "cd edk2-platforms\Platform\Intel\PurleyOpenBoardPkg\BoardMtOlympu= s". -3. Type "GitEdk2MinMtOlympus.bat" to setup GIT environment. -4. Type "bld" to build Purley Mt Olympus board UEFI firmware image, "bld r= elease" for release build, "bld clean" to - remove intermediate files."bld cache-produce" Generate a cache of binar= y files in the specified directory, - "bld cache-consume" Consume a cache of binary files from the specified = directory, BINARY_CACHE_PATH is empty, - used "BinCache" as default path. - -For PurleyOpenBoardPkg (TiogaPass) -1. Open command window, go to the workspace directory, e.g. c:\Edk2Workspa= ce. -2. Type "cd edk2-platforms\Platform\Intel\PurleyOpenBoardPkg\BoardTiogaPas= s". -3. Type "GitEdk2MinBoardTiogaPass.bat" to setup GIT environment. -4. Type "bld" to build Purley BoardTiogaPass board UEFI firmware image, "b= ld release" for release build, "bld clean" to - remove intermediate files."bld cache-produce" Generate a cache of binar= y files in the specified directory, - "bld cache-consume" Consume a cache of binary files from the specified = directory, BINARY_CACHE_PATH is empty, - used "BinCache" as default path. -5. Final BIOS image will be Build\PurleyOpenBoardPkg\BoardTiagoPass\DEBUG_= VS2015x86\FV\PLATFORM.fd or - Build\PurleyOpenBoardPkg\BoardTiagoPass\RELEASE_VS2015x86\FV\PLATFORM.f= d, depending on bld batch script input. -6. This BIOS image needs to be merged with SPS FW - -### **Known limitations** - -**KabylakeOpenBoardPkg** -*GalagoPro3* -1. The firmware project has not been tested on the Galago Pro 3B. - -*KabylakeRvp3* -1. This firmware project has only been tested for Microsoft Windows 10 x64= boot with AHCI mode and Integrated Graphic - Device. - -**PurleyOpenBoardPkg** -1. This firmware project has only been tested booting to Microsoft Windows= Server 2016 with NVME on M.2 slot. -2. This firmware project does not build with the GCC compiler. -3. The validated version of iASL compiler that can build MinPurley is 2018= 0629. Older versions may generate ACPI build errors. - -**PurleyOpenBoardPkg Tioga Pass** -1. This firmware project has only been tested on the Tioga Pass hardware. -2. This firmware project build has only been tested using the Microsoft Vi= sual Studio 2015 build tools. -3. This firmware project does not build with the GCC compiler. -4. The validated version of iASL compiler that can build MinPurley is 2018= 0629. Older versions may generate ACPI build errors. -5. Installed and booted to UEFI Windows 2016 on M.2 NVME slot -6. Installed and booted to UEFI Windows 2019 on M.2 NVME slot and with SAT= A HDD. -7. Installed and booted to UEFI RHEL 7.3 on SATA HDD -8. Installed and booted to Ubuntu 18.04 on M.2 NVME slot. -9. Verified Mellanox card detection during POST and OS -10. LINUX Boot Support (PcdLinuxBootEnable needs to be enabled) - -1. Follow directions on http://osresearch.net/Building/ to compile the hea= ds kernel and initrd for qemu-system_x86_64 -2. Copy the following built files -(1) initrd.cpio.xz to LinuxBootPkg/LinuxBinaries/initrd.cpio.xz -(2) bzimage to LinuxBootPkg/LinuxBinaries/linux.efi - - - -**SimicsOpenBoardPkg** -1. This firmware project has only been tested booting to Microsoft Windows= 10 x64 and Ubuntu 17.10 with AHCI mode. - -**WhiskeylakeOpenBoardPkg** -1. This firmware project has mainly been tested booting to Microsoft Windo= ws 10 x64 with AHCI mode and Integrated Graphic - Device. -2. UP Xtreme boards might hang during Windows 10 boot. -3. The UP Xtreme boards below boot to x64 windows 10 home edition and Ubun= tu 18.04 - * UP Xtreme Intel(R) Core(TM) i3-8145UE CPU @ 2.20GHz with 8GB RAM - * UP Xtreme Intel(R) Core(TM) i7-8565U CPU @ 1.80GHz with 16GB RAM - * UP Xtreme Intel(R) Core(TM) i7-8665UE CPU @ 1.70GHz with 16GB RAM - * UP Xtreme Intel(R) Celeron(R) CPU 4305UE @ 2.00GHz with 4GB RAM - -**CometlakeOpenBoardPkg** -1. This firmware project has been tested booting to Microsoft Windows 10 x= 64 with AHCI mode and External Graphic Device. -2. This firmware project has been also tested booting to Ubuntu 17.10 with= AHCI mode and Integrated Graphic Device. - -**TigerlakeOpenBoardPkg** -1. This firmware project has been tested booting to Microsoft Windows 10 x= 64 with AHCI mode and Integrated Graphic Device. -2. This firmware project has been also tested booting to Puppy Linux Bioni= cPup64 8.0 with AHCI mode and Integrated Graphic Device. - -**WhitleyOpenBoardPkg** -1. This firmware project has been tested booting to UEFI shell with headle= ss serial console - -**JunctionCity** -1. This firmware project has been tested booting to UEFI shell -2. Booted to RHEL 8.2, Ubuntu 18.04 using U2 NVME Disk -3. Booted to Windows 2019 using M2 SSD Disk -4. Booted to Ubuntu 18.04,Windows 2019, RHEL 8.3 using SATA HDD -5. Connected PCIE Network card and made sure PCIE card detected in POST an= d in OS -6. Verified TPM offboard chip detection - -### **Package Builds** - -In some cases, such as BoardModulePkg, a package may provide a set of func= tionality that is included in other -packages. To test the build of the whole package, the "build" command shou= ld be used following the instructions below. - -1. Execute edksetup.bat (Windows) or edksetup.sh (Linux). -2. Verify the "WORKSPACE" environment variable is set to the edk2 director= y in your workspace. -3. Set the "PACKAGES_PATH" environment variable to include the edk2-platfo= rms/Platform/Intel, edk2-platforms/Silicon/Intel, - and edk2-platforms/Features/Intel directories. - * Windows example: set PACKAGES_PATH=3Dc:\Edk2Workspace\edk2-platforms\= Platform\Intel; - c:\Edk2Workspace\edk2-platforms\Silicon\Intel;c:\Edk2Workspace\edk2-p= latforms\Features\Intel -4. Build the package by specifying the package DSC as the platform build t= arget from the Platform/Intel or Silicon/Intel directory: - "build -p BoardModulePkg/BoardModulePkg.dsc -a IA32 -a X64" - - -### **Firmware Image Flashing** - -The full Intel firmware image on a flash device is called the Integrated F= irmware Image (IFWI). Users with access to the Intel -proprietary FITC tool and ME ingredients can build full IFWI images that m= ay be flashed (Descriptor, UEFI FW, ME FW, etc.). - -Users without such access can directly flash a custom built UEFI FW image = over the highest area of the flash region directly. -It is always recommended to have a hardware flash programmer accessible to= recover the firmware image. The original full flash -image should always be backed up so it may be flashed again for recovery. = Please be aware that if a system supports a technology -that authenticates the initial firmware boot image such as Boot Guard, it = will fail to boot with a custom firmware image -that is not signed properly. - -### **Planned Activities** -* Expand Intel's open source platform code presence through new platform a= nd board support. -* Expand advanced feature code and quality. -* Support open source community continuous integration for Minimum Platfor= m compliant boards. - -### **Ideas** -If you would like to help but are not sure where to start some areas curre= ntly identified for improvement include: - * Adding board ports for more motherboards and systems - * Adding Clang support - -Please feel free to contact Isaac Oram (isaac.w.oram at intel.com) -if you would like to discuss contribution ideas. +# **EDK II Minimum Platform Firmware for Intel® Platforms** + +The Minimum Platform is a software architecture that guides uniform delive= ry of Intel platforms enabling firmware +solutions for basic boot functionality with extensibility built-in. Please= see the +[EDK II Minimum Platform Draft Specification](https://edk2-docs.gitbooks.i= o/edk-ii-minimum-platform-specification/) +for more details. + +Package maintainers for the Minimum Platform projects are listed in Mainta= iners.txt. + +## Overview +The key elements of the architecture are organized into a staged boot appr= oach where each stage has requirements and +functionality for specific use cases. The generic control flow through the= boot process is implemented in the +[`MinPlatformPkg`](https://github.com/tianocore/edk2-platforms/tree/master= /Platform/Intel/MinPlatformPkg). +The generic nature of the tasks performed in MinPlatformPkg lends to reuse= across all Intel platforms with no +source modification. Details for any particular board are made accessible = to the MinPlatformPkg through a well-defined +statically linked board API. A complete platform solution then consists of= the MinPlatformPkg and a compatible board +package. + +## Board Naming Convention +The board packages supported by Intel follow the naming convention \= OpenBoardPkg where xxx refers to the +encompassing platform name for a particular platform generation. For examp= le, the [`KabylakeOpenBoardPkg`](https://github.com/tianocore/edk2-platform= s/tree/master/Platform/Intel/KabylakeOpenBoardPkg) contains the +board code for Intel KabyLake reference systems. Intel uses the moniker "O= penBoardPkg" to indicate that this package +is the open source board code. A closed source counterpart may exist which= simply uses "BoardPkg". Both directly use +the MinPlatformPkg from edk2-platforms. + +## Stage Selection +Stage selection is controlled via the PCD `gMinPlatformPkgTokenSpaceGuid.P= cdBootStage` in [`MinPlatformPkg.dec`](https://github.com/tianocore/edk2-pl= atforms/tree/master/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec). +The stage should be configured in the board package DSC file to the approp= riate value. For example, a board may disable +all advanced features by setting this value to 4 instead of 6. This may be= used to improve boot time for a particular +use case. Decrementing the stage can also be used for debug since only the= actions required for that stage objective +should be executed. As an example, ACPI initialization is not required for= a Stage 3 boot. + +The stages are defined as follows: + +| Stage | Functional Objective | Example Capabilities = | +| -------|------------------------------|---------------------------------= -------------------------------------------------------------------| +| I | Minimal Debug | Serial port output, source debug= enabled, hardware debugger enabled | +| II | Memory Functional | Basic hardware initialization ne= cessary to reach memory initialization, permanent memory available | +| III | Boot to UI | Simple console input and output = to a UI, UEFI shell | +| IV | Boot to OS | Boot an operating system with th= e minimally required features | +| V | Security Enable | UEFI Secure Boot, TCG measured b= oot, DMA protections | +| VI | Advanced Feature Enable | Firmware update, power managemen= t, non-essential I/O | + +## Minimum Platform Firmware Solution Stack +A UEFI firmware implementation using MinPlatformPkg is constructed using t= he following pieces. + +| | +|------------------------------------| +| [EDK II](https://github.com/tianocore/edk2) = | +| [Intel(r) FSP](https://github.com/IntelFsp/FSP) = | +| [Minimum Platform (`MinPlatformPkg`)](https://github.com/tianocore/edk2-= platforms/tree/master/Platform/Intel/MinPlatformPkg) = | +| [Board Support (\OpenBoardPkg)](https://github.com/tianocore/edk2-= platforms/tree/master/Platform/Intel) | + + +## Board Support +* The `KabylakeOpenBoardPkg` contains board implementations for KabyLake s= ystems. +* The `PurleyOpenBoardPkg` contains board implementations for Purley syste= ms. +* The `SimicsOpenBoardPkg` contains board implementations for the Simics h= ardware simulator. +* The `WhiskeylakeOpenBoardPkg` contains board implementations for Whiskey= Lake systems. +* The `CometlakeOpenBoardPkg` contains board implementations for CometLake= systems. +* The `TigerlakeOpenBoardPkg` contains board implementations for TigerLake= systems. +* The `WhitleyOpenBoardPkg` contains board implementations for Ice Lake-SP= and Cooper Lake systems. + +### **Supported Hardware** + +#### AAEON + +| Machine Name | Supported Chipsets = | BoardPkg | Board Name | +----------------------------------------|---------------------------------= -----------|------------------------------|--------------------| +| UP Xtreme | Whiskey Lake = | WhiskeylakeOpenBoardPkg | UpXtreme | + +#### Acer + +***Aspire VN7-572G Laptop*** + +| Machine Name | Supported Chipsets = | BoardPkg | Board Name | +----------------------------------------|---------------------------------= -----------|------------------------------|--------------------| +| Aspire VN7-572G | SkyLake = | KabylakeOpenBoardPkg | AspireVn7Dash572G | + +#### Intel + +***Intel Reference and Validation Platform*** + +| Machine Name | Supported Chipsets = | BoardPkg | Board Name | +----------------------------------------|---------------------------------= -----------|------------------------------|--------------------| +| RVP 3 | SkyLake, KabyLake, KabyLake Refr= esh | KabylakeOpenBoardPkg | KabylakeRvp3 | +| WHL-U DDR4 RVP | WhiskeyLake = | WhiskeylakeOpenBoardPkg | WhiskeylakeURvp | +| CML-U LPDDR3 RVP | CometLake V1 = | CometlakeOpenBoardPkg | CometlakeURvp | +| TGL-U DDR4 RVP | TigerLake = | TigerlakeOpenBoardPkg | TigerlakeURvp | +| Wilson City RVP | IceLake-SP (Xeon Scalable) = | WhitleyOpenBoardPkg | WilsonCityRvp | +| Cooper City RVP | Copper Lake = | WhitleyOpenBoardPkg | CooperCityRvp | + +*Note: RVP =3D Reference and Validation Platform* + +#### Open Compute Project (OCP) + +| Machine Name | Supported Chipsets = | BoardPkg | Board Name | +----------------------------------------|---------------------------------= -----------|------------------------------|--------------------| +| Aowanda | IceLake-SP (Xeon Scalable) = | WhitleyOpenBoardPkg | Aowanda | +| Junction City | IceLake-SP (Xeon Scalable) = | WhitleyOpenBoardPkg | JunctionCity | +| Mt. Olympus | Purley = | PurleyOpenBoardPkg | BoardMtOlympus | +| TiogaPass | Purley = | PurleyOpenBoardPkg | BoardTiogaPass | + + +#### Simics + +| Machine Name | Supported Chipsets = | BoardPkg | Board Name | +----------------------------------------|---------------------------------= -----------|------------------------------|--------------------| +| Simics Quick Start Package | Nehalem = | SimicsOpenBoardPkg | BoardX58Ich10 | + +#### System 76 + +***Galago Pro Laptop*** + +| Machine Name | Supported Chipsets = | BoardPkg | Board Name | +----------------------------------------|---------------------------------= -----------|------------------------------|--------------------| +| galp2 | KabyLake = | KabylakeOpenBoardPkg | GalagoPro3 | +| galp3 & galp3-b | KabyLake Refresh = | KabylakeOpenBoardPkg | GalagoPro3 | + +## Board Package Organization +The board package follows the standard EDK II package structure with the f= ollowing additional elements and guidelines: +* Only code usable across more than one board at the root level. +* Board-specific code in a directory. The directory name should match that= of the board supported. +* Features not essential to achieve stage 5 or earlier boots are maintaine= d in edk2-platforms/Features/Intel. + +Shared resources in the package root directory can include interfaces desc= ribed in header files, library instances, +firmware modules, binaries, etc. The UEFI firmware implementation is built= using the process described below from the +board-specific directory. + +A board package must implement the board APIs defined in the MinPlatformPk= g even if a "NULL" implementation is used to +return back to the minimum platform caller. + +## **Windows Build Instructions** + +### Pre-requisites + +* GIT client: Available from https://git-scm.com/downloads +* Microsoft Visual Studio. + - Visual Studio 2015 recommended and is used in the examples below. +* ASL compiler: Available from http://www.acpica.org + - Install into ```C:\ASL``` to match default tools_def.txt configuration= . +* NASM assembler: Available from: http://www.nasm.us/ + - Install into ```C:\NASM``` to match default tools_def.txt configuratio= n. +* Python 3.7.3: Available from: https://www.python.org/downloads/release/= python-373/ + - Other versions of Python 3.x should be compatible. + - It is recommended to use the Python launcher to ensure the Python buil= d script is launched using Python 3. + - E.g. "py -3.7 build_bios.py -l" + +## **Linux Build Instructions** + +### Pre-requisites + + * Set up a EDK II build environment for Linux following the instructions = in + [Using EDK II with Native GCC](https://github.com/tianocore/tianocore.g= ithub.io/wiki/Using-EDK-II-with-Native-GCC). + * Proceed to the [Common EDK II build instructions for Linux](https://git= hub.com/tianocore/tianocore.github.io/wiki/Common-instructions) + to verify your basic EDK II build environment is set up properly. + +### Download the required components + +1. Create a new directory for the EDK II WORKSPACE. + +2. Download below repository to this WORKSPACE: + +* edk2 repository + * ``git clone https://github.com/tianocore/edk2.git`` + +* edk2-platforms repository + * ``git clone https://github.com/tianocore/edk2-platforms.git`` + +* edk2-non-osi repository + * ``git clone https://github.com/tianocore/edk2-non-osi.git`` + +* FSP repository + * ``git clone https://github.com/IntelFsp/FSP.git`` + +### Board Builds + +**Building with the python script** + +1. Open command window, go to the workspace directory, e.g. c:\Edk2Workspa= ce or ~/Edk2Workspace in the case of a linux OS +2. If using a linux OS + * Type "cd edk2" + * Type "source edksetup.sh" + * Type "cd ../" to go back to the workspace directory +3. Type "cd edk2-platforms/Platform/Intel +4. Type "python build_bios.py -p REPLACE_WITH_BOARD_NAME" + +* build_bios.py arguments: + + | Argument | Function | + | ----------------------|-------------------------------------| + | -h, --help | show this help message and exit | + | --platform, -p | the platform to build | + | --toolchain, -t | tool Chain to use in build process | + | --DEBUG, -d | debug flag | + | --RELEASE, -r | release flag | + | --TEST_RELEASE, -tr | test Release flag | + | --RELEASE_PDB, -rp | release flag | + | --list, -l | lists available platforms | + | --cleanall | cleans all | + | --clean | cleans specified platform | + | --capsule | capsule build enabled | + | --silent | silent build enabled | + | --performance | performance build enabled | + | --fsp | fsp wrapper build enabled | + | --fspapi | API mode fsp wrapper build enabled | + | --hash | Enable hash-based caching | + | --binary-destination | create cache in specified directory | + | --binary-source | Consume cache from directory | + | | + +* For more information on build options + * Type "python build_bios.py -h" + +* Note + * The Python build scripts were compatible with Python 2.7.16. But Pytho= n 2.x support is no longer maintained or recommended. + + * This python build script has been tested on Windows 10 and Ubuntu 18.0= 4.1 LTS. + + * Unless otherwise noted, all boards build with the following components= and versions: + * Linux build: Ubuntu 18.04.1 LTS with GCC version 5.4.0 + * Windows build: Windows 10 with the Microsoft Visual Studio 2015 comp= iler + * iASL version: 20190816 + * NASM version: 2.12.02 + + * Unless otherwise noted all boards have been tested for boot to Windows= 10 x64 RS3. + + * See [known limitations](#Known-limitations) + +* Configuration Files + * The edk2-platforms\Platform\Intel\build.cfg file contains the default = settings used by build_bios.py + * The default settings are under the DEFAULT_CONFIG section + * Each board can have a settings file that will override the edk2-platfo= rms\Platform\Intel\build.cfg settings + * An example of a board specific settings: + * edk2-platforms\Platform\Intel\KabylakeOpenBoardPkg\KabylakeRvp3\buil= d_config.cfg + +* Workspace view of the build scripts + * 
+    WORKSPACE
+          |------edk2
+          |------edk2-non-osi
+          |------edk2-platforms
+          |       |---Platform
+          |       |    |--Intel
+          |       |        |------build.cfg: Default build settings. These=
 are overridden by
+          |       |        |                 platform specific settings (b=
uild_config.cfg) and
+          |       |        |                 then command-line settings.
+          |       |        |
+          |       |        |------build_bios.py: Main build script. Generi=
c pre-build, build,
+          |       |        |                     post-build, and clean fun=
ctions.
+          |       |        |
+          |       |        |------KabylakeOpenBoardPkg
+          |       |        |       |------GalagoPro3
+          |       |        |       |       |---build_config.cfg: System 76=
 Galago Pro 3 specific build
+          |       |        |       |                             settings =
environment variables.
+          |       |        |       |------KabylakeRvp3
+          |       |        |               |---build_config.cfg: KabylakeR=
vp3 specific
+          |       |        |               |                     build set=
tings, environment variables.
+          |       |        |               |---build_board.py: Optional bo=
ard-specific pre-build, build
+          |       |        |                                   and clean p=
ost-build functions.
+          |       |        |
+          |       |        |------PurleyOpenBoardPkg
+          |       |        |       |------BoardMtOlympus
+          |       |        |       |       |---build_config.cfg: BoardMtOl=
ympus specific
+          |       |        |       |       |                     build set=
tings, environment variables.
+          |       |        |       |       |---build_board.py: Optional bo=
ard-specific pre-build,
+          |       |        |       |                           build, post=
-build and clean functions.
+          |       |        |       |------BoardTiogaPass
+          |       |        |               |---build_config.cfg: BoardTiog=
aPass specific
+          |       |        |               |                     build set=
tings, environment variables.
+          |       |        |               |---build_board.py: Optional bo=
ard-specific pre-build,
+          |       |        |                                   build, post=
-build and clean functions.
+          |       |        |
+          |       |        |------SimicsOpenBoardPkg
+          |       |        |       |------BoardX58Ich10
+          |       |        |               |---build_config.cfg: BoardX58I=
ch10 specific
+          |       |        |                                     build set=
tings, environment variables.
+          |       |        |
+          |       |        |------WhitleyOpenBoardPkg
+          |       |        |       |------Aowanda
+          |       |        |       |       |---build_config.cfg: Aowanda  =
specific build
+          |       |        |       |       |                     settings =
environment variables.
+          |       |        |       |       |---build_board.py: Board-speci=
fic pre-build,
+          |       |        |       |                           build, post=
-build and clean functions.
+          |       |        |       |------CooperCityRvp
+          |       |        |       |       |---build_config.cfg: CooperCit=
yRvp specific build
+          |       |        |       |       |                     settings =
environment variables.
+          |       |        |       |       |---build_board.py: Board-speci=
fic pre-build,
+          |       |        |       |                           build, post=
-build and clean functions.
+          |       |        |       |------JunctionCity
+          |       |        |       |       |---build_config.cfg: CooperCit=
yRvp specific build
+          |       |        |       |       |                     settings =
environment variables.
+          |       |        |       |       |---build_board.py: Board-speci=
fic pre-build,
+          |       |        |       |                           build, post=
-build and clean functions.
+          |       |        |       |------WilsonCityRvp
+          |       |        |               |---build_config.cfg: WilsonCit=
yRvp specific build
+          |       |        |               |                     settings =
environment variables.
+          |       |        |               |---build_board.py: Board-speci=
fic pre-build,
+          |       |        |                                   build, post=
-build and clean functions.
+          |       |        |
+          |       |        |------WhiskeylakeOpenBoardPkg
+          |       |        |       |------UpXtreme
+          |       |        |       |       |---build_config.cfg: UpXtreme =
specific build
+          |       |        |       |                             settings =
environment variables.
+          |       |        |       |------WhiskeylakeURvp
+          |       |        |               |---build_config.cfg: Whiskeyla=
keURvp specific build
+          |       |        |                                     settings =
environment variables.
+          |       |        |
+          |       |        |------CometlakeOpenBoardPkg
+          |       |        |       |------CometlakeURvp
+          |       |        |               |---build_config.cfg: Cometlake=
URvp specific build
+          |       |        |                                     settings =
environment variables.
+          |       |        |
+          |       |        |------TigerlakeOpenBoardPkg
+          |       |        |       |------TigerlakeURvp
+          |       |        |               |---build_config.cfg: Tigerlake=
URvp specific build
+          |       |        |                                     settings =
environment variables.
+          |       |        |
+          |------FSP
+
+ +**Building with the batch scripts** + +Only PurleyOpenBoardPkg still supports batch script build (in addition to = Python build). Batch scripts are deprecated +and will be removed from PurleyOpenBoardPkg in the future. All other board= packages must only use the Python build +infrastructure. + +For PurleyOpenBoardPkg +1. Open command window, go to the workspace directory, e.g. c:\Edk2Workspa= ce. +2. Type "cd edk2-platforms\Platform\Intel\PurleyOpenBoardPkg\BoardMtOlympu= s". +3. Type "GitEdk2MinMtOlympus.bat" to setup GIT environment. +4. Type "bld" to build Purley Mt Olympus board UEFI firmware image, "bld r= elease" for release build, "bld clean" to + remove intermediate files."bld cache-produce" Generate a cache of binar= y files in the specified directory, + "bld cache-consume" Consume a cache of binary files from the specified = directory, BINARY_CACHE_PATH is empty, + used "BinCache" as default path. + +For PurleyOpenBoardPkg (TiogaPass) +1. Open command window, go to the workspace directory, e.g. c:\Edk2Workspa= ce. +2. Type "cd edk2-platforms\Platform\Intel\PurleyOpenBoardPkg\BoardTiogaPas= s". +3. Type "GitEdk2MinBoardTiogaPass.bat" to setup GIT environment. +4. Type "bld" to build Purley BoardTiogaPass board UEFI firmware image, "b= ld release" for release build, "bld clean" to + remove intermediate files."bld cache-produce" Generate a cache of binar= y files in the specified directory, + "bld cache-consume" Consume a cache of binary files from the specified = directory, BINARY_CACHE_PATH is empty, + used "BinCache" as default path. +5. Final BIOS image will be Build\PurleyOpenBoardPkg\BoardTiagoPass\DEBUG_= VS2015x86\FV\PLATFORM.fd or + Build\PurleyOpenBoardPkg\BoardTiagoPass\RELEASE_VS2015x86\FV\PLATFORM.f= d, depending on bld batch script input. +6. This BIOS image needs to be merged with SPS FW + +### **Known limitations** + +**KabylakeOpenBoardPkg** +*GalagoPro3* +1. The firmware project has not been tested on the Galago Pro 3B. + +*KabylakeRvp3* +1. This firmware project has only been tested for Microsoft Windows 10 x64= boot with AHCI mode and Integrated Graphic + Device. + +**PurleyOpenBoardPkg** +1. This firmware project has only been tested booting to Microsoft Windows= Server 2016 with NVME on M.2 slot. +2. This firmware project does not build with the GCC compiler. +3. The validated version of iASL compiler that can build MinPurley is 2018= 0629. Older versions may generate ACPI build errors. + +**PurleyOpenBoardPkg Tioga Pass** +1. This firmware project has only been tested on the Tioga Pass hardware. +2. This firmware project build has only been tested using the Microsoft Vi= sual Studio 2015 build tools. +3. This firmware project does not build with the GCC compiler. +4. The validated version of iASL compiler that can build MinPurley is 2018= 0629. Older versions may generate ACPI build errors. +5. Installed and booted to UEFI Windows 2016 on M.2 NVME slot +6. Installed and booted to UEFI Windows 2019 on M.2 NVME slot and with SAT= A HDD. +7. Installed and booted to UEFI RHEL 7.3 on SATA HDD +8. Installed and booted to Ubuntu 18.04 on M.2 NVME slot. +9. Verified Mellanox card detection during POST and OS +10. LINUX Boot Support (PcdLinuxBootEnable needs to be enabled) + +1. Follow directions on http://osresearch.net/Building/ to compile the hea= ds kernel and initrd for qemu-system_x86_64 +2. Copy the following built files +(1) initrd.cpio.xz to LinuxBootPkg/LinuxBinaries/initrd.cpio.xz +(2) bzimage to LinuxBootPkg/LinuxBinaries/linux.efi + + + +**SimicsOpenBoardPkg** +1. This firmware project has only been tested booting to Microsoft Windows= 10 x64 and Ubuntu 17.10 with AHCI mode. + +**WhiskeylakeOpenBoardPkg** +1. This firmware project has mainly been tested booting to Microsoft Windo= ws 10 x64 with AHCI mode and Integrated Graphic + Device. +2. UP Xtreme boards might hang during Windows 10 boot. +3. The UP Xtreme boards below boot to x64 windows 10 home edition and Ubun= tu 18.04 + * UP Xtreme Intel(R) Core(TM) i3-8145UE CPU @ 2.20GHz with 8GB RAM + * UP Xtreme Intel(R) Core(TM) i7-8565U CPU @ 1.80GHz with 16GB RAM + * UP Xtreme Intel(R) Core(TM) i7-8665UE CPU @ 1.70GHz with 16GB RAM + * UP Xtreme Intel(R) Celeron(R) CPU 4305UE @ 2.00GHz with 4GB RAM + +**CometlakeOpenBoardPkg** +1. This firmware project has been tested booting to Microsoft Windows 10 x= 64 with AHCI mode and External Graphic Device. +2. This firmware project has been also tested booting to Ubuntu 17.10 with= AHCI mode and Integrated Graphic Device. + +**TigerlakeOpenBoardPkg** +1. This firmware project has been tested booting to Microsoft Windows 10 x= 64 with AHCI mode and Integrated Graphic Device. +2. This firmware project has been also tested booting to Puppy Linux Bioni= cPup64 8.0 with AHCI mode and Integrated Graphic Device. + +**WhitleyOpenBoardPkg** +1. This firmware project has been tested booting to UEFI shell with headle= ss serial console + +**JunctionCity** +1. This firmware project has been tested booting to UEFI shell +2. Booted to RHEL 8.2, Ubuntu 18.04 using U2 NVME Disk +3. Booted to Windows 2019 using M2 SSD Disk +4. Booted to Ubuntu 18.04,Windows 2019, RHEL 8.3 using SATA HDD +5. Connected PCIE Network card and made sure PCIE card detected in POST an= d in OS +6. Verified TPM offboard chip detection + +**Aowanda** +1. This firmware project has been tested booting to UEFI shell +2. Installed and booted to RHEL 8.3 using M2 SSD disk +3. Installed and booted to Windows 2019 using M2 SSD disk +4. Verified TPM chip detection + +Note: =20 +For the network boot using the onboard Intel network card, please download= the UEFI UNDI driver (E9712X3.efi) from https://www.intel.com/content/www/= us/en/download/15755/intel-ethernet-connections-boot-utility-preboot-images= -and-efi-drivers.html +and include it in PlatformPkg.fdf. + +### **Package Builds** + +In some cases, such as BoardModulePkg, a package may provide a set of func= tionality that is included in other +packages. To test the build of the whole package, the "build" command shou= ld be used following the instructions below. + +1. Execute edksetup.bat (Windows) or edksetup.sh (Linux). +2. Verify the "WORKSPACE" environment variable is set to the edk2 director= y in your workspace. +3. Set the "PACKAGES_PATH" environment variable to include the edk2-platfo= rms/Platform/Intel, edk2-platforms/Silicon/Intel, + and edk2-platforms/Features/Intel directories. + * Windows example: set PACKAGES_PATH=3Dc:\Edk2Workspace\edk2-platforms\= Platform\Intel; + c:\Edk2Workspace\edk2-platforms\Silicon\Intel;c:\Edk2Workspace\edk2-p= latforms\Features\Intel +4. Build the package by specifying the package DSC as the platform build t= arget from the Platform/Intel or Silicon/Intel directory: + "build -p BoardModulePkg/BoardModulePkg.dsc -a IA32 -a X64" + + +### **Firmware Image Flashing** + +The full Intel firmware image on a flash device is called the Integrated F= irmware Image (IFWI). Users with access to the Intel +proprietary FITC tool and ME ingredients can build full IFWI images that m= ay be flashed (Descriptor, UEFI FW, ME FW, etc.). + +Users without such access can directly flash a custom built UEFI FW image = over the highest area of the flash region directly. +It is always recommended to have a hardware flash programmer accessible to= recover the firmware image. The original full flash +image should always be backed up so it may be flashed again for recovery. = Please be aware that if a system supports a technology +that authenticates the initial firmware boot image such as Boot Guard, it = will fail to boot with a custom firmware image +that is not signed properly. + +### **Planned Activities** +* Expand Intel's open source platform code presence through new platform a= nd board support. +* Expand advanced feature code and quality. +* Support open source community continuous integration for Minimum Platfor= m compliant boards. + +### **Ideas** +If you would like to help but are not sure where to start some areas curre= ntly identified for improvement include: + * Adding board ports for more motherboards and systems + * Adding Clang support + +Please feel free to contact Isaac Oram (isaac.w.oram at intel.com) +if you would like to discuss contribution ideas. diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/IpmiPlatfor= mHookLib/IpmiPlatformHookLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda= /Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c new file mode 100644 index 0000000000..add93610c2 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/IpmiPlatformHookLi= b/IpmiPlatformHookLib.c @@ -0,0 +1,47 @@ +/** @file + This file implements the IPMI Platform hook functions + + Copyright (c) 2021, American Megatrends International LLC.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +#define KCS_BASE_ADDRESS_MASK 0xFFF0 +#define NUMBER_OF_BYTES_TO_DECODE 0x10 + +/** + This function sets IO Decode Range in LPC registers + + @param[in] IpmiIoBase - IPMI Base IO address + + @retval EFI_SUCCESS - Operation success. + +**/ +EFI_STATUS +EFIAPI +PlatformIpmiIoRangeSet ( + UINT16 IpmiIoBase + ) +{ + EFI_STATUS Status; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi; + + DynamicSiLibraryPpi =3D NULL; + + DEBUG ((DEBUG_INFO, "PlatformIpmiIoRangeSet IpmiIoBase %x\n", IpmiIoBase= )); + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "PeiServicesLocatePpi for gDynamicSiLibraryPpiGui= d failed. Status %r\n", Status)); + ASSERT_EFI_ERROR (Status); + return Status; + } + + DynamicSiLibraryPpi->PchLpcGenIoRangeSet ((IpmiIoBase & KCS_BASE_ADDRESS= _MASK), NUMBER_OF_BYTES_TO_DECODE); + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/IpmiPlatfor= mHookLib/IpmiPlatformHookLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Aowan= da/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf new file mode 100644 index 0000000000..699d89b24a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/IpmiPlatformHookLi= b/IpmiPlatformHookLib.inf @@ -0,0 +1,32 @@ +## @file +# Component description file for IPMI platform hook Library. +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2021, American Megatrends International LLC.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D IpmiPlatformHookLib + FILE_GUID =3D A770BDB8-331A-4110-8B60-81FC17480B36 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D IpmiPlatformHookLib + +[sources] + IpmiPlatformHookLib.c + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + +[LibraryClasses] + DebugLib + +[Ppis] + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Depex] + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/PeiPlatform= HookLib/PeiPlatformHooklib.c b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/L= ibrary/PeiPlatformHookLib/PeiPlatformHooklib.c new file mode 100644 index 0000000000..f115868c4a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/PeiPlatformHookLib= /PeiPlatformHooklib.c @@ -0,0 +1,93 @@ +/** @file + PEI Library Functions. Initialize GPIOs + + Copyright 1999 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +/** + Configure GPIO + + @param[in] None + + @retval None +**/ +VOID +GpioInit ( + VOID + ) +{ + PlatformInitGpios (); +} + +/** + Disables ME PCI devices like IDE-R , KT + + @param[in] None + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +DisableMEDevices ( + VOID + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi; + + DynamicSiLibraryPpi =3D NULL; + + DEBUG ((DEBUG_INFO, "DisableMEDevices\n")); + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // Disable IDE-R + // + DynamicSiLibraryPpi->PchPcrAndThenOr32 ( + PID_PSF1, + (R_PCH_H_PCR_PSF1_T0_SHDW_IDER_REG_BASE + R_PCH_P= SFX_PCR_T0_SHDW_PCIEN), + (UINT32)~0, + B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS + ); + + // + // Disable KT + // + DynamicSiLibraryPpi->PchPcrAndThenOr32 ( + PID_PSF1, + (R_PCH_H_PCR_PSF1_T0_SHDW_KT_REG_BASE + R_PCH_PSF= X_PCR_T0_SHDW_PCIEN), + (UINT32)~0, + B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS + ); + return EFI_SUCCESS; +} + +/** + Configure GPIO and SIO + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInit ( + ) +{ + GpioInit (); + DisableMEDevices (); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/PeiPlatform= HookLib/PeiPlatformHooklib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda= /Library/PeiPlatformHookLib/PeiPlatformHooklib.inf new file mode 100644 index 0000000000..fb3985c4e0 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Library/PeiPlatformHookLib= /PeiPlatformHooklib.inf @@ -0,0 +1,35 @@ +## @file +# +# @copyright +# Copyright 1999 - 2021 Intel Corporation.
+# Copyright (c) 2021, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiPlatformHookLib + FILE_GUID =3D 6E9351C3-A17A-4ADF-8602-55B07962718F + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PeiPlatformHookLib|PEIM PEI_CORE SEC + +[Sources] + PeiPlatformHooklib.c + +[Packages] + MdePkg/MdePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + +[LibraryClasses] + DebugLib + UbaGpioInitLib + +[Pcd] + +[Ppis] + +[Guids] diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/PlatformPkg.dsc b/P= latform/Intel/WhitleyOpenBoardPkg/Aowanda/PlatformPkg.dsc new file mode 100644 index 0000000000..70982396a0 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/PlatformPkg.dsc @@ -0,0 +1,82 @@ +## @file +# DSC file of Aowanda platform +# +# @copyright +# Copyright 2008 - 2021 Intel Corporation.
+# Copyright (c) 2022, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile= . +# +##########################################################################= ###### +[Defines] + PEI_ARCH =3D IA32 + DXE_ARCH =3D X64 + + !include WhitleyOpenBoardPkg/PlatformPkg.dsc + +[PcdsFixedAtBuild] + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|6 + +[PcdsFeatureFlag] +!if $(gMinPlatformPkgTokenSpaceGuid.PcdBootStage) >=3D 5 + gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable |TRUE + gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable |TRUE +!else + gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable |FALSE + gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable |FALSE +!endif + + !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc + +[Defines] + BOARD_NAME =3D Aowanda + PLATFORM_NAME =3D $(BOARD_NAME) + PLATFORM_GUID =3D 240D6B04-AFED-47E7-AB05-64B621A1112D + FLASH_DEFINITION =3D $(RP_PKG)/$(BOARD_NAME)/PlatformPkg.fdf + +[PcdsFixedAtBuild] + +!if $(TARGET) =3D=3D "RELEASE" + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03 + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F # E= nable asserts, prints, code, clear memory, and deadloops on asserts. + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE + gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x80200047 # = Built in messages: Error, MTRR, info, load, warn, init + gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 # = This is set to INT3 (0x2) for Simics source level debugging +!endif + gPlatformTokenSpaceGuid.PcdBoardId|0x26 + +[PcdsFixedAtBuild.X64] + gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|1900 + gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|9999 + +[PcdsDynamicExHii] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|5 # Variable: L"Timeout" + +[LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM] + PeiPlatformHookLib|$(RP_PKG)/$(BOARD_NAME)/Library/PeiPlatformHookLib/Pe= iPlatformHooklib.inf + +!if gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable =3D=3D TRUE + IpmiPlatformHookLib| $(RP_PKG)/$(BOARD_NAME)/Library/IpmiPlatformHookLib= /IpmiPlatformHookLib.inf +!endif + +[Components.IA32] + $(RP_PKG)/Uba/BoardInit/Pei/BoardInitPei.inf { + + NULL|$(RP_PKG)/$(BOARD_NAME)/Uba/TypeAowanda/Pei/PeiBoardInitLib.inf + NULL|$(RP_PKG)/Uba/UbaMain/Common/Pei/PeiCommonBoardInitLib.inf + } + +[Components.X64] + $(RP_PKG)/$(BOARD_NAME)/Uba/TypeAowanda/Dxe/UsbOcUpdateDxe/UsbOcUpdateDx= e.inf + $(RP_PKG)/$(BOARD_NAME)/Uba/TypeAowanda/Dxe/IioCfgUpdateDxe/IioCfgUpdate= Dxe.inf + $(RP_PKG)/$(BOARD_NAME)/Uba/TypeAowanda/Dxe/SlotDataUpdateDxe/SlotDataUp= dateDxe.inf + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/PlatformPkg.fdf b/P= latform/Intel/WhitleyOpenBoardPkg/Aowanda/PlatformPkg.fdf new file mode 100644 index 0000000000..09b0478bce --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/PlatformPkg.fdf @@ -0,0 +1,827 @@ +## @file +# FDF file of Aowanda platform +# This package provides platform specific modules and flash layout informa= tion. +# +# @copyright +# Copyright 2006 - 2021 Intel Corporation.
+# Copyright (c) 2022, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] +DEFINE PLATFORM_PKG =3D MinPlatformPkg + +# 0x00000060 =3D (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_F= FS_FILE_HEADER)) +DEFINE FDF_FIRMWARE_HEADER_SIZE =3D 0x00000060 + +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D = 0x90 # FV Header plus FFS header + +DEFINE VPD_HEADER_SIZE =3D 0x00000090 + +!if $(FSP_MODE) =3D=3D 0 + DEFINE FSP_BIN_DIR =3D Api +!else + DEFINE FSP_BIN_DIR =3D Dispatch +!endif + +# +# Note: FlashNv PCD naming conventions are as follows: +# Note: This should be 100% true of all PCD's in the gCpPlatFlashTo= kenSpaceGuid space, and for +# Others should be examined with an effort to work toward thi= s guideline. +# PcdFlash*Base is an address, usually in the range of 0xf* of FD's,= note change in FDF spec +# PcdFlash*Size is a hex count of the length of the FD or FV +# All Fv will have the form 'PcdFlashFv', and all Fd will have the f= orm 'PcdFlashFd' +# +# Also all values will have a PCD assigned so that they can be used = in the system, and +# the FlashMap edit tool can be used to change the values here, with= out effecting the code. +# This requires all code to only use the PCD tokens to recover the v= alues. + + +# +# 16MiB Total FLASH Image (visible in memory mapped IO) +# +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D 0xFF000000 +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D 0x01000000 + +##########################################################################= ###### +# +# FD SECPEI +# +# Contains all the SEC and PEI modules +# +# Layout: (Low address to high address) +# +# FvBsp for board specific components +# FvPostMemory for compressed post memory MinPlatform spec required co= mponents +# FvFspS for compressed post memory silicon initialization components +# FvPostMemorySilicon for silicon components +# FvFspM for pre memory silicon initialization components +# FvPreMemorySilicon for silicon components +# FvFspT for temp RAM silicon initilization components +# FvBspPreMemory for board specific components required to intialize m= emory +# FvAdvancedPreMemory FV for advanced features components +# FvPreMemory for components required by MinPlatform spec and to initi= alize memory +# FvPreMemorySecurity FV for stage 6 required components +# Contains reset vector +# +##########################################################################= ###### + +[FD.SecPei] + BaseAddress =3D 0xFFCA0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSec= PeiBase #The base address of the FLASH Device + Size =3D 0x00360000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSec= PeiSize #The size in bytes of the FLASH Device + ErasePolarity =3D 1 + BlockSize =3D 0x1000 + NumBlocks =3D 0x360 + + # + # These must add up to the FD Size. + # This makes it easy to adjust the various sizes without having to manua= lly calculate the offsets. + # At this time, the FSP FV must be aligned at the same address they were= built to, 0xFFD00000 + # This will be corrected in the future. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize =3D 0x0001= 0000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must =3D = 0xFFD00000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D 0x0001= 0000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must =3D = 0xFFD00000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D 0x0004= 0000 # Size must match WhitleyFspPkg.fdf content + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D 0x0022= 1000 # Size must match WhitleyFspPkg.fdf content + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D 0x0000= 6000 # Size must match WhitleyFspPkg.fdf content + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize =3D 0x0000= 9000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D gCpPla= tFlashTokenSpaceGuid.PcdFlashFdSecPeiSize - gMinPlatformPkgTokenSpaceGuid.P= cdFlashFvBspSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize -= gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize - gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspMSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSiz= e - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize + + # + # Calculate Offsets Once (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # Each offset is the prior region's offset plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset =3D 0x00= 000000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvBspSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvPostMemorySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvFspSSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvFspMSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvFspTSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvBspPreMemorySize + + # + # FV Layout (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|gMinPlatformPkgTokenSp= aceGuid.PcdFlashFvBspSize + FV =3D FvBsp + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkg= TokenSpaceGuid.PcdFlashFvPostMemorySize + FV =3D FvPostMemory + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvFspSSize + FILE =3D $(FSP_BIN_PKG)/Fsp_Rebased_S.fd + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvFspMSize + FILE =3D $(FSP_BIN_PKG)/Fsp_Rebased_M.fd + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvFspTSize + FILE =3D $(FSP_BIN_PKG)/Fsp_Rebased_T.fd + + # + # Shared FV layout + # + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvBspPreMemorySize + FV =3D FvBspPreMemory + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgT= okenSpaceGuid.PcdFlashFvPreMemorySize + FV =3D FvPreMemory + + # + # Calculate base addresses (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # Each base is the prior region's base plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase =3D gCpP= latFlashTokenSpaceGuid.PcdFlashFdSecPeiBase + gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvBspOffset + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvBspBase + gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvBspSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase + gMinPlatformPkgTokenSp= aceGuid.PcdFlashFvPostMemorySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase + gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspSSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase + gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspMSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase + gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspTSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase + gMinPlatformPkgToken= SpaceGuid.PcdFlashFvBspPreMemorySize + + # + # Set duplicate PCD + # These should not need to be changed + # + + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspMBase + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspMSize + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvPreMemoryBase + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvPreMemorySize + + # + # For API mode, wrappers have some duplicate PCD as well + # + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspSBase + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspMBase + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspTBase + +##########################################################################= ###### +# +# FD Main +# +# All DXE modules and other regions +# +# Layout: (Low address to high address) +# +# FvAdvanced for advanced feature components +# Assorted advanced feature FV +# FvSecurity for MinPlatform spec required components needed to boot s= ecurely +# FvOsBoot for MinPlatform spec required components needed to boot OS +# FvLateSilicon for silicon specific components +# FvUefiBoot for MinPlatform spec required components needed to boot t= o UEFI shell +# +##########################################################################= ###### +[FD.Main] + BaseAddress =3D 0xFF2E0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFd= MainBase # The base address of the FLASH Device + Size =3D 0x009C0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFd= MainSize # The size in bytes of the FLASH Device + ErasePolarity =3D 1 + BlockSize =3D 0x1000 + NumBlocks =3D 0x9C0 + + # + # These must add up to the FD Size. + # This makes it easy to adjust the various sizes without having to manua= lly calculate the offsets. + # These are out of flash layout order because FvAdvanced gets any remain= ing space + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =3D 0x0004= 0000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =3D 0x0023= 0000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D 0x0004= C000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =3D gCpPla= tFlashTokenSpaceGuid.PcdFlashFdMainSize - gMinPlatformPkgTokenSpaceGuid.Pcd= FlashFvUefiBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize - = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize + + # + # Calculate Offsets Once (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # Each offset is the prior region's offset plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D 0x0000= 0000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvAdvancedSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset + gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvSecuritySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvOsBootSize + + # + # FV Layout (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvAdvancedSize + FV =3D FvAdvanced + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvSecuritySize + FV =3D FvSecurity + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvOsBootSize + FV =3D FvOsBoot + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvUefiBootSize + FV =3D FvUefiBoot + + # + # Calculate base addresses (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # Each base is the prior region's base plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase =3D gCpPla= tFlashTokenSpaceGuid.PcdFlashFdMainBase + gMinPlatformPkgTokenSpace= Guid.PcdFlashFvAdvancedOffset + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase + gMinPlatformPkgTokenSpace= Guid.PcdFlashFvAdvancedSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvSecurityBase + gMinPlatformPkgTokenSpace= Guid.PcdFlashFvSecuritySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvOsBootBase + gMinPlatformPkgTokenSpace= Guid.PcdFlashFvOsBootSize + +##########################################################################= ###### +# +# FD BINARY +# +# Contains the OPROM and other binary modules +# +# Layout: (Low address to high address) +# +# FvOpRom containing pre-built components +# FvAcmRegion containing ACM related content +# FV Header + Blank Space (1K) +# Policy block (3K) +# Blank space to align ACM on 64K boundary (60K) +# ACM binary +# FvMicrocode containing microcode update patches +# Unformatted region for PCI Gen 3 Data +# FvVpd containing PCD VPD data +# FvWhea for WHEA data recording +# FvNvStorageVariable for UEFI Variable storage +# FvNvStorageEventLog for NV Store management +# FvNvStorageFtwWorking for Fault Tolerant Write solution +# FvNvStorageFtwSpare for Fault Tolerant Write solution +# +##########################################################################= ###### +[FD.Binary] + BaseAddress =3D 0xFF000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBin= aryBase + Size =3D 0x002E0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBin= arySize + ErasePolarity =3D 1 + BlockSize =3D 0x1000 + NumBlocks =3D 0x2E0 + + # + # These must add up to the FD Size. + # This makes it easy to adjust the various sizes without having to manua= lly calculate the offsets. + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize =3D = 0x00100000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize =3D = 0x00050000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D = 0x000D0000 + SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize =3D = 0x00010000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize =3D = 0x00030000 + # + # These four items are tightly coupled. + # The spare area size must be >=3D the first three areas. + # + # There isn't really a benefit to a larger spare area unless the FLASH d= evice + # block size is larger than the size specified. + # + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D = 0x0003C000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize =3D = 0x00002000 + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D = 0x00002000 + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gCpPlatFlash= TokenSpaceGuid.PcdFlashFvNvStorageEventLogSize +gEfiMdeModulePkgTokenSpaceG= uid.PcdFlashNvStorageFtwWorkingSize + + # + # Calculate Offsets Once (You should not need to modify this section) + # Each offset is the prior region's offset plus the prior region's size. + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset = =3D 0x00000000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset = =3D gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset + gCpPl= atFlashTokenSpaceGuid.PcdFlashFvOpromSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = =3D gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset + gCpPl= atFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize + SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset = =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinP= latformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset = =3D gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset + gPlat= formModuleTokenSpaceGuid.PcdFlashFvVpdSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = =3D gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset + gCpPl= atFlashTokenSpaceGuid.PcdFlashFvWheaSize + SET gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset = =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset + gEfiM= deModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = =3D gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset + gCpPl= atFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset + gEfiM= deModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + + # + # Set gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress dynamically + # + SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = =3D gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gMinP= latformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinPlatformPk= gTokenSpaceGuid.PcdMicrocodeOffsetInFv + SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize - gMinP= latformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv + + # + # FV Layout (You should not need to modify this section) + # + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|gCpPlatFlashTokenSpaceG= uid.PcdFlashFvOpromSize + FV =3D FvOprom + + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset|gCpPlatFlashTokenSp= aceGuid.PcdFlashFvAcmRegionSize + FV =3D FvAcm + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|gMinPlatformPkgT= okenSpaceGuid.PcdFlashFvMicrocodeSize + FV =3D FvMicrocode + + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|gPlatformModuleTokenSp= aceGuid.PcdFlashFvVpdSize + FV =3D FvVPD + + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset|gCpPlatFlashTokenSpaceGu= id.PcdFlashFvWheaSize + FV =3D FvWhea + + # + # Do not modify. + # See comments in size discussion above. These four areas are tightly c= oupled and should be modified with utmost care. + # + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeMod= ulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + !include WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf + gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|gCpPlatF= lashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize + DATA =3D { 0xFF } # Hack to ensure build doesn't treat the next PCD as B= ase/Size to be written + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeM= odulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + !include WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorageFtwWorking.fdf + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeMod= ulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + DATA =3D { 0xFF } # Hack to ensure build doesn't treat the next PCD as B= ase/Size to be written + + # + # Calculate base addresses (You should not need to modify this section) + # Each base is the prior region's base plus the prior region's size. + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvOpromOffset + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvOpromSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvAcmRegionSize + SET gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress =3D = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase + gMinPlatf= ormPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + $(VPD_HEADER_SIZE) + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase =3D = gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress + gPlatform= ModuleTokenSpaceGuid.PcdFlashFvVpdSize - $(VPD_HEADER_SIZE) + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvWheaSize + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase =3D = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeMo= dulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase =3D = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeMo= dulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + + # + # ACM details + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase =3D gCpPlatF= lashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x1000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize =3D 0x3000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase =3D gCpPlatF= lashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x10000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize =3D 0x000400= 00 + + # + # Other duplicate PCD + # + SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase =3D gCpPlatF= lashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFla= shFvAcmRegionSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize + SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize =3D gMinPlat= formPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D gCpuUnco= reTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase + SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D gCpuUnco= reTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize +##########################################################################= ###### +# +# FD FPGA +# +# Contains the FPGA modules +# +##########################################################################= ###### + +[FD.Fpga] + BaseAddress =3D 0xFD000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpg= aBase #The base address of the FPGA Device ( 4G - 48M ) + Size =3D 0x02000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpg= aSize #The size in bytes of the FPGA Device ( 32M ) + ErasePolarity =3D 1 + BlockSize =3D 0x1000 + NumBlocks =3D 0x2000 + + 0x00000000|0x02000000 + gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase | gCpPlatFlashTokenSpac= eGuid.PcdFlashFvFpgaBbsSize + FV =3D FvFpga + +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### + +[FV.FvSecurityPreMemory] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 40ab290f-8494-41cf-b302-31b178b4ce0b + + !include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fdf + +[FV.FvPreMemory] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 6522280D-28F9-4131-ADC4-F40EBFA45864 + + INF UefiCpuPkg/SecCore/SecCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/ExReportStatusC= odeRouterPei.inf + INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/ExStatusCodeHa= ndlerPei.inf + + INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf + + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.= inf + + INF WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf + + INF WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf + + FILE PEIM =3D ac4b7f1b-e057-47d3-b2b5-1137493c0f38 { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f= 1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR= )/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.efi + SECTION UI =3D "DynamicSiLibraryPei" + } + + INF WhitleyOpenBoardPkg/Features/Variable/PlatformVariable/Pei/Platform= VariableInitPei.inf + + INF WhitleyOpenBoardPkg/Platform/Pei/EmulationPlatformInit/EmulationPla= tformInit.inf + + INF WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.inf + + # + # UBA common and board specific components + # + !include WhitleyOpenBoardPkg/Uba/UbaPei.fdf + + INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf + + INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf + + FILE PEIM =3D ca8efb69-d7dc-4e94-aad6-9fb373649161 { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb= 69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR= )/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.efi + SECTION UI =3D "SiliconPolicyInitPreAndPostMem" + } + + INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf + + !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfr= astructurePreMemory.fdf + + INF WhitleyOpenBoardPkg/Universal/PeiInterposerToSvidMap/PeiInterposerTo= SvidMap.inf + + INF RuleOverride =3D LzmaCompress UefiCpuPkg/CpuMpPei/CpuMpPei.inf + + !if $(FSP_MODE) =3D=3D 0 + FILE PEIM =3D 8F7F3D20-9823-42DD-9FF7-53DAC93EF407 { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F= 3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_D= IR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.efi + SECTION UI =3D "CsrPseudoOffsetInitPeim" + } + FILE PEIM =3D 2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352 { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6C= ACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_D= IR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.efi + SECTION UI =3D "RegAccessPeim" + } + FILE PEIM =3D C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67F { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9= BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_D= IR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.efi + SECTION UI =3D "SiliconDataInitPeim" + } + INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf + INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + INF WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi/DummyPchSpi.inf + !endif + + FILE FV_IMAGE =3D 40ab290f-8494-41cf-b302-31b178b4ce0b { + SECTION FV_IMAGE =3D FvSecurityPreMemory + } + +[FV.FvAdvancedPreMemory] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 09f25d44-b2ef-4225-8b2e-e0e094b51775 + + !include AdvancedFeaturePkg/Include/PreMemory.fdf + +[FV.FvBspPreMemory] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D e6c65995-8c2d-4119-a52d-7dbf1acb45a1 + + FILE FV_IMAGE =3D 09f25d44-b2ef-4225-8b2e-e0e094b51775 { + SECTION FV_IMAGE =3D FvAdvancedPreMemory + } + +# +# FvPostMemory includes common hardware, common core variable services, lo= ad and invoke DXE etc +# +[FV.FvPostMemoryUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA + +[FV.FvPostMemory] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 3298afc4-c484-47f1-a65a-5917a54b5e8c + + FILE FV_IMAGE =3D B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvPostMemoryUncompressed + } + } + +# +# FvBsp includes board specific components +# +[FV.FvBspUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D e4c65347-fd90-4143-8a41-113e1015fe07 + +[FV.FvBsp] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 9e151cf3-ca90-444f-b33b-a9941cbc772f + + FILE FV_IMAGE =3D e4c65347-fd90-4143-8a41-113e1015fe07 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvBspUncompressed + } + } + +[FV.FvUefiBootUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D C4D3B0E2-FB26-44f8-A05B-E95895FCB960 + + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.= inf + INF MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDx= e.inf + + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDx= e.inf + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.in= f + #ATA for IDE/AHCI/RAID support + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestD= xe.inf + INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + + FILE DRIVER =3D 85299F8F-F2B9-4487-AF60-231434A5EFF6 { + SECTION PE32 =3D edk2-non-osi/Drivers/ASpeed/ASpeedGopBinPkg/X64/ASpee= dAst2600Gop.efi + } + + +[FV.FvUefiBoot] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D ab9fe87b-1e37-440c-91cc-9aea03ce7bec + + FILE FV_IMAGE =3D C4D3B0E2-FB26-44f8-A05B-E95895FCB960 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvUefiBootUncompressed + } + } + +[FV.FvOsBootUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 + + # + # DXE Phase modules + # + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStat= usCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandl= erRuntimeDxe.inf + + FILE FV_IMAGE =3D B7C9F0CB-15D8-26FC-CA3F-C63947B12831 { + SECTION UI =3D "FvLateSilicon" + SECTION FV_IMAGE =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateS= ilicon.fv + } + + INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.in= f + + !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfr= astructurePostMemory.fdf + + # + # UBA DXE common and board specific components + # + !include WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf + INF $(RP_PKG)/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf + INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeAowanda/Dxe/UsbOcUpdateDxe/UsbOcUpda= teDxe.inf + INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeAowanda/Dxe/IioCfgUpdateDxe/IioCfgUp= dateDxe.inf + INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeAowanda/Dxe/SlotDataUpdateDxe/SlotDa= taUpdateDxe.inf + INF WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/PlatformType.inf + INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + + !if ($(FSP_MODE) =3D=3D 1) + INF WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSave.inf + !else + INF MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf + !endif + + INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + INF WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf + INF UefiCpuPkg/CpuDxe/CpuDxe.inf + INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf + + FILE FV_IMAGE =3D a0277d07-a725-4823-90f9-6cba00782111 { + SECTION UI =3D "FvLateOpenBoard" + SECTION FV_IMAGE =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateO= penBoard.fv + } + + INF MdeModulePkg/Universal/Metronome/Metronome.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntime= Dxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + + INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciHostBridge.in= f + INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf + + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterR= untimeDxe.inf + INF RuleOverride =3D UI MdeModulePkg/Application/UiApp/UiApp.inf + INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + #TPM when TPM enable, SecurityStubDxe needs to be removed from this FV. + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + + INF FatPkg/EnhancedFatDxe/Fat.inf + + INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf + + INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPlatform.inf + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + INF ShellPkg/Application/Shell/Shell.inf + + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + + INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf + INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf + + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeR= outerSmm.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.i= nf + + INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf + + INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf + INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf + + INF IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf + + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.= inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.in= f + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf + + INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBu= fferDxe.inf + + INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf + + INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecuto= rDxe.inf + + # UEFI USB stack + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + + INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf + INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + + INF RuleOverride =3D ACPITABLE WhitleyOpenBoardPkg/Features/Acpi/AcpiTa= bles/AcpiTables10nm.inf + INF WhitleyOpenBoardPkg/Features/Acpi/AcpiPlatform/AcpiPlatform.inf + INF WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf + INF MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf + +[FV.FvOsBoot] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D c7488640-5f51-4969-b63b-89fc369e1725 + + FILE FV_IMAGE =3D CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvOsBootUncompressed + } + } + +[FV.FvSecuritySilicon] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D AD262F8D-BDED-4668-A8D4-8BC73516652F + + !include MinPlatformPkg/Include/Fdf/CoreSecurityLateInclude.fdf + +[FV.FvSecurityUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 03E25550-89A5-4ee6-AF60-DB0553D91FD2 + + FILE FV_IMAGE =3D 81F80AEA-91EB-4AD9-A563-7CEBAA167B25 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvSecuritySilicon + } + } + +[FV.FvSecurity] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 68134833-2ff6-4d22-973b-575d0eae8ffd + + FILE FV_IMAGE =3D 03E25550-89A5-4ee6-AF60-DB0553D91FD2 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvSecurityUncompressed + } + } + +[FV.FvAdvancedUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 70aeaf57-4997-49ce-a4f7-122980745670 + + !include AdvancedFeaturePkg/Include/PostMemory.fdf + +[FV.FvAdvanced] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D f21ee7a1-53a9-453d-aee3-b6a5c25bada5 + + FILE FV_IMAGE =3D 70aeaf57-4997-49ce-a4f7-122980745670 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvAdvancedUncompressed + } + } + +# +# FV for all Microcode Updates. +# +[FV.FvMicrocode] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + LOCK_STATUS =3D FALSE + FvNameGuid =3D D2C29BA7-3809-480F-9C3D-DE389C61425A + +!if $(CPUTARGET) =3D=3D "CPX" + INF RuleOverride =3D MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/M= icrocodeUpdates.inf +!else + INF RuleOverride =3D MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/M= icrocodeUpdates.inf +!endif + + +[FV.FvVPD] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + LOCK_STATUS =3D FALSE + FvNameGuid =3D FFC29BA7-3809-480F-9C3D-DE389C61425A + FILE RAW =3D FF7DB236-F856-4924-90F8-CDF12FB875F3 { + $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/8C3D856A-9BE6-468E-= 850A-24F7A8D38E08.bin + } + +# +# Various Vendor UEFI Drivers (OROMs). +# +[FV.FvOpromUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D B6EDE22C-DE30-45fa-BB09-CA202C1654B7 + +[FV.FvOprom] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 983BCAB5-BF10-42ce-B85D-CB805DCB1EFD + + FILE FV_IMAGE =3D B6EDE22C-DE30-45fa-BB09-CA202C1654B7 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvOpromUncompressed + } + } + +[FV.FvWhea] + BlockSize =3D 0x1000 + NumBlocks =3D 0x30 + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D d6a1cd70-4b33-4994-a6ea-375f2ccc5437 + +# +# FV For ACM Binary. +# +[FV.FvAcm] + BlockSize =3D 0x1000 + NumBlocks =3D 0x50 + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 11668261-8A8D-47ca-9893-052D24435E59 + +[FV.FvFpga] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 974650E7-6DFE-4998-A124-CEDEC5C9B47D + +##########################################################################= ###### +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are = the default +# rules for the different module type. User can add the customized rules t= o define the +# content of the FFS file. +# +##########################################################################= ###### + +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + } + +[Rule.Common.DXE_RUNTIME_DRIVER.DRIVER_ACPITABLE] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe= /IioCfgUpdateDxe/IioCfgUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Aow= anda/Uba/TypeAowanda/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c new file mode 100644 index 0000000000..bbb7cfd272 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/IioCfg= UpdateDxe/IioCfgUpdateDxe.c @@ -0,0 +1,99 @@ +/** @file + IIO Config Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021 - 2022, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "IioCfgUpdateDxe.h" + +EFI_STATUS +UpdateAowandaIioConfig ( + IN IIO_GLOBALS *IioGlobalData + ) +{ + return EFI_SUCCESS; +} + +PLATFORM_IIO_CONFIG_UPDATE_TABLE TypeAowandaIioConfigTable =3D +{ + PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE, + PLATFORM_IIO_CONFIG_UPDATE_VERSION, + + IioBifurcationTable, + sizeof (IioBifurcationTable), + UpdateAowandaIioConfig, + IioSlotTable, + sizeof (IioSlotTable) +}; + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loade= d + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +IioCfgUpdateEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + + DEBUG ((EFI_D_INFO, "UBA:IioCfgUpdate-TypeAowanda\n")); + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid, + &TypeAowandaIioConfigTable, + sizeof(TypeAowandaIioConfigTable) + ); + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid_1, + &TypeAowandaIioConfigTable, + sizeof(TypeAowandaIioConfigTable) + ); + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid_2, + &TypeAowandaIioConfigTable, + sizeof(TypeAowandaIioConfigTable) + ); + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid_3, + &TypeAowandaIioConfigTable, + sizeof(TypeAowandaIioConfigTable) + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe= /IioCfgUpdateDxe/IioCfgUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/Aow= anda/Uba/TypeAowanda/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h new file mode 100644 index 0000000000..5b1e9b7d63 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/IioCfg= UpdateDxe/IioCfgUpdateDxe.h @@ -0,0 +1,99 @@ +/** @file + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ Copyright (c) 2021 - 2022, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IIOCFG_UPDATE_DXE_H_ +#define _IIOCFG_UPDATE_DXE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D 0, + Iio_Iou1, + Iio_Iou2, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + VPP_PORT_0 =3D 0, + VPP_PORT_1, + VPP_PORT_2, + VPP_PORT_3 +} VPP_PORT; + +#define ENABLE 1 +#define DISABLE 0 +#define NO_SLT_IMP 0xFF +#define SLT_IMP 1 +#define HIDE 1 +#define NOT_HIDE 0 +#define VPP_PORT_0 0 +#define VPP_PORT_1 1 +#define VPP_PORT_MAX 0xFF +#define VPP_ADDR_MAX 0xFF +#define PWR_VAL_MAX 0xFF +#define PWR_SCL_MAX 0xFF + +static IIO_BIFURCATION_DATA_ENTRY IioBifurcationTable[] =3D +{ + { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxx8xxx8 }, + { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, +}; + +static IIO_SLOT_CONFIG_DATA_ENTRY IioSlotTable[] =3D { + // Port | Slot | Inter | Power Limit | Power Limit | H= ot | Vpp | Vpp | PcieSSD | PcieSSD | PcieSSD = | Hidden + // Index | | lock | Scale | Value | P= lug | Port | Addr | Cap | VppPort | VppAddr = | + { PORT_1A_INDEX, 1 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x4C = , NOT_HIDE}, + { PORT_2A_INDEX, 7 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX, VPP_ADDR_MAX= , NOT_HIDE}, + { PORT_3A_INDEX, 2 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , E= NABLE , VPP_PORT_0 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 = , NOT_HIDE}, + { SOCKET_1_INDEX + + PORT_0_INDEX , NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX, VPP_ADDR_MAX= , HIDE }, + // Slot 4 supports HP: PCA9554 (CPU1) Address 0x40, SCH (Rev 0.604) P 12= 1 (MRL in J287) + { SOCKET_1_INDEX + + PORT_1A_INDEX, 4 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , E= NABLE , VPP_PORT_1 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 = , NOT_HIDE}, + { SOCKET_1_INDEX + + PORT_1C_INDEX, 3 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 = , NOT_HIDE}, + { SOCKET_1_INDEX + + PORT_2A_INDEX, 6 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_1 , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x44 = , NOT_HIDE}, + { SOCKET_1_INDEX + + PORT_3A_INDEX, 5 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX, VPP_ADDR_MAX= , NOT_HIDE}, +}; + +#endif //_IIOCFG_UPDATE_DXE_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe= /IioCfgUpdateDxe/IioCfgUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/A= owanda/Uba/TypeAowanda/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf new file mode 100644 index 0000000000..73e0fb04c1 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/IioCfg= UpdateDxe/IioCfgUpdateDxe.inf @@ -0,0 +1,49 @@ +## @file +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# Copyright (c) 2021 - 2022, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D IioCfgUpdateDxeAowanda + FILE_GUID =3D 90171648-20AB-469E-A816-F46A2FC7447F + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D IioCfgUpdateEntry + +[Sources] + IioCfgUpdateDxe.c + IioCfgUpdateDxe.h + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Guids] + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gEfiPlatformTypeAowandaProtocolGuid \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe= /SlotDataUpdateDxe/SlotDataUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg= /Aowanda/Uba/TypeAowanda/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c new file mode 100644 index 0000000000..bfc43b361f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/SlotDa= taUpdateDxe/SlotDataUpdateDxe.c @@ -0,0 +1,112 @@ +/** @file + Slot Data Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021 - 2022, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "SlotDataUpdateDxe.h" + +UINT8 +GetTypeAowandaIOU0Setting ( + UINT8 IOU0Data +) +{ + return IOU0Data; +} + +UINT8 +GetTypeAowandaIOU2Setting ( + UINT8 SkuPersonalityType, + UINT8 IOU2Data +) +{ + return IOU2Data; +} + +static IIO_BROADWAY_ADDRESS_DATA_ENTRY SlotTypeAowandaBroadwayTable[] = =3D { + {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 }, + {Iio_Socket1, Iio_Iou1, Bw5_Addr_2}, + {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 }, +}; + + +PLATFORM_SLOT_UPDATE_TABLE TypeAowandaSlotTable =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeAowandaBroadwayTable, + GetTypeAowandaIOU0Setting, + 0 +}; + +PLATFORM_SLOT_UPDATE_TABLE2 TypeAowandaSlotTable2 =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeAowandaBroadwayTable, + GetTypeAowandaIOU0Setting, + 0, + GetTypeAowandaIOU2Setting +}; + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loade= d + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +SlotDataUpdateEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + + DEBUG((DEBUG_INFO, "UBA:SlotDataUpdate-TypeAowanda\n")); + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformSlotDataDxeGuid, + &TypeAowandaSlotTable, + sizeof(TypeAowandaSlotTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformSlotDataDxeGuid, + &TypeAowandaSlotTable2, + sizeof(TypeAowandaSlotTable2) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe= /SlotDataUpdateDxe/SlotDataUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg= /Aowanda/Uba/TypeAowanda/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h new file mode 100644 index 0000000000..51ac64e58b --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/SlotDa= taUpdateDxe/SlotDataUpdateDxe.h @@ -0,0 +1,57 @@ +/** @file + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ Copyright (c) 2021 - 2022, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SLOT_DATA_UPDATE_DXE_H_ +#define _SLOT_DATA_UPDATE_DXE_H_ + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D 0, + Iio_Iou1, + Iio_Iou2, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + Bw5_Addr_0 =3D 0, + Bw5_Addr_1, + Bw5_Addr_2, + Bw5_Addr_3, + Bw5_Addr_Max +} BW5_ADDRESS; + +#endif //_SLOT_DATA_UPDATE_DXE_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe= /SlotDataUpdateDxe/SlotDataUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardP= kg/Aowanda/Uba/TypeAowanda/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf new file mode 100644 index 0000000000..60d093d63c --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/SlotDa= taUpdateDxe/SlotDataUpdateDxe.inf @@ -0,0 +1,49 @@ +## @file +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# Copyright (c) 2021 - 2022, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SlotDataUpdateDxeAowanda + FILE_GUID =3D 5D22BB40-92CA-4A7C-93C5-9AEEC770A634 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SlotDataUpdateEntry + +[Sources] + SlotDataUpdateDxe.c + SlotDataUpdateDxe.h + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Guids] + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gEfiPlatformTypeAowandaProtocolGuid \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe= /UsbOcUpdateDxe/UsbOcUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Aowan= da/Uba/TypeAowanda/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c new file mode 100644 index 0000000000..527cdcdd70 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/UsbOcU= pdateDxe/UsbOcUpdateDxe.c @@ -0,0 +1,128 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021 - 2022, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "UsbOcUpdateDxe.h" + +#include +#include +#include +#include + +USB_OVERCURRENT_PIN TypeAowandaUsb20OverCurrentMappings[PCH_MAX_USB2_PORT= S] =3D { + UsbOverCurrentPin0, // Port01: USB 2.0 CONN= ECTOR + UsbOverCurrentPinSkip, // Port02: NC + UsbOverCurrentPinSkip, // Port03: NC + UsbOverCurrentPinSkip, // Port04: NC + UsbOverCurrentPinSkip, // Port05: NC + UsbOverCurrentPinSkip, // Port06: NC + UsbOverCurrentPinSkip, // Port07: TO BMC + UsbOverCurrentPinSkip, // Port08: NC + UsbOverCurrentPinSkip, // Port09: NC + UsbOverCurrentPinSkip, // Port10: OCP3.0 SLOT + UsbOverCurrentPinSkip, // Port11: NC + UsbOverCurrentPinSkip, // Port12: NC + UsbOverCurrentPinSkip, // Port13: NC + UsbOverCurrentPinSkip, // Port14: NC + UsbOverCurrentPinSkip, // Port15: NC + UsbOverCurrentPinSkip // Port16: NC +}; + +USB_OVERCURRENT_PIN TypeAowandaUsb30OverCurrentMappings[PCH_MAX_USB3_PORT= S] =3D { + UsbOverCurrentPinSkip, // Port01: NC + UsbOverCurrentPinSkip, // Port02: NC + UsbOverCurrentPinSkip, // Port03: NC + UsbOverCurrentPinSkip, // Port04: NC + UsbOverCurrentPinSkip, // Port05: NC + UsbOverCurrentPinSkip, // Port06: NC + UsbOverCurrentPinSkip, // Port07: NC + UsbOverCurrentPinSkip, // Port08: NC + UsbOverCurrentPinSkip, // Port09: NC + UsbOverCurrentPinSkip // Port10: NC +}; + +USB2_PHY_PARAMETERS TypeAowandaUsb20AfeParams[PCH_H_XHCI_MAX_USB2_PHYSICA= L_PORTS] =3D { + { 3, 0, 3, 1 }, // PP0 + { 5, 0, 3, 1 }, // PP1 + { 3, 0, 3, 1 }, // PP2 + { 0, 5, 1, 1 }, // PP3 + { 3, 0, 3, 1 }, // PP4 + { 3, 0, 3, 1 }, // PP5 + { 3, 0, 3, 1 }, // PP6 + { 3, 0, 3, 1 }, // PP7 + { 2, 2, 1, 0 }, // PP8 + { 6, 0, 2, 1 }, // PP9 + { 2, 2, 1, 0 }, // PP10 + { 6, 0, 2, 1 }, // PP11 + { 0, 5, 1, 1 }, // PP12 + { 7, 0, 2, 1 }, // PP13 +}; + +EFI_STATUS +TypeAowandaPlatformUsbOcUpdateCallback ( + IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings, + IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings, + IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams + ) +{ + *Usb20OverCurrentMappings =3D &TypeAowandaUsb20OverCurrentMappings[0]; + *Usb30OverCurrentMappings =3D &TypeAowandaUsb30OverCurrentMappings[0]; + + *Usb20AfeParams =3D TypeAowandaUsb20AfeParams; + return EFI_SUCCESS; +} + +PLATFORM_USBOC_UPDATE_TABLE TypeAowandaUsbOcUpdate =3D +{ + PLATFORM_USBOC_UPDATE_SIGNATURE, + PLATFORM_USBOC_UPDATE_VERSION, + TypeAowandaPlatformUsbOcUpdateCallback +}; + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loade= d + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +UsbOcUpdateEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + + DEBUG ((DEBUG_INFO, "UBA:UsbOcUpdate-TypeAowanda\n")); + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gDxePlatformUbaOcConfigDataGuid, + &TypeAowandaUsbOcUpdate, + sizeof(TypeAowandaUsbOcUpdate) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe= /UsbOcUpdateDxe/UsbOcUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/Aowan= da/Uba/TypeAowanda/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h new file mode 100644 index 0000000000..821ce74041 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/UsbOcU= pdateDxe/UsbOcUpdateDxe.h @@ -0,0 +1,24 @@ +/** @file + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _USBOC_UPDATE_DXE_H_ +#define _USBOC_UPDATE_DXE_H_ + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#endif //_USBOC_UPDATE_DXE_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe= /UsbOcUpdateDxe/UsbOcUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Aow= anda/Uba/TypeAowanda/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf new file mode 100644 index 0000000000..d8ee9497d0 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Dxe/UsbOcU= pdateDxe/UsbOcUpdateDxe.inf @@ -0,0 +1,45 @@ +## @file +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# Copyright (c) 2021 - 2022, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D UsbOcUpdateDxeAowanda + FILE_GUID =3D 24CE8219-DBB5-4FA4-A2ED-DB87DA7EB6EB + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D UsbOcUpdateEntry + +[sources] + UsbOcUpdateDxe.c + UsbOcUpdateDxe.h + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Guids] + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gEfiPlatformTypeAowandaProtocolGuid \ No newline at end of file diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei= /AcpiTablePcds.c b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowan= da/Pei/AcpiTablePcds.c new file mode 100644 index 0000000000..0dfdec9279 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/AcpiTa= blePcds.c @@ -0,0 +1,54 @@ +/** @file + ACPI table pcds update. + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ Copyright (c) 2021 - 2022, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include +#include +#include +#include + +EFI_STATUS +TypeAowandaPlatformUpdateAcpiTablePcds ( + VOID + ) +{ + CHAR8 AcpiName10nm[] =3D "EPRP10NM"; // USED for identify ACP= I table for 10nm in systmeboard dxe driver + CHAR8 OemTableIdXhci[] =3D "xh_nccrb"; + + UINTN Size; + EFI_STATUS Status; + + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + + DEBUG ((DEBUG_INFO, "Uba Callback: PlatformAowandaUpdateAcpiTablePcds en= tered\n")); + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob); + // # + // #ACPI items + // # + Size =3D AsciiStrSize (AcpiName10nm); + Status =3D PcdSetPtrS (PcdOemSkuAcpiName, &Size, AcpiName10nm); + DEBUG ((DEBUG_INFO, "%a TypeAowanda ICX\n", __FUNCTION__)); + ASSERT_EFI_ERROR (Status); + + Size =3D AsciiStrSize (OemTableIdXhci); + Status =3D PcdSetPtrS (PcdOemTableIdXhci, &Size, OemTableIdXhci); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei= /GpioTable.c b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/P= ei/GpioTable.c new file mode 100644 index 0000000000..1414d02728 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/GpioTa= ble.c @@ -0,0 +1,329 @@ +/** @file + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ Copyright (c) 2021 - 2022, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include + +#include +#include +#include +#include + +// +// Board : Aowanda +// +static GPIO_INIT_CONFIG mGpioTableAowanda [] =3D + { =20 +// Group A AWD + {GPIO_SKL_H_GPP_A0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, G= pioPadConfigLock}},//GPP_A_0_PU_IRQ_ESPI_ALERT1_N + {GPIO_SKL_H_GPP_A1, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_1_ESPI_IO0 + {GPIO_SKL_H_GPP_A2, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_2_ESPI_IO1 + {GPIO_SKL_H_GPP_A3, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_3_ESPI_IO2 + {GPIO_SKL_H_GPP_A4, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_4_ESPI_IO3 + {GPIO_SKL_H_GPP_A5, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_5_ESPI_CS0_N + {GPIO_SKL_H_GPP_A6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_6_PU_ESPI_CS1_N + {GPIO_SKL_H_GPP_A7, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_7_IRQ_ESPI_ALERT0_N + {GPIO_SKL_H_GPP_A8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_8_PU_LPC_CLKRUN_N + {GPIO_SKL_H_GPP_A9, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_9_ESPI_CLK + {GPIO_SKL_H_GPP_A10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_10_TP_PCH_GPP_A10 + {GPIO_SKL_H_GPP_A11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_11_PU_LPC_PME_N + {GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_12_PU_IRQ_PCH_SCI_WHEA_N + {GPIO_SKL_H_GPP_A13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_13_TP_PCH_GPP_A13 + {GPIO_SKL_H_GPP_A14, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_14_RST_ESPI_RESET_N=20 + {GPIO_SKL_H_GPP_A15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_15_PU_SUSACK_N =20 + {GPIO_SKL_H_GPP_A16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_16_TP_PCH_GPP_A16 + {GPIO_SKL_H_GPP_A17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_17_TP_PCH_GPP_A17=20 + {GPIO_SKL_H_GPP_A18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_18_TP_PCH_GPP_A18 + //ME recovery jumper =20 + //{GPIO_SKL_H_GPP_A19, { GpioPadModeGpio, GpioHostOwnDefault, Gp= ioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_A_19_FM_ME_RCVR_N + {GPIO_SKL_H_GPP_A20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_20_TP_PCH_GPP_A20 + {GPIO_SKL_H_GPP_A21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_21_TP_PCH_GPP_A21 + {GPIO_SKL_H_GPP_A22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_22_TP_PCH_GPP_A22 + {GPIO_SKL_H_GPP_A23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_23_TP_PCH_GPP_A23 + +// Group B AWD + {GPIO_SKL_H_GPP_B0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_0_FM_PCH_CORE_VID<0> + {GPIO_SKL_H_GPP_B1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_1_FM_PCH_CORE_VID<1> + {GPIO_SKL_H_GPP_B2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_2_PU_PCH_VRALERT_N + {GPIO_SKL_H_GPP_B3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_3_FM_BIOS_ENTER_SETUP_N + {GPIO_SKL_H_GPP_B4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_4_FM_BIOS_POST_START_N + {GPIO_SKL_H_GPP_B5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, G= pioPadConfigLock}},//GPP_B_5_FM_OCP3_BIF_READY + {GPIO_SKL_H_GPP_B6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_6_FM_CLKREQ_M2_SSD1_N + {GPIO_SKL_H_GPP_B7, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_7_FM_CLKREQ_M2_SSD2_N + {GPIO_SKL_H_GPP_B8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_8_PU_GPP_PCH_B8 + {GPIO_SKL_H_GPP_B9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_9_FM_BOARD_REV_ID2 + {GPIO_SKL_H_GPP_B10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_10_FM_TPM_PRSNT_N + {GPIO_SKL_H_GPP_B11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_11_FM_PMBUS_ALERT_BUF_EN_N + {GPIO_SKL_H_GPP_B12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_12_TP_PCH_GPP_B12 + {GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_13_RST_PLTRST_N + {GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_14_FM_PCH_BIOS_RCVR_SPKR + {GPIO_SKL_H_GPP_B15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_15_FM_CPU_ERR0_PCH_N + {GPIO_SKL_H_GPP_B16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_16_FM_CPU_ERR1_PCH_N + {GPIO_SKL_H_GPP_B17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_17_FM_CPU_ERR2_PCH_N + {GPIO_SKL_H_GPP_B18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_18_FM_NO_REBOOT + {GPIO_SKL_H_GPP_B19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_19_FM_BOARD_SKU_ID5 + {GPIO_SKL_H_GPP_B20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_20_FM_BIOS_POST_CMPLT_N + {GPIO_SKL_H_GPP_B21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_21_FM_FAST_PROCHOT_EN_N + {GPIO_SKL_H_GPP_B22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_22_FM_OCP3_FRU + {GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_23_FM_PCH_BMC_THRMTRIP_EXI_STRAP_N + +// Group C AWD + {GPIO_SKL_H_GPP_C0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_0_SMB4_HOST_STBY_BMC_LVC3_SCL + {GPIO_SKL_H_GPP_C1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_1_SMB4_HOST_STBY_BMC_LVC3_SDA + {GPIO_SKL_H_GPP_C2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_2_PU_PCH_TLS_ENABLE_STRAP_PCH + {GPIO_SKL_H_GPP_C3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_3_SMB6_SMLINK0_STBY_LVC3_SCL + {GPIO_SKL_H_GPP_C4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_4_SMB6_SMLINK0_STBY_LVC3_SDA + {GPIO_SKL_H_GPP_C5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_5_IRQ_SML0_ALERT_N + {GPIO_SKL_H_GPP_C6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_6_SMB8_PMBUS_SML1_STBY_LVC3_SCL + {GPIO_SKL_H_GPP_C7, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_7_SMB8_PMBUS_SML1_STBY_LVC3_SDA + {GPIO_SKL_H_GPP_C8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_8_FM_PASSWORD_CLEAR_N + {GPIO_SKL_H_GPP_C9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_9_FM_MFG_MODE + {GPIO_SKL_H_GPP_C10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_10_FM_SATA_RAID_KEY + {GPIO_SKL_H_GPP_C11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_11_TP_PCH_GPP_C11 + {GPIO_SKL_H_GPP_C12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_12_FM_BOARD_REV_ID0 + {GPIO_SKL_H_GPP_C13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_13_FM_BOARD_REV_ID1 + {GPIO_SKL_H_GPP_C14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_14_FM_BMC_PCH_SCI_LPC_N + {GPIO_SKL_H_GPP_C15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_15_FM_RISER1_ID_0 + {GPIO_SKL_H_GPP_C16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_16_FM_RISER1_ID_1 + {GPIO_SKL_H_GPP_C17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_17_FM_RISER1_ID_2 + {GPIO_SKL_H_GPP_C18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_18_FM_RISER2_ID_0 + {GPIO_SKL_H_GPP_C19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_19_FM_RISER2_ID_1 + // ME PROCHOT =20 + //{GPIO_SKL_H_GPP_C20, { GpioPadModeGpio, GpioHostOwnDefault, Gp= ioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_C_20_FM_THROTTLE_N + {GPIO_SKL_H_GPP_C21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_21_RST_PCH_PCIE_SMB_MUX_NX1 + {GPIO_SKL_H_GPP_C22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_22_IRQ_BMC_PCH_SMI_LPC_N + {GPIO_SKL_H_GPP_C23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_23_FM_CPU_CATERR_DLY_LVT3_R_N + +// Group D AWD + {GPIO_SKL_H_GPP_D0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntLevel | GpioIntNmi, GpioResetPwrGood, G= pioTermNone, GpioPadConfigLock}},//GPP_D_0_IRQ_BMC_PCH_NMI + {GPIO_SKL_H_GPP_D1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_1_TP_PCH_GPP_D1 + {GPIO_SKL_H_GPP_D2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_2_TP_PCH_GPP_D2 + {GPIO_SKL_H_GPP_D3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_3_TP_PCH_GPP_D3 + {GPIO_SKL_H_GPP_D4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_4_FM_PLD_PCH_DATA + {GPIO_SKL_H_GPP_D5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_5_FM_OCP3_BIF0 + {GPIO_SKL_H_GPP_D6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_6_FM_OCP3_BIF1 + {GPIO_SKL_H_GPP_D7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_7_FM_OCP3_BIF2 + {GPIO_SKL_H_GPP_D8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_8_TP_PCH_GPP_D8 + {GPIO_SKL_H_GPP_D9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_9_IRQ_FORCE_NM_THROTTLE_N + {GPIO_SKL_H_GPP_D10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_10_TP_PCH_GPP_D10 + {GPIO_SKL_H_GPP_D11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_11_IRQ_LOM_ALERT_N + {GPIO_SKL_H_GPP_D12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_12_PU_PCH_GPP_D12 + {GPIO_SKL_H_GPP_D13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_13_PU_PCH_GPP_D13 + {GPIO_SKL_H_GPP_D14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_14_PU_PCH_GPP_D14 + {GPIO_SKL_H_GPP_D15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_15_PU_PCH_GPP_D15 + {GPIO_SKL_H_GPP_D16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_16_FM_ME_PFR_1 + {GPIO_SKL_H_GPP_D17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_17_FM_ME_PFR_2 + {GPIO_SKL_H_GPP_D18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_18_PU_PCH_GPP_D18 + {GPIO_SKL_H_GPP_D19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_19_FM_PS_PWROK_DLY_SEL_R + {GPIO_SKL_H_GPP_D20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_20_FM_OCP3_PRSNTB0_N + {GPIO_SKL_H_GPP_D21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_21_FM_OCP3_PRSNTB1_N + {GPIO_SKL_H_GPP_D22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_22_FM_OCP3_PRSNTB2_N + {GPIO_SKL_H_GPP_D23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_23_FM_OCP3_PRSNTB3_N + +// Group E AWD =20 + {GPIO_SKL_H_GPP_E0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_0_FM_M2_SSD1_PEDET + // ME Heartbeat =20 + //{GPIO_SKL_H_GPP_E1, { GpioPadModeGpio, GpioHostOwnDefault, Gp= ioDirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_E_1_FM_ME_HEARTBEAT_N + {GPIO_SKL_H_GPP_E2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_2_TP_PCH_GPP_E2 + {GPIO_SKL_H_GPP_E3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_3_FM_ADR_TRIGGER_R_N + {GPIO_SKL_H_GPP_E4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_4_FM_HSC_TIMER_EXP_N + {GPIO_SKL_H_GPP_E5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_5_TP_PCH_GPP_E5 + {GPIO_SKL_H_GPP_E6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_6_TP_PCH_GPP_E6 + {GPIO_SKL_H_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_7_FM_ADR_SMI_GPIO_R_N + {GPIO_SKL_H_GPP_E8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_8_TP_PCH_GPP_E8 + {GPIO_SKL_H_GPP_E9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_9_OC_PCH_USB_P01_N + {GPIO_SKL_H_GPP_E10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_10_TP_PCH_GPP_E10 + {GPIO_SKL_H_GPP_E11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_11_PU_PCH_GPP_E11 + {GPIO_SKL_H_GPP_E12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_12_IRQ_UV_DETECT_N + +// Group F AWD + {GPIO_SKL_H_GPP_F0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_0_IRQ_OC_DETECT_N + {GPIO_SKL_H_GPP_F1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_1_FM_M2_SSD2_PEDET + {GPIO_SKL_H_GPP_F2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_2_FM_PCIE_SLOT1_PRSNT_N + {GPIO_SKL_H_GPP_F3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_3_FM_PCIE_SLOT2_PRSNT_N + {GPIO_SKL_H_GPP_F4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_4_FM_PCIE_SLOT3_PRSNT_N + {GPIO_SKL_H_GPP_F5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_5_IRQ_TPM_SPI_N + {GPIO_SKL_H_GPP_F6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_6_FM_EDSFF0_PRSNT_N + {GPIO_SKL_H_GPP_F7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_7_FM_EDSFF1_PRSNT_N + {GPIO_SKL_H_GPP_F8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_8_FM_EDSFF2_PRSNT_N + {GPIO_SKL_H_GPP_F9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_9_FM_EDSFF3_PRSNT_N + {GPIO_SKL_H_GPP_F10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_10_PU_PCH_GPP_F10 + {GPIO_SKL_H_GPP_F11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_11_PU_PCH_GPP_F11 + {GPIO_SKL_H_GPP_F12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_12_PU_PCH_GPP_F12 + {GPIO_SKL_H_GPP_F13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_13_PU_PCH_GPP_F13 + {GPIO_SKL_H_GPP_F14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_14_PU_PCH_GPP_F14 + {GPIO_SKL_H_GPP_F15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_15_FM_FORCE_ADR_N + {GPIO_SKL_H_GPP_F16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_16_PU_PCH_GPP_F16 + {GPIO_SKL_H_GPP_F17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_17_PU_PCH_GPP_F17 + {GPIO_SKL_H_GPP_F18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_18_PU_PCH_GPP_F18 + {GPIO_SKL_H_GPP_F19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_19_PU_PCH_GPP_F19 + {GPIO_SKL_H_GPP_F20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_20_PU_PCH_GPP_F20 + {GPIO_SKL_H_GPP_F21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_21_PU_PCH_GPP_F21 + {GPIO_SKL_H_GPP_F22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_22_PU_PCH_GPP_F22 + {GPIO_SKL_H_GPP_F23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_23_PU_PCH_GPP_F23 + +// Group G AWD + {GPIO_SKL_H_GPP_G0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_0_TP_PCH_GPP_G0 + {GPIO_SKL_H_GPP_G1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_1_TP_PCH_GPP_G1 + {GPIO_SKL_H_GPP_G2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_2_TP_PCH_GPP_G2 + {GPIO_SKL_H_GPP_G3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_3_TP_PCH_GPP_G3 + {GPIO_SKL_H_GPP_G4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_4_TP_PCH_GPP_G4 + {GPIO_SKL_H_GPP_G5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_5_TP_PCH_GPP_G5 + {GPIO_SKL_H_GPP_G6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_6_TP_PCH_GPP_G6 + {GPIO_SKL_H_GPP_G7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_7_TP_PCH_GPP_G7 + {GPIO_SKL_H_GPP_G8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_8_TP_PCH_GPP_G8 + {GPIO_SKL_H_GPP_G9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_9_TP_PCH_GPP_G9 + {GPIO_SKL_H_GPP_G10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_10_TP_PCH_GPP_G10 + {GPIO_SKL_H_GPP_G11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_11_TP_PCH_GPP_G11 + {GPIO_SKL_H_GPP_G12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_12_FM_BOARD_SKU_ID0 + {GPIO_SKL_H_GPP_G13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_13_FM_BOARD_SKU_ID1 + {GPIO_SKL_H_GPP_G14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_14_FM_BOARD_SKU_ID2 + {GPIO_SKL_H_GPP_G15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_15_FM_BOARD_SKU_ID3 + {GPIO_SKL_H_GPP_G16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_16_FM_BOARD_SKU_ID4 + {GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_17_FM_ADR_COMPLETE + {GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_18_IRQ_NMI_EVENT_N + {GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_19_IRQ_SMI_ACTIVE_N + {GPIO_SKL_H_GPP_G20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_20_IRQ_SML1_PMBUS_PCH_ALERT_N + {GPIO_SKL_H_GPP_G21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_21_PU_PCH_GPP_G21 + {GPIO_SKL_H_GPP_G22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_22_TP_PCH_GPP_G22 + {GPIO_SKL_H_GPP_G23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_23_TP_PCH_GPP_G23 + +// Group H AWD + {GPIO_SKL_H_GPP_H0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_0_TP_PCH_GPP_H0 + {GPIO_SKL_H_GPP_H1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_1_TP_PCH_GPP_H1 + {GPIO_SKL_H_GPP_H2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_2_TP_PCH_GPP_H2 + {GPIO_SKL_H_GPP_H3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_3_M2_SSD1_PRSNT_N + {GPIO_SKL_H_GPP_H4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_4_M2_SSD2_PRSNT_N + {GPIO_SKL_H_GPP_H5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_5_FM_OCP3_CLK0_EN_R_N + {GPIO_SKL_H_GPP_H6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_6_FM_OCP3_CLK1_EN_R_N + {GPIO_SKL_H_GPP_H7, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_7_FM_OCP3_CLK2_EN_R_N + {GPIO_SKL_H_GPP_H8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_8_FM_OCP3_CLK3_EN_R_N + {GPIO_SKL_H_GPP_H9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_9_TP_PCH_GPP_H9 + {GPIO_SKL_H_GPP_H10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_10_SMB11_SMLINK2_STBY_LVC3_SCL + {GPIO_SKL_H_GPP_H11, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_11_SMB11_SMLINK2_STBY_LVC3_SDA + {GPIO_SKL_H_GPP_H12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_12_FM_ESPI_FLASH_MODE + {GPIO_SKL_H_GPP_H13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_13_PU_PCH_GPP_H13 + {GPIO_SKL_H_GPP_H14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_14_PU_PCH_GPP_H14 + {GPIO_SKL_H_GPP_H15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_15_PU_ADR_TIMER_HOLD_OFF_N + {GPIO_SKL_H_GPP_H16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_16_PU_PCH_GPP_H16 + {GPIO_SKL_H_GPP_H17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_17_PU_PCH_GPP_H17 + {GPIO_SKL_H_GPP_H18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_18_FM_LT_KEY_DOWNGRADE_N + {GPIO_SKL_H_GPP_H19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_19_TP_PCH_GPP_H19 + {GPIO_SKL_H_GPP_H20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_20_TP_PCH_GPP_H20 + {GPIO_SKL_H_GPP_H21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_21_TP_PCH_GPP_H21 + {GPIO_SKL_H_GPP_H22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_22_TP_PCH_GPP_H22 + {GPIO_SKL_H_GPP_H23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_23_TP_PCH_GPP_H23 + +// Group I AWD + {GPIO_SKL_H_GPP_I0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_0_TP_PCH_GPP_I0 + {GPIO_SKL_H_GPP_I1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_1_TP_PCH_GPP_I1 + {GPIO_SKL_H_GPP_I2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_2_TP_PCH_GPP_I2 + {GPIO_SKL_H_GPP_I3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_3_TP_PCH_GPP_I3 + {GPIO_SKL_H_GPP_I4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_4_TP_PCH_GPP_I4 + {GPIO_SKL_H_GPP_I5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_5_TP_PCH_GPP_I5 + {GPIO_SKL_H_GPP_I6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_6_TP_PCH_GPP_I6 + {GPIO_SKL_H_GPP_I7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_7_TP_PCH_GPP_I7 + {GPIO_SKL_H_GPP_I8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_8_TP_PCH_GPP_I8 + {GPIO_SKL_H_GPP_I9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_9_TP_PCH_GPP_I9 + {GPIO_SKL_H_GPP_I10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_10_TP_PCH_GPP_I10 +// {GPIO_SKL_H_GPP_I11, { GpioPadModeNative1, GpioHostOwnDefault, Gp= ioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_I_11_PD_3P3_RCOMP + +// Group GPD AWD + {GPIO_SKL_H_GPD0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_0_FM_FIVRBREAK_N + {GPIO_SKL_H_GPD1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_1_PU_ACPRESENT_PCH + {GPIO_SKL_H_GPD2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_2_IRQ_HSC_FAULT_N + {GPIO_SKL_H_GPD3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_3_FM_PCH_PWRBTN_N + {GPIO_SKL_H_GPD4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_4_FM_SLPS3_N + {GPIO_SKL_H_GPD5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_5_FM_SLPS4_N + {GPIO_SKL_H_GPD6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_6_TP_SLPA_N + {GPIO_SKL_H_GPD7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_7_TP_GPD_7 + {GPIO_SKL_H_GPD8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_8_TP_CLK_33K_PCH_SUSCLK + {GPIO_SKL_H_GPD9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_9_TP_GPD_9 + {GPIO_SKL_H_GPD10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_10_TP_SLPS5_N + //{GPIO_SKL_H_GPD10, { GpioPadModeGpio, GpioHostOwnGpio, Gpio= DirIn, GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPD_10_TP_GPD_10_SLPS5_N + {GPIO_SKL_H_GPD11, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_11_FM_GBE_LOM_DISABLE_N + =20 +// Group J AWD + {GPIO_SKL_H_GPP_J0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_0_TP_GPP_J_IO<0> + {GPIO_SKL_H_GPP_J1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_1_TP_GPP_J_IO<1> + {GPIO_SKL_H_GPP_J2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_2_TP_GPP_J_IO<2> + {GPIO_SKL_H_GPP_J3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_3_TP_GPP_J_IO<3> + {GPIO_SKL_H_GPP_J4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_4_TP_GPP_J_IO<4> + {GPIO_SKL_H_GPP_J5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_5_TP_GPP_J_IO<5> + {GPIO_SKL_H_GPP_J6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_6_TP_GPP_J_IO<6> + {GPIO_SKL_H_GPP_J7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_7_TP_GPP_J_IO<7> + {GPIO_SKL_H_GPP_J8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_8_TP_GPP_J_IO<8> + {GPIO_SKL_H_GPP_J9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_9_TP_GPP_J_IO<9> + {GPIO_SKL_H_GPP_J10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_10_TP_GPP_J_IO<10> + {GPIO_SKL_H_GPP_J11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_11_TP_GPP_J_IO<11> + {GPIO_SKL_H_GPP_J12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_12_TP_GPP_J_IO<12> + {GPIO_SKL_H_GPP_J13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_13_TP_GPP_J_IO<13> + {GPIO_SKL_H_GPP_J14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_14_TP_GPP_J_IO<14> + {GPIO_SKL_H_GPP_J15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_15_TP_GPP_J_IO<15> + {GPIO_SKL_H_GPP_J16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_16_TP_GPP_J_IO<16> + {GPIO_SKL_H_GPP_J17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_17_TP_GPP_J_IO<17> + {GPIO_SKL_H_GPP_J18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_18_TP_GPP_J_IO<18> + {GPIO_SKL_H_GPP_J19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_19_TP_GPP_J_IO<19> + {GPIO_SKL_H_GPP_J20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_20_TP_GPP_J_IO<20> + {GPIO_SKL_H_GPP_J21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_21_TP_GPP_J_IO<21> + {GPIO_SKL_H_GPP_J22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_22_TP_GPP_J_IO<22> + {GPIO_SKL_H_GPP_J23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_23_TP_GPP_J_IO<23> + +// Group K AWD + {GPIO_SKL_H_GPP_K0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_0_TP_PCH_GPP_K0 + {GPIO_SKL_H_GPP_K1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_1_TP_PCH_GPP_K1 + {GPIO_SKL_H_GPP_K2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_2_TP_PCH_GPP_K2 + {GPIO_SKL_H_GPP_K3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_3_TP_PCH_GPP_K3 + {GPIO_SKL_H_GPP_K4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_4_TP_PCH_GPP_K4 + {GPIO_SKL_H_GPP_K5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_5_TP_PCH_GPP_K5 + {GPIO_SKL_H_GPP_K6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_6_TP_PCH_GPP_K6 + {GPIO_SKL_H_GPP_K7, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_7_FM_PCH_GBE_DEBUG_EN + {GPIO_SKL_H_GPP_K8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_8_PD_RMII_PCH_CONN_ARB_IN + {GPIO_SKL_H_GPP_K9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_9_PD_RMII_PCH_ARB_OUT + {GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_10_RST_PCIE_PCH_PERST_N +// {GPIO_SKL_H_GPP_K11, { GpioPadModeNative1, GpioHostOwnDefault, Gp= ioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_K_11_PD_1P8_3P3_RCOMP + +// Group L AWD + {GPIO_SKL_H_GPP_L2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_L_2_TP_GPP_L_IO<2> + {GPIO_SKL_H_GPP_L3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_L_3_TP_GPP_L_IO<3> + {GPIO_SKL_H_GPP_L4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_L_4_TP_GPP_L_IO<4> + {GPIO_SKL_H_GPP_L5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_L_5_TP_GPP_L_IO<5> + {GPIO_SKL_H_GPP_L6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_L_6_TP_GPP_L_IO<6> + {GPIO_SKL_H_GPP_L7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_L_7_TP_GPP_L_IO<7> + {GPIO_SKL_H_GPP_L8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_L_8_TP_GPP_L_IO<8> + {GPIO_SKL_H_GPP_L9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_L_9_TP_GPP_L_IO<9> + {GPIO_SKL_H_GPP_L10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_L_10_TP_GPP_L_IO<10> + {GPIO_SKL_H_GPP_L11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_L_11_TP_GPP_L_IO<11> + {GPIO_SKL_H_GPP_L12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_L_12_TP_GPP_L_IO<12> + {GPIO_SKL_H_GPP_L13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_L_13_TP_GPP_L_IO<13> + {GPIO_SKL_H_GPP_L14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_L_14_TP_GPP_L_IO<14> + {GPIO_SKL_H_GPP_L15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_L_15_TP_GPP_L_IO<15> + {GPIO_SKL_H_GPP_L16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_L_16_TP_GPP_L_IO<16> + {GPIO_SKL_H_GPP_L17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_L_17_TP_GPP_L_IO<17> + {GPIO_SKL_H_GPP_L18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_L_18_TP_GPP_L_IO<18> + {GPIO_SKL_H_GPP_L19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, = GpioPadConfigLock}},//GPP_L_19_TP_GPP_L_IO<19> +}; + +EFI_STATUS +TypeAowandaInstallGpioData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformGpioInitDataGuid, + &mGpioTableAowanda, + sizeof(mGpioTableAowanda) + ); + Status =3D PcdSet32S (PcdOemSku_GPIO_TABLE_SIZE, sizeof (mGpioTableAowan= da)); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei= /IioBifurInit.c b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowand= a/Pei/IioBifurInit.c new file mode 100644 index 0000000000..e8b21b2d15 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/IioBif= urInit.c @@ -0,0 +1,186 @@ +/** @file + IIO Config Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021 - 2022, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D 0, + Iio_Iou1, + Iio_Iou2, + Iio_Iou3, + Iio_Iou4, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + VPP_PORT_0 =3D 0, + VPP_PORT_1, + VPP_PORT_2, + VPP_PORT_3 +} VPP_PORT; + +#define ENABLE 1 +#define DISABLE 0 + +#define SPLS_1X 0 + +static IIO_BIFURCATION_DATA_ENTRY_EX IioBifurcationTable[] =3D +{ + { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX } +}; + +static IIO_SLOT_CONFIG_DATA_ENTRY_EX IioSlotTable[] =3D { + // Port Index | Slot |Interlock |power |Power |Hotpl= ug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD |= Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer = |Retimer |Mux |Mux |ExtnCard |ExtnCard |Ex= tnCard |ExtnCard |ExtnCard Retimer|ExtnCard Retimer|ExtnCard |ExtnCard= Hotplug|ExtnCard Hotplug|Max Retimer| + // | | |Limit Scale |Limit Value |Cap = | | |Cap |Port |Address |= |Clock | |Port | |Address |Channel = |Width |Address |Channel |Support |SMBus Port |SM= Bus Addr |Retimer |SMBus Address |Width |Hotplug |Vpp Port= |Vpp Address | | + {SOCKET_0_INDEX + + PORT_1A_INDEX, 1 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + + {SOCKET_0_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + + {SOCKET_0_INDEX + + PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + + {SOCKET_0_INDEX + + PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + + {SOCKET_0_INDEX + + PORT_2A_INDEX, 2 , DISABLE , SPLS_1X , 25 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , SPLS_1X , 25 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2C_INDEX, NO_SLT_IMP , DISABLE , SPLS_1X , 25 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , SPLS_1X , 25 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + =20 + {SOCKET_0_INDEX + + PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + + {SOCKET_0_INDEX + + PORT_4A_INDEX, 0x30 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_4B_INDEX, 0x31 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_1 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_4C_INDEX, 0x32 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_4D_INDEX, 0x33 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_1 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + + {SOCKET_0_INDEX + + PORT_5A_INDEX, 4 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , ENABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_5B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , ENABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_5C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , ENABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_5D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , ENABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 } + +}; + +EFI_STATUS +UpdateAowandaIioConfig ( + IN IIO_GLOBALS *IioGlobalData + ) +{ + return EFI_SUCCESS; +} + +PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX TypeAowandaIioConfigTable =3D +{ + PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE, + PLATFORM_IIO_CONFIG_UPDATE_VERSION_2, + + IioBifurcationTable, + sizeof (IioBifurcationTable), + UpdateAowandaIioConfig, + IioSlotTable, + sizeof (IioSlotTable) +}; + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +TypeAowandaIioPortBifurcationInit ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid, + &TypeAowandaIioConfigTable, + sizeof (TypeAowandaIioConfigTable) + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_1, + &TypeAowandaIioConfigTable, + sizeof (TypeAowandaIioConfigTable) + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_2, + &TypeAowandaIioConfigTable, + sizeof (TypeAowandaIioConfigTable) + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_3, + &TypeAowandaIioConfigTable, + sizeof (TypeAowandaIioConfigTable) + ); + if (EFI_ERROR (Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei= /KtiEparam.c b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/P= ei/KtiEparam.c new file mode 100644 index 0000000000..411301fc40 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/KtiEpa= ram.c @@ -0,0 +1,86 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021 - 2022, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include +#include + +extern EFI_GUID gPlatformKtiEparamUpdateDataGuid; + +ALL_LANES_EPARAM_LINK_INFO KtiAowandaAllLanesEparamTable[] =3D { + // + // SocketID, Freq, Link, TXEQL, CTLEPEAK + // Please propagate changes to WilsonCitySMT and WilsonCityModular UBA K= tiEparam tables + // + // + // Socket 0 + // + { 0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_= 112GT), (1 << KTI_LINK0), 0x2B33373F, ADAPTIVE_CTLE }, + { 0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_= 112GT), (1 << KTI_LINK1), 0x2A33363F, ADAPTIVE_CTLE }, + { 0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_= 112GT), (1 << KTI_LINK2), 0x2B34363F, ADAPTIVE_CTLE } +}; + +PLATFORM_KTI_EPARAM_UPDATE_TABLE TypeAowandaKtiEparamUpdate =3D +{ + PLATFORM_KTIEP_UPDATE_SIGNATURE, + PLATFORM_KTIEP_UPDATE_VERSION, + KtiAowandaAllLanesEparamTable, + sizeof (KtiAowandaAllLanesEparamTable), + NULL, + 0 +}; + +ALL_LANES_EPARAM_LINK_INFO KtiAowandaCpxAllLanesEparamTable[] =3D { + // + // SocketID, Freq, Link, TXEQL, CTLEPEAK + // + // + // Socket 0 + // + { 0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_= 112GT), (1 << KTI_LINK0), 0x2E39343F, ADAPTIVE_CTLE }, + { 0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_= 112GT), (1 << KTI_LINK5), 0x2F39353F, ADAPTIVE_CTLE } +}; + +PLATFORM_KTI_EPARAM_UPDATE_TABLE TypeAowandaCpxKtiEparamUpdate =3D +{ + PLATFORM_KTIEP_UPDATE_SIGNATURE, + PLATFORM_KTIEP_UPDATE_VERSION, + KtiAowandaCpxAllLanesEparamTable, + sizeof (KtiAowandaCpxAllLanesEparamTable), + NULL, + 0 +}; + +EFI_STATUS +TypeAowandaInstallKtiEparamData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob); + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformKtiEparamUpdateDataGuid, + &TypeAowandaKtiEparamUpdate, + sizeof (TypeAowandaKtiEparamUpdate) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei= /PcdData.c b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei= /PcdData.c new file mode 100644 index 0000000000..dab28fa764 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PcdDat= a.c @@ -0,0 +1,382 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021 - 2022, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + + +#define BIOSGUARD_SUPPORT_ENABLED BIT0 +#define GPIO_SKL_H_GPP_B20 0x01010014 +#define PCIE_RISER 0x1A +#define EDSFF_RISER 0x4A + +static GPIO_PAD mEDSFFRiserId [] =3D {=20 + GPIO_SKL_H_GPP_C18, + GPIO_SKL_H_GPP_C19 =20 +}; + +static GPIO_PAD mPCIeRiserId [] =3D {=20 + GPIO_SKL_H_GPP_C15, + GPIO_SKL_H_GPP_C16, + GPIO_SKL_H_GPP_C17 +}; + +const UINT8 EDSFFRiserIdGpioPadsNum =3D sizeof(mEDSFFRiserId)/sizeof(GPIO_= PAD);=20 +const UINT8 PCIeRiserIdGpioPadsNum =3D sizeof(mPCIeRiserId)/sizeof(GPIO_PA= D); + +static EFI_STATUS +GpioGetRiserId ( + IN UINT8 Type, + OUT UINT32 *RiserId + ) +{ + EFI_STATUS Status; + UINT32 Data32; + UINT8 i; + UINT32 RevId =3D 0; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi; + =20 + Status =3D EFI_DEVICE_ERROR; + RevId =3D 0; + DynamicSiLibraryPpi =3D NULL; + + DEBUG((EFI_D_INFO, "%a Entry...\n", __FUNCTION__));=20 + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + if (Type =3D=3D EDSFF_RISER) { + // + //Get EDSFF GPIO Present Ping + // + for (i =3D 0; i < EDSFFRiserIdGpioPadsNum; i++){ + Status =3D DynamicSiLibraryPpi->GpioGetInputValueByPchId (PCH_LEGACY= _ID, mEDSFFRiserId[i], &Data32); =20 + DEBUG((EFI_D_INFO,"GpioGetInputValueByPchId[%x] mEDSFFRiserId Status= =3D %r\n", i, Status)); + if (EFI_ERROR(Status)) { + return Status; + } + if (Data32) { + RevId =3D RevId | (1 << i); + } + } + } else if (Type =3D=3D PCIE_RISER) { + // =20 + //Get PCIe Riser GPIO Present Ping + // + for (i =3D 0; i < PCIeRiserIdGpioPadsNum; i++){ + Status =3D DynamicSiLibraryPpi->GpioGetInputValueByPchId (PCH_LEGACY= _ID, mPCIeRiserId[i], &Data32); =20 + DEBUG((EFI_D_INFO,"GpioGetInputValueByPchId[%x] PCIe Riser Status = =3D %r\n", i, Status)); + if (EFI_ERROR(Status)) { + return Status; + } + if (Data32) { + RevId =3D RevId | (1 << i); + } + } + } + *RiserId =3D RevId; + return EFI_SUCCESS; +} + +/** + Update Aowanda IMON SVID Information + + retval N/A +**/ +VOID +TypeAowandaPlatformUpdateImonAddress ( + VOID + ) +{ + VCC_IMON *VccImon =3D NULL; + UINTN Size =3D 0; + + Size =3D sizeof (VCC_IMON); + VccImon =3D (VCC_IMON *) PcdGetPtr (PcdImonAddr); + if (VccImon =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "UpdateImonAddress() - PcdImonAddr =3D=3D NULL\n"= )); + return; + } + + VccImon->VrSvid[0] =3D PcdGet8 (PcdWilsonCitySvidVrP1V8); + VccImon->VrSvid[1] =3D PcdGet8 (PcdWilsonCitySvidVrVccAna); + VccImon->VrSvid[2] =3D IMON_ADDR_LIST_END; // End array with 0xFF + + PcdSetPtrS (PcdImonAddr, &Size, (VOID *) VccImon); +} + +/** + Update Aowanda VR ID SVID Information + + retval N/A +**/ +VOID +TypeAowandaPlatformUpdateVrIdAddress ( + VOID + ) +{ + MEM_SVID_MAP *MemSvidMap =3D NULL; + UINTN Size =3D 0; + + Size =3D sizeof (MEM_SVID_MAP); + MemSvidMap =3D (MEM_SVID_MAP *) PcdGetPtr (PcdMemSrvidMap); + if (MemSvidMap =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "UpdateVrIdAddress() - PcdMemSrvidMap =3D=3D NULL= \n")); + return; + } + /* + Map VR ID Address to Memory controller + The mailbox command can support up to 4 DDR VR ID's, 0x10, 0x12, 0x14,= and 0x16. + Whitley PHAS indicates that Whitley (like Purley) only connects 2 VRs = (VR ID's 0x10 and 0x12). + Those are typically shared such that MC0/MC2 share the same DDR VR (as= they are on the same side of the CPU) + and MC1/MC3 share the other. Depending on motherboard layout and other= design constraints, this could change + BIT 4 =3D> 0 or 1, SVID BUS\Interface 0 or 1 respectively + BIT 0:3 =3D> SVID ADDRESS + */ + + MemSvidMap->Socket[0].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[0].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[1].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[1].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[2].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[2].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[3].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[3].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[4].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[4].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[5].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[5].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[6].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[6].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[7].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[7].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + + PcdSetPtrS (PcdMemSrvidMap, &Size, (VOID *) MemSvidMap); +} + +EFI_STATUS +TypeAowandaPlatformPcdUpdateCallback ( + VOID +) +{ + CHAR8 FamilyName[] =3D "Whitley"; + + CHAR8 BoardName[] =3D "Aowanda"; + UINT32 Data32; + UINTN Size; + UINTN PlatformFeatureFlag =3D 0; + + UINT32 PCIE_RiserID; + UINT32 EDSFF_RiserID; + + CHAR16 PlatformName[] =3D L"AD1S02"; + UINTN PlatformNameSize =3D 0; + EFI_STATUS Status; + + //#Integer for BoardID, must match the SKU number and be unique. + Status =3D PcdSet16S (PcdOemSkuBoardID, TypeAowanda); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSet16S (PcdOemSkuBoardFamily, 0x30); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + // Number of Sockets on Board. + Status =3D PcdSet32S (PcdOemSkuBoardSocketCount, 1); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + // Max channel and max DIMM + Status =3D PcdSet32S (PcdOemSkuMaxChannel , 8); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSet32S (PcdOemSkuMaxDimmPerChannel , 1); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSetBoolS (PcdOemSkuDimmLayout, TRUE); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //Update Onboard Video Controller PCI Ven_id, Dev_id + Status =3D PcdSet16S (PcdOnboardVideoPciVendorId, 0x1A03); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D PcdSet16S (PcdOnboardVideoPciDeviceId, 0x2000); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# + //# Misc. + //# + //# V_PCIE_PORT_PXPSLOTCTRL_ATNLED_OFF + Status =3D PcdSet16S (PcdOemSkuMrlAttnLed, 0xc0); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //SDP Active Flag + Status =3D PcdSet8S (PcdOemSkuSdpActiveFlag , 0x0); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# Zero terminated string to ID family + Size =3D AsciiStrSize (FamilyName); + Status =3D PcdSetPtrS (PcdOemSkuFamilyName, &Size, FamilyName); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# Zero terminated string to Board Name + Size =3D AsciiStrSize (BoardName); + Status =3D PcdSetPtrS (PcdOemSkuBoardName, &Size, BoardName); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } +// +// Detect riser id to distinguish the SKU +// + + GpioGetRiserId (PCIE_RISER, &PCIE_RiserID); + GpioGetRiserId (EDSFF_RISER, &EDSFF_RiserID); + switch(PCIE_RiserID) { + case 0: + switch (EDSFF_RiserID) { + case 0: + StrCpyS (PlatformName, sizeof (PlatformName) / sizeof (CHAR16), = L"AD1S01"); + break; + case 2://1RU RISER2(AD1S02) + StrCpyS (PlatformName, sizeof (PlatformName) / sizeof (CHAR16), = L"AD1S02"); + break; + default: + StrCpyS (PlatformName, sizeof (PlatformName) / sizeof (CHAR16), = L"AD1S01"); + break; + } + break; + default: + StrCpyS (PlatformName, sizeof (PlatformName) / sizeof (CHAR16), L"AD= 1S01"); + break; + } + + PlatformNameSize =3D sizeof (PlatformName); + Status =3D PcdSet32S (PcdOemSkuPlatformNameSize, (UINT32)PlatformNameSiz= e); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSetPtrS (PcdOemSkuPlatformName, &PlatformNameSize, Platfor= mName); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# FeaturesBasedOnPlatform + Status =3D PcdSet32S (PcdOemSkuPlatformFeatureFlag, (UINT32)PlatformFeat= ureFlag); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# Assert GPIO + Data32 =3D 0; + Status =3D PcdSet32S (PcdOemSkuAssertPostGPIOValue, Data32); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSet32S (PcdOemSkuAssertPostGPIO, GPIO_SKL_H_GPP_B20); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# UplinkPortIndex + Status =3D PcdSet8S (PcdOemSkuUplinkPortIndex, 5); + if (EFI_ERROR(Status)) { + return Status; + } + + DEBUG ((DEBUG_INFO, "Uba Callback: PlatformPcdUpdateCallback is called!\= n")); + Status =3D TypeAowandaPlatformUpdateAcpiTablePcds (); + //# BMC Pcie Port Number + // PCH PCIe port 3 is used for BMC VGA. + //=20 + PcdSet8S (PcdOemSkuBmcPciePortNumber, 3); + + ASSERT_EFI_ERROR(Status); + + //# Board Type Bit Mask + PcdSet32S (PcdBoardTypeBitmask, CPU_TYPE_F_MASK | (CPU_TYPE_F_MASK << 4)= ); + ASSERT_EFI_ERROR(Status); + + //Update IMON Address + TypeAowandaPlatformUpdateImonAddress (); + + return Status; +} + +PLATFORM_PCD_UPDATE_TABLE TypeAowandaPcdUpdateTable =3D +{ + PLATFORM_PCD_UPDATE_SIGNATURE, + PLATFORM_PCD_UPDATE_VERSION, + TypeAowandaPlatformPcdUpdateCallback +}; + +EFI_STATUS +TypeAowandaInstallPcdData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPcdConfigDataGuid, + &TypeAowandaPcdUpdateTable, + sizeof(TypeAowandaPcdUpdateTable) + ); + + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei= /PchEarlyUpdate.c b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowa= nda/Pei/PchEarlyUpdate.c new file mode 100644 index 0000000000..1757529212 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PchEar= lyUpdate.c @@ -0,0 +1,82 @@ +/** @file + Pch Early update. + + @copyright + Copyright 2019 - 2021 Intel Corporation.
+ Copyright (c) 2021 - 2022, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" + +#include + +#include +#include +#include +#include + + +EFI_STATUS +TypeAowandaPchLanConfig ( + IN SYSTEM_CONFIGURATION *SystemConfig +) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +TypeAowandaOemInitLateHook ( + IN SYSTEM_CONFIGURATION *SystemConfig +) +{ + return EFI_SUCCESS; +} + + +PLATFORM_PCH_EARLY_UPDATE_TABLE TypeAowandaPchEarlyUpdateTable =3D +{ + PLATFORM_PCH_EARLY_UPDATE_SIGNATURE, + PLATFORM_PCH_EARLY_UPDATE_VERSION, + TypeAowandaPchLanConfig, + TypeAowandaOemInitLateHook +}; + + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +EFIAPI +TypeAowandaPchEarlyUpdate( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ) +{ + EFI_STATUS Status; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPchEarlyConfigDataGuid, + &TypeAowandaPchEarlyUpdateTable, + sizeof(TypeAowandaPchEarlyUpdateTable) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei= /PeiBoardInit.h b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowand= a/Pei/PeiBoardInit.h new file mode 100644 index 0000000000..fd9cae5331 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PeiBoa= rdInit.h @@ -0,0 +1,77 @@ +/** @file + PeiBoardInit. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021 - 2022, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_BOARD_INIT_PEIM_H_ +#define _PEI_BOARD_INIT_PEIM_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// TypeAowanda +EFI_STATUS +TypeAowandaPlatformUpdateUsbOcMappings ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ); + +EFI_STATUS +TypeAowandaPlatformUpdateAcpiTablePcds ( + VOID + ); + +EFI_STATUS +TypeAowandaInstallClockgenData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ); + +EFI_STATUS +TypeAowandaInstallPcdData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ); + +EFI_STATUS +TypeAowandaPchEarlyUpdate ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ); + +EFI_STATUS +TypeAowandaIioPortBifurcationInit ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ); + +EFI_STATUS +TypeAowandaInstallSlotTableData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ); + +EFI_STATUS +TypeAowandaInstallKtiEparamData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ); + +// TypeAowanda +EFI_STATUS +TypeAowandaInstallGpioData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ); + +EFI_STATUS +TypeAowandaInstallSoftStrapData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ); + +#endif // _PEI_BOARD_INIT_PEIM_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei= /PeiBoardInitLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAow= anda/Pei/PeiBoardInitLib.c new file mode 100644 index 0000000000..c3cd0897ca --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PeiBoa= rdInitLib.c @@ -0,0 +1,154 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation. + Copyright (c) 2021 - 2022, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +/** + The constructor function for Board Init Libray. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS Table initialization successfully. + @retval EFI_OUT_OF_RESOURCES No enough memory to initialize table. +**/ + +#include "PeiBoardInit.h" +#include + +EFI_STATUS +EFIAPI +TypeAowandaPeiBoardInitLibConstructor ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi; + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + UINT8 SocketIndex; + UINT8 ChannelIndex; + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob); + + if (PlatformInfo->BoardId =3D=3D TypeAowanda) { + DEBUG ((DEBUG_INFO, "PEI UBA init BoardId 0x%X: TypeAowanda\n", Platfo= rmInfo->BoardId)); + + // Socket 0 has SMT DIMM connector, Socket 1 has PTH DIMM connector + for (SocketIndex =3D 0; SocketIndex < MAX_SOCKET; SocketIndex++) { + for (ChannelIndex =3D 0; ChannelIndex < MAX_CH; ChannelIndex++) { + switch (SocketIndex) { + case 0: + PlatformInfo->MemoryConnectorType[SocketIndex][ChannelIndex] = =3D DimmConnectorSmt; + break; + case 1: + // Fall through since socket 1 is PTH type + default: + // Use the more restrictive type as the default case + PlatformInfo->MemoryConnectorType[SocketIndex][ChannelIndex] = =3D DimmConnectorPth; + break; + } + } + } + + BuildGuidDataHob ( + &gEfiPlatformInfoGuid, + &(PlatformInfo), + sizeof (EFI_PLATFORM_INFO) + ); + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->InitSku ( + UbaConfigPpi, + PlatformInfo->BoardId, + NULL, + NULL + ); + ASSERT_EFI_ERROR (Status); + + Status =3D TypeAowandaInstallGpioData (UbaConfigPpi); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D TypeAowandaInstallPcdData (UbaConfigPpi); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D TypeAowandaInstallSoftStrapData (UbaConfigPpi); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D TypeAowandaPchEarlyUpdate (UbaConfigPpi); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D TypeAowandaPlatformUpdateUsbOcMappings (UbaConfigPpi); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D TypeAowandaInstallSlotTableData (UbaConfigPpi); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D TypeAowandaInstallKtiEparamData (UbaConfigPpi); + if (EFI_ERROR (Status)) { + return Status; + } + + for (SocketIndex =3D 0; SocketIndex < MAX_SOCKET; SocketIndex++) { + // + // Set default memory type connector. + // Socket 0: DimmConnectorSmt + // Socket 1: DimmConnectorPth + // + if (SocketIndex % 2 =3D=3D 0) { + (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType[SocketI= ndex], sizeof (PlatformInfo->MemoryConnectorType[SocketIndex]), DimmConnect= orSmt); + } else { + (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType[SocketI= ndex], sizeof (PlatformInfo->MemoryConnectorType[SocketIndex]), DimmConnect= orPth); + } + } + + // + // Initialize InterposerType to InterposerUnknown + // + for (SocketIndex =3D 0; SocketIndex < MAX_SOCKET; ++SocketIndex) { + PlatformInfo->InterposerType[SocketIndex] =3D InterposerUnknown; + } + + // + // TypeAowandaIioPortBifurcationInit will use PlatformInfo->Interpose= rType for PPO. + // + Status =3D TypeAowandaIioPortBifurcationInit (UbaConfigPpi); + if (EFI_ERROR (Status)) { + return Status; + } + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei= /PeiBoardInitLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeA= owanda/Pei/PeiBoardInitLib.inf new file mode 100644 index 0000000000..dc91169967 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/PeiBoa= rdInitLib.inf @@ -0,0 +1,167 @@ +## @file +# Component information file for BoardInitLib in PEI post memory phase. +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation. +# Copyright (c) 2021 - 2022, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# @par Specification Reference: +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D TypeAowandaPeiBoardInitLib + FILE_GUID =3D 60EDF2C0-42D1-4868-A038-9CC7F2CD0E59 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NULL|PEIM + CONSTRUCTOR =3D TypeAowandaPeiBoardInitLibConstructor + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PeiServicesLib + HobLib + PeiServicesTablePointerLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + +[Sources] + PeiBoardInitLib.c + GpioTable.c + PcdData.c + UsbOC.c + AcpiTablePcds.c + IioBifurInit.c + SlotTable.c + KtiEparam.c + PchEarlyUpdate.c + SoftStrapFixup.c + PeiBoardInit.h + +[FixedPcd] + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + + gOemSkuTokenSpaceGuid.PcdOemSkuBoardID + gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID + gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily + + gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName + gOemSkuTokenSpaceGuid.PcdOemSkuBoardName + + gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount + + gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel + gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel + gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout + + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13 + + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13 + + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05 + + gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName + + gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed + gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag + + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE + + gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32 + + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11 + + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue + gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber + gOemSkuTokenSpaceGuid.PcdOemTableIdXhci + gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex + gPlatformTokenSpaceGuid.PcdBoardTypeBitmask + gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrP1V8 + gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrVccAna + gEfiCpRcPkgTokenSpaceGuid.PcdImonAddr + gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidMap + + gPlatformTokenSpaceGuid.PcdMemInterposerMap + gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId + gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId + +[Ppis] + gUbaConfigDatabasePpiGuid + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Guids] + gPlatformGpioInitDataGuid + +[Depex] + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei= /SlotTable.c b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/P= ei/SlotTable.c new file mode 100644 index 0000000000..28b8ded92e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/SlotTa= ble.c @@ -0,0 +1,167 @@ +/** @file + Slot Table Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021 - 2022, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include + +#define PCI_DEVICE_ON_BOARD_TRUE 0 +#define PCI_DEVICE_ON_BOARD_FALSE 1 + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D 0, + Iio_Iou1, + Iio_Iou2, + Iio_Iou3, + Iio_Iou4, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + Bw5_Addr_0 =3D 0, + Bw5_Addr_1, + Bw5_Addr_2, + Bw5_Addr_3, + Bw5_Addr_Max +} BW5_ADDRESS; + +static UINT8 TypeAowandaPchPciSlotImpementedTableData[] =3D { + PCI_DEVICE_ON_BOARD_TRUE, // Root Port 0 I210 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 1 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 2 + PCI_DEVICE_ON_BOARD_TRUE, // Root Port 3 BMC Video + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 4 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 5 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 6 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 7 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 8 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 9 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 10 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 11 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 12 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 13 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 14 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 15 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 16 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 17 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 18 + PCI_DEVICE_ON_BOARD_FALSE // Root Port 19 +}; + +UINT8 +GetTypeAowandaIOU0Setting ( + UINT8 IOU0Data + ) +{ + return IOU0Data; +} + +UINT8 +GetTypeAowandaIOU2Setting ( + UINT8 SkuPersonalityType, + UINT8 IOU2Data + ) +{ + return IOU2Data; +} + +static IIO_BROADWAY_ADDRESS_DATA_ENTRY SlotTypeAowandaBroadwayTable[] =3D= { + { Iio_Socket0, Iio_Iou2, Bw5_Addr_0 }, + { Iio_Socket1, Iio_Iou1, Bw5_Addr_2 }, + { Iio_Socket1, Iio_Iou0, Bw5_Addr_1 }, +}; + +PLATFORM_SLOT_UPDATE_TABLE TypeAowandaSlotTable =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeAowandaBroadwayTable, + GetTypeAowandaIOU0Setting, + 0 +}; + +PLATFORM_SLOT_UPDATE_TABLE2 TypeAowandaSlotTable2 =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeAowandaBroadwayTable, + GetTypeAowandaIOU0Setting, + 0, + GetTypeAowandaIOU2Setting +}; + +PLATFORM_PCH_PCI_SLOT_IMPLEMENTED_UPDATE_TABLE TypeAowandaPchPciSlotImple= mentedTable =3D { + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + TypeAowandaPchPciSlotImpementedTableData +}; + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +TypeAowandaInstallSlotTableData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformSlotDataGuid, + &TypeAowandaSlotTable, + sizeof (TypeAowandaSlotTable) + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformSlotDataGuid2, + &TypeAowandaSlotTable2, + sizeof (TypeAowandaSlotTable2) + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPciSlotImplementedGuid, + &TypeAowandaPchPciSlotImplementedTable, + sizeof (TypeAowandaPchPciSlotImplemented= Table) + ); + if (EFI_ERROR (Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei= /SoftStrapFixup.c b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowa= nda/Pei/SoftStrapFixup.c new file mode 100644 index 0000000000..29b1729b4d --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/SoftSt= rapFixup.c @@ -0,0 +1,73 @@ +/** @file + Soft Strap update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021 - 2022, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include +#include +#include +#include +#include + +PLATFORM_PCH_SOFTSTRAP_FIXUP_ENTRY TypeAowandaSoftStrapTable[] =3D +{ + // SoftStrapNumber, LowBit, BitLength, Value + { 0, 0, 0, 0 } +}; + +UINT32 +TypeAowandaSystemBoardRevIdValue ( + VOID + ) +{ + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return 0xFF; + } + + PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob); + return PlatformInfo->TypeRevisionId; +} + +VOID +TypeAowandaPlatformSpecificUpdate ( + IN OUT UINT8 *FlashDescriptorCopy + ) +{ +} + +PLATFORM_PCH_SOFTSTRAP_UPDATE TypeAowandaSoftStrapUpdate =3D +{ + PLATFORM_SOFT_STRAP_UPDATE_SIGNATURE, + PLATFORM_SOFT_STRAP_UPDATE_VERSION, + TypeAowandaSoftStrapTable, + TypeAowandaPlatformSpecificUpdate +}; + +EFI_STATUS +TypeAowandaInstallSoftStrapData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPchSoftStrapConfigDataGuid, + &TypeAowandaSoftStrapUpdate, + sizeof (TypeAowandaSoftStrapUpdate) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei= /UsbOC.c b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/U= sbOC.c new file mode 100644 index 0000000000..06fb8ab385 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/Uba/TypeAowanda/Pei/UsbOC.= c @@ -0,0 +1,124 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021 - 2022, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" + +#include +#include +#include +#include +#include + +USB_OVERCURRENT_PIN TypeAowandaUsb20OverCurrentMappings[PCH_MAX_USB2_PORT= S] =3D { + UsbOverCurrentPin0, // Port01: USB 2.0 CONN= ECTOR + UsbOverCurrentPinSkip, // Port02: NC + UsbOverCurrentPinSkip, // Port03: NC + UsbOverCurrentPinSkip, // Port04: NC + UsbOverCurrentPinSkip, // Port05: NC + UsbOverCurrentPinSkip, // Port06: NC + UsbOverCurrentPinSkip, // Port07: TO BMC + UsbOverCurrentPinSkip, // Port08: NC + UsbOverCurrentPinSkip, // Port09: NC + UsbOverCurrentPinSkip, // Port10: OCP3.0 SLOT + UsbOverCurrentPinSkip, // Port11: NC + UsbOverCurrentPinSkip, // Port12: NC + UsbOverCurrentPinSkip, // Port13: NC + UsbOverCurrentPinSkip, // Port14: NC + UsbOverCurrentPinSkip, // Port15: NC + UsbOverCurrentPinSkip // Port16: NC +}; + +USB_OVERCURRENT_PIN TypeAowandaUsb30OverCurrentMappings[PCH_MAX_USB3_PORT= S] =3D { + UsbOverCurrentPinSkip, // Port01: NC + UsbOverCurrentPinSkip, // Port02: NC + UsbOverCurrentPinSkip, // Port03: NC + UsbOverCurrentPinSkip, // Port04: NC + UsbOverCurrentPinSkip, // Port05: NC + UsbOverCurrentPinSkip, // Port06: NC + UsbOverCurrentPinSkip, // Port07: NC + UsbOverCurrentPinSkip, // Port08: NC + UsbOverCurrentPinSkip, // Port09: NC + UsbOverCurrentPinSkip // Port10: NC +}; + +USB2_PHY_PARAMETERS TypeAowandaUsb20AfeParams[PCH_H_XHCI_MAX_USB2_PHYSICA= L_PORTS] =3D { + { 3, 0, 3, 1 }, // PP0 + { 5, 0, 3, 1 }, // PP1 + { 3, 0, 3, 1 }, // PP2 + { 0, 5, 1, 1 }, // PP3 + { 3, 0, 3, 1 }, // PP4 + { 3, 0, 3, 1 }, // PP5 + { 3, 0, 3, 1 }, // PP6 + { 3, 0, 3, 1 }, // PP7 + { 2, 2, 1, 0 }, // PP8 + { 6, 0, 2, 1 }, // PP9 + { 2, 2, 1, 0 }, // PP10 + { 6, 0, 2, 1 }, // PP11 + { 0, 5, 1, 1 }, // PP12 + { 7, 0, 2, 1 }, // PP13 +}; + +EFI_STATUS +TypeAowandaPlatformUsbOcUpdateCallback ( + IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings, + IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings, + IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams + ) +{ + *Usb20OverCurrentMappings =3D &TypeAowandaUsb20OverCurrentMappings[0]; + *Usb30OverCurrentMappings =3D &TypeAowandaUsb30OverCurrentMappings[0]; + + *Usb20AfeParams =3D TypeAowandaUsb20AfeParams; + return EFI_SUCCESS; +} + +PLATFORM_USBOC_UPDATE_TABLE TypeAowandaUsbOcUpdate =3D +{ + PLATFORM_USBOC_UPDATE_SIGNATURE, + PLATFORM_USBOC_UPDATE_VERSION, + TypeAowandaPlatformUsbOcUpdateCallback +}; + +EFI_STATUS +TypeAowandaPlatformUpdateUsbOcMappings ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ) +{ + // # + // # USB, see PG 104 in GZP SCH + // # + + // USB2 USB3 Port OC + // + // Port00: PORT5 Back Panel ,OC0# + // Port01: PORT2 Back Panel ,OC0# + // Port02: PORT3 Back Panel ,OC1# + // Port03: PORT0 NOT USED ,NA + // Port04: BMC1.0 ,NA + // Port05: INTERNAL_2X5_A ,OC2# + // Port06: INTERNAL_2X5_A ,OC2# + // Port07: NOT USED ,NA + // Port08: EUSB (AKA SSD) ,NA + // Port09: INTERNAL_TYPEA ,OC6# + // Port10: PORT1 Front Panel ,OC5# + // Port11: NOT USED ,NA + // Port12: BMC2.0 ,NA + // Port13: PORT4 Front Panel ,OC5# + + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPeiPlatformUbaOcConfigDataGuid, + &TypeAowandaUsbOcUpdate, + sizeof (TypeAowandaUsbOcUpdate) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/build_board.py b/Pl= atform/Intel/WhitleyOpenBoardPkg/Aowanda/build_board.py new file mode 100644 index 0000000000..5fa451fab1 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/build_board.py @@ -0,0 +1,195 @@ +# @ build_board.py +# Extensions for building Aowanda using build_bios.py +# +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2022, American Megatrends International LLC.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +""" +This module serves as a sample implementation of the build extension +scripts +""" + +import os +import sys + +def pre_build_ex(config, functions): + """Additional Pre BIOS build function + + :param config: The environment variables to be used in the build proce= ss + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: nothing + """ + print("pre_build_ex") + + config["BUILD_DIR_PATH"] =3D os.path.join(config["WORKSPACE"], + 'Build', + config["PLATFORM_BOARD_PACKAGE= "], + "{}_{}".format( + config["TARGET"], + config["TOOL_CHAIN_TAG"])) + # set BUILD_DIR path + config["BUILD_DIR"] =3D os.path.join('Build', + config["PLATFORM_BOARD_PACKAGE"], + "{}_{}".format( + config["TARGET"], + config["TOOL_CHAIN_TAG"])) + config["BUILD_X64"] =3D os.path.join(config["BUILD_DIR_PATH"], 'X64') + config["BUILD_IA32"] =3D os.path.join(config["BUILD_DIR_PATH"], 'IA32'= ) + + if not os.path.isdir(config["BUILD_DIR_PATH"]): + try: + os.makedirs(config["BUILD_DIR_PATH"]) + except OSError: + print("Error while creating Build folder") + sys.exit(1) + + #@todo: Replace this with PcdFspModeSelection + if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") =3D=3D "TRUE": + config["EXT_BUILD_FLAGS"] +=3D " -D FSP_MODE=3D0" + else: + config["EXT_BUILD_FLAGS"] +=3D " -D FSP_MODE=3D1" + + if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") =3D=3D "TRUE": + raise ValueError("FSP API Mode is currently unsupported on Ice Lak= e Xeon Scalable") + + # Build the ACPI AML offset table *.offset.h + print("Info: re-generating PlatformOffset header files") + + execute_script =3D functions.get("execute_script") + + # AML offset arch is X64, not sure if it matters. + command =3D ["build", "-a", "X64", "-t", config["TOOL_CHAIN_TAG"], "-D= ", "MAX_SOCKET=3D" + config["MAX_SOCKET"]] + + if config["EXT_BUILD_FLAGS"] and config["EXT_BUILD_FLAGS"] !=3D "": + ext_build_flags =3D config["EXT_BUILD_FLAGS"].split(" ") + ext_build_flags =3D [x.strip() for x in ext_build_flags] + ext_build_flags =3D [x for x in ext_build_flags if x !=3D ""] + command.extend(ext_build_flags) + + aml_offsets_split =3D os.path.split(os.path.normpath(config["AML_OFFSE= TS_PATH"])) + command.append("-p") + command.append(os.path.normpath(config["AML_OFFSETS_PATH"]) + '.dsc') + command.append("-m") + command.append(os.path.join(aml_offsets_split[0], aml_offsets_split[1]= , aml_offsets_split[1] + '.inf')) + command.append("-y") + command.append(os.path.join(config["WORKSPACE"], "PreBuildReport.txt")= ) + command.append("--log=3D" + os.path.join(config["WORKSPACE"], "PreBuil= d.log")) + + shell =3D True + if os.name =3D=3D "posix": # linux + shell =3D False + + _, _, _, code =3D execute_script(command, config, shell=3Dshell) + if code !=3D 0: + print(" ".join(command)) + print("Error re-generating PlatformOffset header files") + sys.exit(1) + + # Build AmlGenOffset command to consume the *.offset.h and produce Aml= OffsetTable.c for StaticSkuDataDxe use. + + # Get destination path and filename from config + relative_file_path =3D os.path.normpath(config["STRIPPED_AML_OFFSETS_F= ILE_PATH"]) # get path relative to Platform/Intel + out_file_path =3D os.path.join(config["WORKSPACE_PLATFORM"], relative_= file_path) # full path to output file + out_file_dir =3D os.path.dirname(out_file_path) = # remove filename + + out_file_root_ext =3D os.path.splitext(os.path.basename(out_file_path)= ) # root and extension of output file + + # Get relative path for the generated offset.h file + relative_dsdt_file_path =3D os.path.normpath(config["DSDT_TABLE_FILE_P= ATH"]) # path relative to Platform/Intel + dsdt_file_root_ext =3D os.path.splitext(os.path.basename(relative_dsdt= _file_path)) # root and extension of generated offset.h file + + # Generate output directory if it doesn't exist + if not os.path.exists(out_file_dir): + os.mkdir(out_file_dir) + + command =3D ["python", + os.path.join(config["MIN_PACKAGE_TOOLS"], "AmlGenOffset", "= AmlGenOffset.py"), + "-d", "--aml_filter", config["AML_FILTER"], + "-o", out_file_path, + os.path.join(config["BUILD_X64"], aml_offsets_split[0], aml= _offsets_split[1], aml_offsets_split[1], "OUTPUT", os.path.dirname(relative= _dsdt_file_path), dsdt_file_root_ext[0] + ".offset.h")] + + # execute the command + _, _, _, code =3D execute_script(command, config, shell=3Dshell) + if code !=3D 0: + print(" ".join(command)) + print("Error re-generating PlatformOffset header files") + sys.exit(1) + + print("GenOffset done") + + + return None + +def _merge_files(files, ofile): + with open(ofile, 'wb') as of: + for x in files: + if not os.path.exists(x): + return + + with open(x, 'rb') as f: + of.write(f.read()) + +def build_ex(config, functions): + """Additional BIOS build function + + :param config: The environment variables to be used in the build proce= ss + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("build_ex") + fv_path =3D os.path.join(config["BUILD_DIR_PATH"], "FV") + binary_fd =3D os.path.join(fv_path, "BINARY.fd") + main_fd =3D os.path.join(fv_path, "MAIN.fd") + secpei_fd =3D os.path.join(fv_path, "SECPEI.fd") + board_fd =3D config["BOARD"].upper() + final_fd =3D os.path.join(fv_path, "{}.fd".format(board_fd)) + _merge_files((binary_fd, main_fd, secpei_fd), final_fd) + return None + + +def post_build_ex(config, functions): + """Additional Post BIOS build function + + :param config: The environment variables to be used in the post + build process + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("post_build_ex") + fv_path =3D os.path.join(config["BUILD_DIR_PATH"], "FV") + board_fd =3D config["BOARD"].upper() + final_fd =3D os.path.join(fv_path, "{}.fd".format(board_fd)) + final_ifwi =3D os.path.join(fv_path, "{}.bin".format(board_fd)) + + ifwi_ingredients_path =3D os.path.join(config["WORKSPACE_PLATFORM_BIN"= ], "Ifwi", config["BOARD"]) + flash_descriptor =3D os.path.join(ifwi_ingredients_path, "FlashDescrip= tor.bin") + intel_me =3D os.path.join(ifwi_ingredients_path, "Me.bin") + _merge_files((flash_descriptor, intel_me, final_fd), final_ifwi) + if os.path.isfile(final_fd): + print("IFWI image can be found at {}".format(final_ifwi)) + return None + + +def clean_ex(config, functions): + """Additional clean function + + :param config: The environment variables to be used in the build proce= ss + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("clean_ex") + return None diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/build_config.cfg b/= Platform/Intel/WhitleyOpenBoardPkg/Aowanda/build_config.cfg new file mode 100644 index 0000000000..7ea3af08ae --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Aowanda/build_config.cfg @@ -0,0 +1,52 @@ +# @ build_config.cfg +# This is the Aowanda board specific build settings +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2022, American Megatrends International LLC.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + + +[CONFIG] +WORKSPACE_PLATFORM_BIN =3D edk2-non-osi/Platform/Intel/WhitleyOpenBoardBin= Pkg +EDK_SETUP_OPTION =3D +openssl_path =3D +PLATFORM_BOARD_PACKAGE =3D WhitleyOpenBoardPkg +PROJECT =3D WhitleyOpenBoardPkg/Aowanda +BOARD =3D Aowanda +FLASH_MAP_FDF =3D WhitleyOpenBoardPkg/FspFlashOffsets.fdf +PROJECT_DSC =3D WhitleyOpenBoardPkg/Aowanda/PlatformPkg.dsc +BOARD_PKG_PCD_DSC =3D WhitleyOpenBoardPkg/PlatformPkgConfig.dsc +ADDITIONAL_SCRIPTS =3D WhitleyOpenBoardPkg/Aowanda/build_board.py +PrepRELEASE =3D DEBUG +SILENT_MODE =3D FALSE +EXT_CONFIG_CLEAR =3D +CapsuleBuild =3D FALSE +EXT_BUILD_FLAGS =3D -D CPUTARGET=3DICX -D RP_PKG=3DWhitleyOpenBoardPkg -D = SILICON_PKG=3DWhitleySiliconPkg -D PCD_DYNAMIC_AS_DYNAMICEX -D MAX_CORE=3D6= 4 -D MAX_THREAD=3D2 -D PLATFORM_PKG=3DMinPlatformPkg +MAX_SOCKET =3D 4 +CAPSULE_BUILD =3D 0 +TARGET =3D DEBUG +TARGET_SHORT =3D D +PERFORMANCE_BUILD =3D FALSE +FSP_WRAPPER_BUILD =3D TRUE +FSP_BIN_PKG =3D WhitleyFspBinPkg +FSP_PKG_NAME =3D WhitleyFspPkg +FSP_BINARY_BUILD =3D FALSE +FSP_TEST_RELEASE =3D FALSE +SECURE_BOOT_ENABLE =3D FALSE +BIOS_INFO_GUID =3D 4A4CA1C6-871C-45BB-8801-6910A7AA5807 + +# +# AML offset table generation configuration options +# All paths should use / and be relative to edk2-platforms/Platform/Intel +# +# AML_FILTER - AML filter is used to strip out unused= AML offset data +# AML_OFFSETS_PATH - Path to INF file that builds AML offse= ts C source file +# The directory name, DSC file name, INF file name, and BASE_NAME must m= atch identically +# DSDT_TABLE_FILE_PATH - Path to DSDT ASL file for the board +# STRIPPED_AML_OFFSETS_FILE_PATH - Target AML offset data file consumed b= y UBA driver +# +AML_FILTER =3D \"PSYS\" .\.DRVT\" .\.FIX[0-9,A-Z] BBI[0] BBU[0] CRCM BAR0 = .\.CCT[0-9A-Z]\" .\.CFH[0-9A-Z]\" .\.FXCD\" .\.FXST\" .\.FXIN\" .\.FXOU\" .= \.FXBS\" .\.FXFH\" .\.CENA\" .\.DRVT\" .\.CFIS\" {NULL }; +AML_OFFSETS_PATH =3D WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets +DSDT_TABLE_FILE_PATH =3D WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt= /EPRPPlatform10nm.asl +STRIPPED_AML_OFFSETS_FILE_PATH =3D WhitleyOpenBoardPkg/Uba/UbaMain/StaticS= kuDataDxe/AmlOffsetTable.c diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec b/Platform/= Intel/WhitleyOpenBoardPkg/PlatformPkg.dec index 27253b1a58..fb071b0ac0 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec @@ -1,906 +1,907 @@ -## @file -# Platform Package -# Cross Platform Modules for Tiano -# -# @copyright -# Copyright 2008 - 2021 Intel Corporation.
-# Copyright (c) 2021, American Megatrends International LLC.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -## - -[Defines] - DEC_SPECIFICATION =3D 0x00010005 - PACKAGE_NAME =3D PlatformPkg - PACKAGE_GUID =3D 9A29FD32-8C72-4b25-A7C4-767F7A2838EB - PACKAGE_VERSION =3D 0.91 - -[Includes] - Include - Include/Protocol - -#TODO: Move these generated temp files into include. - Uba/BoardInit/Dxe - -[Guids] - gBiosInfoGuid =3D { 0x1b453c67, 0x= cb1a, 0x46ec, { 0x86, 0x4b, 0xe2, 0x24, 0xa6, 0xb7, 0xfe, 0xe8 } } - gEfiAcpiTableStorageGuid =3D { 0x7e374e25, 0x= 8e01, 0x4fee, { 0x87, 0xf2, 0x39, 0x0c, 0x23, 0xc6, 0x06, 0xcd } } - gClvBootTimeTestExecution =3D { 0x3ff7d152, 0x= ef86, 0x47c3, { 0x97, 0xb0, 0xce, 0xd9, 0xbb, 0x80, 0x9a, 0x67 } } - gUbaCurrentConfigHobGuid =3D { 0xe4b2025b, 0x= c7db, 0x4e5d, { 0xa6, 0x5e, 0x2b, 0x25, 0x7e, 0xb1, 0x5, 0x8e } } - - gCommonSystemConfigurationGuid =3D { 0xec87d643, 0x= eba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 } } - gEfiSetupVariableGuid =3D { 0xec87d643, 0x= eba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0x0d, 0xa9 } } - gEfiSetupVariableDefaultGuid =3D { 0x8d247131, 0x= 385e, 0x491f, { 0xba, 0x68, 0x8d, 0xe9, 0x55, 0x30, 0xb3, 0xa6 } } - gEfiGlobalVariableControlGuid =3D { 0x99a96812, 0x= 4730, 0x4290, { 0x8b, 0xfe, 0x7b, 0x4e, 0x51, 0x4f, 0xf9, 0x3b } } - gMainPkgListGuid =3D { 0x6205c3a4, 0x= 1149, 0x491a, { 0xa6, 0xd6, 0x1e, 0x72, 0x3b, 0x87, 0x83, 0xb1 } } - gAdvancedPkgListGuid =3D { 0xc09c81cb, 0x= 31e9, 0x4de6, { 0xa9, 0xf9, 0x17, 0xa1, 0x44, 0x35, 0x42, 0x45 } } - gTpmPkgListGuid =3D { 0x7da45aa9, 0x= 6dbf, 0x4f1b, { 0xa4, 0x3e, 0x32, 0x87, 0xcb, 0xe5, 0x13, 0x51 } } - gSecurityPkgListGuid =3D { 0x3a885aae, 0x= 3e30, 0x42b9, { 0xa9, 0x76, 0x2f, 0x1f, 0x13, 0xbd, 0x70, 0x15 } } - gBootOptionsPkgListGuid =3D { 0x62197ef0, 0x= 7b7e, 0x11e2, { 0xb9, 0x2a, 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66 } } - gEfiOcDataGuid =3D { 0x4af92599, 0x= 8e76, 0x4bb4, { 0xbf, 0xd2, 0xf5, 0xa6, 0x6e, 0x30, 0x41, 0xd4 } } - gEfiDprRegsProgrammedGuid =3D { 0x4b844201, 0x= 6fe9, 0x41d1, { 0xb4, 0x6f, 0xdf, 0xfc, 0x34, 0xe4, 0x92, 0xa2 } } - gPlatformModuleTokenSpaceGuid =3D { 0x69d13bf0, 0x= af91, 0x4d96, { 0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0 } } - gCpPlatFlashTokenSpaceGuid =3D { 0xc9c39664, 0x= 96dd, 0x4c5c, { 0xaf, 0xd7, 0xcd, 0x65, 0x76, 0x29, 0xcf, 0xb0 } } - gPchSetupVariableGuid =3D { 0x4570b7f1, 0x= ade8, 0x4943, { 0x8d, 0xc3, 0x40, 0x64, 0x72, 0x84, 0x23, 0x84 } } - -# -# UBA_START -# - #OEM SKU - gOemSkuTokenSpaceGuid =3D { 0x9e37d253, 0x= abf8, 0x4985, { 0x8e, 0x23, 0xba, 0xca, 0x10, 0x39, 0x56, 0x13 } } - gPlatformKtiEparamUpdateDataGuid =3D { 0x7bc065cf, 0x= afe8, 0x4396, { 0xae, 0x9f, 0xba, 0x27, 0xdf, 0xbe, 0xcf, 0x3d } } - gSmbiosTablesTokenSpaceGuid =3D { 0x5e80ad48, 0x= f240, 0x4fe9, { 0x87, 0xef, 0x4b, 0x46, 0xf4, 0xde, 0x78, 0xa0 } } - gPlatformGpioInitDataGuid =3D { 0x9282563e, 0x= ae17, 0x4e12, { 0xb1, 0xdc, 0x7, 0xf, 0x29, 0xf3, 0x71, 0x20 } } -# -# UBA_END -# - gReserveMemFlagVariableGuid =3D { 0xb87aa73f, 0x= dcb3, 0x4533, { 0x83, 0x98, 0x6c, 0x12, 0x84, 0x27, 0x28, 0x40 } } - gEfiOpaSocketMapHobGuid =3D { 0x829d41d2, 0x= 6ca5, 0x485b, { 0xa1, 0xa2, 0xd1, 0xb7, 0x96, 0x27, 0xab, 0xcd } } - gEfiPlatformTxtPolicyDataGuid =3D { 0xa353290b, 0x= 867d, 0x4cd3, { 0xa8, 0x1b, 0x4b, 0x7e, 0x5e, 0x10, 0x0e, 0x16 } } - gEfiSmmPeiSmramMemoryReserveGuid =3D { 0x6dadf1d1, 0x= d4cc, 0x4910, { 0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d } } - gSystemBoardInfoConfigDataGuid =3D { 0x68B046F7, 0x= 15A0, 0x4778, { 0xBE, 0xA3, 0x9B, 0xA2, 0xDB, 0xD1, 0x3B, 0x82 } } - - # Fce multi mode support - gPlatformVariableHobGuid =3D { 0x71e6d4bc, 0x= 4837, 0x45f1, { 0xa2, 0xd7, 0x3f, 0x93, 0x08, 0xb1, 0x7e, 0xd7 } } - gDefaultDataFileGuid =3D { 0x1ae42876, 0x= 008f, 0x4161, { 0xb2, 0xb7, 0x1c, 0x0d, 0x15, 0xc5, 0xef, 0x43 } } - - gCpPlatIpmiTokenSpaceGuid =3D { 0xd1112ebf, 0x= d82, 0x4071, { 0x96, 0x7c, 0xe1, 0x69, 0x23, 0x27, 0x40, 0xba } } - gEfiIpmiFormatFruGuid =3D { 0x3531fdc6, 0x= eae, 0x4cd2, { 0xb0, 0xa6, 0x5f, 0x48, 0xa0, 0xdf, 0xe3, 0x8 } } - gServerCommonIpmiTokenSpaceGuid =3D { 0xd1112ebf, 0x= d82, 0x4071, { 0x96, 0x7c, 0xe1, 0x69, 0x23, 0x27, 0x40, 0xba } } - - gServerMgmtPkgListGuid =3D { 0x35dcfcd1, 0x= c14e, 0x45e9, { 0xbe, 0xd3, 0xbb, 0x1, 0x64, 0xf8, 0x80, 0x7b } } - - - ## Include/Guid/CpPlatPkgTokenSpace.h - gCpPlatTokenSpaceGuid =3D { 0xc9c39664, 0x= 96dd, 0x4c5c, { 0xaf, 0xd7, 0xcd, 0x65, 0x76, 0x29, 0xcf, 0xb0 } } - gEfiSetupEnterGuid =3D { 0x71202EEE, 0x= 5F53, 0x40d9, { 0xAB, 0x3D, 0x9E, 0x0C, 0x26, 0xD9, 0x66, 0x57 } } - gEfiSetupExitGuid =3D { 0xD6E335EC, 0x= 0336, 0x4CB1, { 0x87, 0xA2, 0xDA, 0x87, 0xD7, 0xE9, 0x99, 0x40 }} - - gPlatformTokenSpaceGuid =3D { 0x07dfa0d2, 0x= 2ac5, 0x4cab, { 0xac, 0x14, 0x30, 0x5c, 0x62, 0x48, 0x87, 0xe4 } } - -[Ppis] -# -# UBA_START -# - gEfiPeiPlatformTypeWolfPassPpiGuid =3D { 0xd2a92001, 0x= 22ad, 0x43b9, { 0xbe, 0xbc, 0x1b, 0x15, 0x21, 0x00, 0xd8, 0xcc } } - gEfiPeiPlatformTypeNeonCityEPRPPpiGuid =3D { 0xa2e5609e, 0x= 8c2d, 0x42e6, { 0xa2, 0xfc, 0x12, 0xbc, 0x74, 0xbd, 0x43, 0x7f } } - gEfiPeiPlatformTypeTennesseePassPpiGuid =3D { 0xf7b87a79, 0x= a640, 0x4aa5, { 0x8c, 0x1e, 0x45, 0x3f, 0xb2, 0x6e, 0xf3, 0x76 } } - gEfiPeiPlatformTypeNeonCityEPECBPpiGuid =3D { 0x21877e2f, 0x= f86e, 0x4e8a, { 0x9c, 0x9b, 0xd7, 0xb1, 0x52, 0xdd, 0x40, 0xd8 } } - gEfiPeiPlatformTypeOpalCitySTHIPpiGuid =3D { 0xa07b3bdf, 0x= b78a, 0x41ee, { 0xa2, 0x76, 0x55, 0xc2, 0x25, 0xa0, 0x7b, 0x0b } } - gEfiPeiPlatformTypePurleyLBGEPDVPPpiGuid =3D { 0x3c234470, 0x= 69d3, 0x42e1, { 0xb3, 0x23, 0xc8, 0x09, 0x30, 0x0f, 0x39, 0x25 } } - gEfiPeiPlatformTypeCrescentCityPpiGuid =3D { 0x4ad920ef, 0x= 4d6f, 0x4915, { 0x98, 0x2a, 0xdc, 0x16, 0x67, 0x71, 0x31, 0xd5 } } - gEfiPeiPlatformTypeHedtEVPpiGuid =3D { 0x41781f4f, 0x= a3cd, 0x4750, { 0x8a, 0x2c, 0x21, 0x92, 0xb4, 0xdf, 0xe5, 0x2b } } - gEfiPeiPlatformTypeHedtCRBPpiGuid =3D { 0x9bb6e29a, 0x= 2272, 0x426a, { 0xab, 0x77, 0x9b, 0x7f, 0xe5, 0xef, 0xea, 0x84 } } - gEfiPeiPlatformTypeLightningRidgeEXRPPpiGuid =3D { 0xaf2417f4, 0x= 7b7e, 0x4c2e, { 0x94, 0xbb, 0x7a, 0x33, 0x89, 0xa1, 0x57, 0xca } } - gEfiPeiPlatformTypeLightningRidgeEXECB1PpiGuid =3D { 0xf70a4116, 0x= fdf6, 0x45fb, { 0x93, 0xcd, 0x84, 0xcd, 0xdd, 0x73, 0xdf, 0xd4 } } - gEfiPeiPlatformTypeLightningRidgeEXECB2PpiGuid =3D { 0x0c04b0ff, 0x= 227d, 0x479a, { 0x93, 0x5a, 0xf6, 0xe5, 0xa8, 0xb5, 0x19, 0x8c } } - gEfiPeiPlatformTypeLightningRidgeEXECB3PpiGuid =3D { 0x94c0203b, 0x= 54c9, 0x416e, { 0xa6, 0xe0, 0x47, 0xe8, 0xd4, 0x78, 0x69, 0x01 } } - gEfiPeiPlatformTypeLightningRidgeEXECB4PpiGuid =3D { 0x4284a11c, 0x= 18c1, 0x4c10, { 0xb2, 0xd9, 0x58, 0x6a, 0x01, 0x60, 0xa5, 0x23 } } - gEfiPeiPlatformTypeLightningRidgeEX8S1NPpiGuid =3D { 0x4f51c243, 0x= 7cee, 0x4144, { 0x8e, 0xed, 0x23, 0x4a, 0xc2, 0xda, 0xbd, 0x53 } } - gEfiPeiPlatformTypeLightningRidgeEX8S2NPpiGuid =3D { 0x5d9516d3, 0x= bc49, 0x4337, { 0x9f, 0xc7, 0x29, 0xdf, 0x35, 0x26, 0xec, 0x87 } } - gEfiPeiPlatformTypeKyanitePpiGuid =3D { 0xb23ce2c1, 0x= 16a0, 0x4f69, { 0x98, 0x0a, 0x95, 0xc7, 0x72, 0x16, 0xf9, 0xa2 } } - gEfiPeiPlatformTypeNeonCityFPGAPpiGuid =3D { 0x48e796bd, 0x= 4ed3, 0x4755, { 0xa8, 0xca, 0x4c, 0xf4, 0x37, 0x25, 0x82, 0x41 } } - gEfiPeiPlatformTypeOpalCityFPGAPpiGuid =3D { 0xe5434b26, 0x= aedf, 0x43de, { 0x89, 0x35, 0xd1, 0xc4, 0x85, 0xa9, 0x12, 0xb9 } } - gEfiPeiPlatformTypeWilsonCityRPPpiGuid =3D { 0x0629aff2, 0x= 4e23, 0x45c6, { 0x90, 0xc5, 0xb3, 0x21, 0x7b, 0x00, 0x09, 0x23 } } - gEfiPeiPlatformTypeWilsonCityModularPpiGuid =3D { 0x3170ea7b, 0x= 6784, 0x4366, { 0xb4, 0xc6, 0xfe, 0x69, 0x9f, 0x69, 0x42, 0x21 } } - gEfiPlatformTypeIsoscelesPeakPpiGuid =3D { 0xfc7b089f, 0x= 5395, 0x40c0, { 0x9e, 0xfb, 0xca, 0x90, 0x59, 0xe2, 0x7f, 0xea } } - - gPeiIpmiTransportPpiGuid =3D { 0x7bf5fecc, 0x= c5b5, 0x4b25, { 0x81, 0x1b, 0xb4, 0xb5, 0xb, 0x28, 0x79, 0xf7 } } - -# -# UBA_END -# - - gBoardInitGuid =3D { 0xecc07551, 0x= d64c, 0x4c07, { 0xab, 0x95, 0x94, 0x5, 0x66, 0xed, 0x31, 0xf1 } } - gUbaConfigDatabasePpiGuid =3D { 0xc1176733, 0x= 159f, 0x42d5, { 0xbc, 0xb9, 0x32, 0x6, 0x60, 0xb1, 0x73, 0x10 } } - - gPeiSpiSoftStrapsPpiGuid =3D { 0x7F19E716, 0x= 419C, 0x4E79, { 0x8E, 0x37, 0xC2, 0xBD, 0x84, 0xEB, 0x65, 0x28 } } - gUpdatePcdGuid =3D { 0xa08e4c6b, 0x= ff28, 0x4fff, { 0x93, 0x56, 0x78, 0x36, 0x26, 0xc3, 0xe0, 0x38 } } - gPlatformVariableInitPpiGuid =3D { 0x9b1b911b, 0x= 4259, 0x4539, { 0xaf, 0x86, 0xe5, 0xf3, 0x61, 0xca, 0x09, 0x02 } } - gUpdateBootModePpiGuid =3D { 0x927186a0, 0x= a13e, 0x4b53, { 0xad, 0x41, 0xad, 0xd1, 0x65, 0x6f, 0x62, 0x62 } } - - gEfiPeiExStatusCodeHandlerPpiGuid =3D { 0x4e942617, 0x= bbca, 0x4726, { 0x77, 0xb9, 0x49, 0x68, 0x85, 0xf9, 0xc4, 0xf4 } } - - -[Protocols] - gEfiPlatformTypeProtocolGuid =3D { 0x171e9398, 0x= 269c, 0x4081, { 0x90, 0x99, 0x38, 0x44, 0xe2, 0x60, 0x46, 0x6c } } - gUbaConfigDatabaseProtocolGuid =3D { 0xe03e0d46, 0x= 5263, 0x4845, { 0xb0, 0xa4, 0x58, 0xd5, 0x7b, 0x31, 0x77, 0xe2 } } -# -# UBA_START -# - gEfiPlatformTypeNeonCityEPRPProtocolGuid =3D { 0xc0cd2d36, 0x= a81b, 0x450d, { 0xa5, 0x02, 0x37, 0x67, 0xdf, 0xa2, 0x98, 0x26 } } - gEfiPlatformTypeHedtCRBProtocolGuid =3D { 0x2c824f87, 0x= 0f2c, 0x45d7, { 0x81, 0xa6, 0x4f, 0x39, 0xe0, 0x42, 0xbd, 0xdf } } - gEfiPlatformTypeLightningRidgeEXRPProtocolGuid =3D { 0x1b4ae0f8, 0x= ed1f, 0x4fd1, { 0x9b, 0x18, 0xb0, 0x82, 0x29, 0x0f, 0x86, 0xf5 } } - gEfiPlatformTypeLightningRidgeEX8S1NProtocolGuid =3D { 0x45b59855, 0x= 500c, 0x443b, { 0xb5, 0x04, 0x9a, 0xb4, 0xca, 0x29, 0xbc, 0x68 } } - gEfiPlatformTypeWilsonCityRPProtocolGuid =3D { 0x8430776f, 0x= bd75, 0x4fc8, { 0xa5, 0x4f, 0x7f, 0x6b, 0xf6, 0x18, 0x9c, 0x13 } } - gEfiPlatformTypeIsoscelesPeakProtocolGuid =3D { 0xcff3f211, 0x= 5d51, 0x4f87, { 0x94, 0xb0, 0x9b, 0x94, 0xf8, 0x4e, 0x8a, 0x48 } } - gEfiPlatformTypeWilsonCityModularProtocolGuid =3D { 0x28e862f4, 0x= a4ed, 0x4acb, { 0x9a, 0x35, 0x36, 0xd0, 0x90, 0x2d, 0xf7, 0x82 } } - - gEfiPlatformTypeWilsonCitySMTProtocolGuid =3D { 0xEE55562D, 0x= 4001, 0xFC27, { 0xDF, 0x16, 0x7B, 0x90, 0xEB, 0xE1, 0xAB, 0x04 } } - gEfiPlatformTypeCooperCityRPProtocolGuid =3D { 0x45c302e1, 0x= 4b86, 0x89be, { 0xab, 0x0f, 0x5e, 0xb5, 0x57, 0xdf, 0xe8, 0xd8 } } - gEfiPlatformTypeJunctionCityProtocolGuid =3D { 0xB1C2B1C9, 0x= B606, 0x4B62, { 0x9D, 0x78, 0xCB, 0xD6, 0x0F, 0xF9, 0x0D, 0x0C } } - -# -# UBA_END -# - - gEfiPciIovPlatformProtocolGuid =3D { 0xf3a4b484, 0x= 9b26, 0x4eea, { 0x90, 0xe5, 0xa2, 0x06, 0x54, 0x0c, 0xa5, 0x25 } } - gEfiWindowsInt10Workaround =3D { 0x387f555, 0x2= 0a8, 0x4fc2, { 0xbb, 0x94, 0xcd, 0x30, 0xda, 0x1b, 0x40, 0x08 } } - gEfiVMDDriverProtocolGuid =3D { 0x5a676ae9, 0x= db23, 0x4a68, { 0xa2, 0x4d, 0xaa, 0x5f, 0xec, 0xd5, 0x74, 0x86 } } - gEfiHfiPcieGen3ProtocolGuid =3D { 0x7b59316e, 0x= e9df, 0x435f, { 0x98, 0xcd, 0x57, 0x26, 0x64, 0x5b, 0xe8, 0x63 } } - gEfiLegacyBiosProtocolGuid =3D { 0xdb9a1e3d, 0x= 45cb, 0x4abb, { 0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d } } - - gEfiIpmiSolStatusProtocolGuid =3D { 0xe790848e, 0x= b6ab, 0x44ab, { 0x84, 0x91, 0xdc, 0xa5, 0xc, 0x39, 0x7, 0xc6 } } - gEfiIpmiTransportProtocolGuid =3D { 0x6bb945e8, 0x= 3743, 0x433e, { 0xb9, 0xe, 0x29, 0xb3, 0xd, 0x5d, 0xc6, 0x30 } } - gSmmIpmiTransportProtocolGuid =3D { 0x8bb070f1, 0x= a8f3, 0x471d, { 0x86, 0x16, 0x77, 0x4b, 0xa3, 0xf4, 0x30, 0xa0 } } - gEfiIpmiBootGuid =3D { 0x5c9b75ec, 0x= 8ec7, 0x45f2, { 0x8f, 0x8f, 0xc1, 0xd8, 0x8f, 0x3b, 0x93, 0x45 } } - gEfiGenericIpmiDriverInstalledGuid =3D { 0x7cdad61a, 0x= 3df8, 0x4425, { 0x96, 0x8c, 0x66, 0x28, 0xc8, 0x35, 0xff, 0xce } } - - gDmaRemapProtocolGuid =3D { 0x4e873773, 0x839= 1, 0x4e47, { 0xb7, 0xf4, 0xca, 0xfb, 0xdc, 0xc4, 0xb2, 0x04 } } - -[PcdsFixedAtBuild] - - gPlatformTokenSpaceGuid.PcdEfiAcpiPm1aEvtBlkAddress|0x00000500|UINT32|0x= 00000031 - - gCpPlatFlashTokenSpaceGuid.PcdFlashBase|0x00000000 |UINT32|0x3000000E - gCpPlatFlashTokenSpaceGuid.PcdFlashSize|0x00000000 |UINT32|0x3000000F - gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaBase|0x00000000|UINT32|0x300000= 1A - gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaSize|0x00000000|UINT32|0x300000= 1B - gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsSize|0x00000000|UINT32|0x300= 0001C - gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase|0x00000000|UINT32|0x300= 0001D - gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinarySize|0x00000000|UINT32|0x3000= 001E - gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase|0x00000000|UINT32|0x3000= 001F - gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize|0x00000000|UINT32|0x30000= 020 - gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase|0x00000000|UINT32|0x30000= 021 - gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|0x0000000|UINT32|0x3000= 0027 - - gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize|0x0000000|UINT32|0x30000= 001 - gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|0x0000000|UINT32|0x300= 00004 - gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|0x000000= 0|UINT32|0x30000006 - gPlatformModuleTokenSpaceGuid.PcdFlashFreeSpaceOffset|0x0000000|UINT32|0= x30000008 - - gPlatformTokenSpaceGuid.PcdSupportLegacyStack|TRUE|BOOLEAN|0x30000030 - gPlatformTokenSpaceGuid.PcdMaxOptionRomNumber|0x4|UINT8|0x30000031 - - # - # Debug Mode indicator - # - gPlatformTokenSpaceGuid.PcdDebugModeEnable|0x01|UINT8|0xE0000040 - - gPlatformTokenSpaceGuid.PcdCmosDebugPrintLevelReg|0x4C|UINT8|0x30000032 - - # Choose the default serial debug message level when CMOS is bad; in the= later BIOS phase, the setup default is applied - # 0 - Disable; 1 - Minimum; 2 - Normal; 3 - Max - gPlatformTokenSpaceGuid.PcdSerialDbgLvlAtBadCmos|0x1|UINT8|0x30000033 - gPlatformTokenSpaceGuid.PcdWilsonPointSvidVrP1V8|0x05|UINT8|0x30000000 = #BIT4 =3D> SVID BUS 0, BIT3-BIT0 =3D> VR ADDRESS - gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrP1V8|0x15|UINT8|0x30000002 - gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrVccAna|0x16|UINT8|0x30000003 - - # PCD for failsafe variable ffs in other FV rather than bb1 - # by default, FCE will insert into SECPEI, and you don't need to set the= se two PCD if bb1(secpei)is used - gPlatformTokenSpaceGuid.PcdFailSafeVarFfsSize|0|UINT32|0x30000034 - gPlatformTokenSpaceGuid.PcdFailSafeVarFvBase|0|UINT32|0x30000035 - - gPlatformTokenSpaceGuid.PcdSetupVariableGuid|{ 0x43,0xd6,0x87,0xec,0xa4,= 0xeb, 0xb5,0x4b, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9}|VOID*|0x30= 000036 - - # - # These need to move to MinPlatformPkg.dec - # - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize|0|UINT32|0xF000= 00A9 - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase|0|UINT32|0xF000= 00AA - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|0|UINT32|0xF0= 0000AB - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize|0|UINT32|0xF00000AC - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase|0|UINT32|0xF00000AD - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|0|UINT32|0xF00000AE - - #IIO configuration data for socket 3 will be used for sockets 4..7 - gPlatformTokenSpaceGuid.PcdSocketCopy|FALSE|BOOLEAN|0xF00000AF - - gCpPlatFlashTokenSpaceGuid.PcdFlashCfrRegionSize|0x01000000|UINT32|0xF00= 000B0 - gCpPlatFlashTokenSpaceGuid.PcdFlashCfrRegionBase|0xFF900000|UINT32|0xF00= 000B1 - - #If True, extend PCR7 when VT-d disabled. - gPlatformTokenSpaceGuid.PcdConditionallyExtendPcr7|FALSE|BOOLEAN|0xE0000= 045 - - #If 0 BoardId detection is done using GPIO. Otherwise Board id will be f= orced to value set by this PCD - #Non zero value should match the values defined in PlatformInfoTypes.h - gPlatformTokenSpaceGuid.PcdBoardId|0|UINT8|0xE0000046 - - # BoardRevion Id value. Valid only if PcdBoardId is not equal to 0 - gPlatformTokenSpaceGuid.PcdBoardRevId|0|UINT8|0xE0000047 - -[PcdsFixedAtBuild, PcdsPatchableInModule] - gPlatformTokenSpaceGuid.PcdShellFile|{ 0xB7, 0xD6, 0x7A, 0xC5, 0x15, 0x0= 5, 0xA8, 0x40, 0x9D, 0x21, 0x55, 0x16, 0x52, 0x85, 0x4E, 0x37 }|VOID*|0x400= 00004 - ## Specify memory size with page number for a pre-allocated reserved mem= ory to be used - # by PEI in S3 phase. The default size 32K. When changing the value mak= e sure the memory size - # is large enough to meet PEI requirement in the S3 phase. - # @Prompt Reserved S3 Boot ACPI Memory Size - gPlatformModuleTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x8000|UINT32|= 0x90010039 - gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012 - gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013 - gPlatformModuleTokenSpaceGuid.PcdPcIoApicCount|0|UINT8|0x90000015 - gPlatformModuleTokenSpaceGuid.PcdPcIoApicIdBase|0x09|UINT8|0x90000016 - gPlatformModuleTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000|UINT32|0= x90000017 - gPlatformModuleTokenSpaceGuid.PcdPcIoApicInterruptBase|24|UINT32|0x90000= 018 - - - gPlatformModuleTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0x900= 00025 - gPlatformModuleTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x900000= 26 - gPlatformModuleTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x90000027 - gPlatformModuleTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000|UINT32|0x90= 00000B - gPlatformModuleTokenSpaceGuid.PcdIoApicAddress|0xFEC00000|UINT32|0x90000= 00D - gPlatformModuleTokenSpaceGuid.PcdIoApicId|0x02|UINT8|0x90000014 - gPlatformModuleTokenSpaceGuid.PcdWsmtProtectionFlags|0|UINT32|0x10001006 - -[PcdsDynamicEx] - -# -# PAL -# - gPlatformTokenSpaceGuid.PcdOemSkuPcieSlotOpromBitMap|0xFF|UINT32|0x00000= 008 - -#SKX_TODO: gPlatformTokenSpaceGuid are not correct GUIDs to use here, use = local GUID... - gPlatformTokenSpaceGuid.PcdBootDeviceScratchPad5Changed|FALSE|BOOLEAN|0x= 00000048 - - ## This value is used to save memory address of MRC data structure. - gPlatformTokenSpaceGuid.PcdBoardTypeBitmask|0x00000000|UINT32|0x30000041 - gPlatformTokenSpaceGuid.PcdHalfWidth|FALSE|BOOLEAN|0x30000042 - -# -# IMR0 programming values -# - gPlatformTokenSpaceGuid.PcdImr0Enable|FALSE|BOOLEAN|0xA5000000 - gPlatformTokenSpaceGuid.PcdImr0Base|0x0|UINT64|0xA5000001 - gPlatformTokenSpaceGuid.PcdImr0Mask|0x0|UINT64|0xA5000002 - gPlatformTokenSpaceGuid.PcdImr0Rac|0xFFFFFFFFFFFFFFFF|UINT64|0xA5000003 - gPlatformTokenSpaceGuid.PcdImr0Wac|0xFFFFFFFFFFFFFFFF|UINT64|0xA5000004 - -# -# IMR3 programming values -# - gPlatformTokenSpaceGuid.PcdImr3Enable|FALSE|BOOLEAN|0xA5000022 - -# -# Server common Hot Key binding -# - # EFI Scan codes - # SCAN_F2 0x000C - # SCAN_F6 0x0010 - # SCAN_F7 0x0011 - gPlatformTokenSpaceGuid.PcdSetupMenuScanCode|0x00|UINT16|0x00000009 - gPlatformTokenSpaceGuid.PcdBootDeviceListScanCode|0x00|UINT16|0x0000000A - - - gPlatformTokenSpaceGuid.PcdBootMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee, 0xf2, = 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d }|VOID*|0x= 0000000B - -#Indicate whether to perform LT Config lock -# The PCD can be set to false when there is the debug request -# TRUE - Force the LT config lock -# FALSE - Allow the LT config unlock for debug - gPlatformModuleTokenSpaceGuid.PcdLtConfigLockEnable|TRUE|BOOLEAN|0x30000= 00e - -#Indicate whether LTSX enabled -# TRUE - Intel (R) TXT feature enabled on the platform -# FALSE - Disable Intel(R) TXT feature on the platform - gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable | TRUE|BOOLEAN|0x30= 00000f - - # - # SMBIOS Type 0 - BIOS Information - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosVendor|"TBD"|VOID*|0x5B00= 0000 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosVersion|"TBD"|VOID*|0x5B0= 00001 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosReleaseDate|"TBD"|VOID*|0= x5B000002 - - # - # SMBIOS Type 1 - System Information - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemManufacturer|"TBD"|VOID= *|0x5B010000 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemProductName|"TBD"|VOID*= |0x5B010001 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemVersion|"TBD"|VOID*|0x5= B010002 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemSerialNumber|"TBD"|VOID= *|0x5B010003 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemSkuNumber|"TBD"|VOID*|0= x5B010004 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemFamily|"TBD"|VOID*|0x5B= 010005 - - # - # SMBIOS Type 2 - Base Board (or Module) Information - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardManufacturer|"TBD"|V= OID*|0x5B020000 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardProductName|"TBD"|VO= ID*|0x5B020001 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardVersion|"TBD"|VOID*|= 0x5B020002 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardSerialNumber|"TBD"|V= OID*|0x5B020003 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardAssetTag|"TBD"|VOID*= |0x5B020004 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardLocationInChassis|"T= BD"|VOID*|0x5B020005 - - # - # SMBIOS Type 3 - System Enclosure or Chassis Information - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisManufacturer|"TBD"|VOI= D*|0x5B030000 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisVersion|"TBD"|VOID*|0x= 5B030001 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisSerialNumber|"TBD"|VOI= D*|0x5B030002 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisAssetTag|"TBD"|VOID*|0= x5B030003 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisSkuNumber|"TBD"|VOID*|= 0x5B030004 - - # - # SMBIOS Type 11 - OEM Strings - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesOemString1|"TBD"|VOID*|0x5B0B= 0001 - - # - # SMBIOS Type 12 - System Configuration Options - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSysConfigOption1|"TBD"|VOID*|= 0x5B0C0001 - - # - # SMBIOS Type 14 - Group Associations - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTableType|0xDD|UINT8|0x5B0D0001 - - # - # SMBIOS Type 17 - Memory Device - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesMemorySerialNumberFormat|0x00= |UINT8|0x5B110000 - - # - # SMBIOS Type 27 - Cooling Device - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesCoolingDeviceDescription|"TBD= "|VOID*|0x5B1B0000 - - # - # SMBIOS Type 28 - Temperature Probe - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesTemperatureProbeDescription|"= TBD"|VOID*|0x5B1C0000 - - # - # SMBIOS Type 34 - Management Device - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesManagementDeviceDescription|"= TBD"|VOID*|0x5B220000 - - # - # SMBIOS Type 35 - Management Device Component - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesManagementDeviceComponentDesc= ription|"TBD"|VOID*|0x5B230000 - - # - # SMBIOS Type 39 - System Power Supply - # - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyLocation|"TB= D"|VOID*|0x5B270000 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyDeviceName|"= TBD"|VOID*|0x5B270001 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyManufacturer= |"TBD"|VOID*|0x5B270002 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplySerialNumber= |"TBD"|VOID*|0x5B270003 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyAssetTagNumb= er|"TBD"|VOID*|0x5B270004 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyModelPartNum= ber|"TBD"|VOID*|0x5B270005 - gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyRevisionLeve= l|"TBD"|VOID*|0x5B270006 - -[PcdsFeatureFlag] - gPlatformTokenSpaceGuid.PcdSupportUnsignedCapsuleImage|TRUE|BOOLEAN|0x00= 000020 - - ## - ## High Speed UART - ## - gPlatformModuleTokenSpaceGuid.PcdEnableHighSpeedUart|FALSE|BOOLEAN|0x000= 0002C - - ## Platform Not support Acpi Table - # - gPlatformTokenSpaceGuid.PcdPlatformNotSupportAcpiTable|FALSE|BOOLEAN|0x4= 0000012 - gPlatformTokenSpaceGuid.PcdPlatformNotSupportAcpiBdatTable|FALSE|BOOLEAN= |0x40000013 - -[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx] - ## MemoryCheck value for checking memory before boot OS. - # To save the boot performance, the default MemoryCheck is set to 0. - gPlatformTokenSpaceGuid.PcdPlatformMemoryCheck|0|UINT8|0x40000005 - - - ## following PCDs should remove if CORE accept the fix - gPlatformTokenSpaceGuid.PcdPerfPkgPchPmBaseFunctionNumber|0x0|UINT32|4 - - ## Vendor ID and Device ID of device producing onboard video - gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId|0|UINT16|0x00000013 - gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId|0|UINT16|0x00000014 - gPlatformModuleTokenSpaceGuid.PcdPlatformMemoryCheckLevel|0|UINT32|0x300= 00009 - ## This PCD is to control which device is the potential trusted console = input device.

- # For example:
- # USB Short Form: UsbHID(0xFFFF,0xFFFF,0x1,0x1)
- # //Header VendorId ProductId Class SubClass P= rotocol
- # {0x03, 0x0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0= x01,
- # //Header
- # 0x7F, 0xFF, 0x04, 0x00}
- gPlatformModuleTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{0x03, 0x= 0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0x01, 0x7F, 0xFF, 0x04,= 0x00}|VOID*|0x300000A - - ## This PCD is to control which device is the potential trusted console = output device.

- # For example:
- # Integrated Graphic: PciRoot(0x0)/Pci(0x2,0x0)
- # //Header HID UID
- # {0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00= , 0x00,
- # //Header Func Dev
- # 0x01, 0x01, 0x06, 0x00, 0x00, 0x02, - # //Header
- # 0x7F, 0xFF, 0x04, 0x00}
- gPlatformModuleTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{0x02, 0= x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01= , 0x06, 0x00, 0x00, 0x02, 0x7F, 0xFF, 0x04, 0x00}|VOID*|0x300000C - - - gPlatformModuleTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x1800|UINT16= |0x00010035 - gPlatformModuleTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0x0000|UINT16= |0x00010036 - gPlatformModuleTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x1804|UINT= 16|0x0001037 - gPlatformModuleTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0x0000|UINT= 16|0x00010038 - gPlatformModuleTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x1850|UINT1= 6|0x00010039 - gPlatformModuleTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x1808|UINT16|0= x0001003A - gPlatformModuleTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x1880|UINT16|0x00= 01003B - gPlatformModuleTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0x0000|UINT16|0x00= 01003C - -# -# UBA_START -# -[PcdsDynamicEx] - -# -#Board Definitions -# -#Integer for BoardID, must match the SKU number and be unique. - gOemSkuTokenSpaceGuid.PcdOemSkuBoardID|0x0|UINT16|0x00000000 -#Integer for BoardFamily, must be unique - gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily|0x0|UINT16|0x00000001 -# Zero terminated unicode string to ID family - gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName|L"DEFAULT = "|VOID*|0x0000002 -# Zero terminated unicode string to Board Name - gOemSkuTokenSpaceGuid.PcdOemSkuBoardName|L"DEFAULT = "|VOID*|0x00000003 -# Number of Sockets on Board. - gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount|0x0|UINT32|0x00000004 - -# Number of DIMM slots per channel for each Socket - gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel|0x0|UINT32|0x00000005 - gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel|0x0|UINT32|0x00000006 - gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout|FALSE|BOOLEAN|0x00000007 - gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID|0x0|UINT16|0x00000008 - - gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmSize|0x100|UINT32|0x00000009 -# Form factor is MemoryFormFactorDimm by default -# MemoryFormFactorOther =3D 0x01 -# MemoryFormFactorUnknown =3D 0x02 -# MemoryFormFactorSimm =3D 0x03 -# MemoryFormFactorSip =3D 0x04 -# MemoryFormFactorChip =3D 0x05 -# MemoryFormFactorDip =3D 0x06 -# MemoryFormFactorZip =3D 0x07 -# MemoryFormFactorProprietaryCard =3D 0x08 -# MemoryFormFactorDimm =3D 0x09 -# MemoryFormFactorTsop =3D 0x0A -# MemoryFormFactorRowOfChips =3D 0x0B -# MemoryFormFactorRimm =3D 0x0C -# MemoryFormFactorSodimm =3D 0x0D -# MemoryFormFactorSrimm =3D 0x0E -# MemoryFormFactorFbDimm =3D 0x0F -# MemoryFormFactorDie =3D 0x10 - gOemSkuTokenSpaceGuid.PcdOemSkuMemDevFormFactor|0x09|UINT8|0x10000010 - -# -# USB -# -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00|0x0|UINT16|0x000000= 10 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01|0x0|UINT16|0x000000= 11 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02|0x0|UINT16|0x000000= 12 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03|0x0|UINT16|0x000000= 13 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04|0x0|UINT16|0x000000= 14 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05|0x0|UINT16|0x000000= 15 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06|0x0|UINT16|0x000000= 16 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07|0x0|UINT16|0x000000= 17 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08|0x0|UINT16|0x000000= 18 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09|0x0|UINT16|0x000000= 19 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10|0x0|UINT16|0x000000= 1A -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11|0x0|UINT16|0x000000= 1B -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12|0x0|UINT16|0x000000= 1C -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13|0x0|UINT16|0x000000= 1D - -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00|0x0|UINT16|0x0000002= 0 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01|0x0|UINT16|0x0000002= 1 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02|0x0|UINT16|0x0000002= 2 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03|0x0|UINT16|0x0000002= 3 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04|0x0|UINT16|0x0000002= 4 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05|0x0|UINT16|0x0000002= 5 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06|0x0|UINT16|0x0000002= 6 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07|0x0|UINT16|0x0000002= 7 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08|0x0|UINT16|0x0000002= 8 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09|0x0|UINT16|0x0000002= 9 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10|0x0|UINT16|0x0000002= A -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11|0x0|UINT16|0x0000002= B -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12|0x0|UINT16|0x0000002= C -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13|0x0|UINT16|0x0000002= D - -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00|0x0|UINT16|0x00000= 100 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01|0x0|UINT16|0x00000= 101 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02|0x0|UINT16|0x00000= 102 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03|0x0|UINT16|0x00000= 103 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04|0x0|UINT16|0x00000= 104 -gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05|0x0|UINT16|0x00000= 105 - -# -# ACPI items -# -# Acpi Name, MUST be 8 chars long - gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName|"DEFAULT "|VOID*|0x000000= 30 - gOemSkuTokenSpaceGuid.PcdOemTableIdXhci|"DEFAULT "|VOID*|0x000000= 31 -# -# Misc. -# - - gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag|0x0|UINT8|0x00000039 - gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed|0x0|UINT16|0x00000040 - -# -# GPIO -# - - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL|0xFF3DB93D|UINT32|0x000= 00050 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL|0x0382F03F|UINT32|0x00= 000051 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL|0xFFFFF30F|UINT32|0x00= 000052 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL|0x91E3EFFF|UINT32|0x0000= 0053 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL|0xFFFD0FF3|UINT32|0x000= 00054 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL|0xFFFFFDF0|UINT32|0x000= 00055 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL|0x661C1000|UINT32|0x0000005= 6 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL|0x0002F004|UINT32|0x000000= 57 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL|0x0000020D|UINT32|0x000000= 58 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL|0x00000000|UINT32|0x0000005= 9 - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL|0x00000000|UINT32|0x00000= 05a - gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE|0x00000000|UINT32|0x0000= 005c - -# -# SATA registers -# - - gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32|0x99990000|UINT32|0x0000005b - -# -# Clock generator settings -# - - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00|0xFF|UINT8|0x00000060 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01|0x9E|UINT8|0x00000061 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02|0x3F|UINT8|0x00000062 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03|0x00|UINT8|0x00000063 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04|0x00|UINT8|0x00000064 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05|0x0F|UINT8|0x00000065 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06|0x08|UINT8|0x00000066 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07|0x11|UINT8|0x00000067 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08|0x0A|UINT8|0x00000068 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09|0x17|UINT8|0x00000069 - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10|0xFF|UINT8|0x0000006a - gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11|0xFE|UINT8|0x0000006b - gOemSkuTokenSpaceGuid.PcdOemSkuClockGeneratorAddress|0xD2|UINT8|0x000000= 6c - - gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName|L"DEFAULT = "|VOID*|0x00000201 - gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize|0x0|UINT32|0x00000202 - gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag|0x0|UINT32|0x00000203 - -# -# If PcdOemSkuAssertPostGPIO value is 0xFFFFFFFF, current platform don't s= et related GPIO. -# - gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO|0x01010014|UINT32|0x000002= 04 - gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue|0x0|UINT32|0x00000205 - - gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber|0xFF|UINT8|0x00000206 - gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex|0xFF|UINT8|0x00000207 -# -# UBA_END -# - - gCpPlatIpmiTokenSpaceGuid.PcdIpmiIoBaseAddress|0xCA2|UINT16|0x10000022 - gCpPlatIpmiTokenSpaceGuid.PcdIpmiSmmIoBaseAddress|0xCA4|UINT16|0x1000002= 3 - gCpPlatIpmiTokenSpaceGuid.PcdSioMailboxBaseAddress|0x600|UINT32|0x100000= 21 - gCpPlatIpmiTokenSpaceGuid.PcdFRB2EnabledFlag|TRUE|BOOLEAN|0x10000030 - gCpPlatIpmiTokenSpaceGuid.PcdIpmiBmcReadyDelayTimer|0|UINT8|0x00000208 - - -## This PCD replaces the original one gEfiIntelFrameworkModulePkgTokenSpac= eGuid.PcdBootState - gPlatformModuleTokenSpaceGuid.PcdBootState|TRUE|BOOLEAN|0x300000AC - gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x00000208 - -[PcdsDynamicEx] - gCpPlatTokenSpaceGuid.PcdUefiOptimizedBoot|FALSE|BOOLEAN|0x10000026 - gCpPlatTokenSpaceGuid.PcdUefiOptimizedBootEx|FALSE|BOOLEAN|0x10000024 - -[PcdsFixedAtBuild] -# -# Flash map related PCD. -# -# Note: most values here are overridden in the .fdf file -# -# -# Note: FlashNv PCD naming conventions are as follows: -# -# PcdFlash*Base is an address, usually in the range of 0xf* of FD's,= note change in FDF spec -# PcdFlash*Size is a hex count of the length of the FD or FV -# All Fv will have the form 'PcdFlashFv', and all Fd will have the f= orm 'PcdFlashFd' -# -# Also all values will have a PCD assigned so that they can be used = in the system, and -# the FlashMap edit tool can be used to change the values here, with= out effecting the code. -# This requires all code to only use the PCD tokens to recover the v= alues. -# - - - -# PCD's that are for the whole SPI part - - -#Block size of SPI -gCpPlatFlashTokenSpaceGuid.PcdFlashBlockSize |0x00010= 000 |UINT32|0x50000102 - - -#AJW rename this to be more in keeping with the function -gCpPlatFlashTokenSpaceGuid.PcdFlashAreaBase |0xfff00= 000 |UINT32|0x50000105 - - - -# for PeiSec FD - -gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize |0x00100= 000 |UINT32|0x50000221 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase |0x00000= 000 |UINT32|0x50000222 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase |0x00000= 000 |UINT32|0x50000260 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize |0x00040= 000 |UINT32|0x50000261 - -gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase |0x00000= 000 |UINT32|0x50000211 -gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize |0x00100= 000 |UINT32|0x50000212 - -gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize |0x001000= 00 |UINT32|0x50000233 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase |0x000000= 00 |UINT32|0x50000234 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset |0x000000= 00 |UINT32|0x50000235 - -gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize |0x00100= 000 |UINT32|0x50000241 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase |0x00000= 000 |UINT32|0x50000242 - -gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize |0x00100= 000 |UINT32|0x50000251 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase |0x00000= 000 |UINT32|0x50000252 - - -# for Main FD - - -gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase |0xfff0= 0000 |UINT32|0x50000300 -gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize |0x0040= 0000 |UINT32|0x50000301 - -gCpPlatFlashTokenSpaceGuid.PcdFlashFvMainSize |0x0020= 0000 |UINT32|0x50000311 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvMainBase |0xFF82= 0000 |UINT32|0x50000312 - -gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize |0x0020= 0000 |UINT32|0x50000341 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase |0xFF82= 0000 |UINT32|0x50000342 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset |0xFF82= 0000 |UINT32|0x50000343 - - -gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize |0x0020= 0000 |UINT32|0x50000351 -gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase |0xFF82= 0000 |UINT32|0x50000352 - -## This PCD specifies the size of the physical device containing the BIOS,= SMBIOS will use it. - -gCpPlatFlashTokenSpaceGuid.PcdFlashBackupRegionBase |0xFF80= 0000 |UINT32|0x50000001 -gCpPlatFlashTokenSpaceGuid.PcdFlashBackupRegionSize |0x0000= 0000 |UINT32|0x50000002 - -[PcdsFeatureFlag.common] - -## -## Those PCDs are used to control build process. -## - - # - # SV Tools - # - gPlatformFeatureTokenSpaceGuid.PcdXmlCliEnable|TRUE|BOOLEAN|0xE0000000 - gPlatformFeatureTokenSpaceGuid.PcdSvBiosEnable|TRUE|BOOLEAN|0xE000002E - # - # - # - -[PcdsDynamicEx] - ### Sample implementation...No real data. Use this PCD to override a pla= tform with Interposer ### - gPlatformTokenSpaceGuid.PcdMemInterposerMap|{0}|INTERPOSER_MAP|0x8000001= 5 { - - Guid/PlatformInfo.h - - WhitleyOpenBoardPkg/PlatformPkg.dec - } - # Interposer A MC 0 mapped to original MC1 - # Enum values for Interposer - # Interposer A =3D> 1 - # Interposer B =3D> 2 - # Interposer Unknown =3D> 0 - gPlatformTokenSpaceGuid.PcdMemInterposerMap.Interposer[1].MappedMcId[0] = |1 - -### Sample implementation...No real data. Use this PCD to override a platf= orm with Interposer ### - -[Guids] - gStructPcdTokenSpaceGuid =3D {0x3f1406f4, 0x2b, 0x487a, {0x8b, 0x69, 0x7= 4, 0x29, 0x1b, 0x36, 0x16, 0xf4}} - -[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx] -gStructPcdTokenSpaceGuid.PcdEmulationDfxConfig|{0}|EMULATION_DFX_CONFIGURA= TION|0XFCD0000C{ - - Include/Guid/EmulationDfxVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec -} -gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig|{0}|FPGA_SOCKET_CONFIGURATION= |0XFCD00010{ - - Include/Guid/FpgaSocketVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec -} -gStructPcdTokenSpaceGuid.PcdIeRcConfiguration|{0}|IE_RC_CONFIGURATION|0XFC= D00004{ - - Include/Guid/IeRcVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdMeRcConfiguration|{0}|ME_RC_CONFIGURATION|0XFC= D0000B{ - - Include/Guid/MeRcVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig|{0}|MEM_BOOT_HEALTH_CONFIG= |0XFCD00002{ - - Include/Guid/MemBootHealthGuid.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdPchSetup|{0}|PCH_SETUP|0XFCD00007{ - - Include/PchSetupVariableLbg.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdSetup|{0}|SYSTEM_CONFIGURATION|0XFCD0000F{ - - Include/Guid/SetupVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig|{0}|SOCKET_COMMONRC_CONFI= GURATION|0XFCD00001{ - - Include/Guid/SocketCommonRcVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdSocketIioConfig|{0}|SOCKET_IIO_CONFIGURATION|0= XFCD00006{ - - Include/Guid/SocketIioVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig|{0}|SOCKET_MEMORY_CONFIGURA= TION|0XFCD0000D{ - - Include/Guid/SocketMemoryVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig|{0}|SOCKET_MP_LINK_CONFIGUR= ATION|0XFCD00008{ - - Include/Guid/SocketMpLinkVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig|{0}|SOCKET_POWERMA= NAGEMENT_CONFIGURATION|0XFCD00005{ - - Include/Guid/SocketPowermanagementVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig|{0}|SOCKET_PROCESSOR= CORE_CONFIGURATION|0XFCD00003{ - - Include/Guid/SocketProcessorCoreVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdSvConfiguration|{0}|SV_CONFIGURATION|0XFCD0000= 9{ - - Include/Guid/SetupVariable.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec -} -gStructPcdTokenSpaceGuid.PcdTCG2_CONFIGURATION|{0}|TCG2_CONFIGURATION|0XFC= D0000A{ - - Include/Tcg2ConfigNvData.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - SecurityPkg/SecurityPkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec -} -gStructPcdTokenSpaceGuid.PcdTCG2_VERSION|{0}|TCG2_VERSION|0XFCD0000E{ - - Include/Tcg2ConfigNvData.h - - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - SecurityPkg/SecurityPkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec -} -[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx] - gOemSkuTokenSpaceGuid.PcdTurboPowerLimitLock|0x01|UINT8|0x00000209 - gOemSkuTokenSpaceGuid.PcdNumberOfCoresToDisable|0x0|UINT16|0x0000020A - -[LibraryClasses] - ServerManagementTimeStampLib|Include/Library/ServerManagementTimeStampLi= b.inf +## @file +# Platform Package +# Cross Platform Modules for Tiano +# +# @copyright +# Copyright 2008 - 2021 Intel Corporation.
+# Copyright (c) 2021 - 2022, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D PlatformPkg + PACKAGE_GUID =3D 9A29FD32-8C72-4b25-A7C4-767F7A2838EB + PACKAGE_VERSION =3D 0.91 + +[Includes] + Include + Include/Protocol + +#TODO: Move these generated temp files into include. + Uba/BoardInit/Dxe + +[Guids] + gBiosInfoGuid =3D { 0x1b453c67, 0x= cb1a, 0x46ec, { 0x86, 0x4b, 0xe2, 0x24, 0xa6, 0xb7, 0xfe, 0xe8 } } + gEfiAcpiTableStorageGuid =3D { 0x7e374e25, 0x= 8e01, 0x4fee, { 0x87, 0xf2, 0x39, 0x0c, 0x23, 0xc6, 0x06, 0xcd } } + gClvBootTimeTestExecution =3D { 0x3ff7d152, 0x= ef86, 0x47c3, { 0x97, 0xb0, 0xce, 0xd9, 0xbb, 0x80, 0x9a, 0x67 } } + gUbaCurrentConfigHobGuid =3D { 0xe4b2025b, 0x= c7db, 0x4e5d, { 0xa6, 0x5e, 0x2b, 0x25, 0x7e, 0xb1, 0x5, 0x8e } } + + gCommonSystemConfigurationGuid =3D { 0xec87d643, 0x= eba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 } } + gEfiSetupVariableGuid =3D { 0xec87d643, 0x= eba4, 0x4bb5, { 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0x0d, 0xa9 } } + gEfiSetupVariableDefaultGuid =3D { 0x8d247131, 0x= 385e, 0x491f, { 0xba, 0x68, 0x8d, 0xe9, 0x55, 0x30, 0xb3, 0xa6 } } + gEfiGlobalVariableControlGuid =3D { 0x99a96812, 0x= 4730, 0x4290, { 0x8b, 0xfe, 0x7b, 0x4e, 0x51, 0x4f, 0xf9, 0x3b } } + gMainPkgListGuid =3D { 0x6205c3a4, 0x= 1149, 0x491a, { 0xa6, 0xd6, 0x1e, 0x72, 0x3b, 0x87, 0x83, 0xb1 } } + gAdvancedPkgListGuid =3D { 0xc09c81cb, 0x= 31e9, 0x4de6, { 0xa9, 0xf9, 0x17, 0xa1, 0x44, 0x35, 0x42, 0x45 } } + gTpmPkgListGuid =3D { 0x7da45aa9, 0x= 6dbf, 0x4f1b, { 0xa4, 0x3e, 0x32, 0x87, 0xcb, 0xe5, 0x13, 0x51 } } + gSecurityPkgListGuid =3D { 0x3a885aae, 0x= 3e30, 0x42b9, { 0xa9, 0x76, 0x2f, 0x1f, 0x13, 0xbd, 0x70, 0x15 } } + gBootOptionsPkgListGuid =3D { 0x62197ef0, 0x= 7b7e, 0x11e2, { 0xb9, 0x2a, 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66 } } + gEfiOcDataGuid =3D { 0x4af92599, 0x= 8e76, 0x4bb4, { 0xbf, 0xd2, 0xf5, 0xa6, 0x6e, 0x30, 0x41, 0xd4 } } + gEfiDprRegsProgrammedGuid =3D { 0x4b844201, 0x= 6fe9, 0x41d1, { 0xb4, 0x6f, 0xdf, 0xfc, 0x34, 0xe4, 0x92, 0xa2 } } + gPlatformModuleTokenSpaceGuid =3D { 0x69d13bf0, 0x= af91, 0x4d96, { 0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0 } } + gCpPlatFlashTokenSpaceGuid =3D { 0xc9c39664, 0x= 96dd, 0x4c5c, { 0xaf, 0xd7, 0xcd, 0x65, 0x76, 0x29, 0xcf, 0xb0 } } + gPchSetupVariableGuid =3D { 0x4570b7f1, 0x= ade8, 0x4943, { 0x8d, 0xc3, 0x40, 0x64, 0x72, 0x84, 0x23, 0x84 } } + +# +# UBA_START +# + #OEM SKU + gOemSkuTokenSpaceGuid =3D { 0x9e37d253, 0x= abf8, 0x4985, { 0x8e, 0x23, 0xba, 0xca, 0x10, 0x39, 0x56, 0x13 } } + gPlatformKtiEparamUpdateDataGuid =3D { 0x7bc065cf, 0x= afe8, 0x4396, { 0xae, 0x9f, 0xba, 0x27, 0xdf, 0xbe, 0xcf, 0x3d } } + gSmbiosTablesTokenSpaceGuid =3D { 0x5e80ad48, 0x= f240, 0x4fe9, { 0x87, 0xef, 0x4b, 0x46, 0xf4, 0xde, 0x78, 0xa0 } } + gPlatformGpioInitDataGuid =3D { 0x9282563e, 0x= ae17, 0x4e12, { 0xb1, 0xdc, 0x7, 0xf, 0x29, 0xf3, 0x71, 0x20 } } +# +# UBA_END +# + gReserveMemFlagVariableGuid =3D { 0xb87aa73f, 0x= dcb3, 0x4533, { 0x83, 0x98, 0x6c, 0x12, 0x84, 0x27, 0x28, 0x40 } } + gEfiOpaSocketMapHobGuid =3D { 0x829d41d2, 0x= 6ca5, 0x485b, { 0xa1, 0xa2, 0xd1, 0xb7, 0x96, 0x27, 0xab, 0xcd } } + gEfiPlatformTxtPolicyDataGuid =3D { 0xa353290b, 0x= 867d, 0x4cd3, { 0xa8, 0x1b, 0x4b, 0x7e, 0x5e, 0x10, 0x0e, 0x16 } } + gEfiSmmPeiSmramMemoryReserveGuid =3D { 0x6dadf1d1, 0x= d4cc, 0x4910, { 0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d } } + gSystemBoardInfoConfigDataGuid =3D { 0x68B046F7, 0x= 15A0, 0x4778, { 0xBE, 0xA3, 0x9B, 0xA2, 0xDB, 0xD1, 0x3B, 0x82 } } + + # Fce multi mode support + gPlatformVariableHobGuid =3D { 0x71e6d4bc, 0x= 4837, 0x45f1, { 0xa2, 0xd7, 0x3f, 0x93, 0x08, 0xb1, 0x7e, 0xd7 } } + gDefaultDataFileGuid =3D { 0x1ae42876, 0x= 008f, 0x4161, { 0xb2, 0xb7, 0x1c, 0x0d, 0x15, 0xc5, 0xef, 0x43 } } + + gCpPlatIpmiTokenSpaceGuid =3D { 0xd1112ebf, 0x= d82, 0x4071, { 0x96, 0x7c, 0xe1, 0x69, 0x23, 0x27, 0x40, 0xba } } + gEfiIpmiFormatFruGuid =3D { 0x3531fdc6, 0x= eae, 0x4cd2, { 0xb0, 0xa6, 0x5f, 0x48, 0xa0, 0xdf, 0xe3, 0x8 } } + gServerCommonIpmiTokenSpaceGuid =3D { 0xd1112ebf, 0x= d82, 0x4071, { 0x96, 0x7c, 0xe1, 0x69, 0x23, 0x27, 0x40, 0xba } } + + gServerMgmtPkgListGuid =3D { 0x35dcfcd1, 0x= c14e, 0x45e9, { 0xbe, 0xd3, 0xbb, 0x1, 0x64, 0xf8, 0x80, 0x7b } } + + + ## Include/Guid/CpPlatPkgTokenSpace.h + gCpPlatTokenSpaceGuid =3D { 0xc9c39664, 0x= 96dd, 0x4c5c, { 0xaf, 0xd7, 0xcd, 0x65, 0x76, 0x29, 0xcf, 0xb0 } } + gEfiSetupEnterGuid =3D { 0x71202EEE, 0x= 5F53, 0x40d9, { 0xAB, 0x3D, 0x9E, 0x0C, 0x26, 0xD9, 0x66, 0x57 } } + gEfiSetupExitGuid =3D { 0xD6E335EC, 0x= 0336, 0x4CB1, { 0x87, 0xA2, 0xDA, 0x87, 0xD7, 0xE9, 0x99, 0x40 }} + + gPlatformTokenSpaceGuid =3D { 0x07dfa0d2, 0x= 2ac5, 0x4cab, { 0xac, 0x14, 0x30, 0x5c, 0x62, 0x48, 0x87, 0xe4 } } + +[Ppis] +# +# UBA_START +# + gEfiPeiPlatformTypeWolfPassPpiGuid =3D { 0xd2a92001, 0x= 22ad, 0x43b9, { 0xbe, 0xbc, 0x1b, 0x15, 0x21, 0x00, 0xd8, 0xcc } } + gEfiPeiPlatformTypeNeonCityEPRPPpiGuid =3D { 0xa2e5609e, 0x= 8c2d, 0x42e6, { 0xa2, 0xfc, 0x12, 0xbc, 0x74, 0xbd, 0x43, 0x7f } } + gEfiPeiPlatformTypeTennesseePassPpiGuid =3D { 0xf7b87a79, 0x= a640, 0x4aa5, { 0x8c, 0x1e, 0x45, 0x3f, 0xb2, 0x6e, 0xf3, 0x76 } } + gEfiPeiPlatformTypeNeonCityEPECBPpiGuid =3D { 0x21877e2f, 0x= f86e, 0x4e8a, { 0x9c, 0x9b, 0xd7, 0xb1, 0x52, 0xdd, 0x40, 0xd8 } } + gEfiPeiPlatformTypeOpalCitySTHIPpiGuid =3D { 0xa07b3bdf, 0x= b78a, 0x41ee, { 0xa2, 0x76, 0x55, 0xc2, 0x25, 0xa0, 0x7b, 0x0b } } + gEfiPeiPlatformTypePurleyLBGEPDVPPpiGuid =3D { 0x3c234470, 0x= 69d3, 0x42e1, { 0xb3, 0x23, 0xc8, 0x09, 0x30, 0x0f, 0x39, 0x25 } } + gEfiPeiPlatformTypeCrescentCityPpiGuid =3D { 0x4ad920ef, 0x= 4d6f, 0x4915, { 0x98, 0x2a, 0xdc, 0x16, 0x67, 0x71, 0x31, 0xd5 } } + gEfiPeiPlatformTypeHedtEVPpiGuid =3D { 0x41781f4f, 0x= a3cd, 0x4750, { 0x8a, 0x2c, 0x21, 0x92, 0xb4, 0xdf, 0xe5, 0x2b } } + gEfiPeiPlatformTypeHedtCRBPpiGuid =3D { 0x9bb6e29a, 0x= 2272, 0x426a, { 0xab, 0x77, 0x9b, 0x7f, 0xe5, 0xef, 0xea, 0x84 } } + gEfiPeiPlatformTypeLightningRidgeEXRPPpiGuid =3D { 0xaf2417f4, 0x= 7b7e, 0x4c2e, { 0x94, 0xbb, 0x7a, 0x33, 0x89, 0xa1, 0x57, 0xca } } + gEfiPeiPlatformTypeLightningRidgeEXECB1PpiGuid =3D { 0xf70a4116, 0x= fdf6, 0x45fb, { 0x93, 0xcd, 0x84, 0xcd, 0xdd, 0x73, 0xdf, 0xd4 } } + gEfiPeiPlatformTypeLightningRidgeEXECB2PpiGuid =3D { 0x0c04b0ff, 0x= 227d, 0x479a, { 0x93, 0x5a, 0xf6, 0xe5, 0xa8, 0xb5, 0x19, 0x8c } } + gEfiPeiPlatformTypeLightningRidgeEXECB3PpiGuid =3D { 0x94c0203b, 0x= 54c9, 0x416e, { 0xa6, 0xe0, 0x47, 0xe8, 0xd4, 0x78, 0x69, 0x01 } } + gEfiPeiPlatformTypeLightningRidgeEXECB4PpiGuid =3D { 0x4284a11c, 0x= 18c1, 0x4c10, { 0xb2, 0xd9, 0x58, 0x6a, 0x01, 0x60, 0xa5, 0x23 } } + gEfiPeiPlatformTypeLightningRidgeEX8S1NPpiGuid =3D { 0x4f51c243, 0x= 7cee, 0x4144, { 0x8e, 0xed, 0x23, 0x4a, 0xc2, 0xda, 0xbd, 0x53 } } + gEfiPeiPlatformTypeLightningRidgeEX8S2NPpiGuid =3D { 0x5d9516d3, 0x= bc49, 0x4337, { 0x9f, 0xc7, 0x29, 0xdf, 0x35, 0x26, 0xec, 0x87 } } + gEfiPeiPlatformTypeKyanitePpiGuid =3D { 0xb23ce2c1, 0x= 16a0, 0x4f69, { 0x98, 0x0a, 0x95, 0xc7, 0x72, 0x16, 0xf9, 0xa2 } } + gEfiPeiPlatformTypeNeonCityFPGAPpiGuid =3D { 0x48e796bd, 0x= 4ed3, 0x4755, { 0xa8, 0xca, 0x4c, 0xf4, 0x37, 0x25, 0x82, 0x41 } } + gEfiPeiPlatformTypeOpalCityFPGAPpiGuid =3D { 0xe5434b26, 0x= aedf, 0x43de, { 0x89, 0x35, 0xd1, 0xc4, 0x85, 0xa9, 0x12, 0xb9 } } + gEfiPeiPlatformTypeWilsonCityRPPpiGuid =3D { 0x0629aff2, 0x= 4e23, 0x45c6, { 0x90, 0xc5, 0xb3, 0x21, 0x7b, 0x00, 0x09, 0x23 } } + gEfiPeiPlatformTypeWilsonCityModularPpiGuid =3D { 0x3170ea7b, 0x= 6784, 0x4366, { 0xb4, 0xc6, 0xfe, 0x69, 0x9f, 0x69, 0x42, 0x21 } } + gEfiPlatformTypeIsoscelesPeakPpiGuid =3D { 0xfc7b089f, 0x= 5395, 0x40c0, { 0x9e, 0xfb, 0xca, 0x90, 0x59, 0xe2, 0x7f, 0xea } } + + gPeiIpmiTransportPpiGuid =3D { 0x7bf5fecc, 0x= c5b5, 0x4b25, { 0x81, 0x1b, 0xb4, 0xb5, 0xb, 0x28, 0x79, 0xf7 } } + +# +# UBA_END +# + + gBoardInitGuid =3D { 0xecc07551, 0x= d64c, 0x4c07, { 0xab, 0x95, 0x94, 0x5, 0x66, 0xed, 0x31, 0xf1 } } + gUbaConfigDatabasePpiGuid =3D { 0xc1176733, 0x= 159f, 0x42d5, { 0xbc, 0xb9, 0x32, 0x6, 0x60, 0xb1, 0x73, 0x10 } } + + gPeiSpiSoftStrapsPpiGuid =3D { 0x7F19E716, 0x= 419C, 0x4E79, { 0x8E, 0x37, 0xC2, 0xBD, 0x84, 0xEB, 0x65, 0x28 } } + gUpdatePcdGuid =3D { 0xa08e4c6b, 0x= ff28, 0x4fff, { 0x93, 0x56, 0x78, 0x36, 0x26, 0xc3, 0xe0, 0x38 } } + gPlatformVariableInitPpiGuid =3D { 0x9b1b911b, 0x= 4259, 0x4539, { 0xaf, 0x86, 0xe5, 0xf3, 0x61, 0xca, 0x09, 0x02 } } + gUpdateBootModePpiGuid =3D { 0x927186a0, 0x= a13e, 0x4b53, { 0xad, 0x41, 0xad, 0xd1, 0x65, 0x6f, 0x62, 0x62 } } + + gEfiPeiExStatusCodeHandlerPpiGuid =3D { 0x4e942617, 0x= bbca, 0x4726, { 0x77, 0xb9, 0x49, 0x68, 0x85, 0xf9, 0xc4, 0xf4 } } + + +[Protocols] + gEfiPlatformTypeProtocolGuid =3D { 0x171e9398, 0x= 269c, 0x4081, { 0x90, 0x99, 0x38, 0x44, 0xe2, 0x60, 0x46, 0x6c } } + gUbaConfigDatabaseProtocolGuid =3D { 0xe03e0d46, 0x= 5263, 0x4845, { 0xb0, 0xa4, 0x58, 0xd5, 0x7b, 0x31, 0x77, 0xe2 } } +# +# UBA_START +# + gEfiPlatformTypeNeonCityEPRPProtocolGuid =3D { 0xc0cd2d36, 0x= a81b, 0x450d, { 0xa5, 0x02, 0x37, 0x67, 0xdf, 0xa2, 0x98, 0x26 } } + gEfiPlatformTypeHedtCRBProtocolGuid =3D { 0x2c824f87, 0x= 0f2c, 0x45d7, { 0x81, 0xa6, 0x4f, 0x39, 0xe0, 0x42, 0xbd, 0xdf } } + gEfiPlatformTypeLightningRidgeEXRPProtocolGuid =3D { 0x1b4ae0f8, 0x= ed1f, 0x4fd1, { 0x9b, 0x18, 0xb0, 0x82, 0x29, 0x0f, 0x86, 0xf5 } } + gEfiPlatformTypeLightningRidgeEX8S1NProtocolGuid =3D { 0x45b59855, 0x= 500c, 0x443b, { 0xb5, 0x04, 0x9a, 0xb4, 0xca, 0x29, 0xbc, 0x68 } } + gEfiPlatformTypeWilsonCityRPProtocolGuid =3D { 0x8430776f, 0x= bd75, 0x4fc8, { 0xa5, 0x4f, 0x7f, 0x6b, 0xf6, 0x18, 0x9c, 0x13 } } + gEfiPlatformTypeIsoscelesPeakProtocolGuid =3D { 0xcff3f211, 0x= 5d51, 0x4f87, { 0x94, 0xb0, 0x9b, 0x94, 0xf8, 0x4e, 0x8a, 0x48 } } + gEfiPlatformTypeWilsonCityModularProtocolGuid =3D { 0x28e862f4, 0x= a4ed, 0x4acb, { 0x9a, 0x35, 0x36, 0xd0, 0x90, 0x2d, 0xf7, 0x82 } } + + gEfiPlatformTypeWilsonCitySMTProtocolGuid =3D { 0xEE55562D, 0x= 4001, 0xFC27, { 0xDF, 0x16, 0x7B, 0x90, 0xEB, 0xE1, 0xAB, 0x04 } } + gEfiPlatformTypeCooperCityRPProtocolGuid =3D { 0x45c302e1, 0x= 4b86, 0x89be, { 0xab, 0x0f, 0x5e, 0xb5, 0x57, 0xdf, 0xe8, 0xd8 } } + gEfiPlatformTypeJunctionCityProtocolGuid =3D { 0xB1C2B1C9, 0x= B606, 0x4B62, { 0x9D, 0x78, 0xCB, 0xD6, 0x0F, 0xF9, 0x0D, 0x0C } } + gEfiPlatformTypeAowandaProtocolGuid =3D { 0x65231A3C, 0x= C343, 0x4C7E, { 0xA4, 0x5E, 0x0F, 0x99, 0x74, 0xA6, 0x90, 0x83 } } + +# +# UBA_END +# + + gEfiPciIovPlatformProtocolGuid =3D { 0xf3a4b484, 0x= 9b26, 0x4eea, { 0x90, 0xe5, 0xa2, 0x06, 0x54, 0x0c, 0xa5, 0x25 } } + gEfiWindowsInt10Workaround =3D { 0x387f555, 0x2= 0a8, 0x4fc2, { 0xbb, 0x94, 0xcd, 0x30, 0xda, 0x1b, 0x40, 0x08 } } + gEfiVMDDriverProtocolGuid =3D { 0x5a676ae9, 0x= db23, 0x4a68, { 0xa2, 0x4d, 0xaa, 0x5f, 0xec, 0xd5, 0x74, 0x86 } } + gEfiHfiPcieGen3ProtocolGuid =3D { 0x7b59316e, 0x= e9df, 0x435f, { 0x98, 0xcd, 0x57, 0x26, 0x64, 0x5b, 0xe8, 0x63 } } + gEfiLegacyBiosProtocolGuid =3D { 0xdb9a1e3d, 0x= 45cb, 0x4abb, { 0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d } } + + gEfiIpmiSolStatusProtocolGuid =3D { 0xe790848e, 0x= b6ab, 0x44ab, { 0x84, 0x91, 0xdc, 0xa5, 0xc, 0x39, 0x7, 0xc6 } } + gEfiIpmiTransportProtocolGuid =3D { 0x6bb945e8, 0x= 3743, 0x433e, { 0xb9, 0xe, 0x29, 0xb3, 0xd, 0x5d, 0xc6, 0x30 } } + gSmmIpmiTransportProtocolGuid =3D { 0x8bb070f1, 0x= a8f3, 0x471d, { 0x86, 0x16, 0x77, 0x4b, 0xa3, 0xf4, 0x30, 0xa0 } } + gEfiIpmiBootGuid =3D { 0x5c9b75ec, 0x= 8ec7, 0x45f2, { 0x8f, 0x8f, 0xc1, 0xd8, 0x8f, 0x3b, 0x93, 0x45 } } + gEfiGenericIpmiDriverInstalledGuid =3D { 0x7cdad61a, 0x= 3df8, 0x4425, { 0x96, 0x8c, 0x66, 0x28, 0xc8, 0x35, 0xff, 0xce } } + + gDmaRemapProtocolGuid =3D { 0x4e873773, 0x839= 1, 0x4e47, { 0xb7, 0xf4, 0xca, 0xfb, 0xdc, 0xc4, 0xb2, 0x04 } } + +[PcdsFixedAtBuild] + + gPlatformTokenSpaceGuid.PcdEfiAcpiPm1aEvtBlkAddress|0x00000500|UINT32|0x= 00000031 + + gCpPlatFlashTokenSpaceGuid.PcdFlashBase|0x00000000 |UINT32|0x3000000E + gCpPlatFlashTokenSpaceGuid.PcdFlashSize|0x00000000 |UINT32|0x3000000F + gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaBase|0x00000000|UINT32|0x300000= 1A + gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaSize|0x00000000|UINT32|0x300000= 1B + gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsSize|0x00000000|UINT32|0x300= 0001C + gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase|0x00000000|UINT32|0x300= 0001D + gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinarySize|0x00000000|UINT32|0x3000= 001E + gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase|0x00000000|UINT32|0x3000= 001F + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize|0x00000000|UINT32|0x30000= 020 + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase|0x00000000|UINT32|0x30000= 021 + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|0x0000000|UINT32|0x3000= 0027 + + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize|0x0000000|UINT32|0x30000= 001 + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|0x0000000|UINT32|0x300= 00004 + gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|0x000000= 0|UINT32|0x30000006 + gPlatformModuleTokenSpaceGuid.PcdFlashFreeSpaceOffset|0x0000000|UINT32|0= x30000008 + + gPlatformTokenSpaceGuid.PcdSupportLegacyStack|TRUE|BOOLEAN|0x30000030 + gPlatformTokenSpaceGuid.PcdMaxOptionRomNumber|0x4|UINT8|0x30000031 + + # + # Debug Mode indicator + # + gPlatformTokenSpaceGuid.PcdDebugModeEnable|0x01|UINT8|0xE0000040 + + gPlatformTokenSpaceGuid.PcdCmosDebugPrintLevelReg|0x4C|UINT8|0x30000032 + + # Choose the default serial debug message level when CMOS is bad; in the= later BIOS phase, the setup default is applied + # 0 - Disable; 1 - Minimum; 2 - Normal; 3 - Max + gPlatformTokenSpaceGuid.PcdSerialDbgLvlAtBadCmos|0x1|UINT8|0x30000033 + gPlatformTokenSpaceGuid.PcdWilsonPointSvidVrP1V8|0x05|UINT8|0x30000000 = #BIT4 =3D> SVID BUS 0, BIT3-BIT0 =3D> VR ADDRESS + gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrP1V8|0x15|UINT8|0x30000002 + gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrVccAna|0x16|UINT8|0x30000003 + + # PCD for failsafe variable ffs in other FV rather than bb1 + # by default, FCE will insert into SECPEI, and you don't need to set the= se two PCD if bb1(secpei)is used + gPlatformTokenSpaceGuid.PcdFailSafeVarFfsSize|0|UINT32|0x30000034 + gPlatformTokenSpaceGuid.PcdFailSafeVarFvBase|0|UINT32|0x30000035 + + gPlatformTokenSpaceGuid.PcdSetupVariableGuid|{ 0x43,0xd6,0x87,0xec,0xa4,= 0xeb, 0xb5,0x4b, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9}|VOID*|0x30= 000036 + + # + # These need to move to MinPlatformPkg.dec + # + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize|0|UINT32|0xF000= 00A9 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase|0|UINT32|0xF000= 00AA + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|0|UINT32|0xF0= 0000AB + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize|0|UINT32|0xF00000AC + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase|0|UINT32|0xF00000AD + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|0|UINT32|0xF00000AE + + #IIO configuration data for socket 3 will be used for sockets 4..7 + gPlatformTokenSpaceGuid.PcdSocketCopy|FALSE|BOOLEAN|0xF00000AF + + gCpPlatFlashTokenSpaceGuid.PcdFlashCfrRegionSize|0x01000000|UINT32|0xF00= 000B0 + gCpPlatFlashTokenSpaceGuid.PcdFlashCfrRegionBase|0xFF900000|UINT32|0xF00= 000B1 + + #If True, extend PCR7 when VT-d disabled. + gPlatformTokenSpaceGuid.PcdConditionallyExtendPcr7|FALSE|BOOLEAN|0xE0000= 045 + + #If 0 BoardId detection is done using GPIO. Otherwise Board id will be f= orced to value set by this PCD + #Non zero value should match the values defined in PlatformInfoTypes.h + gPlatformTokenSpaceGuid.PcdBoardId|0|UINT8|0xE0000046 + + # BoardRevion Id value. Valid only if PcdBoardId is not equal to 0 + gPlatformTokenSpaceGuid.PcdBoardRevId|0|UINT8|0xE0000047 + +[PcdsFixedAtBuild, PcdsPatchableInModule] + gPlatformTokenSpaceGuid.PcdShellFile|{ 0xB7, 0xD6, 0x7A, 0xC5, 0x15, 0x0= 5, 0xA8, 0x40, 0x9D, 0x21, 0x55, 0x16, 0x52, 0x85, 0x4E, 0x37 }|VOID*|0x400= 00004 + ## Specify memory size with page number for a pre-allocated reserved mem= ory to be used + # by PEI in S3 phase. The default size 32K. When changing the value mak= e sure the memory size + # is large enough to meet PEI requirement in the S3 phase. + # @Prompt Reserved S3 Boot ACPI Memory Size + gPlatformModuleTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0x8000|UINT32|= 0x90010039 + gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012 + gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013 + gPlatformModuleTokenSpaceGuid.PcdPcIoApicCount|0|UINT8|0x90000015 + gPlatformModuleTokenSpaceGuid.PcdPcIoApicIdBase|0x09|UINT8|0x90000016 + gPlatformModuleTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000|UINT32|0= x90000017 + gPlatformModuleTokenSpaceGuid.PcdPcIoApicInterruptBase|24|UINT32|0x90000= 018 + + + gPlatformModuleTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0x900= 00025 + gPlatformModuleTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x900000= 26 + gPlatformModuleTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x90000027 + gPlatformModuleTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000|UINT32|0x90= 00000B + gPlatformModuleTokenSpaceGuid.PcdIoApicAddress|0xFEC00000|UINT32|0x90000= 00D + gPlatformModuleTokenSpaceGuid.PcdIoApicId|0x02|UINT8|0x90000014 + gPlatformModuleTokenSpaceGuid.PcdWsmtProtectionFlags|0|UINT32|0x10001006 + +[PcdsDynamicEx] + +# +# PAL +# + gPlatformTokenSpaceGuid.PcdOemSkuPcieSlotOpromBitMap|0xFF|UINT32|0x00000= 008 + +#SKX_TODO: gPlatformTokenSpaceGuid are not correct GUIDs to use here, use = local GUID... + gPlatformTokenSpaceGuid.PcdBootDeviceScratchPad5Changed|FALSE|BOOLEAN|0x= 00000048 + + ## This value is used to save memory address of MRC data structure. + gPlatformTokenSpaceGuid.PcdBoardTypeBitmask|0x00000000|UINT32|0x30000041 + gPlatformTokenSpaceGuid.PcdHalfWidth|FALSE|BOOLEAN|0x30000042 + +# +# IMR0 programming values +# + gPlatformTokenSpaceGuid.PcdImr0Enable|FALSE|BOOLEAN|0xA5000000 + gPlatformTokenSpaceGuid.PcdImr0Base|0x0|UINT64|0xA5000001 + gPlatformTokenSpaceGuid.PcdImr0Mask|0x0|UINT64|0xA5000002 + gPlatformTokenSpaceGuid.PcdImr0Rac|0xFFFFFFFFFFFFFFFF|UINT64|0xA5000003 + gPlatformTokenSpaceGuid.PcdImr0Wac|0xFFFFFFFFFFFFFFFF|UINT64|0xA5000004 + +# +# IMR3 programming values +# + gPlatformTokenSpaceGuid.PcdImr3Enable|FALSE|BOOLEAN|0xA5000022 + +# +# Server common Hot Key binding +# + # EFI Scan codes + # SCAN_F2 0x000C + # SCAN_F6 0x0010 + # SCAN_F7 0x0011 + gPlatformTokenSpaceGuid.PcdSetupMenuScanCode|0x00|UINT16|0x00000009 + gPlatformTokenSpaceGuid.PcdBootDeviceListScanCode|0x00|UINT16|0x0000000A + + + gPlatformTokenSpaceGuid.PcdBootMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee, 0xf2, = 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d }|VOID*|0x= 0000000B + +#Indicate whether to perform LT Config lock +# The PCD can be set to false when there is the debug request +# TRUE - Force the LT config lock +# FALSE - Allow the LT config unlock for debug + gPlatformModuleTokenSpaceGuid.PcdLtConfigLockEnable|TRUE|BOOLEAN|0x30000= 00e + +#Indicate whether LTSX enabled +# TRUE - Intel (R) TXT feature enabled on the platform +# FALSE - Disable Intel(R) TXT feature on the platform + gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable | TRUE|BOOLEAN|0x30= 00000f + + # + # SMBIOS Type 0 - BIOS Information + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosVendor|"TBD"|VOID*|0x5B00= 0000 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosVersion|"TBD"|VOID*|0x5B0= 00001 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosReleaseDate|"TBD"|VOID*|0= x5B000002 + + # + # SMBIOS Type 1 - System Information + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemManufacturer|"TBD"|VOID= *|0x5B010000 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemProductName|"TBD"|VOID*= |0x5B010001 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemVersion|"TBD"|VOID*|0x5= B010002 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemSerialNumber|"TBD"|VOID= *|0x5B010003 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemSkuNumber|"TBD"|VOID*|0= x5B010004 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemFamily|"TBD"|VOID*|0x5B= 010005 + + # + # SMBIOS Type 2 - Base Board (or Module) Information + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardManufacturer|"TBD"|V= OID*|0x5B020000 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardProductName|"TBD"|VO= ID*|0x5B020001 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardVersion|"TBD"|VOID*|= 0x5B020002 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardSerialNumber|"TBD"|V= OID*|0x5B020003 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardAssetTag|"TBD"|VOID*= |0x5B020004 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardLocationInChassis|"T= BD"|VOID*|0x5B020005 + + # + # SMBIOS Type 3 - System Enclosure or Chassis Information + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisManufacturer|"TBD"|VOI= D*|0x5B030000 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisVersion|"TBD"|VOID*|0x= 5B030001 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisSerialNumber|"TBD"|VOI= D*|0x5B030002 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisAssetTag|"TBD"|VOID*|0= x5B030003 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisSkuNumber|"TBD"|VOID*|= 0x5B030004 + + # + # SMBIOS Type 11 - OEM Strings + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesOemString1|"TBD"|VOID*|0x5B0B= 0001 + + # + # SMBIOS Type 12 - System Configuration Options + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSysConfigOption1|"TBD"|VOID*|= 0x5B0C0001 + + # + # SMBIOS Type 14 - Group Associations + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTableType|0xDD|UINT8|0x5B0D0001 + + # + # SMBIOS Type 17 - Memory Device + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesMemorySerialNumberFormat|0x00= |UINT8|0x5B110000 + + # + # SMBIOS Type 27 - Cooling Device + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesCoolingDeviceDescription|"TBD= "|VOID*|0x5B1B0000 + + # + # SMBIOS Type 28 - Temperature Probe + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesTemperatureProbeDescription|"= TBD"|VOID*|0x5B1C0000 + + # + # SMBIOS Type 34 - Management Device + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesManagementDeviceDescription|"= TBD"|VOID*|0x5B220000 + + # + # SMBIOS Type 35 - Management Device Component + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesManagementDeviceComponentDesc= ription|"TBD"|VOID*|0x5B230000 + + # + # SMBIOS Type 39 - System Power Supply + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyLocation|"TB= D"|VOID*|0x5B270000 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyDeviceName|"= TBD"|VOID*|0x5B270001 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyManufacturer= |"TBD"|VOID*|0x5B270002 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplySerialNumber= |"TBD"|VOID*|0x5B270003 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyAssetTagNumb= er|"TBD"|VOID*|0x5B270004 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyModelPartNum= ber|"TBD"|VOID*|0x5B270005 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyRevisionLeve= l|"TBD"|VOID*|0x5B270006 + +[PcdsFeatureFlag] + gPlatformTokenSpaceGuid.PcdSupportUnsignedCapsuleImage|TRUE|BOOLEAN|0x00= 000020 + + ## + ## High Speed UART + ## + gPlatformModuleTokenSpaceGuid.PcdEnableHighSpeedUart|FALSE|BOOLEAN|0x000= 0002C + + ## Platform Not support Acpi Table + # + gPlatformTokenSpaceGuid.PcdPlatformNotSupportAcpiTable|FALSE|BOOLEAN|0x4= 0000012 + gPlatformTokenSpaceGuid.PcdPlatformNotSupportAcpiBdatTable|FALSE|BOOLEAN= |0x40000013 + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx] + ## MemoryCheck value for checking memory before boot OS. + # To save the boot performance, the default MemoryCheck is set to 0. + gPlatformTokenSpaceGuid.PcdPlatformMemoryCheck|0|UINT8|0x40000005 + + + ## following PCDs should remove if CORE accept the fix + gPlatformTokenSpaceGuid.PcdPerfPkgPchPmBaseFunctionNumber|0x0|UINT32|4 + + ## Vendor ID and Device ID of device producing onboard video + gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId|0|UINT16|0x00000013 + gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId|0|UINT16|0x00000014 + gPlatformModuleTokenSpaceGuid.PcdPlatformMemoryCheckLevel|0|UINT32|0x300= 00009 + ## This PCD is to control which device is the potential trusted console = input device.

+ # For example:
+ # USB Short Form: UsbHID(0xFFFF,0xFFFF,0x1,0x1)
+ # //Header VendorId ProductId Class SubClass P= rotocol
+ # {0x03, 0x0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0= x01,
+ # //Header
+ # 0x7F, 0xFF, 0x04, 0x00}
+ gPlatformModuleTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{0x03, 0x= 0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0x01, 0x7F, 0xFF, 0x04,= 0x00}|VOID*|0x300000A + + ## This PCD is to control which device is the potential trusted console = output device.

+ # For example:
+ # Integrated Graphic: PciRoot(0x0)/Pci(0x2,0x0)
+ # //Header HID UID
+ # {0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00= , 0x00,
+ # //Header Func Dev
+ # 0x01, 0x01, 0x06, 0x00, 0x00, 0x02, + # //Header
+ # 0x7F, 0xFF, 0x04, 0x00}
+ gPlatformModuleTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{0x02, 0= x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01= , 0x06, 0x00, 0x00, 0x02, 0x7F, 0xFF, 0x04, 0x00}|VOID*|0x300000C + + + gPlatformModuleTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x1800|UINT16= |0x00010035 + gPlatformModuleTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0x0000|UINT16= |0x00010036 + gPlatformModuleTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x1804|UINT= 16|0x0001037 + gPlatformModuleTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0x0000|UINT= 16|0x00010038 + gPlatformModuleTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x1850|UINT1= 6|0x00010039 + gPlatformModuleTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x1808|UINT16|0= x0001003A + gPlatformModuleTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x1880|UINT16|0x00= 01003B + gPlatformModuleTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0x0000|UINT16|0x00= 01003C + +# +# UBA_START +# +[PcdsDynamicEx] + +# +#Board Definitions +# +#Integer for BoardID, must match the SKU number and be unique. + gOemSkuTokenSpaceGuid.PcdOemSkuBoardID|0x0|UINT16|0x00000000 +#Integer for BoardFamily, must be unique + gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily|0x0|UINT16|0x00000001 +# Zero terminated unicode string to ID family + gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName|L"DEFAULT = "|VOID*|0x0000002 +# Zero terminated unicode string to Board Name + gOemSkuTokenSpaceGuid.PcdOemSkuBoardName|L"DEFAULT = "|VOID*|0x00000003 +# Number of Sockets on Board. + gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount|0x0|UINT32|0x00000004 + +# Number of DIMM slots per channel for each Socket + gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel|0x0|UINT32|0x00000005 + gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel|0x0|UINT32|0x00000006 + gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout|FALSE|BOOLEAN|0x00000007 + gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID|0x0|UINT16|0x00000008 + + gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmSize|0x100|UINT32|0x00000009 +# Form factor is MemoryFormFactorDimm by default +# MemoryFormFactorOther =3D 0x01 +# MemoryFormFactorUnknown =3D 0x02 +# MemoryFormFactorSimm =3D 0x03 +# MemoryFormFactorSip =3D 0x04 +# MemoryFormFactorChip =3D 0x05 +# MemoryFormFactorDip =3D 0x06 +# MemoryFormFactorZip =3D 0x07 +# MemoryFormFactorProprietaryCard =3D 0x08 +# MemoryFormFactorDimm =3D 0x09 +# MemoryFormFactorTsop =3D 0x0A +# MemoryFormFactorRowOfChips =3D 0x0B +# MemoryFormFactorRimm =3D 0x0C +# MemoryFormFactorSodimm =3D 0x0D +# MemoryFormFactorSrimm =3D 0x0E +# MemoryFormFactorFbDimm =3D 0x0F +# MemoryFormFactorDie =3D 0x10 + gOemSkuTokenSpaceGuid.PcdOemSkuMemDevFormFactor|0x09|UINT8|0x10000010 + +# +# USB +# +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00|0x0|UINT16|0x000000= 10 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01|0x0|UINT16|0x000000= 11 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02|0x0|UINT16|0x000000= 12 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03|0x0|UINT16|0x000000= 13 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04|0x0|UINT16|0x000000= 14 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05|0x0|UINT16|0x000000= 15 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06|0x0|UINT16|0x000000= 16 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07|0x0|UINT16|0x000000= 17 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08|0x0|UINT16|0x000000= 18 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09|0x0|UINT16|0x000000= 19 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10|0x0|UINT16|0x000000= 1A +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11|0x0|UINT16|0x000000= 1B +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12|0x0|UINT16|0x000000= 1C +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13|0x0|UINT16|0x000000= 1D + +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00|0x0|UINT16|0x0000002= 0 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01|0x0|UINT16|0x0000002= 1 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02|0x0|UINT16|0x0000002= 2 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03|0x0|UINT16|0x0000002= 3 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04|0x0|UINT16|0x0000002= 4 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05|0x0|UINT16|0x0000002= 5 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06|0x0|UINT16|0x0000002= 6 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07|0x0|UINT16|0x0000002= 7 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08|0x0|UINT16|0x0000002= 8 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09|0x0|UINT16|0x0000002= 9 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10|0x0|UINT16|0x0000002= A +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11|0x0|UINT16|0x0000002= B +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12|0x0|UINT16|0x0000002= C +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13|0x0|UINT16|0x0000002= D + +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00|0x0|UINT16|0x00000= 100 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01|0x0|UINT16|0x00000= 101 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02|0x0|UINT16|0x00000= 102 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03|0x0|UINT16|0x00000= 103 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04|0x0|UINT16|0x00000= 104 +gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05|0x0|UINT16|0x00000= 105 + +# +# ACPI items +# +# Acpi Name, MUST be 8 chars long + gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName|"DEFAULT "|VOID*|0x000000= 30 + gOemSkuTokenSpaceGuid.PcdOemTableIdXhci|"DEFAULT "|VOID*|0x000000= 31 +# +# Misc. +# + + gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag|0x0|UINT8|0x00000039 + gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed|0x0|UINT16|0x00000040 + +# +# GPIO +# + + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL|0xFF3DB93D|UINT32|0x000= 00050 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL|0x0382F03F|UINT32|0x00= 000051 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL|0xFFFFF30F|UINT32|0x00= 000052 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL|0x91E3EFFF|UINT32|0x0000= 0053 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL|0xFFFD0FF3|UINT32|0x000= 00054 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL|0xFFFFFDF0|UINT32|0x000= 00055 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL|0x661C1000|UINT32|0x0000005= 6 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL|0x0002F004|UINT32|0x000000= 57 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL|0x0000020D|UINT32|0x000000= 58 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL|0x00000000|UINT32|0x0000005= 9 + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL|0x00000000|UINT32|0x00000= 05a + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE|0x00000000|UINT32|0x0000= 005c + +# +# SATA registers +# + + gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32|0x99990000|UINT32|0x0000005b + +# +# Clock generator settings +# + + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00|0xFF|UINT8|0x00000060 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01|0x9E|UINT8|0x00000061 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02|0x3F|UINT8|0x00000062 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03|0x00|UINT8|0x00000063 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04|0x00|UINT8|0x00000064 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05|0x0F|UINT8|0x00000065 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06|0x08|UINT8|0x00000066 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07|0x11|UINT8|0x00000067 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08|0x0A|UINT8|0x00000068 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09|0x17|UINT8|0x00000069 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10|0xFF|UINT8|0x0000006a + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11|0xFE|UINT8|0x0000006b + gOemSkuTokenSpaceGuid.PcdOemSkuClockGeneratorAddress|0xD2|UINT8|0x000000= 6c + + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName|L"DEFAULT = "|VOID*|0x00000201 + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize|0x0|UINT32|0x00000202 + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag|0x0|UINT32|0x00000203 + +# +# If PcdOemSkuAssertPostGPIO value is 0xFFFFFFFF, current platform don't s= et related GPIO. +# + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO|0x01010014|UINT32|0x000002= 04 + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue|0x0|UINT32|0x00000205 + + gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber|0xFF|UINT8|0x00000206 + gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex|0xFF|UINT8|0x00000207 +# +# UBA_END +# + + gCpPlatIpmiTokenSpaceGuid.PcdIpmiIoBaseAddress|0xCA2|UINT16|0x10000022 + gCpPlatIpmiTokenSpaceGuid.PcdIpmiSmmIoBaseAddress|0xCA4|UINT16|0x1000002= 3 + gCpPlatIpmiTokenSpaceGuid.PcdSioMailboxBaseAddress|0x600|UINT32|0x100000= 21 + gCpPlatIpmiTokenSpaceGuid.PcdFRB2EnabledFlag|TRUE|BOOLEAN|0x10000030 + gCpPlatIpmiTokenSpaceGuid.PcdIpmiBmcReadyDelayTimer|0|UINT8|0x00000208 + + +## This PCD replaces the original one gEfiIntelFrameworkModulePkgTokenSpac= eGuid.PcdBootState + gPlatformModuleTokenSpaceGuid.PcdBootState|TRUE|BOOLEAN|0x300000AC + gOemSkuTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x00000208 + +[PcdsDynamicEx] + gCpPlatTokenSpaceGuid.PcdUefiOptimizedBoot|FALSE|BOOLEAN|0x10000026 + gCpPlatTokenSpaceGuid.PcdUefiOptimizedBootEx|FALSE|BOOLEAN|0x10000024 + +[PcdsFixedAtBuild] +# +# Flash map related PCD. +# +# Note: most values here are overridden in the .fdf file +# +# +# Note: FlashNv PCD naming conventions are as follows: +# +# PcdFlash*Base is an address, usually in the range of 0xf* of FD's,= note change in FDF spec +# PcdFlash*Size is a hex count of the length of the FD or FV +# All Fv will have the form 'PcdFlashFv', and all Fd will have the f= orm 'PcdFlashFd' +# +# Also all values will have a PCD assigned so that they can be used = in the system, and +# the FlashMap edit tool can be used to change the values here, with= out effecting the code. +# This requires all code to only use the PCD tokens to recover the v= alues. +# + + + +# PCD's that are for the whole SPI part + + +#Block size of SPI +gCpPlatFlashTokenSpaceGuid.PcdFlashBlockSize |0x00010= 000 |UINT32|0x50000102 + + +#AJW rename this to be more in keeping with the function +gCpPlatFlashTokenSpaceGuid.PcdFlashAreaBase |0xfff00= 000 |UINT32|0x50000105 + + + +# for PeiSec FD + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize |0x00100= 000 |UINT32|0x50000221 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase |0x00000= 000 |UINT32|0x50000222 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase |0x00000= 000 |UINT32|0x50000260 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize |0x00040= 000 |UINT32|0x50000261 + +gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase |0x00000= 000 |UINT32|0x50000211 +gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize |0x00100= 000 |UINT32|0x50000212 + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize |0x001000= 00 |UINT32|0x50000233 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase |0x000000= 00 |UINT32|0x50000234 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset |0x000000= 00 |UINT32|0x50000235 + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize |0x00100= 000 |UINT32|0x50000241 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase |0x00000= 000 |UINT32|0x50000242 + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize |0x00100= 000 |UINT32|0x50000251 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase |0x00000= 000 |UINT32|0x50000252 + + +# for Main FD + + +gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase |0xfff0= 0000 |UINT32|0x50000300 +gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize |0x0040= 0000 |UINT32|0x50000301 + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvMainSize |0x0020= 0000 |UINT32|0x50000311 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvMainBase |0xFF82= 0000 |UINT32|0x50000312 + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize |0x0020= 0000 |UINT32|0x50000341 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase |0xFF82= 0000 |UINT32|0x50000342 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset |0xFF82= 0000 |UINT32|0x50000343 + + +gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize |0x0020= 0000 |UINT32|0x50000351 +gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase |0xFF82= 0000 |UINT32|0x50000352 + +## This PCD specifies the size of the physical device containing the BIOS,= SMBIOS will use it. + +gCpPlatFlashTokenSpaceGuid.PcdFlashBackupRegionBase |0xFF80= 0000 |UINT32|0x50000001 +gCpPlatFlashTokenSpaceGuid.PcdFlashBackupRegionSize |0x0000= 0000 |UINT32|0x50000002 + +[PcdsFeatureFlag.common] + +## +## Those PCDs are used to control build process. +## + + # + # SV Tools + # + gPlatformFeatureTokenSpaceGuid.PcdXmlCliEnable|TRUE|BOOLEAN|0xE0000000 + gPlatformFeatureTokenSpaceGuid.PcdSvBiosEnable|TRUE|BOOLEAN|0xE000002E + # + # + # + +[PcdsDynamicEx] + ### Sample implementation...No real data. Use this PCD to override a pla= tform with Interposer ### + gPlatformTokenSpaceGuid.PcdMemInterposerMap|{0}|INTERPOSER_MAP|0x8000001= 5 { + + Guid/PlatformInfo.h + + WhitleyOpenBoardPkg/PlatformPkg.dec + } + # Interposer A MC 0 mapped to original MC1 + # Enum values for Interposer + # Interposer A =3D> 1 + # Interposer B =3D> 2 + # Interposer Unknown =3D> 0 + gPlatformTokenSpaceGuid.PcdMemInterposerMap.Interposer[1].MappedMcId[0] = |1 + +### Sample implementation...No real data. Use this PCD to override a platf= orm with Interposer ### + +[Guids] + gStructPcdTokenSpaceGuid =3D {0x3f1406f4, 0x2b, 0x487a, {0x8b, 0x69, 0x7= 4, 0x29, 0x1b, 0x36, 0x16, 0xf4}} + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx] +gStructPcdTokenSpaceGuid.PcdEmulationDfxConfig|{0}|EMULATION_DFX_CONFIGURA= TION|0XFCD0000C{ + + Include/Guid/EmulationDfxVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec +} +gStructPcdTokenSpaceGuid.PcdFpgaSocketConfig|{0}|FPGA_SOCKET_CONFIGURATION= |0XFCD00010{ + + Include/Guid/FpgaSocketVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec +} +gStructPcdTokenSpaceGuid.PcdIeRcConfiguration|{0}|IE_RC_CONFIGURATION|0XFC= D00004{ + + Include/Guid/IeRcVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdMeRcConfiguration|{0}|ME_RC_CONFIGURATION|0XFC= D0000B{ + + Include/Guid/MeRcVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdMemBootHealthConfig|{0}|MEM_BOOT_HEALTH_CONFIG= |0XFCD00002{ + + Include/Guid/MemBootHealthGuid.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdPchSetup|{0}|PCH_SETUP|0XFCD00007{ + + Include/PchSetupVariableLbg.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSetup|{0}|SYSTEM_CONFIGURATION|0XFCD0000F{ + + Include/Guid/SetupVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig|{0}|SOCKET_COMMONRC_CONFI= GURATION|0XFCD00001{ + + Include/Guid/SocketCommonRcVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSocketIioConfig|{0}|SOCKET_IIO_CONFIGURATION|0= XFCD00006{ + + Include/Guid/SocketIioVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig|{0}|SOCKET_MEMORY_CONFIGURA= TION|0XFCD0000D{ + + Include/Guid/SocketMemoryVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig|{0}|SOCKET_MP_LINK_CONFIGUR= ATION|0XFCD00008{ + + Include/Guid/SocketMpLinkVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSocketPowerManagementConfig|{0}|SOCKET_POWERMA= NAGEMENT_CONFIGURATION|0XFCD00005{ + + Include/Guid/SocketPowermanagementVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSocketProcessorCoreConfig|{0}|SOCKET_PROCESSOR= CORE_CONFIGURATION|0XFCD00003{ + + Include/Guid/SocketProcessorCoreVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdSvConfiguration|{0}|SV_CONFIGURATION|0XFCD0000= 9{ + + Include/Guid/SetupVariable.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec +} +gStructPcdTokenSpaceGuid.PcdTCG2_CONFIGURATION|{0}|TCG2_CONFIGURATION|0XFC= D0000A{ + + Include/Tcg2ConfigNvData.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + SecurityPkg/SecurityPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec +} +gStructPcdTokenSpaceGuid.PcdTCG2_VERSION|{0}|TCG2_VERSION|0XFCD0000E{ + + Include/Tcg2ConfigNvData.h + + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + SecurityPkg/SecurityPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec +} +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx] + gOemSkuTokenSpaceGuid.PcdTurboPowerLimitLock|0x01|UINT8|0x00000209 + gOemSkuTokenSpaceGuid.PcdNumberOfCoresToDisable|0x0|UINT16|0x0000020A + +[LibraryClasses] + ServerManagementTimeStampLib|Include/Library/ServerManagementTimeStampLi= b.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInit= Dxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c index 6cfa43a59d..cb87ddfbc5 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c @@ -1,108 +1,118 @@ -/** @file - BOARD INIT DXE Driver. - - @copyright - Copyright 2014 - 2021 Intel Corporation. - Copyright (c) 2021, American Megatrends International LLC.
- - SPDX-License-Identifier: BSD-2-Clause-Patent -**/ - -#include "BoardInitDxe.h" -#include - -/** - The Driver Entry Point. - - The function is the driver Entry point. - - @param ImageHandle A handle for the image that is initializing this dr= iver - @param SystemTable A pointer to the EFI system table - - @retval EFI_SUCCESS: Driver initialized successfully - @retval EFI_LOAD_ERROR: Failed to Initialize or has been loade= d - @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources - -**/ -EFI_STATUS -EFIAPI -BoardInitDxeDriverEntry ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable -) -{ - EFI_STATUS Status =3D EFI_SUCCESS; - UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; - UINT32 PlatformType =3D 0; - EFI_HANDLE Handle =3D NULL; - - Status =3D gBS->LocateProtocol ( - &gUbaConfigDatabaseProtocolGuid, - NULL, - &UbaConfigProtocol - ); - if (EFI_ERROR(Status)) { - return Status; - } - - Status =3D UbaConfigProtocol->GetSku( - UbaConfigProtocol, - &PlatformType, - NULL, - NULL - ); - ASSERT_EFI_ERROR (Status); - - DEBUG ((DEBUG_INFO, "Uba init Dxe driver:PlatformType=3D%d\n", PlatformT= ype)); - - //according to the platform type to install different dummy maker. - //later, the PEIM will be loaded by the dependency. - switch(PlatformType) - { - case TypeWilsonCityRP: - Status =3D gBS->InstallProtocolInterface ( - &Handle, - &gEfiPlatformTypeWilsonCityRPProtocolGuid, - EFI_NATIVE_INTERFACE, - NULL - ); - ASSERT_EFI_ERROR (Status); - break; - - case TypeWilsonCitySMT: - Status =3D gBS->InstallProtocolInterface( - &Handle, - &gEfiPlatformTypeWilsonCitySMTProtocolGuid, - EFI_NATIVE_INTERFACE, - NULL - ); - ASSERT_EFI_ERROR(Status); - break; - - case TypeCooperCityRP: - Status =3D gBS->InstallProtocolInterface ( - &Handle, - &gEfiPlatformTypeCooperCityRPProtocolGuid, - EFI_NATIVE_INTERFACE, - NULL - ); - ASSERT_EFI_ERROR (Status); - break; - - case TypeJunctionCity: - Status =3D gBS->InstallProtocolInterface ( - &Handle, - &gEfiPlatformTypeJunctionCityProtocolGuid, - EFI_NATIVE_INTERFACE, - NULL - ); - ASSERT_EFI_ERROR (Status); - break; - - default: - // CAN'T GO TO HERE. - ASSERT (FALSE); - } - - return Status; -} +/** @file + BOARD INIT DXE Driver. + + @copyright + Copyright 2014 - 2021 Intel Corporation. + Copyright (c) 2021 - 2022, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BoardInitDxe.h" +#include + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loade= d + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +BoardInitDxeDriverEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + UINT32 PlatformType =3D 0; + EFI_HANDLE Handle =3D NULL; + + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->GetSku( + UbaConfigProtocol, + &PlatformType, + NULL, + NULL + ); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "Uba init Dxe driver:PlatformType=3D%d\n", PlatformT= ype)); + + //according to the platform type to install different dummy maker. + //later, the PEIM will be loaded by the dependency. + switch(PlatformType) + { + case TypeWilsonCityRP: + Status =3D gBS->InstallProtocolInterface ( + &Handle, + &gEfiPlatformTypeWilsonCityRPProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + ASSERT_EFI_ERROR (Status); + break; + + case TypeWilsonCitySMT: + Status =3D gBS->InstallProtocolInterface( + &Handle, + &gEfiPlatformTypeWilsonCitySMTProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + ASSERT_EFI_ERROR(Status); + break; + + case TypeCooperCityRP: + Status =3D gBS->InstallProtocolInterface ( + &Handle, + &gEfiPlatformTypeCooperCityRPProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + ASSERT_EFI_ERROR (Status); + break; + + case TypeJunctionCity: + Status =3D gBS->InstallProtocolInterface ( + &Handle, + &gEfiPlatformTypeJunctionCityProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + ASSERT_EFI_ERROR (Status); + break; + + case TypeAowanda: + Status =3D gBS->InstallProtocolInterface ( + &Handle, + &gEfiPlatformTypeAowandaProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + ASSERT_EFI_ERROR (Status); + break; + + default: + // CAN'T GO TO HERE. + ASSERT (FALSE); + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInit= Dxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe= .inf index 8948ab1f0a..ef47d1b1b8 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf @@ -1,72 +1,73 @@ -## @file -# Uba init for multi-boards support in DXE phase. -# -# @copyright -# Copyright 2014 - 2021 Intel Corporation. -# Copyright (c) 2021, American Megatrends International LLC.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -## - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D BoardInitDxe - FILE_GUID =3D 69E6DD6D-F09E-485f-9627-EB70E9CFC82A - MODULE_TYPE =3D DXE_DRIVER - VERSION_STRING =3D 1.0 - - ENTRY_POINT =3D BoardInitDxeDriverEntry - -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D IA32 -# - -[Sources] - BoardInitDxe.c - BoardInitDxe.h - -[Packages] - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - - -[LibraryClasses] - DebugLib - IoLib - HobLib - UefiLib - BaseLib - BaseMemoryLib - MemoryAllocationLib - DebugLib - UefiBootServicesTableLib - UefiRuntimeServicesTableLib - UefiDriverEntryPoint - PrintLib - -[Guids] - -[Protocols] - gUbaConfigDatabaseProtocolGuid #CONSUMER - gEfiPlatformTypeNeonCityEPRPProtocolGuid #PRODUCER - gEfiPlatformTypeHedtCRBProtocolGuid #PRODUCER - gEfiPlatformTypeLightningRidgeEXRPProtocolGuid #PRODUCER - gEfiPlatformTypeLightningRidgeEX8S1NProtocolGuid #PRODUCER - gEfiPlatformTypeWilsonCityRPProtocolGuid #PRODUCER - gEfiPlatformTypeWilsonCityModularProtocolGuid #PRODUCER - gEfiPlatformTypeIsoscelesPeakProtocolGuid #PRODUCER - gEfiPlatformTypeWilsonCitySMTProtocolGuid #PRODUCER - gEfiPlatformTypeCooperCityRPProtocolGuid #PRODUCER - gEfiPlatformTypeJunctionCityProtocolGuid #PRODUCER - -[FixedPcd] - gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount - -[Depex] - gUbaConfigDatabaseProtocolGuid +## @file +# Uba init for multi-boards support in DXE phase. +# +# @copyright +# Copyright 2014 - 2021 Intel Corporation. +# Copyright (c) 2021 - 2022, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BoardInitDxe + FILE_GUID =3D 69E6DD6D-F09E-485f-9627-EB70E9CFC82A + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D BoardInitDxeDriverEntry + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 +# + +[Sources] + BoardInitDxe.c + BoardInitDxe.h + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + + +[LibraryClasses] + DebugLib + IoLib + HobLib + UefiLib + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + UefiDriverEntryPoint + PrintLib + +[Guids] + +[Protocols] + gUbaConfigDatabaseProtocolGuid #CONSUMER + gEfiPlatformTypeNeonCityEPRPProtocolGuid #PRODUCER + gEfiPlatformTypeHedtCRBProtocolGuid #PRODUCER + gEfiPlatformTypeLightningRidgeEXRPProtocolGuid #PRODUCER + gEfiPlatformTypeLightningRidgeEX8S1NProtocolGuid #PRODUCER + gEfiPlatformTypeWilsonCityRPProtocolGuid #PRODUCER + gEfiPlatformTypeWilsonCityModularProtocolGuid #PRODUCER + gEfiPlatformTypeIsoscelesPeakProtocolGuid #PRODUCER + gEfiPlatformTypeWilsonCitySMTProtocolGuid #PRODUCER + gEfiPlatformTypeCooperCityRPProtocolGuid #PRODUCER + gEfiPlatformTypeJunctionCityProtocolGuid #PRODUCER + gEfiPlatformTypeAowandaProtocolGuid #PRODUCER + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Depex] + gUbaConfigDatabaseProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDx= e/StaticSkuDataDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/Sta= ticSkuDataDxe/StaticSkuDataDxe.inf index 97a1931c84..74b64bca8b 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/Stati= cSkuDataDxe.inf +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/Stati= cSkuDataDxe.inf @@ -1,59 +1,61 @@ -## @file -# Static Board Data DXE Driver. -# -# @copyright -# Copyright 2018 - 2022 Intel Corporation.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -## - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D StaticSkuDataDxeBaseline - FILE_GUID =3D 2C03C058-4305-7829-7E84-C7B3D6232F42 - MODULE_TYPE =3D DXE_DRIVER - VERSION_STRING =3D 1.0 - - ENTRY_POINT =3D StaticSkuConfigDataDxeEntry - -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D x64 -# - -[Sources] - StaticSkuDataDxe.c - StaticSkuDataDxe.h - DeviceDataInstall.c - PlatformDeviceDataSRP10nm.c - AcpiStaticData.c - -[Packages] - MdePkg/MdePkg.dec - MdeModulePkg/MdeModulePkg.dec - WhitleySiliconPkg/SiliconPkg.dec - WhitleySiliconPkg/CpRcPkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - -[LibraryClasses] - BaseLib - BaseMemoryLib - MemoryAllocationLib - UefiBootServicesTableLib - UefiDriverEntryPoint - UefiLib - DebugLib - IoLib - HobLib - -[Guids] - gEfiPlatformInfoGuid - -[Protocols] - gUbaConfigDatabaseProtocolGuid - -[Depex] - gEfiPlatformTypeWilsonCitySMTProtocolGuid OR - gEfiPlatformTypeWilsonCityRPProtocolGuid OR - gEfiPlatformTypeJunctionCityProtocolGuid +## @file +# Static Board Data DXE Driver. +# +# @copyright +# Copyright 2018 - 2022 Intel Corporation.
+# Copyright (c) 2022, American Megatrends International LLC.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D StaticSkuDataDxeBaseline + FILE_GUID =3D 2C03C058-4305-7829-7E84-C7B3D6232F42 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D StaticSkuConfigDataDxeEntry + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D x64 +# + +[Sources] + StaticSkuDataDxe.c + StaticSkuDataDxe.h + DeviceDataInstall.c + PlatformDeviceDataSRP10nm.c + AcpiStaticData.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + DebugLib + IoLib + HobLib + +[Guids] + gEfiPlatformInfoGuid + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gEfiPlatformTypeWilsonCitySMTProtocolGuid OR + gEfiPlatformTypeWilsonCityRPProtocolGuid OR + gEfiPlatformTypeJunctionCityProtocolGuid OR + gEfiPlatformTypeAowandaProtocolGuid diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg index de656633cd..037f7fabde 100644 --- a/Platform/Intel/build.cfg +++ b/Platform/Intel/build.cfg @@ -1,70 +1,71 @@ -# @ build.cfg -# This is the main/default build configuration file -# -# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
-# Copyright (c) 2021, American Megatrends International LLC.
-# SPDX-License-Identifier: BSD-2-Clause-Patent -# - - -[DEFAULT_CONFIG] -WORKSPACE =3D -WORKSPACE_FSP_BIN =3D FSP -EDK_TOOLS_BIN =3D edk2-BaseTools-win32 -EDK_BASETOOLS =3D BaseTools -WORKSPACE_DRIVERS =3D edk2-platforms/Drivers -WORKSPACE_FEATURES =3D edk2-platforms/Features/Intel -WORKSPACE_PLATFORM =3D edk2-platforms/Platform/Intel -WORKSPACE_SILICON =3D edk2-platforms/Silicon/Intel -WORKSPACE_PLATFORM_BIN =3D -WORKSPACE_SILICON_BIN =3D edk2-non-osi/Silicon/Intel -MIN_PACKAGE_TOOLS =3D edk2-platforms/Platform/Intel/MinPlatformPkg/Tools -PACKAGES_PATH =3D -EDK_SETUP_OPTION =3D -BASE_TOOLS_PATH =3D edk2/BaseTools -EDK_TOOLS_PATH =3D edk2/BaseTools -openssl_path =3D -PLATFORM_BOARD_PACKAGE =3D -BIOS_SIZE_OPTION =3D -DBIOS_SIZE_OPTION=3DSIZE_70 -WORKSPACE_CORE =3D edk2 -EFI_SOURCE =3D edk2 -PATHEXT =3D .COM;.EXE;.BAT;.CMD;.VBS;.JS;.WS;.MSC -PROMPT =3D $P$G -PLATFORM_PACKAGE =3D MinPlatformPkg -BOARD =3D -PrepRELEASE =3D DEBUG -SILENT_MODE =3D FALSE -EXT_CONFIG_CLEAR =3D -CapsuleBuild =3D FALSE -EXT_BUILD_FLAGS =3D -CAPSULE_BUILD =3D 0 -TARGET =3D DEBUG -TARGET_SHORT =3D D -PERFORMANCE_BUILD =3D FALSE -FSP_WRAPPER_BUILD =3D FALSE -FSP_BIN_PKG =3D -FSP_PKG_NAME =3D -FSP_BINARY_BUILD =3D FALSE -FSP_TEST_RELEASE =3D FALSE -SECURE_BOOT_ENABLE =3D FALSE -REBUILD_MODE =3D -BUILD_ROM_ONLY =3D -NUMBER_OF_PROCESSORS =3D 0 -BIOS_INFO_GUID =3D - - -[PLATFORMS] -# board_name =3D path_to_board_build_config.cfg -BoardMtOlympus =3D PurleyOpenBoardPkg/BoardMtOlympus/build_config.cfg -BoardX58Ich10 =3D SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg -AspireVn7Dash572G =3D KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.= cfg -GalagoPro3 =3D KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg -KabylakeRvp3 =3D KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg -UpXtreme =3D WhiskeylakeOpenBoardPkg/UpXtreme/build_config.cfg -WhiskeylakeURvp =3D WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.c= fg -CometlakeURvp =3D CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg -TigerlakeURvp =3D TigerlakeOpenBoardPkg/TigerlakeURvp/build_config.cfg -CooperCityRvp =3D WhitleyOpenBoardPkg/CooperCityRvp/build_config.cfg -WilsonCityRvp =3D WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg -BoardTiogaPass =3D PurleyOpenBoardPkg/BoardTiogaPass/build_config.cfg -JunctionCity =3D WhitleyOpenBoardPkg/JunctionCity/build_config.cfg +# @ build.cfg +# This is the main/default build configuration file +# +# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2021 - 2022, American Megatrends International LLC.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + + +[DEFAULT_CONFIG] +WORKSPACE =3D +WORKSPACE_FSP_BIN =3D FSP +EDK_TOOLS_BIN =3D edk2-BaseTools-win32 +EDK_BASETOOLS =3D BaseTools +WORKSPACE_DRIVERS =3D edk2-platforms/Drivers +WORKSPACE_FEATURES =3D edk2-platforms/Features/Intel +WORKSPACE_PLATFORM =3D edk2-platforms/Platform/Intel +WORKSPACE_SILICON =3D edk2-platforms/Silicon/Intel +WORKSPACE_PLATFORM_BIN =3D +WORKSPACE_SILICON_BIN =3D edk2-non-osi/Silicon/Intel +MIN_PACKAGE_TOOLS =3D edk2-platforms/Platform/Intel/MinPlatformPkg/Tools +PACKAGES_PATH =3D +EDK_SETUP_OPTION =3D +BASE_TOOLS_PATH =3D edk2/BaseTools +EDK_TOOLS_PATH =3D edk2/BaseTools +openssl_path =3D +PLATFORM_BOARD_PACKAGE =3D +BIOS_SIZE_OPTION =3D -DBIOS_SIZE_OPTION=3DSIZE_70 +WORKSPACE_CORE =3D edk2 +EFI_SOURCE =3D edk2 +PATHEXT =3D .COM;.EXE;.BAT;.CMD;.VBS;.JS;.WS;.MSC +PROMPT =3D $P$G +PLATFORM_PACKAGE =3D MinPlatformPkg +BOARD =3D +PrepRELEASE =3D DEBUG +SILENT_MODE =3D FALSE +EXT_CONFIG_CLEAR =3D +CapsuleBuild =3D FALSE +EXT_BUILD_FLAGS =3D +CAPSULE_BUILD =3D 0 +TARGET =3D DEBUG +TARGET_SHORT =3D D +PERFORMANCE_BUILD =3D FALSE +FSP_WRAPPER_BUILD =3D FALSE +FSP_BIN_PKG =3D +FSP_PKG_NAME =3D +FSP_BINARY_BUILD =3D FALSE +FSP_TEST_RELEASE =3D FALSE +SECURE_BOOT_ENABLE =3D FALSE +REBUILD_MODE =3D +BUILD_ROM_ONLY =3D +NUMBER_OF_PROCESSORS =3D 0 +BIOS_INFO_GUID =3D + + +[PLATFORMS] +# board_name =3D path_to_board_build_config.cfg +BoardMtOlympus =3D PurleyOpenBoardPkg/BoardMtOlympus/build_config.cfg +BoardX58Ich10 =3D SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg +AspireVn7Dash572G =3D KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.= cfg +GalagoPro3 =3D KabylakeOpenBoardPkg/GalagoPro3/build_config.cfg +KabylakeRvp3 =3D KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg +UpXtreme =3D WhiskeylakeOpenBoardPkg/UpXtreme/build_config.cfg +WhiskeylakeURvp =3D WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.c= fg +CometlakeURvp =3D CometlakeOpenBoardPkg/CometlakeURvp/build_config.cfg +TigerlakeURvp =3D TigerlakeOpenBoardPkg/TigerlakeURvp/build_config.cfg +CooperCityRvp =3D WhitleyOpenBoardPkg/CooperCityRvp/build_config.cfg +WilsonCityRvp =3D WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg +BoardTiogaPass =3D PurleyOpenBoardPkg/BoardTiogaPass/build_config.cfg +JunctionCity =3D WhitleyOpenBoardPkg/JunctionCity/build_config.cfg +Aowanda =3D WhitleyOpenBoardPkg/Aowanda/build_config.cfg diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h b/= Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h index bfc6a49138..76bd9dd293 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h @@ -1,114 +1,115 @@ -/** @file - - @copyright - Copyright 2020 - 2021 Intel Corporation.
- Copyright (c) 2021, American Megatrends International LLC.
- - SPDX-License-Identifier: BSD-2-Clause-Patent -**/ - -#ifndef _PLATFORM_INFO_TYPES_H_ -#define _PLATFORM_INFO_TYPES_H_ - -// -// DIMM Connector type -// -typedef enum { - DimmConnectorPth =3D 0x00, // Through hole connector - DimmConnectorSmt, // Surface mount connector - DimmConnectorMemoryDown, // Platform soldered DRAMs - DimmConnectorIgnore, // Ignore connector type - DimmConnectorMax -} EFI_MEMORY_DIMM_CONNECTOR_TYPE; - -// -// Platform types - used with EFI_PLATFORM_INFO BoardId -// -typedef enum { - StartOfEfiPlatformTypeEnum =3D 0x00, - //For PPO - TypeNeonCityEPRP, - TypeWolfPass, - TypeTennesseePass, - TypeHedtCRB, - TypeLightningRidgeEXRP, - TypeLightningRidgeEX8S1N, - TypeBarkPeak, - TypeYubaCityRP, - TypeRidgeport, - //End PPO - TypeWilsonCityRP, - TypeWilsonCityModular, - TypeCoyotePass, - TypeIdaville, - TypeMoroCityRP, - TypeBrightonCityRp, - TypeJacobsville, - TypeSnrSvp, - TypeSnrSvpSodimm, - TypeJacobsvilleMDV, - TypeFrostCreekRP, - TypeVictoriaCanyonRP, - TypeArcherCityRP, - TypeNeonCityEPECB, - TypeIsoscelesPeak, - TypeWilsonPointRP, - TypeWilsonPointModular, - TypeBretonSound, - TypeWilsonCityPPV, - TypeCooperCityRP, - TypeWilsonCitySMT, - TypeSnrSvpSodimmB, - TypeArcherCityModular, - TypeArcherCityEVB, - TypeArcherCityXPV, - TypeBigPineKey, - TypeExperWorkStationRP, - TypeJunctionCity, - EndOfEfiPlatformTypeEnum, - // - // Vendor board range currently starts at 0x80 - // - TypeBoardPortTemplate // 0x80 -} EFI_PLATFORM_TYPE; - -#define TypePlatformUnknown 0xFF -#define TypePlatformMin StartOfEfiPlatformTypeEnum + 1 -#define TypePlatformMax EndOfEfiPlatformTypeEnum - 1 -#define TypePlatformDefault TypeWilsonPointRP -#define TypePlatformVendorMin 0x80 -#define TypePlatformVendorMax TypeBoardPortTemplate - 1 - -// -// CPU type: Standard (no MCP), -F, etc -// -typedef enum { - CPU_TYPE_STD, - CPU_TYPE_F, - CPU_TYPE_P, - CPU_TYPE_MAX -} CPU_TYPE; - -#define CPU_TYPE_STD_MASK (1 << CPU_TYPE_STD) -#define CPU_TYPE_F_MASK (1 << CPU_TYPE_F) -#define CPU_TYPE_P_MASK (1 << CPU_TYPE_P) - -typedef enum { - DaisyChainTopology =3D 0x00, - InvSlotsDaisyChainTopology, - TTopology -} EFI_MEMORY_TOPOLOGY_TYPE; - -// -// Values for SocketConfig -// - -#define SOCKET_UNDEFINED 0 -#define SOCKET_4S 1 -#define SOCKET_HEDT 2 -#define SOCKET_1S 3 -#define SOCKET_1SWS 4 -#define SOCKET_8S 5 -#define SOCKET_2S 6 - -#endif // #ifndef _PLATFORM_INFO_TYPES_H_ +/** @file + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ Copyright (c) 2021 - 2022, American Megatrends International LLC.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_INFO_TYPES_H_ +#define _PLATFORM_INFO_TYPES_H_ + +// +// DIMM Connector type +// +typedef enum { + DimmConnectorPth =3D 0x00, // Through hole connector + DimmConnectorSmt, // Surface mount connector + DimmConnectorMemoryDown, // Platform soldered DRAMs + DimmConnectorIgnore, // Ignore connector type + DimmConnectorMax +} EFI_MEMORY_DIMM_CONNECTOR_TYPE; + +// +// Platform types - used with EFI_PLATFORM_INFO BoardId +// +typedef enum { + StartOfEfiPlatformTypeEnum =3D 0x00, + //For PPO + TypeNeonCityEPRP, + TypeWolfPass, + TypeTennesseePass, + TypeHedtCRB, + TypeLightningRidgeEXRP, + TypeLightningRidgeEX8S1N, + TypeBarkPeak, + TypeYubaCityRP, + TypeRidgeport, + //End PPO + TypeWilsonCityRP, + TypeWilsonCityModular, + TypeCoyotePass, + TypeIdaville, + TypeMoroCityRP, + TypeBrightonCityRp, + TypeJacobsville, + TypeSnrSvp, + TypeSnrSvpSodimm, + TypeJacobsvilleMDV, + TypeFrostCreekRP, + TypeVictoriaCanyonRP, + TypeArcherCityRP, + TypeNeonCityEPECB, + TypeIsoscelesPeak, + TypeWilsonPointRP, + TypeWilsonPointModular, + TypeBretonSound, + TypeWilsonCityPPV, + TypeCooperCityRP, + TypeWilsonCitySMT, + TypeSnrSvpSodimmB, + TypeArcherCityModular, + TypeArcherCityEVB, + TypeArcherCityXPV, + TypeBigPineKey, + TypeExperWorkStationRP, + TypeJunctionCity, + TypeAowanda, + EndOfEfiPlatformTypeEnum, + // + // Vendor board range currently starts at 0x80 + // + TypeBoardPortTemplate // 0x80 +} EFI_PLATFORM_TYPE; + +#define TypePlatformUnknown 0xFF +#define TypePlatformMin StartOfEfiPlatformTypeEnum + 1 +#define TypePlatformMax EndOfEfiPlatformTypeEnum - 1 +#define TypePlatformDefault TypeWilsonPointRP +#define TypePlatformVendorMin 0x80 +#define TypePlatformVendorMax TypeBoardPortTemplate - 1 + +// +// CPU type: Standard (no MCP), -F, etc +// +typedef enum { + CPU_TYPE_STD, + CPU_TYPE_F, + CPU_TYPE_P, + CPU_TYPE_MAX +} CPU_TYPE; + +#define CPU_TYPE_STD_MASK (1 << CPU_TYPE_STD) +#define CPU_TYPE_F_MASK (1 << CPU_TYPE_F) +#define CPU_TYPE_P_MASK (1 << CPU_TYPE_P) + +typedef enum { + DaisyChainTopology =3D 0x00, + InvSlotsDaisyChainTopology, + TTopology +} EFI_MEMORY_TOPOLOGY_TYPE; + +// +// Values for SocketConfig +// + +#define SOCKET_UNDEFINED 0 +#define SOCKET_4S 1 +#define SOCKET_HEDT 2 +#define SOCKET_1S 3 +#define SOCKET_1SWS 4 +#define SOCKET_8S 5 +#define SOCKET_2S 6 + +#endif // #ifndef _PLATFORM_INFO_TYPES_H_ --=20 2.31.0.windows.1 Please consider the environment before printing this email. The information contained in this message may be confidential and proprieta= ry to American Megatrends (AMI). This communication is intended to be read= only by the individual or entity to whom it is addressed or by their desig= nee. If the reader of this message is not the intended recipient, you are o= n notice that any distribution of this message, in any form, is strictly pr= ohibited. Please promptly notify the sender by reply e-mail or by telephon= e at 770-246-8600, and then delete or destroy all copies of the transmissio= n.