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charset="us-ascii" Content-Transfer-Encoding: quoted-printable It seems like: UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf Are not S3 specific and belong with common stage 4 or 5 content. It seems = many features could require them. DSC can deal with duplicates, but FDF wo= uld fail if there were collisions. S3Feature.dsc - Remove commented out code Regards, Isaac -----Original Message----- From: Benjamin Doron =20 Sent: Tuesday, September 6, 2022 10:02 AM To: devel@edk2.groups.io Cc: Desimone, Nathaniel L ; Sinha, Ankit ; Chaganty, Rangasai V = ; Oram, Isaac W ; Gao, Liming Subject: [edk2-devel][edk2-platforms][PATCH v2 4/6] S3FeaturePkg: Implement= working S3 resume Follow-up commits to MinPlatform (PeiFspWrapperHobProcessLib for memory) and FSP-related board libraries (policy overrides) required for suc= cessful S3 resume. Factored allocation logic into new module to avoid MinPlatform dependency o= n S3Feature package. TODO: Can optimise required size. Cc: Nate DeSimone Cc: Ankit Sinha Cc: Sai Chaganty Cc: Isaac Oram Cc: Liming Gao Signed-off-by: Benjamin Doron --- .../S3FeaturePkg/Include/PostMemory.fdf | 13 ++ .../S3FeaturePkg/Include/PreMemory.fdf | 8 +- .../S3FeaturePkg/Include/S3Feature.dsc | 38 ++++- .../S3FeaturePkg/S3Dxe/S3Dxe.c | 155 ++++++++++++++++++ .../S3FeaturePkg/S3Dxe/S3Dxe.inf | 49 ++++++ .../S3FeaturePkg/S3Pei/S3Pei.c | 83 +++++++++- .../S3FeaturePkg/S3Pei/S3Pei.inf | 8 +- .../Include/AcpiS3MemoryNvData.h | 22 +++ 8 files changed, 365 insertions(+), 11 deletions(-) create mode 100644 Fe= atures/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe= .inf create mode 100644 Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvDat= a.h diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory= .fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf index 9e17f853c630..7f630908fa2c 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf @@ -2,7 +2,20 @@ # FDF file for post-memory S3 advanced feature modules. # # Copyright (c)= 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2022, Ba= ruch Binyamin Doron.
# # SPDX-License-Identifier: BSD-2-Clause-Patent #= ##++## Dependencies+ INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunication= Smm.inf+ INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf++## = Save-state module stack+ INF S3FeaturePkg/S3Dxe/S3Dxe.inf+ INF MdeModuleP= kg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf+ INF UefiCpuPkg/CpuS3D= ataDxe/CpuS3DataDxe.inf++## Restore-state module stack+ INF MdeModulePkg/U= niversal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.infdiff --git a/F= eatures/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf b/Features= /Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf index fdd16a4e0356..e130fa5f098d 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf @@ -2,9 +2,15 @@ # FDF file for pre-memory S3 advanced feature modules. # # Copyright (c) = 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2022, Bar= uch Binyamin Doron.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # = ## -INF S3FeaturePkg/S3Pei/S3Pei.inf+## Dependencies+ INF S3FeaturePkg/S3P= ei/S3Pei.inf+ INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf+= +## Restore-state module stack+ INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei= /S3Resume2Pei.infdiff --git a/Features/Intel/PowerManagement/S3FeaturePkg/I= nclude/S3Feature.dsc b/Features/Intel/PowerManagement/S3FeaturePkg/Include/= S3Feature.dsc index cc34e785076a..d8bfc7909413 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc @@ -7,6 +7,7 @@ # for the build infrastructure. # # Copyright (c) 2019 - 2021, Intel Corpo= ration. All rights reserved.
+# Copyright (c) 2022, Baruch Binyamin Doro= n.
# # SPDX-License-Identifier: BSD-2-Clause-Patent #@@ -25,6 +26,10 @@ !error "DXE_ARCH must be specified to build this feature!" !endif +[= PcdsFixedAtBuild]+ # Attempts to improve performance at the cost of more D= RAM usage+ gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE+ ####= ###########################################################################= # # # Library Class section - list of all Library Classes needed by this fe= ature.@@ -32,7 +37,14 @@ ##########################################################################= ###### [LibraryClasses.common.PEIM]- SmmAccessLib|IntelSiliconPkg/Feature= /SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.inf+ #SmmAccessLib|Inte= lSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib= .inf+ SmmControlLib|IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmContr= olLib/PeiSmmControlLib.inf++[LibraryClasses.common.DXE_DRIVER, LibraryClass= es.common.DXE_SMM_DRIVER]+ #######################################+ # Edk= 2 Packages+ #######################################+ S3BootScriptLib|MdeM= odulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf #############= ################################################################### #@@ -60= ,8 +72,26 @@ # S3 Feature Package ##################################### - # Add li= brary instances here that are not included in package components and should= be tested- # in the package build.- # Add components here that should b= e included in the package build. S3FeaturePkg/S3Pei/S3Pei.inf+ UefiCpuPk= g/PiSmmCommunication/PiSmmCommunicationPei.inf+ UefiCpuPkg/Universal/Acpi/= S3Resume2Pei/S3Resume2Pei.inf++#+# Feature DXE Components+#++# @todo: Chang= e below line to [Components.$(DXE_ARCH)] after https://bugzilla.tianocore.o= rg/show_bug.cgi?id=3D2308+# is completed.+[Components.X64]+ #######= ##############################+ # S3 Feature Package+ ###################= ##################++ # Add components here that should be included in the = package build.+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf+ = MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf+ S3FeaturePkg/S3D= xe/S3Dxe.inf+ MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.in= f+ UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf+ MdeModulePkg/Universal/Acpi/= BootScriptExecutorDxe/BootScriptExecutorDxe.infdiff --git a/Features/Intel/= PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c b/Features/Intel/PowerManagement= /S3FeaturePkg/S3Dxe/S3Dxe.c new file mode 100644 index 000000000000..1a7ccb8eedab --- /dev/null +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c @@ -0,0 +1,155 @@ +/** @file+ Source code file for S3 DXE module++Copyright (c) 2022, Baruch= Binyamin Doron.
+SPDX-License-Identifier: BSD-2-Clause-Patent++**/++#in= clude +#include +#include +#include +#include +#include +#include +#include +#include +#include ++#define PEI_ADDITIONAL_MEMORY_SIZE = (16 * EFI_PAGE_SIZE)++/**+ Get the mem size in memory type information ta= ble.++ @return the mem size in memory type information table.+**/+UINT64+E= FIAPI+GetMemorySizeInMemoryTypeInformation (+ VOID+ )+{+ EFI_STATUS = Status;+ EFI_MEMORY_TYPE_INFORMATION *MemoryData;+ UINT8 = Index;+ UINTN TempPageNum;++ Sta= tus =3D EfiGetSystemConfigurationTable (&gEfiMemoryTypeInformationGuid, (VO= ID **) &MemoryData);++ if (EFI_ERROR (Status) || MemoryData =3D=3D NULL) {= + return 0;+ }++ TempPageNum =3D 0;+ for (Index =3D 0; MemoryData[Ind= ex].Type !=3D EfiMaxMemoryType; Index++) {+ //+ // Accumulate default= memory size requirements+ //+ TempPageNum +=3D MemoryData[Index].Num= berOfPages;+ }++ return TempPageNum * EFI_PAGE_SIZE;+}++/**+ Get the mem= size need to be consumed and reserved for PEI phase resume.++ @return the= mem size to be reserved for PEI phase resume.+**/+UINT64+EFIAPI+GetPeiMemS= ize (+ VOID+ )+{+ UINT64 Size;++ Size =3D GetMemorySizeInMemoryTypeInf= ormation ();++ return PcdGet32 (PcdPeiMinMemSize) + Size + PEI_ADDITIONAL_= MEMORY_SIZE;+}++/**+ Allocate EfiACPIMemoryNVS below 4G memory address.++ = This function allocates EfiACPIMemoryNVS below 4G memory address.++ @para= m Size Size of memory to allocate.++ @return Allocated address fo= r output.++**/+VOID *+EFIAPI+AllocateAcpiNvsMemoryBelow4G (+ IN UINTN S= ize+ )+{+ UINTN Pages;+ EFI_PHYSICAL_ADDRESS Address;+ = EFI_STATUS Status;+ VOID *Buffer;++ Pages = =3D EFI_SIZE_TO_PAGES (Size);+ Address =3D 0xffffffff;++ Status =3D gBS->= AllocatePages (+ AllocateMaxAddress,+ Efi= ACPIMemoryNVS,+ Pages,+ &Address+ = );+ ASSERT_EFI_ERROR (Status);++ Buffer =3D (VOID *)(UINTN)Addr= ess;+ ZeroMem (Buffer, Size);++ return Buffer;+}++/**+ Allocates memory = to use on S3 resume.++ @param[in] ImageHandle Not used.+ @param= [in] SystemTable General purpose services available to every DXE = driver.++ @retval EFI_SUCCESS The function completes successf= ully+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create da= tabase+**/+EFI_STATUS+EFIAPI+S3DxeEntryPoint (+ IN EFI_HANDLE Image= Handle,+ IN EFI_SYSTEM_TABLE *SystemTable+ )+{+ UINT64 S3PeiMe= mSize;+ UINT64 S3PeiMemBase;+ ACPI_S3_MEMORY S3MemoryInfo;+ EF= I_STATUS Status;++ DEBUG ((DEBUG_INFO, "%a() Start\n", __FUNCTION__))= ;++ S3PeiMemSize =3D GetPeiMemSize ();+ S3PeiMemBase =3D (UINTN) Allocate= AcpiNvsMemoryBelow4G (S3PeiMemSize);+ ASSERT (S3PeiMemBase !=3D 0);++ S3M= emoryInfo.S3PeiMemBase =3D S3PeiMemBase;+ S3MemoryInfo.S3PeiMemSize =3D S3= PeiMemSize;++ DEBUG ((DEBUG_INFO, "S3PeiMemBase: 0x%x\n", S3PeiMemBase));+= DEBUG ((DEBUG_INFO, "S3PeiMemSize: 0x%x\n", S3PeiMemSize));++ Status =3D= gRT->SetVariable (+ ACPI_S3_MEMORY_NV_NAME,+ = &gEfiAcpiVariableGuid,+ EFI_VARIABLE_NON_VOLATILE | E= FI_VARIABLE_BOOTSERVICE_ACCESS,+ sizeof (S3MemoryInfo),+ = &S3MemoryInfo+ );+ ASSERT_EFI_ERROR (Stat= us);++ DEBUG ((DEBUG_INFO, "%a() End\n", __FUNCTION__));+ return EFI_SUCC= ESS;+}diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.= inf b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf new file mode 100644 index 000000000000..28589c2c869b --- /dev/null +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf @@ -0,0 +1,49 @@ +### @file+# Component information file for the S3 DXE module.+#+# Copyrigh= t (c) 2022, Baruch Binyamin Doron.
+#+# SPDX-License-Identifier: BSD-2-C= lause-Patent+#+###++[Defines]+ INF_VERSION =3D 0x00010017+ BASE_NAM= E =3D S3Dxe+ FILE_GUID =3D 30926F92-CC83-4381-9F70-AC96EDB= 5BEE0+ VERSION_STRING =3D 1.0+ MODULE_TYPE =3D DXE_DRIVER+ ENTR= Y_POINT =3D S3DxeEntryPoint++[LibraryClasses]+ UefiDriverEntryPoint+= UefiBootServicesTableLib+ UefiRuntimeServicesTableLib+ BaseMemoryLib+ = DebugLib+ PcdLib+ UefiLib++[Packages]+ MdePkg/MdePkg.dec+ MdeModulePkg/= MdeModulePkg.dec+ MinPlatformPkg/MinPlatformPkg.dec+ IntelFsp2WrapperPkg/= IntelFsp2WrapperPkg.dec+ S3FeaturePkg/S3FeaturePkg.dec++[Sources]+ S3Dxe.= c++[Pcd]+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize++[FeaturePcd]+ = gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable++[Guids]+ gEfiMemoryTypeIn= formationGuid ## CONSUMES+ gEfiAcpiVariableGuid ## CONSUMES++[D= epex]+ gEfiVariableArchProtocolGuid AND+ gEfiVariableWriteArchProtoc= olGuiddiff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.= c b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c index b0aaa04962c8..6acb894b6fc9 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c @@ -2,12 +2,87 @@ Source code file for S3 PEI module Copyright (c) 2019, Intel Corporatio= n. All rights reserved.
+Copyright (c) 2022, Baruch Binyamin Doron.
= SPDX-License-Identifier: BSD-2-Clause-Patent **/ +#include +#incl= ude +#include #include #include +#include ++// TODO: Finalise implementation factoring+#define R_SA_PAM0 (0x8= 0)+#define R_SA_PAM5 (0x85)+#define R_SA_PAM6 (0x86)++/**+ This function= is called after FspSiliconInitDone installed PPI.+ For FSP API mode, this= is when FSP-M HOBs are installed into EDK2.++ @param[in] PeiServices P= ointer to PEI Services Table.+ @param[in] NotifyDesc Pointer to the de= scriptor for the Notification event that+ caused= this function to execute.+ @param[in] Ppi Pointer to the PPI d= ata associated with this function.++ @retval EFI_STATUS Always retu= rn EFI_SUCCESS+**/+EFI_STATUS+EFIAPI+FspSiliconInitDoneNotify (+ IN EFI_PE= I_SERVICES **PeiServices,+ IN EFI_PEI_NOTIFY_DESCRIPTOR *Notify= Desc,+ IN VOID *Ppi+ )+{+ EFI_STATUS Status;+ = EFI_BOOT_MODE BootMode;+ UINT64 MchBaseAddress;++ Status =3D Pe= iServicesGetBootMode (&BootMode);+ ASSERT_EFI_ERROR (Status);++ // Enable= PAM regions for AP wakeup vector (resume)+ // - CPU is finalised by PiSmm= CpuDxeSmm, not FSP. So, it's safe here?+ // TODO/TEST: coreboot does this = unconditionally, vendor FWs may not (test resume). Should we?+ // - It is = certainly interesting that only PAM0, PAM5 and PAM6 are defined for Kabylak= eSiliconPkg.+ // - Also note that 0xA0000-0xFFFFF is marked "reserved" in = FSP HOB - this does not mean+ // that the memory is unusable, perhaps th= is is precisely because it will contain+ // the AP wakeup vector.+ if (= BootMode =3D=3D BOOT_ON_S3_RESUME) {+ MchBaseAddress =3D PCI_LIB_ADDRESS= (0, 0, 0, 0);+ PciWrite8 (MchBaseAddress + R_SA_PAM0, 0x30);+ PciWri= te8 (MchBaseAddress + (R_SA_PAM0 + 1), 0x33);+ PciWrite8 (MchBaseAddress= + (R_SA_PAM0 + 2), 0x33);+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 3),= 0x33);+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 4), 0x33);+ PciWrit= e8 (MchBaseAddress + R_SA_PAM5, 0x33);+ PciWrite8 (MchBaseAddress + R_SA= _PAM6, 0x33);+ }++ //+ // Install EFI_PEI_MM_ACCESS_PPI for S3 resume ca= se+ //+ Status =3D PeiInstallSmmAccessPpi ();+ ASSERT_EFI_ERROR (Status)= ;++ //+ // Install EFI_PEI_MM_CONTROL_PPI for S3 resume case+ //+ Statu= s =3D PeiInstallSmmControlPpi ();+ ASSERT_EFI_ERROR (Status);++ return St= atus;+}++EFI_PEI_NOTIFY_DESCRIPTOR mFspSiliconInitDoneNotifyDesc =3D {+ (= EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_L= IST),+ &gFspSiliconInitDonePpiGuid,+ FspSiliconInitDoneNotify+}; /** S= 3 PEI module entry point@@ -25,12 +100,10 @@ S3PeiEntryPoint ( IN CONST EFI_PEI_SERVICES **PeiServices ) {- EFI_STATUS Status;+ = EFI_STATUS Status; - //- // Install EFI_PEI_MM_ACCESS_PPI for S3 resume= case- //- Status =3D PeiInstallSmmAccessPpi ();+ Status =3D PeiServices= NotifyPpi (&mFspSiliconInitDoneNotifyDesc);+ ASSERT_EFI_ERROR (Status); = return Status; }diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S= 3Pei/S3Pei.inf b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.in= f index e485eac9521f..173919bb881e 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf @@ -18,10 +18,13 @@ [LibraryClasses] PeimEntryPoint PeiServicesLib+ DebugLib SmmAccessL= ib+ SmmControlLib [Packages] MdePkg/MdePkg.dec+ IntelFsp2WrapperPkg/In= telFsp2WrapperPkg.dec IntelSiliconPkg/IntelSiliconPkg.dec S3FeaturePkg/= S3FeaturePkg.dec @@ -31,5 +34,8 @@ [FeaturePcd] gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable +[Ppis]+ gF= spSiliconInitDonePpiGuid+ [Depex]- gEfiPeiMemoryDiscoveredPpiGuid+ TRUEdi= ff --git a/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h b/Pla= tform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h new file mode 100644 index 000000000000..0d75af8e9a03 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h @@ -0,0 +1,22 @@ +/** @file + Header file for NV data structure definition. + +Copyright (c) 2021, Baruch Binyamin Doron +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __ACPI_S3_MEMORY_NV_DATA_H__ +#define __ACPI_S3_MEMORY_NV_DATA_H__ + +// +// NV data structure +// +typedef struct { + UINT64 S3PeiMemBase; + UINT64 S3PeiMemSize; +} ACPI_S3_MEMORY; + +#define ACPI_S3_MEMORY_NV_NAME L"S3MemoryInfo" + +#endif -- 2.37.2