From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web12.2834.1662594578769836920 for ; Wed, 07 Sep 2022 16:49:39 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=fuaOd1k0; spf=permerror, err=too many SPF records (domain: intel.com, ip: 192.55.52.43, mailfrom: isaac.w.oram@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662594578; x=1694130578; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=dA6cCyH1tbhrT4+/3qiUIMv9BEsJPq2+xqyGRQ9Albo=; b=fuaOd1k0wKaEHEdMTaTAdJu5M6nnMGo6XNtIrtUNoxodD9jlU4NN33GX e2eq/zqnEPjr1VIJCeMw3w9dzgLMO4du8vCVwK5AARnRuEXCqSYq3CfhS F7b0eooN0+4s6X2B+2Lb5lz4usP3MXh/3elOK2HJAi6hlQTyFD/DYIh/A N78vXPN3mMQ2as8p0CuJGh6DSs3W2B6smdkH32xhVTK51O0m3I779uXqH PhMnlHFESfpyZLa08Bgjm7pXYh8uFm/C4eMgjwH6T5hjx9plkuYvIVBOe TF53u7REca3Z3gLig07LS2O+P6B4IYp3H+dQPVkWwbe2BrJu6fVmFavg5 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10463"; a="383317458" X-IronPort-AV: E=Sophos;i="5.93,298,1654585200"; d="scan'208";a="383317458" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2022 16:49:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,298,1654585200"; d="scan'208";a="610494544" Received: from orsmsx603.amr.corp.intel.com ([10.22.229.16]) by orsmga007.jf.intel.com with ESMTP; 07 Sep 2022 16:49:18 -0700 Received: from orsmsx609.amr.corp.intel.com (10.22.229.22) by ORSMSX603.amr.corp.intel.com (10.22.229.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Wed, 7 Sep 2022 16:49:17 -0700 Received: from orsmsx607.amr.corp.intel.com (10.22.229.20) by ORSMSX609.amr.corp.intel.com (10.22.229.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Wed, 7 Sep 2022 16:49:17 -0700 Received: from ORSEDG601.ED.cps.intel.com (10.7.248.6) by orsmsx607.amr.corp.intel.com (10.22.229.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31 via Frontend Transport; Wed, 7 Sep 2022 16:49:17 -0700 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (104.47.59.168) by edgegateway.intel.com (134.134.137.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2375.31; Wed, 7 Sep 2022 16:49:17 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=IwMGJorq7uuyzcEvfUCAf8ohpHstN1c1kP/+yxNY32cLOo1FU/9wPzGv3wZB86BHcFDPHOQJc5dRAWltQ1ccRq6Vb7jl4Oq+Qq49M4v3+MgwQE4pvbkFfSWcLnyfcdZ1CSA0Vo0e8s/K6qhLKzQ1hDRUGsmFE3Fgo6uXgxktOX+XUV9GzL8kFYR7BqnVh73aANJ6a/f7Rvs52B/EWS7lQxdIwe175qmDqrDpuUU7xls29XlNRoMACdKrePbmfhA9HhIVAe+qv6e4Nt25tZdm2AjN/fmZw4NJsMXa5ylgh+sQiYHhwYjqJ7iN/YH/5FOa+A5z5tCi9St+u0MWxNFd3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Wu9R2TYT5zoZ0fPKK/zVU8DsKZFlMNIoTrGsaWLosPU=; b=Db+InSnIhPp74HipU0juJ/U7l1pmWLlqbet1shb+ruxlkoDp91ixc24hFCYxBbsjEAg7CFjhiwn6Sp5QBDapSCouAfo8QK1iCn7b9+DbeUhoCjYL8QZE1CyKoPTEAQxT2EkRGfJ7t0ETHarPcEwhMKvciirjAu1KuVOJuY/Hb51n0GLI18d6xDpeK+DJ2TTjYGqf25SAlQOVzIrW6qThI6vckpqgW64O0+z/glUEeN7Ad5bdst1L/jDYDmFcODhlNGFDC1CtJmAk+GoWNU86BzBb/NYhekvKT7KRVW7sqVj6RwIEEsSmTSCvMcjWG5wk5XmezLM7dRy/mUdqSsBG0g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from SA1PR11MB5801.namprd11.prod.outlook.com (2603:10b6:806:23d::13) by BN6PR11MB1569.namprd11.prod.outlook.com (2603:10b6:405:11::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5612.14; Wed, 7 Sep 2022 23:49:12 +0000 Received: from SA1PR11MB5801.namprd11.prod.outlook.com ([fe80::4149:e96e:480e:e1c3]) by SA1PR11MB5801.namprd11.prod.outlook.com ([fe80::4149:e96e:480e:e1c3%5]) with mapi id 15.20.5588.010; Wed, 7 Sep 2022 23:49:12 +0000 From: "Isaac Oram" To: Benjamin Doron , "devel@edk2.groups.io" CC: "Desimone, Nathaniel L" , "Sinha, Ankit" , "Ni, Ray" , "Chaganty, Rangasai V" Subject: Re: [edk2-devel][edk2-platforms][PATCH v2 2/6] IntelSiliconPkg/Feature/SmmAccess: Implement PPI with chipset support Thread-Topic: [edk2-devel][edk2-platforms][PATCH v2 2/6] IntelSiliconPkg/Feature/SmmAccess: Implement PPI with chipset support Thread-Index: AQHYwhLSGM8zzsU4QkSEJMQcuGKiKa3UpKvA Date: Wed, 7 Sep 2022 23:49:12 +0000 Message-ID: References: <2c1e044f0d9236a43f77c5dc8bc9d7dd39bf7612.1662483691.git.benjamin.doron00@gmail.com> In-Reply-To: <2c1e044f0d9236a43f77c5dc8bc9d7dd39bf7612.1662483691.git.benjamin.doron00@gmail.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.6.500.17 dlp-reaction: no-action authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 0b9952ed-b29f-4a33-4a41-08da912b90da x-ms-traffictypediagnostic: BN6PR11MB1569:EE_ x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: uqSZhu0ELALfVbo0+gSr4FntIy5gmc/OAYKpWl7XHMoIfEjyR2hyeXFBpcW6qLSFbGVGLtCYlr3TtCJQddoKl75fd1aEeHfNqNowfw/YoV9S/+wc73Bl35mE2hTUzLDJHyLKAK4Mq71/u9pE7B4dvqH1r6Q8IfS/03k0QpI5QSNnAHl6GFviMse+FZ1wzUV4yPW4vhMQukcAQVY6/AIHms52scUa0Vw6sWPIgFizEUqTs5eyJ8DW9XuWYcdDO9eqPIHCF5NgTRXKORzrvuCzRO51a+uMU//5bypR3tYcK2QNZbTK2TxufcXaW6rFlBrc3mKG06r4KpzbrhzJVDoPswg2o4ZE+nNdj+McTytTKNl6O2RDR/F0AdTVxXJPLNFXvvx+e7s5h0Wdmdi4XuYWq2uD9qV6yPCFcW3PIe0pHL7jBuEJZ0OA9c16g8fISItSJwiXKq/3evfQ3MomfWl71GoNUJ8hlMfJsDwJJKQp2ttcYG8nbBPyBlv0OaoN2175O87KNYyO/Tr18a35EM/3HBimh+27ap3JCyPYwbfBa4JDg6wdCvwv0reavFY+Bd3cFclL8Umf4+I7UcpiQJEv8VWqKW022rpXuzekbh4CG3AieD0vO1FUILfvhneirgVEc56x7nQkeWhDqKNyUU6G6fIwOP8etYG/HAttIsWmef5JtzWIu5eMPZr6L0BkNIa9AS+KxcTqRGG6F7Wco/y0NLVqjoq0y0MdZYdR3ce5IM4svDYSz1Z4a49I6JYTE//1OPTiwNI8OH79FXlve7N5eg== x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SA1PR11MB5801.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230016)(136003)(396003)(346002)(376002)(39860400002)(366004)(38070700005)(38100700002)(122000001)(110136005)(54906003)(316002)(71200400001)(82960400001)(52536014)(64756008)(5660300002)(2906002)(8936002)(66446008)(76116006)(66946007)(30864003)(4326008)(66476007)(8676002)(66556008)(186003)(55016003)(83380400001)(41300700001)(107886003)(478600001)(53546011)(6506007)(26005)(7696005)(9686003)(86362001)(33656002);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?1pWkfx82m/z4uqROCg2mwBbL1n5WNcw5Oa9+moLuhYZgFA1SVlFkakgEmWxh?= =?us-ascii?Q?Ica199Axfb3DZ5DF1Pe2zQeaCmV1l4X+GzFrfiCDh9Oz3HDiTqUEwH8CXboO?= =?us-ascii?Q?TSirJ9C1KQCftiUwDmuxwzgzbX9Nf+eJcvHw3NOLvCrhxN5vtOEcgoxjV+TR?= =?us-ascii?Q?JsgFEhpVr0v8Att6KsBAoarAWMzI6+1Wl9STNm39VM0ej2SyOePKT2lWQgJI?= =?us-ascii?Q?NFa/rN6gZlu+ZHEEMmV7wJ+WY/uoZrzqrAtmOXpLWrzCjhIpKqOBf1+ku1v4?= =?us-ascii?Q?V0Rmj/8MW+kp1H8tQVbgKwmz/dYN7YvxeVgC8pR1oJnQA38UoxvT4vSJv3Li?= =?us-ascii?Q?1tOGBfOvEVoMrLjnboYHDXXs6oNx2hTxfB5hLQ8CjvmWsVY7QG8+gVAl40MB?= =?us-ascii?Q?Uy8AnEbXUpEd3WuPsMZ6WYGEgc2hT1iypZdOeVpUCx0qHimprmABwuDaenAP?= =?us-ascii?Q?hwRaAlzPzaWf7WKDqLNFKuDEX0fiRgn7o2U0xE77ePM5b8mczlqWD9RkY0BQ?= =?us-ascii?Q?JqZ6lgCw1Z7RmpEVk4JxyDnCPWar2X/aMefroF9eEEcM+qwOYH0Ate09ibSx?= =?us-ascii?Q?viDDBcMPvASFb8u7UcueSPm0df+LACPi78AcxxyPyBBBpHHyFek+qfeNY1JW?= =?us-ascii?Q?grGInZWa1YUsSZAZ7oSupFBOmTYkXeE26pCRy29IvEfzD+3Hx2ZzCSwIHNH3?= =?us-ascii?Q?vY0IBxKaxINrHu5IUu1dsZ4Xh0567aVQjQVQNjR65XxNHwHEWfC2vnhl3pjo?= =?us-ascii?Q?RNAsT3TU/TmWz+6wL+sPtFmt9sLG46TdEaVzW+kQnChsM7sMBN0S9CQt4Snv?= =?us-ascii?Q?STAuo41DXrh19xNSuS4kgXB2Uv0JMDhP+81MmLjpkTgNxtTEN/zKFKt1jJhz?= =?us-ascii?Q?AWmyCKLh9s/ioaj6ZeJFSSeVWaxecQOkb3UWqRLcZ6bRk7Ola7Gj8sfBiYmE?= =?us-ascii?Q?PacTykvUe5A1SAnH965LDtYUhj+COUkFeabpzV0q2jE3bXAc/QIeOPJ7+Jpy?= =?us-ascii?Q?F22EEjhq9Rk4dcUPTil+nOXmMBFJ9h9toLufGfVMdUoywEg65lcWD8icLtVU?= =?us-ascii?Q?d1clvsR23wrDK23rFa7dYwwMGQcCFnyZHGmMkh1GHhY3zck2Q95wJXnS1dAp?= =?us-ascii?Q?xsavU9TMlNRMx44znm7liH1Bdh7bOOH56onYsYSEUa9myGwVCal1o7akTfgs?= =?us-ascii?Q?eOI20w1EKD2kCUf6RziUX+Depf2/KPFIrA7+XRPCi4cf32PHrjHYZ7BNK3Q1?= =?us-ascii?Q?tFHS0BQjrSdsP+H0KImCkCcagV7Mep5TJPBB0DMO0ze0AEnXl52QSSdC9+k/?= =?us-ascii?Q?qduDn1i0Qk0OkhoIM0itNRsg7nGOFFM/h/WmmV79UuBc3iM1ytaxq0O4Hc1e?= =?us-ascii?Q?Qh1CpS1saRPzIm/nI+TBaPiYeJy75Rfx6XQHiQsk67xQKcTFZe07IoDXbpSf?= =?us-ascii?Q?ksse8Y+BVEFssIuOO/cIBx7Rb3vKYGmUPqv8udUg1nrTBxShKKOM5YNJaahY?= =?us-ascii?Q?4Bo0gLtLnVhsPlEyivghTOKPJK3YPfLBtmVK42abC1hPkzFD/OST0OcYg6YU?= =?us-ascii?Q?quXx/yN6p/kr7qxqe3bKXKnRaGCfeA7IcnWfLacp?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SA1PR11MB5801.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0b9952ed-b29f-4a33-4a41-08da912b90da X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Sep 2022 23:49:12.5568 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: TdC+obCGYXvk6Gd8yBTFBsSDHxIGe5S7w2fDeHF7eaNckXyYa8nLz20/YEmXwaBfO+N8axRT9Ocu//HbRWfbtw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR11MB1569 Return-Path: isaac.w.oram@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Isaac Oram -----Original Message----- From: Benjamin Doron =20 Sent: Tuesday, September 6, 2022 10:02 AM To: devel@edk2.groups.io Cc: Desimone, Nathaniel L ; Sinha, Ankit ; Ni, Ray ; Chaganty, Rangasai V ; Oram, Isaac W Subject: [edk2-devel][edk2-platforms][PATCH v2 2/6] IntelSiliconPkg/Feature= /SmmAccess: Implement PPI with chipset support SMRAM must be opened to retrieve the lockbox for S3, and SMM communication = depends on this PPI. For security purposes, SMRAM lock must be performed be= fore EndOfPei (although FSP notify performs lockdown too). It seems to me that this library is generic and applicable to all Intel pla= tforms in the tree using the MCH SMRAMC register. Cc: Nate DeSimone Cc: Ankit Sinha Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Isaac Oram Signed-off-by: Benjamin Doron --- .../PeiSmmAccessLibSmramc/PeiSmmAccessLib.c | 430 ++++++++++++++++++ .../PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf | 36 ++ 2 files changed, 466 insertions(+) create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library= /PeiSmmAccessLibSmramc/PeiSmmAccessLib.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library= /PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmm= AccessLibSmramc/PeiSmmAccessLib.c b/Silicon/Intel/IntelSiliconPkg/Feature/S= mmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.c new file mode 100644 index 000000000000..5b472bf86abf --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAcce +++ ssLibSmramc/PeiSmmAccessLib.c @@ -0,0 +1,430 @@ +/** @file+ This is to publish the SMM Access Ppi instance.++ Copyright (= c) 2019 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License-= Identifier: BSD-2-Clause-Patent++**/+#include +#in= clude +#include +#includ= e +#include +#include +#include +#include ++#include +#include ++#= define SMM_ACCESS_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('4', '5', 's', 'a')+= +///+/// Private data+///+typedef struct {+ UINTN Signatur= e;+ EFI_HANDLE Handle;+ EFI_PEI_MM_ACCESS_PPI SmmAccess;+ //+= // Local Data for SMM Access interface goes here+ //+ UINTN = NumberRegions;+ EFI_SMRAM_DESCRIPTOR *SmramDesc;+} SMM_ACCESS_PRIVAT= E_DATA;++#define SMM_ACCESS_PRIVATE_DATA_FROM_THIS(a) \+ CR (a, \+ = SMM_ACCESS_PRIVATE_DATA, \+ SmmAccess, \+ SMM_ACC= ESS_PRIVATE_DATA_SIGNATURE \+ )++//+// Common registers:+//+// DEVICE = 0 (Memory Controller Hub)+//+#define SA_MC_BUS 0x00+#define SA_MC_= DEV 0x00+#define SA_MC_FUN 0x00+///+/// Description:+/// = The SMRAMC register controls how accesses to Compatible SMRAM spaces are t= reated. The Open, Close and Lock bits function only when G_SMRAME bit is s= et to 1. Also, the Open bit must be reset before the Lock bit is set.+///+= #define R_SA_SMRAMC (0x88)+#define B_SA_SMRAMC_D_LCK_MASK (0x10)+#defi= ne B_SA_SMRAMC_D_CLS_MASK (0x20)+#define B_SA_SMRAMC_D_OPEN_MASK (0x= 40)++/**+ This routine accepts a request to "open" a region of SMRAM. The= + region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.= + The use of "open" means that the memory is visible from all PEIM+ and S= MM agents.++ @param[in] PeiServices - General purpose services av= ailable to every PEIM.+ @param[in] This - Pointer to the S= MM Access Interface.+ @param[in] DescriptorIndex - Region of SMRAM to= Open.++ @retval EFI_SUCCESS - The region was successfully ope= ned.+ @retval EFI_DEVICE_ERROR - The region could not be opened bec= ause locked by+ chipset.+ @retval EFI_I= NVALID_PARAMETER - The descriptor index was out of bounds.+**/+EFI_STATUS= +EFIAPI+Open (+ IN EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_= MM_ACCESS_PPI *This,+ IN UINTN DescriptorIndex+ = )+{+ SMM_ACCESS_PRIVATE_DATA *SmmAccess;+ UINT8 Index;= + UINT64 Address;+ UINT8 SmramControl;= ++ SmmAccess =3D SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);+ if (Descripto= rIndex >=3D SmmAccess->NumberRegions) {+ DEBUG ((DEBUG_WARN, "SMRAM regi= on out of range\n"));++ return EFI_INVALID_PARAMETER;+ } else if (SmmAc= cess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_LOCKED) {+ //+ = // Cannot open a "locked" region+ //+ DEBUG ((DEBUG_WARN, "Cannot = open a locked SMRAM region\n"));++ return EFI_DEVICE_ERROR;+ }++ ///+ = /// BEGIN CHIPSET CODE+ ///+ ///+ /// SMRAM register is PCI 0:0:0:88, S= MRAMC (8 bit)+ ///+ Address =3D PCI_SEGMENT_LIB_ADDRESS (0, SA_MC_BUS, SA= _MC_DEV, SA_MC_FUN, R_SA_SMRAMC);+ SmramControl =3D PciSegmentRead8 (Addre= ss);+ ///+ /// Is SMRAM locked?+ ///+ if ((SmramControl & B_SA_SMRAMC_= D_LCK_MASK) !=3D 0) {+ ///+ /// Cannot Open a locked region+ ///+ = for (Index =3D 0; Index < SmmAccess->NumberRegions; Index++) {+ Smm= Access->SmramDesc[Index].RegionState |=3D EFI_SMRAM_LOCKED;+ }+ DEBUG= ((DEBUG_WARN, "Cannot open a locked SMRAM region\n"));+ return EFI_DEVI= CE_ERROR;+ }+ ///+ /// Open SMRAM region+ ///+ SmramControl |=3D B_SA_= SMRAMC_D_OPEN_MASK;+ SmramControl &=3D ~(B_SA_SMRAMC_D_CLS_MASK);++ PciSe= gmentWrite8 (Address, SmramControl);+ ///+ /// END CHIPSET CODE+ ///++ = SmmAccess->SmramDesc[DescriptorIndex].RegionState &=3D (UINT64) ~(EFI_SMRAM= _CLOSED | EFI_ALLOCATED);+ SmmAccess->SmramDesc[DescriptorIndex].RegionSta= te |=3D (UINT64) EFI_SMRAM_OPEN;+ SmmAccess->SmmAccess.OpenState =3D TRUE;= + return EFI_SUCCESS;+}++/**+ This routine accepts a request to "close" a= region of SMRAM. This is valid for+ compatible SMRAM region.++ @param[i= n] PeiServices - General purpose services available to every PEIM.= + @param[in] This - Pointer to the SMM Access Interface.+ = @param[in] DescriptorIndex - Region of SMRAM to Close.++ @retval EFI= _SUCCESS - The region was successfully closed.+ @retval EFI_DE= VICE_ERROR - The region could not be closed because locked by+ = chipset.+ @retval EFI_INVALID_PARAMETER - = The descriptor index was out of bounds.+**/+EFI_STATUS+EFIAPI+Close (+ IN = EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_ACCESS_PPI *This,+= IN UINTN DescriptorIndex+ )+{+ SMM_ACCESS_PRIVATE_DAT= A *SmmAccess;+ BOOLEAN OpenState;+ UINT8 = Index;+ UINT64 Address;+ UINT8 Smram= Control;++ SmmAccess =3D SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);+ if (D= escriptorIndex >=3D SmmAccess->NumberRegions) {+ DEBUG ((DEBUG_WARN, "SM= RAM region out of range\n"));++ return EFI_INVALID_PARAMETER;+ } else i= f (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_LOCKED) {+= //+ // Cannot close a "locked" region+ //+ DEBUG ((DEBUG_WARN,= "Cannot close a locked SMRAM region\n"));++ return EFI_DEVICE_ERROR;+ = }++ if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_CLOS= ED) {+ return EFI_DEVICE_ERROR;+ }++ ///+ /// BEGIN CHIPSET CODE+ //= /+ ///+ /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit)+ ///+ Addres= s =3D PCI_SEGMENT_LIB_ADDRESS (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMR= AMC);+ SmramControl =3D PciSegmentRead8 (Address);+ ///+ /// Is SMRAM l= ocked?+ ///+ if ((SmramControl & B_SA_SMRAMC_D_LCK_MASK) !=3D 0) {+ //= /+ /// Cannot Close a locked region+ ///+ for (Index =3D 0; Index = < SmmAccess->NumberRegions; Index++) {+ SmmAccess->SmramDesc[Index].Re= gionState |=3D EFI_SMRAM_LOCKED;+ }+ DEBUG ((DEBUG_WARN, "Cannot clos= e a locked SMRAM region\n"));+ return EFI_DEVICE_ERROR;+ }+ ///+ /// = Close SMRAM region+ ///+ SmramControl &=3D ~(B_SA_SMRAMC_D_OPEN_MASK);++ = PciSegmentWrite8 (Address, SmramControl);+ ///+ /// END CHIPSET CODE+ /= //++ SmmAccess->SmramDesc[DescriptorIndex].RegionState &=3D (UINT64) ~EFI_= SMRAM_OPEN;+ SmmAccess->SmramDesc[DescriptorIndex].RegionState |=3D (UINT6= 4) (EFI_SMRAM_CLOSED | EFI_ALLOCATED);++ //+ // Find out if any regions a= re still open+ //+ OpenState =3D FALSE;+ for (Index =3D 0; Index < SmmAc= cess->NumberRegions; Index++) {+ if ((SmmAccess->SmramDesc[Index].Region= State & EFI_SMRAM_OPEN) =3D=3D EFI_SMRAM_OPEN) {+ OpenState =3D TRUE;+= }+ }++ SmmAccess->SmmAccess.OpenState =3D OpenState;+ return EFI_SUC= CESS;+}++/**+ This routine accepts a request to "lock" SMRAM. The+ regio= n could be legacy AB or TSEG near top of physical memory.+ The use of "loc= k" means that the memory can no longer be opened+ to PEIM.++ @param[in] P= eiServices - General purpose services available to every PEIM.+ @p= aram[in] This - Pointer to the SMM Access Interface.+ @par= am[in] DescriptorIndex - Region of SMRAM to Lock.++ @retval EFI_SUCCE= SS - The region was successfully locked.+ @retval EFI_DEVICE_E= RROR - The region could not be locked because at least+ = one range is still open.+ @retval EFI_INVALID_PARAM= ETER - The descriptor index was out of bounds.+**/+EFI_STATUS+EFIAPI+Lock= (+ IN EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_ACCESS_PPI= *This,+ IN UINTN DescriptorIndex+ )+{+ SMM_ACCE= SS_PRIVATE_DATA *SmmAccess;+ UINT64 Address;+ UINT8 = SmramControl;++ SmmAccess =3D SMM_ACCESS_PRIVATE_DATA_FROM_T= HIS (This);+ if (DescriptorIndex >=3D SmmAccess->NumberRegions) {+ DEBU= G ((DEBUG_WARN, "SMRAM region out of range\n"));++ return EFI_INVALID_PA= RAMETER;+ } else if (SmmAccess->SmmAccess.OpenState) {+ DEBUG ((DEBUG_W= ARN, "Cannot lock SMRAM when SMRAM regions are still open\n"));++ return= EFI_DEVICE_ERROR;+ }++ SmmAccess->SmramDesc[DescriptorIndex].RegionState= |=3D (UINT64) EFI_SMRAM_LOCKED;+ SmmAccess->SmmAccess.LockState =3D TRUE;= ++ ///+ /// BEGIN CHIPSET CODE+ ///+ ///+ /// SMRAM register is PCI 0:= 0:0:88, SMRAMC (8 bit)+ ///+ Address =3D PCI_SEGMENT_LIB_ADDRESS (0, SA_M= C_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC);+ SmramControl =3D PciSegmentRea= d8 (Address);++ ///+ /// Lock the SMRAM+ ///+ SmramControl |=3D B_SA_SM= RAMC_D_LCK_MASK;++ PciSegmentWrite8 (Address, SmramControl);+ ///+ /// E= ND CHIPSET CODE+ ///++ return EFI_SUCCESS;+}++/**+ This routine services= a user request to discover the SMRAM+ capabilities of this platform. Thi= s will report the possible+ ranges that are possible for SMRAM access, bas= ed upon the+ memory controller capabilities.++ @param[in] PeiServices = - General purpose services available to every PEIM.+ @param[in] This = - Pointer to the SMRAM Access Interface.+ @param[in, out] Sm= ramMapSize - Pointer to the variable containing size of the+ = buffer to contain the description information.+ @par= am[in, out] SmramMap - Buffer containing the data describing the Smra= m+ region descriptors.++ @retval EFI_BUF= FER_TOO_SMALL - The user did not provide a sufficient buffer.+ @retval E= FI_SUCCESS - The user provided a sufficiently-sized buffer.+**/+= EFI_STATUS+EFIAPI+GetCapabilities (+ IN EFI_PEI_SERVICES **= PeiServices,+ IN EFI_PEI_MM_ACCESS_PPI *This,+ IN OUT UINTN = *SmramMapSize,+ IN OUT EFI_SMRAM_DESCRIPTOR *Smr= amMap+ )+{+ EFI_STATUS Status;+ SMM_ACCESS_PRIVATE_DATA *Sm= mAccess;+ UINTN NecessaryBufferSize;++ SmmAccess = =3D SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);+ NecessaryBufferSize =3D= SmmAccess->NumberRegions * sizeof (EFI_SMRAM_DESCRIPTOR);+ if (*SmramMapS= ize < NecessaryBufferSize) {+ DEBUG ((DEBUG_WARN, "SMRAM Map Buffer too = small\n"));++ Status =3D EFI_BUFFER_TOO_SMALL;+ } else {+ CopyMem (S= mramMap, SmmAccess->SmramDesc, NecessaryBufferSize);+ Status =3D EFI_SUC= CESS;+ }++ *SmramMapSize =3D NecessaryBufferSize;+ return Status;+}++/**= + This function is to install an SMM Access PPI+ - Introduction \n= + An API to install an instance of EFI_PEI_MM_ACCESS_PPI. This PPI is co= mmonly used to control SMM mode memory access for S3 resume.++ @retval E= FI_SUCCESS - Ppi successfully started and installed.+ @retval = EFI_NOT_FOUND - Ppi can't be found.+ @retval EFI_OUT_OF_RESOURCE= S - Ppi does not have enough resources to initialize the driver.+**/+EFI_S= TATUS+EFIAPI+PeiInstallSmmAccessPpi (+ VOID+ )+{+ EFI_STATUS = Status;+ UINTN Index;+ EFI_PEI_PPI_DE= SCRIPTOR *PpiList;+ EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *DescriptorBl= ock;+ SMM_ACCESS_PRIVATE_DATA *SmmAccessPrivate;+ VOID = *HobList;++ //+ // Initialize private data+ //+ SmmAcc= essPrivate =3D AllocateZeroPool (sizeof (*SmmAccessPrivate));+ ASSERT (Sm= mAccessPrivate !=3D NULL);+ if (SmmAccessPrivate =3D=3D NULL) {+ return= EFI_OUT_OF_RESOURCES;+ }+ PpiList =3D AllocateZeroPool (sizeof= (*PpiList));+ ASSERT (PpiList !=3D NULL);+ if (PpiList =3D=3D NULL) {+ = return EFI_OUT_OF_RESOURCES;+ }++ SmmAccessPrivate->Signature =3D SMM_A= CCESS_PRIVATE_DATA_SIGNATURE;+ SmmAccessPrivate->Handle =3D NULL;++ //= + // Get Hob list+ //+ HobList =3D GetFirstGuidHob (&gEfiSmmSmramMemoryG= uid);+ if (HobList =3D=3D NULL) {+ DEBUG ((DEBUG_WARN, "SmramMemoryRese= rve HOB not found\n"));+ return EFI_NOT_FOUND;+ }++ DescriptorBlock = =3D (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) ((UINT8 *) HobList + sizeof (EFI_HOB= _GUID_TYPE));++ //+ // Alloc space for SmmAccessPrivate->SmramDesc+ //+ = SmmAccessPrivate->SmramDesc =3D AllocateZeroPool ((DescriptorBlock->Number= OfSmmReservedRegions) * sizeof (EFI_SMRAM_DESCRIPTOR));+ if (SmmAccessPriv= ate->SmramDesc =3D=3D NULL) {+ DEBUG ((DEBUG_WARN, "Alloc SmmAccessPriva= te->SmramDesc fail.\n"));+ return EFI_OUT_OF_RESOURCES;+ }++ DEBUG ((D= EBUG_INFO, "Alloc SmmAccessPrivate->SmramDesc success.\n"));++ //+ // use= the hob to publish SMRAM capabilities+ //+ for (Index =3D 0; Index < Des= criptorBlock->NumberOfSmmReservedRegions; Index++) {+ SmmAccessPrivate->= SmramDesc[Index].PhysicalStart =3D DescriptorBlock->Descriptor[Index].Phys= icalStart;+ SmmAccessPrivate->SmramDesc[Index].CpuStart =3D Descri= ptorBlock->Descriptor[Index].CpuStart;+ SmmAccessPrivate->SmramDesc[Inde= x].PhysicalSize =3D DescriptorBlock->Descriptor[Index].PhysicalSize;+ = SmmAccessPrivate->SmramDesc[Index].RegionState =3D DescriptorBlock->Desc= riptor[Index].RegionState;+ }++ SmmAccessPrivate->NumberRegions = =3D Index;+ SmmAccessPrivate->SmmAccess.Open =3D Open;+ Smm= AccessPrivate->SmmAccess.Close =3D Close;+ SmmAccessPrivate->Smm= Access.Lock =3D Lock;+ SmmAccessPrivate->SmmAccess.GetCapabilit= ies =3D GetCapabilities;+ SmmAccessPrivate->SmmAccess.LockState =3D = FALSE;+ SmmAccessPrivate->SmmAccess.OpenState =3D FALSE;++ //+ // = Install PPI+ //+ PpiList->Flags =3D (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PE= I_PPI_DESCRIPTOR_TERMINATE_LIST);+ PpiList->Guid =3D &gEfiPeiMmAccessPpi= Guid;+ PpiList->Ppi =3D &SmmAccessPrivate->SmmAccess;++ Status = =3D PeiServicesInstallPpi (PpiList);+ ASSERT_EFI_ERROR (Status);++ retu= rn EFI_SUCCESS;+}diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAcce= ss/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf b/Silicon/Intel/IntelS= iliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.i= nf new file mode 100644 index 000000000000..160210d429d9 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAcce +++ ssLibSmramc/PeiSmmAccessLib.inf @@ -0,0 +1,36 @@ +## @file+# Library description file for the SmmAccess PPI+#+# Copyright (c= ) 2019, Intel Corporation. All rights reserved.
+# SPDX-License-Identifi= er: BSD-2-Clause-Patent+#+##++[Defines]+ INF_VERSION = =3D 0x00010017+ BASE_NAME =3D PeiSmmAccessLibSmramc+ = FILE_GUID =3D 3D28FD4B-F46F-4E24-88AA-9DA09C51BE87+ = VERSION_STRING =3D 1.0+ MODULE_TYPE =3D= PEIM+ LIBRARY_CLASS =3D SmmAccessLib++[LibraryClasses]+ = BaseMemoryLib+ MemoryAllocationLib+ DebugLib+ HobLib+ PciSegmentLib+ = PeiServicesLib++[Packages]+ MdePkg/MdePkg.dec+ IntelSiliconPkg/IntelSilic= onPkg.dec++[Sources]+ PeiSmmAccessLib.c++[Ppis]+ gEfiPeiMmAccessPpiGuid = ## PRODUCES++[Guids]+ gEfiSmmSmramMemoryGuid--=20 2.37.2