* [edk2-devel][edk2-platforms][PATCH v2 0/6] Implement S3 resume
@ 2022-09-06 17:02 Benjamin Doron
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 1/6] {Platform,Silicon}/Intel: Move PcdAcpiBaseAddress definition Benjamin Doron
` (5 more replies)
0 siblings, 6 replies; 17+ messages in thread
From: Benjamin Doron @ 2022-09-06 17:02 UTC (permalink / raw)
To: devel
MinPlatform is an open-source EDK2 firmware project that can boot some
mainstream boards. However, it lacked working support for S3 resume, an
important feature for mobile platforms, which means that its
applicability as-is to mainstream use is limited. Therefore, I have now
implemented working S3 resume support on MinPlatform. This patch series
comprises a majority of one of my work products for GSoC 2022.
The BootScript-related modules are EDK2 open-source and fairly
straightforward to include. However, the partial dependency
PiSmmCommunicationPei (for signalling SMM) creates a dependency on both
the SmmAccess and SmmControl PPIs, so these are implemented here as
libraries, ported from the DXE drivers. As the register definitions are
generic, one library shim is implemented for compatibility, so the
library can be generic too. SmmAccess shall be required regardless of
SMM signalling, for the LockBox.
Like all boots, S3 resume will require working DRAM. To my
understanding, we do not need to parse the memory map HOBs again, so
some memory is allocated in DXE phase (to reserve it), the address
stashed in a variable and consumed on S3 resume flows. Some
optimisation can be performed here, regarding how much is necessary.
Stashing in a variable is imperfect, but the details must be available
without DRAM. As the FSP HOBs are published later, SmmAccess cannot be
used to retrieve from the LockBox.
Per my suspicions, notes from my mentors, Nate and Ankit, and the
coreboot code, the PAMs are opened for access to the AP wake vectors.
Presently, all are opened, more research can be performed here.
As noted, either FSP or PiSmmCpuDxeSmm can apply boot CPU structures
(GDT, IDT, MTRRs, etc). Per my research and findings by my mentors, the
closed-source module CpuInitDxe would be required, so this
implementation includes CpuS3DataDxe and open-source code will perform
this task instead.
Unfortunately, board-specific code has some tasks to perform too. I've
implemented these for Kabylake, the platform I can test. This includes
detecting the boot mode, policy (memory overwrite is contraindicated,
do not pass a VBT so FSP does not initialise graphics again) and
ensuring a special provision, if desired, for debugging
BootScriptExecutorDxe.
One major bug that blocked progress was simply specific to debugging.
DebugLibReportStatusCode should not be used for that module, because
RSC has uninstalled the serial port handler at end-of-BS. Furthermore,
it's obvious that the boot services are now unavailable. So,
DebugLibSerialPort should be used. As an aside, due to AutoGen ordering,
gBS cannot be used in SerialPortInitialize(). What really makes this
module a unique case is the fact that it's behaviour is very like
runtime drivers. For the integrity of the platform's security, the
module is copied to the LockBox at DxeSmmReadyToLock. This caused one
major bug that was blocking progress: libraries cannot attempt to
modify globals (the data section) with end-of-BS events; they will
never reach the true copy. So, rather than using flags to control code
flow, it must be coded this way instead. For instance, there is now a
special variant of I2cHdmiDebugSerialPortLib that does not use gBS in
SerialPortWrite().
Previous revisions of this patch-set tested on my Aspire VN7-572G
(Skylake). It's my belief and intention that this implementation be
ready for other platforms too (some Intel-specific assumptions made),
with a minimum of porting effort, though readying for some debugging is
recommended.
Some potential bugs include:
- Power failure is being set (PMC PWR_FLR), so BootMode == 0x0. This bit
is RW/1C, so mitigate it. Until finalised and I close the laptop
chassis, I don't know if this is a bug in Kabylake's PchPmcLib.
- Very early in testing I saw a memory init error, which means that
self-refresh failed. A BaseMemoryTest() predictably failed too,
inserted before the PEI core installs memory. Either this was fixed
in the code as I finished the implementation, or it's a bug. A major
difference in build options is SerialPortSpiFlash ->
I2cHdmiDebugSerialPortLib, but this seemed irrelevant. If it's simply
the finalised implementation, I think this isn't worth a diff against
the reflog.
Benjamin Doron (6):
{Platform,Silicon}/Intel: Move PcdAcpiBaseAddress definition
IntelSiliconPkg/Feature/SmmAccess: Implement PPI with chipset support
IntelSiliconPkg/Feature/SmmControl: Implement PPI with chipset support
S3FeaturePkg: Implement working S3 resume
MinPlatformPkg: Implement working S3 resume
KabylakeOpenBoardPkg: Example of board S3
.../S3FeaturePkg/Include/PostMemory.fdf | 13 +
.../S3FeaturePkg/Include/PreMemory.fdf | 8 +-
.../S3FeaturePkg/Include/S3Feature.dsc | 38 +-
.../S3FeaturePkg/S3Dxe/S3Dxe.c | 155 +++++++
.../S3FeaturePkg/S3Dxe/S3Dxe.inf | 49 ++
.../S3FeaturePkg/S3Pei/S3Pei.c | 83 +++-
.../S3FeaturePkg/S3Pei/S3Pei.inf | 8 +-
.../CometlakeURvp/OpenBoardPkgPcd.dsc | 1 +
.../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
.../PeiFspMiscUpdUpdateLib.c | 12 +-
.../PeiSaPolicyUpdate.c | 12 +-
.../PeiAspireVn7Dash572GInitPreMemLib.c | 61 ++-
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 3 +
.../AspireVn7Dash572G/OpenBoardPkg.dsc | 21 +
.../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 17 +-
.../PeiSiliconPolicyUpdateLib.c | 11 +-
.../PeiSiliconPolicyUpdateLib.inf | 1 +
.../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
.../PeiFspMiscUpdUpdateLib.c | 11 +-
.../PeiSaPolicyUpdate.c | 12 +-
.../BasePlatformHookLib.inf | 2 +-
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 +
.../BoardInitLib/PeiGalagoPro3InitPreMemLib.c | 27 +-
.../PeiMultiBoardInitPreMemLib.inf | 1 +
.../GalagoPro3/OpenBoardPkg.dsc | 15 +
.../GalagoPro3/OpenBoardPkgPcd.dsc | 3 +-
.../PeiFspMiscUpdUpdateLib.c | 12 +-
.../PeiSaPolicyUpdate.c | 12 +-
.../BasePlatformHookLib.inf | 2 +-
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 +
.../PeiKabylakeRvp3InitPreMemLib.c | 27 +-
.../PeiMultiBoardInitPreMemLib.inf | 1 +
.../KabylakeRvp3/OpenBoardPkg.dsc | 12 +
.../KabylakeRvp3/OpenBoardPkgPcd.dsc | 3 +-
.../PeiSiliconPolicyUpdateLib.c | 11 +-
.../PeiSiliconPolicyUpdateLib.inf | 1 +
.../FspWrapperHobProcessLib.c | 69 ++-
.../PeiFspWrapperHobProcessLib.inf | 2 +
.../Include/AcpiS3MemoryNvData.h | 22 +
.../Include/Dsc/CorePeiInclude.dsc | 2 +
.../Include/Fdf/CorePostMemoryInclude.fdf | 2 +
.../TigerlakeURvp/OpenBoardPkgPcd.dsc | 1 +
.../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
.../UpXtreme/OpenBoardPkgPcd.dsc | 1 +
.../WhiskeylakeURvp/OpenBoardPkgPcd.dsc | 1 +
.../CoffeelakeSiliconPkg.dsc | 1 +
.../PeiSiliconInitLib/PeiSiliconInitLib.inf | 5 +-
.../PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf | 3 +-
.../PeiDxeSmmPmcPrivateLibCnl.inf | 2 +-
Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec | 1 -
.../PeiSmmAccessLibSmramc/PeiSmmAccessLib.c | 430 ++++++++++++++++++
.../PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf | 36 ++
.../PeiSmmControlLib/PeiSmmControlLib.c | 309 +++++++++++++
.../PeiSmmControlLib/PeiSmmControlLib.inf | 34 ++
.../Include/Library/SmmControlLib.h | 26 ++
.../Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 8 +
.../KabylakeSiliconPkg/KabylakeSiliconPkg.dsc | 1 +
.../PeiSiliconInitLib/PeiSiliconInitLib.inf | 2 +-
.../PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf | 3 +-
.../PeiPchPolicyLib/PeiPchPolicyLib.inf | 2 +-
.../Pch/Library/PeiSpiLib/PeiSpiLib.inf | 2 +-
Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec | 1 -
.../PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf | 3 +-
.../PeiDxeSmmPmcPrivateLibVer2.inf | 3 +-
Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec | 1 -
.../TigerlakeSiliconPkg.dsc | 1 +
66 files changed, 1557 insertions(+), 70 deletions(-)
create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
create mode 100644 Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.c
create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf
create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.c
create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf
create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h
--
2.37.2
^ permalink raw reply [flat|nested] 17+ messages in thread
* [edk2-devel][edk2-platforms][PATCH v2 1/6] {Platform,Silicon}/Intel: Move PcdAcpiBaseAddress definition
2022-09-06 17:02 [edk2-devel][edk2-platforms][PATCH v2 0/6] Implement S3 resume Benjamin Doron
@ 2022-09-06 17:02 ` Benjamin Doron
2022-09-07 22:50 ` Isaac Oram
2022-09-07 22:57 ` Chaganty, Rangasai V
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 2/6] IntelSiliconPkg/Feature/SmmAccess: Implement PPI with chipset support Benjamin Doron
` (4 subsequent siblings)
5 siblings, 2 replies; 17+ messages in thread
From: Benjamin Doron @ 2022-09-06 17:02 UTC (permalink / raw)
To: devel
Cc: Rangasai V Chaganty, Isaac Oram, Nate DeSimone, Ankit Sinha,
Ray Ni, Chasel Chiu, Heng Luo
All these platforms have an ABase, so move the definition to enable
common silicon code in IntelSiliconPkg. Otherwise, library shims would
be required, because PCDs are GUID-ed and package DEC specific.
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Heng Luo <heng.luo@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc | 1 +
.../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
.../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 1 +
.../KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
.../Library/BasePlatformHookLib/BasePlatformHookLib.inf | 2 +-
.../KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc | 1 +
.../Library/BasePlatformHookLib/BasePlatformHookLib.inf | 2 +-
.../KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 1 +
.../TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc | 1 +
.../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
.../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 1 +
.../WhiskeylakeURvp/OpenBoardPkgPcd.dsc | 1 +
Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc | 1 +
.../Library/PeiSiliconInitLib/PeiSiliconInitLib.inf | 5 +++--
.../Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf | 3 ++-
.../PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf | 2 +-
Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec | 1 -
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 4 ++++
Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc | 1 +
.../Library/PeiSiliconInitLib/PeiSiliconInitLib.inf | 2 +-
.../Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf | 3 ++-
.../Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf | 2 +-
.../KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf | 2 +-
Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec | 1 -
.../IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf | 3 ++-
.../PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf | 3 ++-
Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec | 1 -
Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc | 1 +
28 files changed, 34 insertions(+), 18 deletions(-)
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
index 79924f1fda7f..81dc0747fab8 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
@@ -65,6 +65,7 @@
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800
#
# PCIe Reserved Memory Space Range
#
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
index e3fdd3981653..c4dd863c3ee8 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
@@ -49,7 +49,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES
[FixedPcd]
- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
[Sources]
TbtSmiHandler.h
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
index a4ea524e26bc..3ed7aa0a2b10 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
@@ -241,6 +241,7 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
!endif
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800
gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
index e6c185a4bd91..13116488eaa0 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
@@ -46,7 +46,7 @@
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES
[FixedPcd]
- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
[Sources]
TbtSmiHandler.h
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
index 1de10aa0080f..5f65f02a9f64 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
@@ -35,7 +35,7 @@
KabylakeSiliconPkg/SiPkg.dec
[Pcd]
- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSUMES
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
index c6b9df842936..ec23c691b2fe 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
@@ -194,6 +194,7 @@
gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
!endif
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800
!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
!endif
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
index 7a5e290657f2..8bdf13b1ce11 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
@@ -35,7 +35,7 @@
KabylakeSiliconPkg/SiPkg.dec
[Pcd]
- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSUMES
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
index 2f7765e58a69..cfd032814850 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
@@ -194,6 +194,7 @@
gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
!endif
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800
!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
!endif
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
index 2fd6d0c50e05..2fb2e1ce58f4 100644
--- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
@@ -117,6 +117,7 @@
#!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
#!endif
+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800
gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000
#
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
index bfe299d73374..83ebc790aeb4 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
@@ -49,7 +49,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES
[FixedPcd]
- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
[Sources]
TbtSmiHandler.h
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
index a7e9a41e2c34..dbe068d0c123 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
@@ -65,6 +65,7 @@
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800
[PcdsFeatureFlag.common]
######################################
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
index daf5411ac358..451926d67190 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
@@ -65,6 +65,7 @@
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800
[PcdsFeatureFlag.common]
######################################
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
index c5f10492edc8..e62e37cda036 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
@@ -42,6 +42,7 @@ gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE
[PcdsFixedAtBuild.common]
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xE0000000
gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength |0x10000000
+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress |0x1800
gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin |10
gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax |18
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
index 1534a24dd240..432d4c0c2656 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
@@ -32,6 +32,7 @@
[Packages]
MdePkg/MdePkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
CoffeelakeSiliconPkg/SiPkg.dec
[Sources]
@@ -42,5 +43,5 @@
gTcoWdtHobGuid ## CONSUMES
[Pcd]
- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
- gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMES
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
index 78e212eeb0fd..61778ed5a066 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
@@ -32,11 +32,12 @@ BaseMemoryLib
[Packages]
MdePkg/MdePkg.dec
+IntelSiliconPkg/IntelSiliconPkg.dec
CoffeelakeSiliconPkg/SiPkg.dec
[Pcd]
-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress
[Sources]
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf
index 573acfc25e31..1f84337afafb 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf
@@ -39,7 +39,7 @@ CoffeelakeSiliconPkg/SiPkg.dec
IntelSiliconPkg/IntelSiliconPkg.dec
[Pcd]
-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress
[Sources]
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
index efc2d8788168..ca3e83bd61da 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
@@ -516,7 +516,6 @@ gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFED10000|UINT64|0x00010030
## This value is used to set the base address of PCH devices
gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031
gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010034
-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035
## 32KB window
gSiPkgTokenSpaceGuid.PcdMchMmioSize|0x8000|UINT32|0x50000000
diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index c36d130a0197..deefdc55b5d6 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -147,6 +147,10 @@
# @Prompt Error code for VTd error.
gIntelSiliconPkgTokenSpaceGuid.PcdErrorCodeVTdError|0x02008000|UINT32|0x00000005
+ ## ABase I/O address.<BR><BR>
+ # @Prompt ABase I/O address.
+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x0|UINT16|0x0000000D
+
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
## This is the GUID of the FFS which contains the Graphics Video BIOS Table (VBT)
# The VBT content is stored as a RAW section which is consumed by GOP PEI/UEFI driver.
diff --git a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc b/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc
index d980a2c5369a..ff7728279a08 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc
+++ b/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc
@@ -48,6 +48,7 @@ gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE
[PcdsFixedAtBuild.common]
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xE0000000
gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength |0x10000000
+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress |0x1800
#
# This DSC mainly for GreenH Silicon code build so PciExpressBaseAddress can be FixedAtBuild
#
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
index 3b94a02e6bf4..32205bb04f64 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
@@ -46,7 +46,7 @@
SiliconInitPreMem.c
[Pcd]
- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMES
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf
index 1e6103f4ca38..5ae3b4d6256a 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf
@@ -30,11 +30,12 @@ PchCycleDecodingLib
[Packages]
MdePkg/MdePkg.dec
+IntelSiliconPkg/IntelSiliconPkg.dec
KabylakeSiliconPkg/SiPkg.dec
[Pcd]
-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress
[Sources]
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf
index a5ccf4698b7d..41eaffe52e66 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf
@@ -35,7 +35,7 @@ KabylakeSiliconPkg/SiPkg.dec
IntelSiliconPkg/IntelSiliconPkg.dec
[Pcd]
-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress
gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress
gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable
gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf
index ba57c44e1e12..f912d6e76d4a 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf
@@ -39,7 +39,7 @@
PeiSpiLib.c
[Pcd]
- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
[Ppis]
gPchSpi2PpiGuid ## PRODUCES
diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
index d9ae9f6dfd91..6c9af567f5ee 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
+++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
@@ -497,7 +497,6 @@ gSiPkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|40|UINT8|0x0001002f
gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFED10000|UINT64|0x00010030
gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031
gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010034
-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035
## 32KB window
gSiPkgTokenSpaceGuid.PcdMchMmioSize|0x8000|UINT32|0x50000000
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
index eba6db767c5c..c52a157c7d39 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
+++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
@@ -31,11 +31,12 @@ BaseMemoryLib
[Packages]
MdePkg/MdePkg.dec
+IntelSiliconPkg/IntelSiliconPkg.dec
TigerlakeSiliconPkg/SiPkg.dec
[Pcd]
-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress
gSiPkgTokenSpaceGuid.PcdTcoBaseAddress
[Sources]
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf
index 2bd57b79f035..32a4e9a07a76 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf
+++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf
@@ -27,11 +27,12 @@ PmcLib
[Packages]
MdePkg/MdePkg.dec
+IntelSiliconPkg/IntelSiliconPkg.dec
TigerlakeSiliconPkg/SiPkg.dec
[Pcd]
-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress
[FixedPcd]
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec b/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec
index 7cdbb3748155..991ca1555bf7 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec
+++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec
@@ -976,7 +976,6 @@ gMeConfigSpaceGuid.PcdHeciTimeoutsEnabled|TRUE|BOOLEAN|0x50000002
## This value is used to set the base address of PCH devices
gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031
gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010033
-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035
## Stack size in the temporary RAM.
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc b/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc
index 36df41f09fb4..f11305d266cb 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc
+++ b/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc
@@ -60,6 +60,7 @@ gSiPkgTokenSpaceGuid.PcdSpaEnable |FALSE
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xC0000000
gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress |gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength |0x10000000
+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress |0x1800
[PcdsDynamicDefault.common]
gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength |0x10000000
--
2.37.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [edk2-devel][edk2-platforms][PATCH v2 2/6] IntelSiliconPkg/Feature/SmmAccess: Implement PPI with chipset support
2022-09-06 17:02 [edk2-devel][edk2-platforms][PATCH v2 0/6] Implement S3 resume Benjamin Doron
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 1/6] {Platform,Silicon}/Intel: Move PcdAcpiBaseAddress definition Benjamin Doron
@ 2022-09-06 17:02 ` Benjamin Doron
2022-09-07 23:49 ` Isaac Oram
[not found] ` <1712B8F6079EA3A9.20240@groups.io>
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 3/6] IntelSiliconPkg/Feature/SmmControl: " Benjamin Doron
` (3 subsequent siblings)
5 siblings, 2 replies; 17+ messages in thread
From: Benjamin Doron @ 2022-09-06 17:02 UTC (permalink / raw)
To: devel; +Cc: Nate DeSimone, Ankit Sinha, Ray Ni, Rangasai V Chaganty,
Isaac Oram
SMRAM must be opened to retrieve the lockbox for S3, and SMM
communication depends on this PPI. For security purposes, SMRAM
lock must be performed before EndOfPei (although FSP notify performs
lockdown too).
It seems to me that this library is generic and applicable to all Intel
platforms in the tree using the MCH SMRAMC register.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../PeiSmmAccessLibSmramc/PeiSmmAccessLib.c | 430 ++++++++++++++++++
.../PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf | 36 ++
2 files changed, 466 insertions(+)
create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.c
create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.c b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.c
new file mode 100644
index 000000000000..5b472bf86abf
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.c
@@ -0,0 +1,430 @@
+/** @file
+ This is to publish the SMM Access Ppi instance.
+
+ Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/HobLib.h>
+#include <Uefi/UefiBaseType.h>
+#include <Guid/SmramMemoryReserve.h>
+
+#include <Ppi/MmAccess.h>
+#include <IndustryStandard/Pci22.h>
+
+#define SMM_ACCESS_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('4', '5', 's', 'a')
+
+///
+/// Private data
+///
+typedef struct {
+ UINTN Signature;
+ EFI_HANDLE Handle;
+ EFI_PEI_MM_ACCESS_PPI SmmAccess;
+ //
+ // Local Data for SMM Access interface goes here
+ //
+ UINTN NumberRegions;
+ EFI_SMRAM_DESCRIPTOR *SmramDesc;
+} SMM_ACCESS_PRIVATE_DATA;
+
+#define SMM_ACCESS_PRIVATE_DATA_FROM_THIS(a) \
+ CR (a, \
+ SMM_ACCESS_PRIVATE_DATA, \
+ SmmAccess, \
+ SMM_ACCESS_PRIVATE_DATA_SIGNATURE \
+ )
+
+//
+// Common registers:
+//
+// DEVICE 0 (Memory Controller Hub)
+//
+#define SA_MC_BUS 0x00
+#define SA_MC_DEV 0x00
+#define SA_MC_FUN 0x00
+///
+/// Description:
+/// The SMRAMC register controls how accesses to Compatible SMRAM spaces are treated. The Open, Close and Lock bits function only when G_SMRAME bit is set to 1. Also, the Open bit must be reset before the Lock bit is set.
+///
+#define R_SA_SMRAMC (0x88)
+#define B_SA_SMRAMC_D_LCK_MASK (0x10)
+#define B_SA_SMRAMC_D_CLS_MASK (0x20)
+#define B_SA_SMRAMC_D_OPEN_MASK (0x40)
+
+/**
+ This routine accepts a request to "open" a region of SMRAM. The
+ region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.
+ The use of "open" means that the memory is visible from all PEIM
+ and SMM agents.
+
+ @param[in] PeiServices - General purpose services available to every PEIM.
+ @param[in] This - Pointer to the SMM Access Interface.
+ @param[in] DescriptorIndex - Region of SMRAM to Open.
+
+ @retval EFI_SUCCESS - The region was successfully opened.
+ @retval EFI_DEVICE_ERROR - The region could not be opened because locked by
+ chipset.
+ @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Open (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_MM_ACCESS_PPI *This,
+ IN UINTN DescriptorIndex
+ )
+{
+ SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+ UINT8 Index;
+ UINT64 Address;
+ UINT8 SmramControl;
+
+ SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);
+ if (DescriptorIndex >= SmmAccess->NumberRegions) {
+ DEBUG ((DEBUG_WARN, "SMRAM region out of range\n"));
+
+ return EFI_INVALID_PARAMETER;
+ } else if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_LOCKED) {
+ //
+ // Cannot open a "locked" region
+ //
+ DEBUG ((DEBUG_WARN, "Cannot open a locked SMRAM region\n"));
+
+ return EFI_DEVICE_ERROR;
+ }
+
+ ///
+ /// BEGIN CHIPSET CODE
+ ///
+ ///
+ /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit)
+ ///
+ Address = PCI_SEGMENT_LIB_ADDRESS (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC);
+ SmramControl = PciSegmentRead8 (Address);
+ ///
+ /// Is SMRAM locked?
+ ///
+ if ((SmramControl & B_SA_SMRAMC_D_LCK_MASK) != 0) {
+ ///
+ /// Cannot Open a locked region
+ ///
+ for (Index = 0; Index < SmmAccess->NumberRegions; Index++) {
+ SmmAccess->SmramDesc[Index].RegionState |= EFI_SMRAM_LOCKED;
+ }
+ DEBUG ((DEBUG_WARN, "Cannot open a locked SMRAM region\n"));
+ return EFI_DEVICE_ERROR;
+ }
+ ///
+ /// Open SMRAM region
+ ///
+ SmramControl |= B_SA_SMRAMC_D_OPEN_MASK;
+ SmramControl &= ~(B_SA_SMRAMC_D_CLS_MASK);
+
+ PciSegmentWrite8 (Address, SmramControl);
+ ///
+ /// END CHIPSET CODE
+ ///
+
+ SmmAccess->SmramDesc[DescriptorIndex].RegionState &= (UINT64) ~(EFI_SMRAM_CLOSED | EFI_ALLOCATED);
+ SmmAccess->SmramDesc[DescriptorIndex].RegionState |= (UINT64) EFI_SMRAM_OPEN;
+ SmmAccess->SmmAccess.OpenState = TRUE;
+ return EFI_SUCCESS;
+}
+
+/**
+ This routine accepts a request to "close" a region of SMRAM. This is valid for
+ compatible SMRAM region.
+
+ @param[in] PeiServices - General purpose services available to every PEIM.
+ @param[in] This - Pointer to the SMM Access Interface.
+ @param[in] DescriptorIndex - Region of SMRAM to Close.
+
+ @retval EFI_SUCCESS - The region was successfully closed.
+ @retval EFI_DEVICE_ERROR - The region could not be closed because locked by
+ chipset.
+ @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Close (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_MM_ACCESS_PPI *This,
+ IN UINTN DescriptorIndex
+ )
+{
+ SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+ BOOLEAN OpenState;
+ UINT8 Index;
+ UINT64 Address;
+ UINT8 SmramControl;
+
+ SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);
+ if (DescriptorIndex >= SmmAccess->NumberRegions) {
+ DEBUG ((DEBUG_WARN, "SMRAM region out of range\n"));
+
+ return EFI_INVALID_PARAMETER;
+ } else if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_LOCKED) {
+ //
+ // Cannot close a "locked" region
+ //
+ DEBUG ((DEBUG_WARN, "Cannot close a locked SMRAM region\n"));
+
+ return EFI_DEVICE_ERROR;
+ }
+
+ if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_CLOSED) {
+ return EFI_DEVICE_ERROR;
+ }
+
+ ///
+ /// BEGIN CHIPSET CODE
+ ///
+ ///
+ /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit)
+ ///
+ Address = PCI_SEGMENT_LIB_ADDRESS (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC);
+ SmramControl = PciSegmentRead8 (Address);
+ ///
+ /// Is SMRAM locked?
+ ///
+ if ((SmramControl & B_SA_SMRAMC_D_LCK_MASK) != 0) {
+ ///
+ /// Cannot Close a locked region
+ ///
+ for (Index = 0; Index < SmmAccess->NumberRegions; Index++) {
+ SmmAccess->SmramDesc[Index].RegionState |= EFI_SMRAM_LOCKED;
+ }
+ DEBUG ((DEBUG_WARN, "Cannot close a locked SMRAM region\n"));
+ return EFI_DEVICE_ERROR;
+ }
+ ///
+ /// Close SMRAM region
+ ///
+ SmramControl &= ~(B_SA_SMRAMC_D_OPEN_MASK);
+
+ PciSegmentWrite8 (Address, SmramControl);
+ ///
+ /// END CHIPSET CODE
+ ///
+
+ SmmAccess->SmramDesc[DescriptorIndex].RegionState &= (UINT64) ~EFI_SMRAM_OPEN;
+ SmmAccess->SmramDesc[DescriptorIndex].RegionState |= (UINT64) (EFI_SMRAM_CLOSED | EFI_ALLOCATED);
+
+ //
+ // Find out if any regions are still open
+ //
+ OpenState = FALSE;
+ for (Index = 0; Index < SmmAccess->NumberRegions; Index++) {
+ if ((SmmAccess->SmramDesc[Index].RegionState & EFI_SMRAM_OPEN) == EFI_SMRAM_OPEN) {
+ OpenState = TRUE;
+ }
+ }
+
+ SmmAccess->SmmAccess.OpenState = OpenState;
+ return EFI_SUCCESS;
+}
+
+/**
+ This routine accepts a request to "lock" SMRAM. The
+ region could be legacy AB or TSEG near top of physical memory.
+ The use of "lock" means that the memory can no longer be opened
+ to PEIM.
+
+ @param[in] PeiServices - General purpose services available to every PEIM.
+ @param[in] This - Pointer to the SMM Access Interface.
+ @param[in] DescriptorIndex - Region of SMRAM to Lock.
+
+ @retval EFI_SUCCESS - The region was successfully locked.
+ @retval EFI_DEVICE_ERROR - The region could not be locked because at least
+ one range is still open.
+ @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Lock (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_MM_ACCESS_PPI *This,
+ IN UINTN DescriptorIndex
+ )
+{
+ SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+ UINT64 Address;
+ UINT8 SmramControl;
+
+ SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);
+ if (DescriptorIndex >= SmmAccess->NumberRegions) {
+ DEBUG ((DEBUG_WARN, "SMRAM region out of range\n"));
+
+ return EFI_INVALID_PARAMETER;
+ } else if (SmmAccess->SmmAccess.OpenState) {
+ DEBUG ((DEBUG_WARN, "Cannot lock SMRAM when SMRAM regions are still open\n"));
+
+ return EFI_DEVICE_ERROR;
+ }
+
+ SmmAccess->SmramDesc[DescriptorIndex].RegionState |= (UINT64) EFI_SMRAM_LOCKED;
+ SmmAccess->SmmAccess.LockState = TRUE;
+
+ ///
+ /// BEGIN CHIPSET CODE
+ ///
+ ///
+ /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit)
+ ///
+ Address = PCI_SEGMENT_LIB_ADDRESS (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC);
+ SmramControl = PciSegmentRead8 (Address);
+
+ ///
+ /// Lock the SMRAM
+ ///
+ SmramControl |= B_SA_SMRAMC_D_LCK_MASK;
+
+ PciSegmentWrite8 (Address, SmramControl);
+ ///
+ /// END CHIPSET CODE
+ ///
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This routine services a user request to discover the SMRAM
+ capabilities of this platform. This will report the possible
+ ranges that are possible for SMRAM access, based upon the
+ memory controller capabilities.
+
+ @param[in] PeiServices - General purpose services available to every PEIM.
+ @param[in] This - Pointer to the SMRAM Access Interface.
+ @param[in, out] SmramMapSize - Pointer to the variable containing size of the
+ buffer to contain the description information.
+ @param[in, out] SmramMap - Buffer containing the data describing the Smram
+ region descriptors.
+
+ @retval EFI_BUFFER_TOO_SMALL - The user did not provide a sufficient buffer.
+ @retval EFI_SUCCESS - The user provided a sufficiently-sized buffer.
+**/
+EFI_STATUS
+EFIAPI
+GetCapabilities (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_MM_ACCESS_PPI *This,
+ IN OUT UINTN *SmramMapSize,
+ IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
+ )
+{
+ EFI_STATUS Status;
+ SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+ UINTN NecessaryBufferSize;
+
+ SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);
+ NecessaryBufferSize = SmmAccess->NumberRegions * sizeof (EFI_SMRAM_DESCRIPTOR);
+ if (*SmramMapSize < NecessaryBufferSize) {
+ DEBUG ((DEBUG_WARN, "SMRAM Map Buffer too small\n"));
+
+ Status = EFI_BUFFER_TOO_SMALL;
+ } else {
+ CopyMem (SmramMap, SmmAccess->SmramDesc, NecessaryBufferSize);
+ Status = EFI_SUCCESS;
+ }
+
+ *SmramMapSize = NecessaryBufferSize;
+ return Status;
+}
+
+/**
+ This function is to install an SMM Access PPI
+ - <b>Introduction</b> \n
+ An API to install an instance of EFI_PEI_MM_ACCESS_PPI. This PPI is commonly used to control SMM mode memory access for S3 resume.
+
+ @retval EFI_SUCCESS - Ppi successfully started and installed.
+ @retval EFI_NOT_FOUND - Ppi can't be found.
+ @retval EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to initialize the driver.
+**/
+EFI_STATUS
+EFIAPI
+PeiInstallSmmAccessPpi (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ EFI_PEI_PPI_DESCRIPTOR *PpiList;
+ EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *DescriptorBlock;
+ SMM_ACCESS_PRIVATE_DATA *SmmAccessPrivate;
+ VOID *HobList;
+
+ //
+ // Initialize private data
+ //
+ SmmAccessPrivate = AllocateZeroPool (sizeof (*SmmAccessPrivate));
+ ASSERT (SmmAccessPrivate != NULL);
+ if (SmmAccessPrivate == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ PpiList = AllocateZeroPool (sizeof (*PpiList));
+ ASSERT (PpiList != NULL);
+ if (PpiList == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SmmAccessPrivate->Signature = SMM_ACCESS_PRIVATE_DATA_SIGNATURE;
+ SmmAccessPrivate->Handle = NULL;
+
+ //
+ // Get Hob list
+ //
+ HobList = GetFirstGuidHob (&gEfiSmmSmramMemoryGuid);
+ if (HobList == NULL) {
+ DEBUG ((DEBUG_WARN, "SmramMemoryReserve HOB not found\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ DescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) ((UINT8 *) HobList + sizeof (EFI_HOB_GUID_TYPE));
+
+ //
+ // Alloc space for SmmAccessPrivate->SmramDesc
+ //
+ SmmAccessPrivate->SmramDesc = AllocateZeroPool ((DescriptorBlock->NumberOfSmmReservedRegions) * sizeof (EFI_SMRAM_DESCRIPTOR));
+ if (SmmAccessPrivate->SmramDesc == NULL) {
+ DEBUG ((DEBUG_WARN, "Alloc SmmAccessPrivate->SmramDesc fail.\n"));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ DEBUG ((DEBUG_INFO, "Alloc SmmAccessPrivate->SmramDesc success.\n"));
+
+ //
+ // use the hob to publish SMRAM capabilities
+ //
+ for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {
+ SmmAccessPrivate->SmramDesc[Index].PhysicalStart = DescriptorBlock->Descriptor[Index].PhysicalStart;
+ SmmAccessPrivate->SmramDesc[Index].CpuStart = DescriptorBlock->Descriptor[Index].CpuStart;
+ SmmAccessPrivate->SmramDesc[Index].PhysicalSize = DescriptorBlock->Descriptor[Index].PhysicalSize;
+ SmmAccessPrivate->SmramDesc[Index].RegionState = DescriptorBlock->Descriptor[Index].RegionState;
+ }
+
+ SmmAccessPrivate->NumberRegions = Index;
+ SmmAccessPrivate->SmmAccess.Open = Open;
+ SmmAccessPrivate->SmmAccess.Close = Close;
+ SmmAccessPrivate->SmmAccess.Lock = Lock;
+ SmmAccessPrivate->SmmAccess.GetCapabilities = GetCapabilities;
+ SmmAccessPrivate->SmmAccess.LockState = FALSE;
+ SmmAccessPrivate->SmmAccess.OpenState = FALSE;
+
+ //
+ // Install PPI
+ //
+ PpiList->Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
+ PpiList->Guid = &gEfiPeiMmAccessPpiGuid;
+ PpiList->Ppi = &SmmAccessPrivate->SmmAccess;
+
+ Status = PeiServicesInstallPpi (PpiList);
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf
new file mode 100644
index 000000000000..160210d429d9
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf
@@ -0,0 +1,36 @@
+## @file
+# Library description file for the SmmAccess PPI
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiSmmAccessLibSmramc
+ FILE_GUID = 3D28FD4B-F46F-4E24-88AA-9DA09C51BE87
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = SmmAccessLib
+
+[LibraryClasses]
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+ HobLib
+ PciSegmentLib
+ PeiServicesLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+ PeiSmmAccessLib.c
+
+[Ppis]
+ gEfiPeiMmAccessPpiGuid ## PRODUCES
+
+[Guids]
+ gEfiSmmSmramMemoryGuid
--
2.37.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [edk2-devel][edk2-platforms][PATCH v2 3/6] IntelSiliconPkg/Feature/SmmControl: Implement PPI with chipset support
2022-09-06 17:02 [edk2-devel][edk2-platforms][PATCH v2 0/6] Implement S3 resume Benjamin Doron
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 1/6] {Platform,Silicon}/Intel: Move PcdAcpiBaseAddress definition Benjamin Doron
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 2/6] IntelSiliconPkg/Feature/SmmAccess: Implement PPI with chipset support Benjamin Doron
@ 2022-09-06 17:02 ` Benjamin Doron
2022-09-07 23:50 ` Isaac Oram
[not found] ` <1712B905B760092F.20378@groups.io>
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 4/6] S3FeaturePkg: Implement working S3 resume Benjamin Doron
` (2 subsequent siblings)
5 siblings, 2 replies; 17+ messages in thread
From: Benjamin Doron @ 2022-09-06 17:02 UTC (permalink / raw)
To: devel; +Cc: Nate DeSimone, Ankit Sinha, Ray Ni, Rangasai V Chaganty,
Isaac Oram
S3 resume may require communication with SMM, for which we need the
SmmControl PPI. Therefore, port the DXE drivers to a library, like there
is for SMM Access.
Tested, working on Kabylake. Further testing required after the refactor
for compatibility.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../PeiSmmControlLib/PeiSmmControlLib.c | 309 ++++++++++++++++++
.../PeiSmmControlLib/PeiSmmControlLib.inf | 34 ++
.../Include/Library/SmmControlLib.h | 26 ++
.../Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 4 +
4 files changed, 373 insertions(+)
create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.c
create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf
create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.c b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.c
new file mode 100644
index 000000000000..cc6c7f8fe672
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.c
@@ -0,0 +1,309 @@
+/** @file
+ This is to publish the SMM Control Ppi instance.
+
+ Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+
+#include <Ppi/MmControl.h>
+#include <IndustryStandard/Pci30.h>
+
+#define SMM_CONTROL_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('i', '4', 's', 'c')
+
+typedef struct {
+ UINTN Signature;
+ EFI_HANDLE Handle;
+ EFI_PEI_MM_CONTROL_PPI SmmControl;
+} SMM_CONTROL_PRIVATE_DATA;
+
+#define SMM_CONTROL_PRIVATE_DATA_FROM_THIS(a) \
+ CR (a, \
+ SMM_CONTROL_PRIVATE_DATA, \
+ SmmControl, \
+ SMM_CONTROL_DEV_SIGNATURE \
+ )
+
+//
+// Common registers:
+//
+//
+// APM Registers
+//
+#define R_PCH_APM_CNT 0xB2
+//
+// ACPI and legacy I/O register offsets from ACPIBASE
+//
+#define R_PCH_ACPI_PM1_STS 0x00
+#define B_PCH_ACPI_PM1_STS_PRBTNOR BIT11
+
+#define R_PCH_SMI_EN 0x30
+
+#define R_PCH_SMI_STS 0x34
+#define B_PCH_SMI_STS_APM BIT5
+#define B_PCH_SMI_EN_APMC BIT5
+#define B_PCH_SMI_EN_EOS BIT1
+#define B_PCH_SMI_EN_GBL_SMI BIT0
+
+/**
+ Trigger the software SMI
+
+ @param[in] Data The value to be set on the software SMI data port
+
+ @retval EFI_SUCCESS Function completes successfully
+**/
+EFI_STATUS
+EFIAPI
+SmmTrigger (
+ UINT8 Data
+ )
+{
+ UINT16 ABase;
+ UINT32 OutputData;
+ UINT32 OutputPort;
+
+ ABase = FixedPcdGet16 (PcdAcpiBaseAddress);
+
+ ///
+ /// Enable the APMC SMI
+ ///
+ OutputPort = ABase + R_PCH_SMI_EN;
+ OutputData = IoRead32 ((UINTN) OutputPort);
+ OutputData |= (B_PCH_SMI_EN_APMC | B_PCH_SMI_EN_GBL_SMI);
+ DEBUG (
+ (DEBUG_EVENT,
+ "The SMI Control Port at address %x will be written to %x.\n",
+ OutputPort,
+ OutputData)
+ );
+ IoWrite32 (
+ (UINTN) OutputPort,
+ (UINT32) (OutputData)
+ );
+
+ OutputPort = R_PCH_APM_CNT;
+ OutputData = Data;
+
+ ///
+ /// Generate the APMC SMI
+ ///
+ IoWrite8 (
+ (UINTN) OutputPort,
+ (UINT8) (OutputData)
+ );
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Clear the SMI status
+
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_DEVICE_ERROR Something error occurred
+**/
+EFI_STATUS
+EFIAPI
+SmmClear (
+ VOID
+ )
+{
+ UINT16 ABase;
+ UINT32 OutputData;
+ UINT32 OutputPort;
+
+ ABase = FixedPcdGet16 (PcdAcpiBaseAddress);
+
+ ///
+ /// Clear the Power Button Override Status Bit, it gates EOS from being set.
+ ///
+ OutputPort = ABase + R_PCH_ACPI_PM1_STS;
+ OutputData = B_PCH_ACPI_PM1_STS_PRBTNOR;
+ DEBUG (
+ (DEBUG_EVENT,
+ "The PM1 Status Port at address %x will be written to %x.\n",
+ OutputPort,
+ OutputData)
+ );
+ IoWrite16 (
+ (UINTN) OutputPort,
+ (UINT16) (OutputData)
+ );
+
+ ///
+ /// Clear the APM SMI Status Bit
+ ///
+ OutputPort = ABase + R_PCH_SMI_STS;
+ OutputData = B_PCH_SMI_STS_APM;
+ DEBUG (
+ (DEBUG_EVENT,
+ "The SMI Status Port at address %x will be written to %x.\n",
+ OutputPort,
+ OutputData)
+ );
+ IoWrite32 (
+ (UINTN) OutputPort,
+ (UINT32) (OutputData)
+ );
+
+ ///
+ /// Set the EOS Bit
+ ///
+ OutputPort = ABase + R_PCH_SMI_EN;
+ OutputData = IoRead32 ((UINTN) OutputPort);
+ OutputData |= B_PCH_SMI_EN_EOS;
+ DEBUG (
+ (DEBUG_EVENT,
+ "The SMI Control Port at address %x will be written to %x.\n",
+ OutputPort,
+ OutputData)
+ );
+ IoWrite32 (
+ (UINTN) OutputPort,
+ (UINT32) (OutputData)
+ );
+
+ ///
+ /// There is no need to read EOS back and check if it is set.
+ /// This can lead to a reading of zero if an SMI occurs right after the SMI_EN port read
+ /// but before the data is returned to the CPU.
+ /// SMM Dispatcher should make sure that EOS is set after all SMI sources are processed.
+ ///
+ return EFI_SUCCESS;
+}
+
+/**
+ This routine generates an SMI
+
+ @param[in] This The EFI SMM Control protocol instance
+ @param[in, out] ArgumentBuffer The buffer of argument
+ @param[in, out] ArgumentBufferSize The size of the argument buffer
+ @param[in] Periodic Periodic or not
+ @param[in] ActivationInterval Interval of periodic SMI
+
+ @retval EFI Status Describing the result of the operation
+ @retval EFI_INVALID_PARAMETER Some parameter value passed is not supported
+**/
+EFI_STATUS
+EFIAPI
+Activate (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_MM_CONTROL_PPI * This,
+ IN OUT INT8 *ArgumentBuffer OPTIONAL,
+ IN OUT UINTN *ArgumentBufferSize OPTIONAL,
+ IN BOOLEAN Periodic OPTIONAL,
+ IN UINTN ActivationInterval OPTIONAL
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Data;
+
+ if (Periodic) {
+ DEBUG ((DEBUG_WARN, "Invalid parameter\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // NOTE: Copied from Quark. Matches the usage in PiSmmCommunicationPei
+ if (ArgumentBuffer == NULL) {
+ Data = 0xFF;
+ } else {
+ if (ArgumentBufferSize == NULL || *ArgumentBufferSize != 1) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Data = *ArgumentBuffer;
+ }
+ ///
+ /// Clear any pending the APM SMI
+ ///
+ Status = SmmClear ();
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ return SmmTrigger (Data);
+}
+
+/**
+ This routine clears an SMI
+
+ @param[in] This The EFI SMM Control protocol instance
+ @param[in] Periodic Periodic or not
+
+ @retval EFI Status Describing the result of the operation
+ @retval EFI_INVALID_PARAMETER Some parameter value passed is not supported
+**/
+EFI_STATUS
+EFIAPI
+Deactivate (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_MM_CONTROL_PPI * This,
+ IN BOOLEAN Periodic OPTIONAL
+ )
+{
+ if (Periodic) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return SmmClear ();
+}
+
+/**
+ This function is to install an SMM Control PPI
+ - <b>Introduction</b> \n
+ An API to install an instance of EFI_PEI_MM_CONTROL_PPI. This PPI provides a standard
+ way for other modules to trigger software SMIs.
+
+ @retval EFI_SUCCESS - Ppi successfully started and installed.
+ @retval EFI_NOT_FOUND - Ppi can't be found.
+ @retval EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to initialize the driver.
+**/
+EFI_STATUS
+EFIAPI
+PeiInstallSmmControlPpi (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PPI_DESCRIPTOR *PpiList;
+ SMM_CONTROL_PRIVATE_DATA *SmmControlPrivate;
+
+ //
+ // Initialize private data
+ //
+ SmmControlPrivate = AllocateZeroPool (sizeof (*SmmControlPrivate));
+ ASSERT (SmmControlPrivate != NULL);
+ if (SmmControlPrivate == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ PpiList = AllocateZeroPool (sizeof (*PpiList));
+ ASSERT (PpiList != NULL);
+ if (PpiList == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SmmControlPrivate->Signature = SMM_CONTROL_PRIVATE_DATA_SIGNATURE;
+ SmmControlPrivate->Handle = NULL;
+
+ SmmControlPrivate->SmmControl.Trigger = Activate;
+ SmmControlPrivate->SmmControl.Clear = Deactivate;
+
+ //
+ // Install PPI
+ //
+ PpiList->Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);
+ PpiList->Guid = &gEfiPeiMmControlPpiGuid;
+ PpiList->Ppi = &SmmControlPrivate->SmmControl;
+
+ Status = PeiServicesInstallPpi (PpiList);
+ ASSERT_EFI_ERROR (Status);
+
+ // Unlike driver, do not disable SMIs as S3 resume continues
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf
new file mode 100644
index 000000000000..91c761366446
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf
@@ -0,0 +1,34 @@
+## @file
+# Library description file for the SmmControl PPI
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiSmmControlLib
+ FILE_GUID = F45D521A-C0DF-4283-A3CA-65AD01B479E7
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = SmmControlLib
+
+[LibraryClasses]
+ IoLib
+ DebugLib
+ MemoryAllocationLib
+ PeiServicesLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+ PeiSmmControlLib.c
+
+[Pcd]
+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
+
+[Ppis]
+ gEfiPeiMmControlPpiGuid ## PRODUCES
diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h b/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h
new file mode 100644
index 000000000000..b532dd13f373
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h
@@ -0,0 +1,26 @@
+/** @file
+ This is to publish the SMM Control Ppi instance.
+
+ Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _SMM_CONTROL_LIB_H_
+#define _SMM_CONTROL_LIB_H_
+
+/**
+ This function is to install an SMM Control PPI
+ - <b>Introduction</b> \n
+ An API to install an instance of EFI_PEI_MM_CONTROL_PPI. This PPI provides a standard
+ way for other modules to trigger software SMIs.
+
+ @retval EFI_SUCCESS - Ppi successfully started and installed.
+ @retval EFI_NOT_FOUND - Ppi can't be found.
+ @retval EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to initialize the driver.
+**/
+EFI_STATUS
+EFIAPI
+PeiInstallSmmControlPpi (
+ VOID
+ );
+#endif
diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index deefdc55b5d6..440c7d0255ce 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -35,6 +35,10 @@
#
SmmAccessLib|Include/Library/SmmAccessLib.h
+ ## @libraryclass Provides services to trigger SMI
+ #
+ SmmControlLib|Include/Library/SmmControlLib.h
+
## @libraryclass Provides services to access config block
#
ConfigBlockLib|Include/Library/ConfigBlockLib.h
--
2.37.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [edk2-devel][edk2-platforms][PATCH v2 4/6] S3FeaturePkg: Implement working S3 resume
2022-09-06 17:02 [edk2-devel][edk2-platforms][PATCH v2 0/6] Implement S3 resume Benjamin Doron
` (2 preceding siblings ...)
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 3/6] IntelSiliconPkg/Feature/SmmControl: " Benjamin Doron
@ 2022-09-06 17:02 ` Benjamin Doron
2022-09-08 0:38 ` Isaac Oram
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 5/6] MinPlatformPkg: " Benjamin Doron
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 6/6] KabylakeOpenBoardPkg: Example of board S3 Benjamin Doron
5 siblings, 1 reply; 17+ messages in thread
From: Benjamin Doron @ 2022-09-06 17:02 UTC (permalink / raw)
To: devel; +Cc: Nate DeSimone, Ankit Sinha, Sai Chaganty, Isaac Oram, Liming Gao
Follow-up commits to MinPlatform (PeiFspWrapperHobProcessLib for
memory) and FSP-related board libraries (policy overrides)
required for successful S3 resume.
Factored allocation logic into new module to avoid MinPlatform
dependency on S3Feature package.
TODO: Can optimise required size.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../S3FeaturePkg/Include/PostMemory.fdf | 13 ++
.../S3FeaturePkg/Include/PreMemory.fdf | 8 +-
.../S3FeaturePkg/Include/S3Feature.dsc | 38 ++++-
.../S3FeaturePkg/S3Dxe/S3Dxe.c | 155 ++++++++++++++++++
.../S3FeaturePkg/S3Dxe/S3Dxe.inf | 49 ++++++
.../S3FeaturePkg/S3Pei/S3Pei.c | 83 +++++++++-
.../S3FeaturePkg/S3Pei/S3Pei.inf | 8 +-
.../Include/AcpiS3MemoryNvData.h | 22 +++
8 files changed, 365 insertions(+), 11 deletions(-)
create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
create mode 100644 Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf
index 9e17f853c630..7f630908fa2c 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf
@@ -2,7 +2,20 @@
# FDF file for post-memory S3 advanced feature modules.
#
# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2022, Baruch Binyamin Doron.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
+
+## Dependencies
+ INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
+ INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
+
+## Save-state module stack
+ INF S3FeaturePkg/S3Dxe/S3Dxe.inf
+ INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+ INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
+
+## Restore-state module stack
+ INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf
index fdd16a4e0356..e130fa5f098d 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf
@@ -2,9 +2,15 @@
# FDF file for pre-memory S3 advanced feature modules.
#
# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2022, Baruch Binyamin Doron.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
-INF S3FeaturePkg/S3Pei/S3Pei.inf
+## Dependencies
+ INF S3FeaturePkg/S3Pei/S3Pei.inf
+ INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
+
+## Restore-state module stack
+ INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc
index cc34e785076a..d8bfc7909413 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc
@@ -7,6 +7,7 @@
# for the build infrastructure.
#
# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2022, Baruch Binyamin Doron.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -25,6 +26,10 @@
!error "DXE_ARCH must be specified to build this feature!"
!endif
+[PcdsFixedAtBuild]
+ # Attempts to improve performance at the cost of more DRAM usage
+ gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE
+
################################################################################
#
# Library Class section - list of all Library Classes needed by this feature.
@@ -32,7 +37,14 @@
################################################################################
[LibraryClasses.common.PEIM]
- SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.inf
+ #SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf
+ SmmControlLib|IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf
+
+[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_SMM_DRIVER]
+ #######################################
+ # Edk2 Packages
+ #######################################
+ S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf
################################################################################
#
@@ -60,8 +72,26 @@
# S3 Feature Package
#####################################
- # Add library instances here that are not included in package components and should be tested
- # in the package build.
-
# Add components here that should be included in the package build.
S3FeaturePkg/S3Pei/S3Pei.inf
+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
+ UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
+
+#
+# Feature DXE Components
+#
+
+# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzilla.tianocore.org/show_bug.cgi?id=2308
+# is completed.
+[Components.X64]
+ #####################################
+ # S3 Feature Package
+ #####################################
+
+ # Add components here that should be included in the package build.
+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
+ MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
+ S3FeaturePkg/S3Dxe/S3Dxe.inf
+ MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+ UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
+ MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
new file mode 100644
index 000000000000..1a7ccb8eedab
--- /dev/null
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
@@ -0,0 +1,155 @@
+/** @file
+ Source code file for S3 DXE module
+
+Copyright (c) 2022, Baruch Binyamin Doron.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Guid/AcpiS3Context.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <AcpiS3MemoryNvData.h>
+
+#define PEI_ADDITIONAL_MEMORY_SIZE (16 * EFI_PAGE_SIZE)
+
+/**
+ Get the mem size in memory type information table.
+
+ @return the mem size in memory type information table.
+**/
+UINT64
+EFIAPI
+GetMemorySizeInMemoryTypeInformation (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_MEMORY_TYPE_INFORMATION *MemoryData;
+ UINT8 Index;
+ UINTN TempPageNum;
+
+ Status = EfiGetSystemConfigurationTable (&gEfiMemoryTypeInformationGuid, (VOID **) &MemoryData);
+
+ if (EFI_ERROR (Status) || MemoryData == NULL) {
+ return 0;
+ }
+
+ TempPageNum = 0;
+ for (Index = 0; MemoryData[Index].Type != EfiMaxMemoryType; Index++) {
+ //
+ // Accumulate default memory size requirements
+ //
+ TempPageNum += MemoryData[Index].NumberOfPages;
+ }
+
+ return TempPageNum * EFI_PAGE_SIZE;
+}
+
+/**
+ Get the mem size need to be consumed and reserved for PEI phase resume.
+
+ @return the mem size to be reserved for PEI phase resume.
+**/
+UINT64
+EFIAPI
+GetPeiMemSize (
+ VOID
+ )
+{
+ UINT64 Size;
+
+ Size = GetMemorySizeInMemoryTypeInformation ();
+
+ return PcdGet32 (PcdPeiMinMemSize) + Size + PEI_ADDITIONAL_MEMORY_SIZE;
+}
+
+/**
+ Allocate EfiACPIMemoryNVS below 4G memory address.
+
+ This function allocates EfiACPIMemoryNVS below 4G memory address.
+
+ @param Size Size of memory to allocate.
+
+ @return Allocated address for output.
+
+**/
+VOID *
+EFIAPI
+AllocateAcpiNvsMemoryBelow4G (
+ IN UINTN Size
+ )
+{
+ UINTN Pages;
+ EFI_PHYSICAL_ADDRESS Address;
+ EFI_STATUS Status;
+ VOID *Buffer;
+
+ Pages = EFI_SIZE_TO_PAGES (Size);
+ Address = 0xffffffff;
+
+ Status = gBS->AllocatePages (
+ AllocateMaxAddress,
+ EfiACPIMemoryNVS,
+ Pages,
+ &Address
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Buffer = (VOID *)(UINTN)Address;
+ ZeroMem (Buffer, Size);
+
+ return Buffer;
+}
+
+/**
+ Allocates memory to use on S3 resume.
+
+ @param[in] ImageHandle Not used.
+ @param[in] SystemTable General purpose services available to every DXE driver.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
+**/
+EFI_STATUS
+EFIAPI
+S3DxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ UINT64 S3PeiMemSize;
+ UINT64 S3PeiMemBase;
+ ACPI_S3_MEMORY S3MemoryInfo;
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "%a() Start\n", __FUNCTION__));
+
+ S3PeiMemSize = GetPeiMemSize ();
+ S3PeiMemBase = (UINTN) AllocateAcpiNvsMemoryBelow4G (S3PeiMemSize);
+ ASSERT (S3PeiMemBase != 0);
+
+ S3MemoryInfo.S3PeiMemBase = S3PeiMemBase;
+ S3MemoryInfo.S3PeiMemSize = S3PeiMemSize;
+
+ DEBUG ((DEBUG_INFO, "S3PeiMemBase: 0x%x\n", S3PeiMemBase));
+ DEBUG ((DEBUG_INFO, "S3PeiMemSize: 0x%x\n", S3PeiMemSize));
+
+ Status = gRT->SetVariable (
+ ACPI_S3_MEMORY_NV_NAME,
+ &gEfiAcpiVariableGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
+ sizeof (S3MemoryInfo),
+ &S3MemoryInfo
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "%a() End\n", __FUNCTION__));
+ return EFI_SUCCESS;
+}
diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
new file mode 100644
index 000000000000..28589c2c869b
--- /dev/null
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
@@ -0,0 +1,49 @@
+### @file
+# Component information file for the S3 DXE module.
+#
+# Copyright (c) 2022, Baruch Binyamin Doron.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = S3Dxe
+ FILE_GUID = 30926F92-CC83-4381-9F70-AC96EDB5BEE0
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_DRIVER
+ ENTRY_POINT = S3DxeEntryPoint
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ BaseMemoryLib
+ DebugLib
+ PcdLib
+ UefiLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ S3FeaturePkg/S3FeaturePkg.dec
+
+[Sources]
+ S3Dxe.c
+
+[Pcd]
+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize
+
+[FeaturePcd]
+ gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable
+
+[Guids]
+ gEfiMemoryTypeInformationGuid ## CONSUMES
+ gEfiAcpiVariableGuid ## CONSUMES
+
+[Depex]
+ gEfiVariableArchProtocolGuid AND
+ gEfiVariableWriteArchProtocolGuid
diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c
index b0aaa04962c8..6acb894b6fc9 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c
@@ -2,12 +2,87 @@
Source code file for S3 PEI module
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2022, Baruch Binyamin Doron.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PciLib.h>
#include <Library/PeiServicesLib.h>
#include <Library/SmmAccessLib.h>
+#include <Library/SmmControlLib.h>
+
+// TODO: Finalise implementation factoring
+#define R_SA_PAM0 (0x80)
+#define R_SA_PAM5 (0x85)
+#define R_SA_PAM6 (0x86)
+
+/**
+ This function is called after FspSiliconInitDone installed PPI.
+ For FSP API mode, this is when FSP-M HOBs are installed into EDK2.
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this function.
+
+ @retval EFI_STATUS Always return EFI_SUCCESS
+**/
+EFI_STATUS
+EFIAPI
+FspSiliconInitDoneNotify (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
+ UINT64 MchBaseAddress;
+
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ // Enable PAM regions for AP wakeup vector (resume)
+ // - CPU is finalised by PiSmmCpuDxeSmm, not FSP. So, it's safe here?
+ // TODO/TEST: coreboot does this unconditionally, vendor FWs may not (test resume). Should we?
+ // - It is certainly interesting that only PAM0, PAM5 and PAM6 are defined for KabylakeSiliconPkg.
+ // - Also note that 0xA0000-0xFFFFF is marked "reserved" in FSP HOB - this does not mean
+ // that the memory is unusable, perhaps this is precisely because it will contain
+ // the AP wakeup vector.
+ if (BootMode == BOOT_ON_S3_RESUME) {
+ MchBaseAddress = PCI_LIB_ADDRESS (0, 0, 0, 0);
+ PciWrite8 (MchBaseAddress + R_SA_PAM0, 0x30);
+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 1), 0x33);
+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 2), 0x33);
+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 3), 0x33);
+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 4), 0x33);
+ PciWrite8 (MchBaseAddress + R_SA_PAM5, 0x33);
+ PciWrite8 (MchBaseAddress + R_SA_PAM6, 0x33);
+ }
+
+ //
+ // Install EFI_PEI_MM_ACCESS_PPI for S3 resume case
+ //
+ Status = PeiInstallSmmAccessPpi ();
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Install EFI_PEI_MM_CONTROL_PPI for S3 resume case
+ //
+ Status = PeiInstallSmmControlPpi ();
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+EFI_PEI_NOTIFY_DESCRIPTOR mFspSiliconInitDoneNotifyDesc = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gFspSiliconInitDonePpiGuid,
+ FspSiliconInitDoneNotify
+};
/**
S3 PEI module entry point
@@ -25,12 +100,10 @@ S3PeiEntryPoint (
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
- //
- // Install EFI_PEI_MM_ACCESS_PPI for S3 resume case
- //
- Status = PeiInstallSmmAccessPpi ();
+ Status = PeiServicesNotifyPpi (&mFspSiliconInitDoneNotifyDesc);
+ ASSERT_EFI_ERROR (Status);
return Status;
}
diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf
index e485eac9521f..173919bb881e 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf
@@ -18,10 +18,13 @@
[LibraryClasses]
PeimEntryPoint
PeiServicesLib
+ DebugLib
SmmAccessLib
+ SmmControlLib
[Packages]
MdePkg/MdePkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
IntelSiliconPkg/IntelSiliconPkg.dec
S3FeaturePkg/S3FeaturePkg.dec
@@ -31,5 +34,8 @@
[FeaturePcd]
gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable
+[Ppis]
+ gFspSiliconInitDonePpiGuid
+
[Depex]
- gEfiPeiMemoryDiscoveredPpiGuid
+ TRUE
diff --git a/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h b/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
new file mode 100644
index 000000000000..0d75af8e9a03
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
@@ -0,0 +1,22 @@
+/** @file
+ Header file for NV data structure definition.
+
+Copyright (c) 2021, Baruch Binyamin Doron
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __ACPI_S3_MEMORY_NV_DATA_H__
+#define __ACPI_S3_MEMORY_NV_DATA_H__
+
+//
+// NV data structure
+//
+typedef struct {
+ UINT64 S3PeiMemBase;
+ UINT64 S3PeiMemSize;
+} ACPI_S3_MEMORY;
+
+#define ACPI_S3_MEMORY_NV_NAME L"S3MemoryInfo"
+
+#endif
--
2.37.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [edk2-devel][edk2-platforms][PATCH v2 5/6] MinPlatformPkg: Implement working S3 resume
2022-09-06 17:02 [edk2-devel][edk2-platforms][PATCH v2 0/6] Implement S3 resume Benjamin Doron
` (3 preceding siblings ...)
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 4/6] S3FeaturePkg: Implement working S3 resume Benjamin Doron
@ 2022-09-06 17:02 ` Benjamin Doron
2022-09-08 2:46 ` Isaac Oram
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 6/6] KabylakeOpenBoardPkg: Example of board S3 Benjamin Doron
5 siblings, 1 reply; 17+ messages in thread
From: Benjamin Doron @ 2022-09-06 17:02 UTC (permalink / raw)
To: devel
Cc: Chasel Chiu, Nate DeSimone, Ankit Sinha, Isaac Oram, Liming Gao,
Eric Dong
Consume S3 resume memory allocation on resume flow.
Also, include complementary FirmwarePerformanceDataTablePei module in
MinPlatform FV for S3 resume performance measurement.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../FspWrapperHobProcessLib.c | 69 ++++++++++++++++++-
.../PeiFspWrapperHobProcessLib.inf | 2 +
.../Include/Dsc/CorePeiInclude.dsc | 2 +
.../Include/Fdf/CorePostMemoryInclude.fdf | 2 +
4 files changed, 74 insertions(+), 1 deletion(-)
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c
index 7ee4d3a31c49..9bd6fe6290c5 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c
@@ -16,14 +16,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/HobLib.h>
#include <Library/PcdLib.h>
#include <Library/FspWrapperPlatformLib.h>
+#include <Guid/AcpiS3Context.h>
#include <Guid/GuidHobFspEas.h>
#include <Guid/MemoryTypeInformation.h>
#include <Guid/GraphicsInfoHob.h>
#include <Guid/PcdDataBaseHobGuid.h>
#include <Guid/ZeroGuid.h>
#include <Ppi/Capsule.h>
+#include <Ppi/ReadOnlyVariable2.h>
#include <FspEas.h>
+#include <AcpiS3MemoryNvData.h>
//
// Additional pages are used by DXE memory manager.
@@ -130,6 +133,55 @@ GetPeiMemSize (
return MinSize + Size + PEI_ADDITIONAL_MEMORY_SIZE;
}
+/**
+ Get S3 PEI memory information.
+
+ @note At this point, memory is ready, and PeiServices are available to use.
+ Platform can get some data from SMRAM directly.
+
+ @param[out] S3PeiMemSize PEI memory size to be installed in S3 phase.
+ @param[out] S3PeiMemBase PEI memory base to be installed in S3 phase.
+
+ @return If S3 PEI memory information is got successfully.
+**/
+EFI_STATUS
+EFIAPI
+GetS3MemoryInfo (
+ OUT UINT64 *S3PeiMemSize,
+ OUT EFI_PHYSICAL_ADDRESS *S3PeiMemBase
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi;
+ UINTN DataSize;
+ ACPI_S3_MEMORY S3MemoryInfo;
+
+ *S3PeiMemBase = 0;
+ *S3PeiMemSize = 0;
+
+ Status = PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NULL, (VOID **) &VariablePpi);
+ ASSERT_EFI_ERROR (Status);
+
+ DataSize = sizeof (S3MemoryInfo);
+ Status = VariablePpi->GetVariable (
+ VariablePpi,
+ ACPI_S3_MEMORY_NV_NAME,
+ &gEfiAcpiVariableGuid,
+ NULL,
+ &DataSize,
+ &S3MemoryInfo
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ *S3PeiMemBase = S3MemoryInfo.S3PeiMemBase;
+ *S3PeiMemSize = S3MemoryInfo.S3PeiMemSize;
+ return EFI_SUCCESS;
+}
+
/**
Post FSP-M HOB process for Memory Resource Descriptor.
@@ -280,7 +332,7 @@ PostFspmHobProcess (
0x1000
);
-
+ if (BootMode != BOOT_ON_S3_RESUME) {
//
// Capsule mode
//
@@ -337,7 +389,22 @@ PostFspmHobProcess (
if (Capsule != NULL) {
Status = Capsule->CreateState ((EFI_PEI_SERVICES **)PeiServices, CapsuleBuffer, CapsuleBufferLength);
}
+ } else {
+ Status = GetS3MemoryInfo (&PeiMemSize, &PeiMemBase);
+ ASSERT_EFI_ERROR (Status);
+ DEBUG ((DEBUG_INFO, "S3 resume PeiMemBase : 0x%08x\n", PeiMemBase));
+ DEBUG ((DEBUG_INFO, "S3 resume PeiMemSize : 0x%08x\n", PeiMemSize));
+
+ //
+ // Install efi memory
+ //
+ Status = PeiServicesInstallPeiMemory (
+ PeiMemBase,
+ PeiMemSize
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
//
// Create a memory allocation HOB at fixed location for MP Services PPI AP wait loop.
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
index b846e7af1d2d..e2aac36bf018 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
@@ -75,7 +75,9 @@
gZeroGuid
gEfiGraphicsInfoHobGuid
gEfiGraphicsDeviceInfoHobGuid
+ gEfiAcpiVariableGuid
[Ppis]
gEfiPeiCapsulePpiGuid ## CONSUMES
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
gEdkiiSiliconInitializedPpiGuid ## PRODUCES
diff --git a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc b/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
index 08e50cac075f..f271fb26b189 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
+++ b/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
@@ -41,3 +41,5 @@
NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf
}
!endif
+
+ MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf
diff --git a/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf b/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf
index 3c2716d6728a..160f02650a8c 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf
+++ b/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf
@@ -6,3 +6,5 @@
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
+
+ INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf
--
2.37.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [edk2-devel][edk2-platforms][PATCH v2 6/6] KabylakeOpenBoardPkg: Example of board S3
2022-09-06 17:02 [edk2-devel][edk2-platforms][PATCH v2 0/6] Implement S3 resume Benjamin Doron
` (4 preceding siblings ...)
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 5/6] MinPlatformPkg: " Benjamin Doron
@ 2022-09-06 17:02 ` Benjamin Doron
5 siblings, 0 replies; 17+ messages in thread
From: Benjamin Doron @ 2022-09-06 17:02 UTC (permalink / raw)
To: devel
Cc: Nate DeSimone, Ankit Sinha, Chasel Chiu, Jeremy Soller,
Sai Chaganty, Isaac Oram
Use silicon code to detect S3 resume state. Apply some relevant policy
modifications.
PcdPeiMemSize must be in common scope, for a DXE module to allocate
required memory. Libraries that produce required PPIs are defined.
BootScriptExecutorDxe should only be linked against a functionally
compatible debug stack.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Jeremy Soller <jeremy@system76.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../PeiFspMiscUpdUpdateLib.c | 12 +++-
.../PeiSaPolicyUpdate.c | 12 +++-
.../PeiAspireVn7Dash572GInitPreMemLib.c | 61 ++++++++++++++-----
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 3 +
.../AspireVn7Dash572G/OpenBoardPkg.dsc | 21 +++++++
.../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 16 ++---
.../PeiSiliconPolicyUpdateLib.c | 11 +++-
.../PeiSiliconPolicyUpdateLib.inf | 1 +
.../PeiFspMiscUpdUpdateLib.c | 11 +++-
.../PeiSaPolicyUpdate.c | 12 +++-
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 +
.../BoardInitLib/PeiGalagoPro3InitPreMemLib.c | 27 +++++++-
.../PeiMultiBoardInitPreMemLib.inf | 1 +
.../GalagoPro3/OpenBoardPkg.dsc | 15 +++++
.../GalagoPro3/OpenBoardPkgPcd.dsc | 2 +-
.../PeiFspMiscUpdUpdateLib.c | 12 +++-
.../PeiSaPolicyUpdate.c | 12 +++-
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 +
.../PeiKabylakeRvp3InitPreMemLib.c | 27 +++++++-
.../PeiMultiBoardInitPreMemLib.inf | 1 +
.../KabylakeRvp3/OpenBoardPkg.dsc | 12 ++++
.../KabylakeRvp3/OpenBoardPkgPcd.dsc | 2 +-
.../PeiSiliconPolicyUpdateLib.c | 11 +++-
.../PeiSiliconPolicyUpdateLib.inf | 1 +
24 files changed, 245 insertions(+), 40 deletions(-)
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
index a9b7e446c8d6..7e4194bf4fe6 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -11,6 +11,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/DebugLib.h>
#include <Library/PciLib.h>
#include <Library/PeiLib.h>
+#include <Library/PeiServicesLib.h>
+
#include <FspEas.h>
#include <FspmUpd.h>
#include <FspsUpd.h>
@@ -32,11 +34,15 @@ PeiFspMiscUpdUpdatePreMem (
)
{
EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
UINTN VariableSize;
VOID *FspNvsBufferPtr;
UINT8 MorControl;
VOID *MorControlPtr;
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
//
// Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths.
//
@@ -70,7 +76,11 @@ PeiFspMiscUpdUpdatePreMem (
&VariableSize
);
DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status));
- if (MOR_CLEAR_MEMORY_VALUE (MorControl)) {
+ //
+ // Do not set CleanMemory on S3 resume
+ // TODO: Handle advanced features later - capsule update is in-memory list
+ //
+ if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode != BOOT_ON_S3_RESUME) {
FspmUpd->FspmConfig.CleanMemory = (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK);
}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
index 4621cbd3ca3a..1299bf504fbd 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
@@ -11,6 +11,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/MemoryAllocationLib.h>
#include <Library/PeiSaPolicyLib.h>
#include <Library/PeiLib.h>
+#include <Library/PeiServicesLib.h>
/**
Performs FSP SA PEI Policy initialization.
@@ -27,12 +28,17 @@ PeiFspSaPolicyUpdate (
IN OUT FSPS_UPD *FspsUpd
)
{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
VOID *Buffer;
VOID *MemBuffer;
UINT32 Size;
DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1;
Size = 0;
@@ -40,7 +46,11 @@ PeiFspSaPolicyUpdate (
PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);
if (Buffer == NULL) {
DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
- } else {
+ //
+ // Graphics initialisation is unnecessary,
+ // OS has present framebuffer.
+ //
+ } else if (BootMode != BOOT_ON_S3_RESUME) {
MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
if ((MemBuffer != NULL) && (Buffer != NULL)) {
CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c
index 1c9a65399b54..1b4c6b484b43 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c
@@ -11,7 +11,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
#include <Library/PchCycleDecodingLib.h>
+#include <Library/PchPmcLib.h>
#include <Library/PchResetLib.h>
+#include <Library/PciLib.h>
#include <Library/SiliconInitLib.h>
#include <Library/TimerLib.h>
#include <Library/PeiLib.h>
@@ -248,6 +250,8 @@ AspireVn7Dash572GBoardDebugInit (
VOID
)
{
+ UINT16 ABase;
+
///
/// Do Early PCH init
///
@@ -258,6 +262,16 @@ AspireVn7Dash572GBoardDebugInit (
// - Alternatively, move the preceding calls to BoardDetect()
AspireVn7Dash572GBoardDetect ();
+ // Dump relevant registers
+ // - TODO: Remove after debugging
+ DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_A= 0x%x\n", PciRead32 ((UINTN)PCI_LIB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PCH_PMC_GEN_PMCON_A))));
+ DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_B= 0x%x\n", PciRead32 ((UINTN)PCI_LIB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PCH_PMC_GEN_PMCON_B))));
+
+ PchAcpiBaseGet (&ABase);
+ DEBUG ((DEBUG_INFO, "ABase PM1_STS= 0x%x\n", IoRead16 (ABase)));
+ DEBUG ((DEBUG_INFO, "ABase PM1_EN= 0x%x\n", IoRead16 (ABase + R_PCH_ACPI_PM1_EN)));
+ DEBUG ((DEBUG_INFO, "ABase PM1_CNT= 0x%x\n", IoRead32 (ABase + R_PCH_ACPI_PM1_CNT)));
+
return EFI_SUCCESS;
}
@@ -267,25 +281,42 @@ AspireVn7Dash572GBoardBootModeDetect (
VOID
)
{
- UINT16 ABase;
+ EFI_BOOT_MODE BootMode;
UINT32 SleepType;
+ UINT16 ABase;
DEBUG ((DEBUG_INFO, "Performing boot mode detection\n"));
- // TODO: Perform advanced detection (recovery/capsule)
- // FIXME: This violates PI specification? But BOOT_WITH* would always take precedence
- // over BOOT_ON_S{4,5}...
- PchAcpiBaseGet (&ABase);
- SleepType = IoRead32 (ABase + R_PCH_ACPI_PM1_CNT) & B_PCH_ACPI_PM1_CNT_SLP_TYP;
+ // Known sane defaults; TODO: Consider "default"?
+ BootMode = BOOT_WITH_FULL_CONFIGURATION;
- switch (SleepType) {
- case V_PCH_ACPI_PM1_CNT_S3:
- return BOOT_ON_S3_RESUME;
- case V_PCH_ACPI_PM1_CNT_S4:
- return BOOT_ON_S4_RESUME;
-// case V_PCH_ACPI_PM1_CNT_S5:
-// return BOOT_ON_S5_RESUME;
- default:
- return BOOT_WITH_FULL_CONFIGURATION;
+ // TODO: Perform advanced detection (capsule/recovery)
+ // TODO: Perform "IsFirstBoot" test with VariablePpi for "minimal"/"assume"
+ if (GetSleepTypeAfterWakeup (&SleepType)) {
+ switch (SleepType) {
+ case V_PCH_ACPI_PM1_CNT_S3:
+ BootMode = BOOT_ON_S3_RESUME;
+ break;
+ case V_PCH_ACPI_PM1_CNT_S4:
+ BootMode = BOOT_ON_S4_RESUME;
+ break;
+ case V_PCH_ACPI_PM1_CNT_S5:
+ BootMode = BOOT_ON_S5_RESUME;
+ break;
+ }
}
+
+ DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode));
+
+ // Dump relevant registers
+ // - TODO: Remove after debugging
+ DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_A= 0x%x\n", PciRead32 ((UINTN)PCI_LIB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PCH_PMC_GEN_PMCON_A))));
+ DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_B= 0x%x\n", PciRead32 ((UINTN)PCI_LIB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PCH_PMC_GEN_PMCON_B))));
+
+ PchAcpiBaseGet (&ABase);
+ DEBUG ((DEBUG_INFO, "ABase PM1_STS= 0x%x\n", IoRead16 (ABase)));
+ DEBUG ((DEBUG_INFO, "ABase PM1_EN= 0x%x\n", IoRead16 (ABase + R_PCH_ACPI_PM1_EN)));
+ DEBUG ((DEBUG_INFO, "ABase PM1_CNT= 0x%x\n", IoRead32 (ABase + R_PCH_ACPI_PM1_CNT)));
+
+ return BootMode;
}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
index cd9f979d313c..c53114e15450 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
@@ -25,11 +25,14 @@
TimerLib
PchCycleDecodingLib
PchResetLib
+ PciLib
IoLib
EcLib
BoardEcLib
GpioLib
PeiLib
+ PeiServicesLib
+ PchPmcLib
[Packages]
MinPlatformPkg/MinPlatformPkg.dec
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc
index c71b7169a38a..f4552ee83d6b 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc
@@ -248,6 +248,7 @@
# Silicon Package
#######################################
ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf
+ SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf
#######################################
# Platform Package
@@ -711,6 +712,26 @@
!endif
}
+!if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable == TRUE
+ MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf {
+ <LibraryClasses>
+ # On S3 resume, RSC is in end-of-BS state
+ # - Moreover: Library cannot effectively use some end-of-BS events
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+ # Reverse-ranked priority list
+# TODO: Requires testing
+# - Strongly suspect DebugLibSerialPort constructor presents PeiDxeSerialPortLibMem dependency on services as a bug
+!if FALSE # $(USE_MEMORY_LOGGING) == TRUE
+ SerialPortLib|MdeModulePkg/Library/PeiDxeSerialPortLibMem/DxeSerialPortLibMem.inf
+!endif
+ # Also, can debug CpuExceptionHandlerLib
+!if $(USE_HDMI_DEBUG_PORT) == TRUE
+ SerialPortLib|$(PLATFORM_BOARD_PACKAGE)/Library/I2cHdmiDebugSerialPortLib/BootScriptExecutorDxeI2cHdmiDebugSerialPortLib.inf
+!endif
+ }
+!endif
+
!endif
#######################################
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
index 3ed7aa0a2b10..490c3ee6bf76 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
@@ -127,10 +127,7 @@
# PcdIpmiFeatureEnable will not be enabled (no BMC)
# TODO: Can be build-time (user) choice
gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable |FALSE
- # TODO: Continue developing support. Broken at present.
- # - PeiSmmAccessLib in IntelSiliconPkg seems like a stub
- # - May require a PeiSmmControlLib to SMM communicate
- gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable |FALSE
+ gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable |TRUE
# TODO: Definitions (now added SmbiosDxe)
gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable |TRUE
# Requires actual hook-up
@@ -335,6 +332,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|4
gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
#
# The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
@@ -360,13 +358,8 @@
# 0x7F, 0xFF, 0x04, 0x00}<BR>
gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x7F, 0xFF, 0x04, 0x00}
-!if $(TARGET) == RELEASE
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x800
-!else
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B # TODO
-!endif
- # TODO: Consider using reserved space instead for debug log
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x200
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0x4800
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x100
!if $(TARGET) == RELEASE
gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70
!else
@@ -447,7 +440,6 @@
# Edk2 Configuration
######################################
gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
- gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
######################################
# Platform Configuration
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
index 3764f7c3ac09..ab8abac6be1c 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
@@ -20,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/DebugLib.h>
#include <Library/ConfigBlockLib.h>
#include <Library/PeiLib.h>
+#include <Library/PeiServicesLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/CpuPlatformLib.h>
@@ -549,6 +550,7 @@ SiliconPolicyUpdatePostMem (
)
{
EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
VOID *Buffer;
VOID *MemBuffer;
UINT32 Size;
@@ -557,6 +559,9 @@ SiliconPolicyUpdatePostMem (
DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n"));
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
GtConfig = NULL;
Status = GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VOID *)&GtConfig);
ASSERT_EFI_ERROR (Status);
@@ -571,7 +576,11 @@ SiliconPolicyUpdatePostMem (
PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);
if (Buffer == NULL) {
DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
- } else {
+ //
+ // Graphics initialisation is unnecessary,
+ // OS has present framebuffer.
+ //
+ } else if (BootMode != BOOT_ON_S3_RESUME) {
MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
if ((MemBuffer != NULL) && (Buffer != NULL)) {
CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
index 1ce26fc3dcec..31a45292209d 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
@@ -23,6 +23,7 @@
BaseMemoryLib
MemoryAllocationLib
PeiLib
+ PeiServicesLib
CpuPlatformLib
PchPcieRpLib
PchInfoLib
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
index dbc84631acaa..ce309bd378d2 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -11,6 +11,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/DebugLib.h>
#include <Library/PeiLib.h>
#include <Library/ConfigBlockLib.h>
+#include <Library/PeiServicesLib.h>
#include <FspEas.h>
#include <FspmUpd.h>
@@ -36,11 +37,15 @@ PeiFspMiscUpdUpdatePreMem (
)
{
EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
UINTN VariableSize;
VOID *FspNvsBufferPtr;
UINT8 MorControl;
VOID *MorControlPtr;
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
//
// Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths.
//
@@ -75,7 +80,11 @@ PeiFspMiscUpdUpdatePreMem (
&VariableSize
);
DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status));
- if (MOR_CLEAR_MEMORY_VALUE (MorControl)) {
+ //
+ // Do not set CleanMemory on S3 resume
+ // TODO: Handle advanced features later - capsule update is in-memory list
+ //
+ if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode != BOOT_ON_S3_RESUME) {
FspmUpd->FspmConfig.CleanMemory = (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK);
}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
index 133b8c963f65..48899aa63b4f 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
@@ -17,6 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/MemoryAllocationLib.h>
#include <Library/PeiSaPolicyLib.h>
#include <Library/PeiLib.h>
+#include <Library/PeiServicesLib.h>
/**
Performs FSP SA PEI Policy initialization.
@@ -33,12 +34,17 @@ PeiFspSaPolicyUpdate (
IN OUT FSPS_UPD *FspsUpd
)
{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
VOID *Buffer;
VOID *MemBuffer;
UINT32 Size;
DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1;
Size = 0;
@@ -46,7 +52,11 @@ PeiFspSaPolicyUpdate (
PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);
if (Buffer == NULL) {
DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
- } else {
+ //
+ // Graphics initialisation is unnecessary,
+ // OS has present framebuffer.
+ //
+ } else if (BootMode != BOOT_ON_S3_RESUME) {
MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
if ((MemBuffer != NULL) && (Buffer != NULL)) {
CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
index d6c91cd2b94b..5b3a6921d0ee 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
@@ -23,6 +23,7 @@
PcdLib
SiliconInitLib
PchResetLib
+ PchPmcLib
[Packages]
MinPlatformPkg/MinPlatformPkg.dec
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPreMemLib.c
index 051dac0b204d..1cd2baf4a4dd 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPreMemLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPreMemLib.c
@@ -14,6 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/HobLib.h>
#include <Library/PcdLib.h>
#include <Library/PchCycleDecodingLib.h>
+#include <Library/PchPmcLib.h>
#include <Library/PciLib.h>
#include <Library/PcdLib.h>
#include <Library/BaseMemoryLib.h>
@@ -236,5 +237,29 @@ GalagoPro3BoardBootModeDetect (
VOID
)
{
- return BOOT_WITH_FULL_CONFIGURATION;
+ EFI_BOOT_MODE BootMode;
+ UINT32 SleepType;
+
+ DEBUG ((DEBUG_INFO, "Performing boot mode detection\n"));
+
+ // Known sane defaults
+ BootMode = BOOT_WITH_FULL_CONFIGURATION;
+
+ if (GetSleepTypeAfterWakeup (&SleepType)) {
+ switch (SleepType) {
+ case V_PCH_ACPI_PM1_CNT_S3:
+ BootMode = BOOT_ON_S3_RESUME;
+ break;
+ case V_PCH_ACPI_PM1_CNT_S4:
+ BootMode = BOOT_ON_S4_RESUME;
+ break;
+ case V_PCH_ACPI_PM1_CNT_S5:
+ BootMode = BOOT_ON_S5_RESUME;
+ break;
+ }
+ }
+
+ DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode));
+
+ return BootMode;
}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
index fe31f421356e..20ddac1d994d 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
@@ -25,6 +25,7 @@
SiliconInitLib
MultiBoardInitSupportLib
PchResetLib
+ PchPmcLib
[Packages]
MinPlatformPkg/MinPlatformPkg.dec
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
index 2e3c6d3ca506..1cab167e6580 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
@@ -177,6 +177,7 @@
# Silicon Package
#######################################
ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf
+ SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf
#######################################
# Platform Package
@@ -488,6 +489,20 @@
NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf
!endif
}
+
+!if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable == TRUE
+ MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf {
+ <LibraryClasses>
+ # On S3 resume, RSC is in end-of-BS state
+ # - Moreover: Libraries cannot effectively use some end-of-BS events
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+ # Reverse-ranked priority list
+!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdI2cHdmiDebugPortEnable == TRUE
+ SerialPortLib|$(PLATFORM_BOARD_PACKAGE)/Library/I2cHdmiDebugSerialPortLib/BootScriptExecutorDxeI2cHdmiDebugSerialPortLib.inf
+!endif
+ }
+!endif
MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf {
<LibraryClasses>
DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
index ec23c691b2fe..4d0ea7ac43ad 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
@@ -279,6 +279,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
#
# The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
@@ -379,7 +380,6 @@
######################################
gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
- gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
######################################
# Platform Configuration
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
index 699f4297fad6..71b03f2da464 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -11,11 +11,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/DebugLib.h>
#include <Library/PeiLib.h>
#include <Library/ConfigBlockLib.h>
+#include <Library/PeiServicesLib.h>
#include <FspEas.h>
#include <FspmUpd.h>
#include <FspsUpd.h>
-
#include <Library/DebugLib.h>
#include <Library/DebugPrintErrorLevelLib.h>
#include <Library/PciLib.h>
@@ -36,11 +36,15 @@ PeiFspMiscUpdUpdatePreMem (
)
{
EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
UINTN VariableSize;
VOID *FspNvsBufferPtr;
UINT8 MorControl;
VOID *MorControlPtr;
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
//
// Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths.
//
@@ -73,7 +77,11 @@ PeiFspMiscUpdUpdatePreMem (
&VariableSize
);
DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status));
- if (MOR_CLEAR_MEMORY_VALUE (MorControl)) {
+ //
+ // Do not set CleanMemory on S3 resume
+ // TODO: Handle advanced features later - capsule update is in-memory list
+ //
+ if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode != BOOT_ON_S3_RESUME) {
FspmUpd->FspmConfig.CleanMemory = (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK);
}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
index d6ec3e38dd7e..b69abd11cbce 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
@@ -17,6 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/MemoryAllocationLib.h>
#include <Library/PeiSaPolicyLib.h>
#include <Library/PeiLib.h>
+#include <Library/PeiServicesLib.h>
/**
Performs FSP SA PEI Policy initialization.
@@ -33,12 +34,17 @@ PeiFspSaPolicyUpdate (
IN OUT FSPS_UPD *FspsUpd
)
{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
VOID *Buffer;
VOID *MemBuffer;
UINT32 Size;
DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1;
Size = 0;
@@ -46,7 +52,11 @@ PeiFspSaPolicyUpdate (
PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);
if (Buffer == NULL) {
DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
- } else {
+ //
+ // Graphics initialisation is unnecessary,
+ // OS has present framebuffer.
+ //
+ } else if (BootMode != BOOT_ON_S3_RESUME) {
MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
if ((MemBuffer != NULL) && (Buffer != NULL)) {
CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
index 850fc514188b..e0022e8d6118 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
@@ -24,6 +24,7 @@
SiliconInitLib
EcLib
PchResetLib
+ PchPmcLib
[Packages]
MinPlatformPkg/MinPlatformPkg.dec
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c
index 87ae3b531ed6..02cd37227e50 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c
@@ -13,6 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/HobLib.h>
#include <Library/PcdLib.h>
#include <Library/PchCycleDecodingLib.h>
+#include <Library/PchPmcLib.h>
#include <Library/PciLib.h>
#include <Library/PcdLib.h>
#include <Library/BaseMemoryLib.h>
@@ -330,5 +331,29 @@ KabylakeRvp3BoardBootModeDetect (
VOID
)
{
- return BOOT_WITH_FULL_CONFIGURATION;
+ EFI_BOOT_MODE BootMode;
+ UINT32 SleepType;
+
+ DEBUG ((DEBUG_INFO, "Performing boot mode detection\n"));
+
+ // Known sane defaults
+ BootMode = BOOT_WITH_FULL_CONFIGURATION;
+
+ if (GetSleepTypeAfterWakeup (&SleepType)) {
+ switch (SleepType) {
+ case V_PCH_ACPI_PM1_CNT_S3:
+ BootMode = BOOT_ON_S3_RESUME;
+ break;
+ case V_PCH_ACPI_PM1_CNT_S4:
+ BootMode = BOOT_ON_S4_RESUME;
+ break;
+ case V_PCH_ACPI_PM1_CNT_S5:
+ BootMode = BOOT_ON_S5_RESUME;
+ break;
+ }
+ }
+
+ DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode));
+
+ return BootMode;
}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
index 23fe6b6f03c5..0112bf84a193 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
@@ -26,6 +26,7 @@
MultiBoardInitSupportLib
EcLib
PchResetLib
+ PchPmcLib
[Packages]
MinPlatformPkg/MinPlatformPkg.dec
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
index 26a54b0dc7cc..7c640ecb1559 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
@@ -201,6 +201,7 @@
# Silicon Package
#######################################
ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf
+ SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf
#######################################
# Platform Package
@@ -505,6 +506,17 @@
!endif
}
+!if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable == TRUE
+ MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf {
+ <LibraryClasses>
+ # On S3 resume, RSC is in end-of-BS state
+ # - Moreover: Libraries cannot effectively use some end-of-BS events
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+ # TODO: Insert a reverse-ranked priority list of compatible libraries here
+ }
+!endif
+
!endif
#######################################
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
index cfd032814850..87510748783f 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
@@ -279,6 +279,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
#
# The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
@@ -349,7 +350,6 @@
######################################
gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
- gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
######################################
# Platform Configuration
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
index 22aadc0221df..2061efb2445c 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
@@ -20,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/DebugLib.h>
#include <Library/ConfigBlockLib.h>
#include <Library/PeiLib.h>
+#include <Library/PeiServicesLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/CpuPlatformLib.h>
@@ -513,6 +514,7 @@ SiliconPolicyUpdatePostMem (
)
{
EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
VOID *Buffer;
VOID *MemBuffer;
UINT32 Size;
@@ -521,6 +523,9 @@ SiliconPolicyUpdatePostMem (
DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n"));
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
GtConfig = NULL;
Status = GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VOID *)&GtConfig);
ASSERT_EFI_ERROR (Status);
@@ -535,7 +540,11 @@ SiliconPolicyUpdatePostMem (
PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);
if (Buffer == NULL) {
DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
- } else {
+ //
+ // Graphics initialisation is unnecessary,
+ // OS has present framebuffer.
+ //
+ } else if (BootMode != BOOT_ON_S3_RESUME) {
MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
if ((MemBuffer != NULL) && (Buffer != NULL)) {
CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
index 25eae88f5989..e9a23593e133 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
@@ -23,6 +23,7 @@
BaseMemoryLib
MemoryAllocationLib
PeiLib
+ PeiServicesLib
CpuPlatformLib
PchPcieRpLib
PchInfoLib
--
2.37.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [edk2-devel][edk2-platforms][PATCH v2 1/6] {Platform,Silicon}/Intel: Move PcdAcpiBaseAddress definition
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 1/6] {Platform,Silicon}/Intel: Move PcdAcpiBaseAddress definition Benjamin Doron
@ 2022-09-07 22:50 ` Isaac Oram
2022-09-07 22:57 ` Chaganty, Rangasai V
1 sibling, 0 replies; 17+ messages in thread
From: Isaac Oram @ 2022-09-07 22:50 UTC (permalink / raw)
To: Benjamin Doron, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Desimone, Nathaniel L, Sinha, Ankit,
Ni, Ray, Chiu, Chasel, Luo, Heng
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>
-----Original Message-----
From: Benjamin Doron <benjamin.doron00@gmail.com>
Sent: Tuesday, September 6, 2022 10:02 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Ni, Ray <ray.ni@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Luo, Heng <heng.luo@intel.com>
Subject: [edk2-devel][edk2-platforms][PATCH v2 1/6] {Platform,Silicon}/Intel: Move PcdAcpiBaseAddress definition
All these platforms have an ABase, so move the definition to enable common silicon code in IntelSiliconPkg. Otherwise, library shims would be required, because PCDs are GUID-ed and package DEC specific.
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Heng Luo <heng.luo@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc | 1 +
.../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
.../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 1 +
.../KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
.../Library/BasePlatformHookLib/BasePlatformHookLib.inf | 2 +-
.../KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc | 1 +
.../Library/BasePlatformHookLib/BasePlatformHookLib.inf | 2 +-
.../KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 1 +
.../TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc | 1 +
.../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
.../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 1 +
.../WhiskeylakeURvp/OpenBoardPkgPcd.dsc | 1 +
Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc | 1 +
.../Library/PeiSiliconInitLib/PeiSiliconInitLib.inf | 5 +++--
.../Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf | 3 ++-
.../PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf | 2 +-
Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec | 1 -
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 4 ++++
Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc | 1 +
.../Library/PeiSiliconInitLib/PeiSiliconInitLib.inf | 2 +-
.../Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf | 3 ++-
.../Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf | 2 +-
.../KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf | 2 +-
Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec | 1 -
.../IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf | 3 ++-
.../PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf | 3 ++-
Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec | 1 -
Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc | 1 +
28 files changed, 34 insertions(+), 18 deletions(-)
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
index 79924f1fda7f..81dc0747fab8 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd
+++ .dsc
@@ -65,6 +65,7 @@
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 # # PCIe Reserved Memory Space Range #diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
index e3fdd3981653..c4dd863c3ee8 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtS
+++ mm.inf
@@ -49,7 +49,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES [FixedPcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES [Sources] TbtSmiHandler.hdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
index a4ea524e26bc..3ed7aa0a2b10 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg
+++ Pcd.dsc
@@ -241,6 +241,7 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 !endif gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
index e6c185a4bd91..13116488eaa0 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSm
+++ m.inf
@@ -46,7 +46,7 @@
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES [FixedPcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES [Sources] TbtSmiHandler.hdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
index 1de10aa0080f..5f65f02a9f64 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatfor
+++ mHookLib/BasePlatformHookLib.inf
@@ -35,7 +35,7 @@
KabylakeSiliconPkg/SiPkg.dec [Pcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSUMESdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
index c6b9df842936..ec23c691b2fe 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
@@ -194,6 +194,7 @@
gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 !endif gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 !endifdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
index 7a5e290657f2..8bdf13b1ce11 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatf
+++ ormHookLib/BasePlatformHookLib.inf
@@ -35,7 +35,7 @@
KabylakeSiliconPkg/SiPkg.dec [Pcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSUMESdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
index 2f7765e58a69..cfd032814850 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d
+++ sc
@@ -194,6 +194,7 @@
gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 !endif gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 !endifdiff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
index 2fd6d0c50e05..2fb2e1ce58f4 100644
--- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd
+++ .dsc
@@ -117,6 +117,7 @@
#!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 #!endif+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000 #diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
index bfe299d73374..83ebc790aeb4 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/Tb
+++ tSmm.inf
@@ -49,7 +49,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES [FixedPcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES [Sources] TbtSmiHandler.hdiff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
index a7e9a41e2c34..dbe068d0c123 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.ds
+++ c
@@ -65,6 +65,7 @@
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 [PcdsFeatureFlag.common] ######################################diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
index daf5411ac358..451926d67190 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPk
+++ gPcd.dsc
@@ -65,6 +65,7 @@
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 [PcdsFeatureFlag.common] ######################################diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
index c5f10492edc8..e62e37cda036 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
@@ -42,6 +42,7 @@ gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE
[PcdsFixedAtBuild.common] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xE0000000 gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength |0x10000000+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress |0x1800 gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin |10 gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax |18diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
index 1534a24dd240..432d4c0c2656 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSi
+++ liconInitLib.inf
@@ -32,6 +32,7 @@
[Packages] MdePkg/MdePkg.dec+ IntelSiliconPkg/IntelSiliconPkg.dec CoffeelakeSiliconPkg/SiPkg.dec [Sources]@@ -42,5 +43,5 @@
gTcoWdtHobGuid ## CONSUMES [Pcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES- gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMESdiff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
index 78e212eeb0fd..61778ed5a066 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/Pei
+++ DxeSmmPmcLib.inf
@@ -32,11 +32,12 @@ BaseMemoryLib
[Packages] MdePkg/MdePkg.dec+IntelSiliconPkg/IntelSiliconPkg.dec CoffeelakeSiliconPkg/SiPkg.dec [Pcd]-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress [Sources]diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf
index 573acfc25e31..1f84337afafb 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPm
+++ cPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf
@@ -39,7 +39,7 @@ CoffeelakeSiliconPkg/SiPkg.dec
IntelSiliconPkg/IntelSiliconPkg.dec [Pcd]-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress [Sources]diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
index efc2d8788168..ca3e83bd61da 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
@@ -516,7 +516,6 @@ gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFED10000|UINT64|0x00010030
## This value is used to set the base address of PCH devices gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031 gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010034-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035 ## 32KB window gSiPkgTokenSpaceGuid.PcdMchMmioSize|0x8000|UINT32|0x50000000diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index c36d130a0197..deefdc55b5d6 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -147,6 +147,10 @@
# @Prompt Error code for VTd error. gIntelSiliconPkgTokenSpaceGuid.PcdErrorCodeVTdError|0x02008000|UINT32|0x00000005 + ## ABase I/O address.<BR><BR>+ # @Prompt ABase I/O address.+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x0|UINT16|0x0000000D+ [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] ## This is the GUID of the FFS which contains the Graphics Video BIOS Table (VBT) # The VBT content is stored as a RAW section which is consumed by GOP PEI/UEFI driver.diff --git a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc b/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc
index d980a2c5369a..ff7728279a08 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc
+++ b/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc
@@ -48,6 +48,7 @@ gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE
[PcdsFixedAtBuild.common] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xE0000000 gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength |0x10000000+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress |0x1800 # # This DSC mainly for GreenH Silicon code build so PciExpressBaseAddress can be FixedAtBuild #diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
index 3b94a02e6bf4..32205bb04f64 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSili
+++ conInitLib.inf
@@ -46,7 +46,7 @@
SiliconInitPreMem.c [Pcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMES diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf
index 1e6103f4ca38..5ae3b4d6256a 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/Pe
+++ iDxeSmmPchPmcLib.inf
@@ -30,11 +30,12 @@ PchCycleDecodingLib
[Packages] MdePkg/MdePkg.dec+IntelSiliconPkg/IntelSiliconPkg.dec KabylakeSiliconPkg/SiPkg.dec [Pcd]-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress [Sources]diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf
index a5ccf4698b7d..41eaffe52e66 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPc
+++ hPolicyLib.inf
@@ -35,7 +35,7 @@ KabylakeSiliconPkg/SiPkg.dec IntelSiliconPkg/IntelSiliconPkg.dec [Pcd]-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable gSiPkgTokenSpaceGuid.PcdSerialIoUartNumberdiff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf
index ba57c44e1e12..f912d6e76d4a 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.i
+++ nf
@@ -39,7 +39,7 @@
PeiSpiLib.c [Pcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES [Ppis] gPchSpi2PpiGuid ## PRODUCESdiff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
index d9ae9f6dfd91..6c9af567f5ee 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
+++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
@@ -497,7 +497,6 @@ gSiPkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|40|UINT8|0x0001002f
gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFED10000|UINT64|0x00010030 gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031 gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010034-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035 ## 32KB window gSiPkgTokenSpaceGuid.PcdMchMmioSize|0x8000|UINT32|0x50000000diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
index eba6db767c5c..c52a157c7d39 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
+++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmc
+++ Lib/PeiDxeSmmPmcLib.inf
@@ -31,11 +31,12 @@ BaseMemoryLib
[Packages] MdePkg/MdePkg.dec+IntelSiliconPkg/IntelSiliconPkg.dec TigerlakeSiliconPkg/SiPkg.dec [Pcd]-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress gSiPkgTokenSpaceGuid.PcdTcoBaseAddress [Sources]diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf
index 2bd57b79f035..32a4e9a07a76 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf
+++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDx
+++ eSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf
@@ -27,11 +27,12 @@ PmcLib
[Packages] MdePkg/MdePkg.dec+IntelSiliconPkg/IntelSiliconPkg.dec TigerlakeSiliconPkg/SiPkg.dec [Pcd]-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress [FixedPcd] diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec b/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec
index 7cdbb3748155..991ca1555bf7 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec
+++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec
@@ -976,7 +976,6 @@ gMeConfigSpaceGuid.PcdHeciTimeoutsEnabled|TRUE|BOOLEAN|0x50000002
## This value is used to set the base address of PCH devices gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031 gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010033-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035 ## Stack size in the temporary RAM.diff --git a/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc b/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc
index 36df41f09fb4..f11305d266cb 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc
+++ b/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc
@@ -60,6 +60,7 @@ gSiPkgTokenSpaceGuid.PcdSpaEnable |FALSE
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xC0000000 gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress |gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength |0x10000000+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress |0x1800 [PcdsDynamicDefault.common] gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength |0x10000000--
2.37.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [edk2-devel][edk2-platforms][PATCH v2 1/6] {Platform,Silicon}/Intel: Move PcdAcpiBaseAddress definition
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 1/6] {Platform,Silicon}/Intel: Move PcdAcpiBaseAddress definition Benjamin Doron
2022-09-07 22:50 ` Isaac Oram
@ 2022-09-07 22:57 ` Chaganty, Rangasai V
2022-09-09 21:11 ` Isaac Oram
1 sibling, 1 reply; 17+ messages in thread
From: Chaganty, Rangasai V @ 2022-09-07 22:57 UTC (permalink / raw)
To: Benjamin Doron, devel@edk2.groups.io
Cc: Oram, Isaac W, Desimone, Nathaniel L, Sinha, Ankit, Ni, Ray,
Chiu, Chasel, Luo, Heng
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Benjamin Doron <benjamin.doron00@gmail.com>
Sent: Tuesday, September 06, 2022 10:02 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Ni, Ray <ray.ni@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Luo, Heng <heng.luo@intel.com>
Subject: [edk2-devel][edk2-platforms][PATCH v2 1/6] {Platform,Silicon}/Intel: Move PcdAcpiBaseAddress definition
All these platforms have an ABase, so move the definition to enable common silicon code in IntelSiliconPkg. Otherwise, library shims would be required, because PCDs are GUID-ed and package DEC specific.
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Heng Luo <heng.luo@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc | 1 +
.../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
.../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 1 +
.../KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
.../Library/BasePlatformHookLib/BasePlatformHookLib.inf | 2 +-
.../KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc | 1 +
.../Library/BasePlatformHookLib/BasePlatformHookLib.inf | 2 +-
.../KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 1 +
.../TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc | 1 +
.../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
.../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 1 +
.../WhiskeylakeURvp/OpenBoardPkgPcd.dsc | 1 +
Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc | 1 +
.../Library/PeiSiliconInitLib/PeiSiliconInitLib.inf | 5 +++--
.../Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf | 3 ++-
.../PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf | 2 +-
Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec | 1 -
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 4 ++++
Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc | 1 +
.../Library/PeiSiliconInitLib/PeiSiliconInitLib.inf | 2 +-
.../Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf | 3 ++-
.../Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf | 2 +-
.../KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf | 2 +-
Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec | 1 -
.../IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf | 3 ++-
.../PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf | 3 ++-
Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec | 1 -
Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc | 1 +
28 files changed, 34 insertions(+), 18 deletions(-)
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
index 79924f1fda7f..81dc0747fab8 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd
+++ .dsc
@@ -65,6 +65,7 @@
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 # # PCIe Reserved Memory Space Range #diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
index e3fdd3981653..c4dd863c3ee8 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtS
+++ mm.inf
@@ -49,7 +49,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES [FixedPcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES [Sources] TbtSmiHandler.hdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
index a4ea524e26bc..3ed7aa0a2b10 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg
+++ Pcd.dsc
@@ -241,6 +241,7 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 !endif gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
index e6c185a4bd91..13116488eaa0 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSm
+++ m.inf
@@ -46,7 +46,7 @@
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES [FixedPcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES [Sources] TbtSmiHandler.hdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
index 1de10aa0080f..5f65f02a9f64 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatfor
+++ mHookLib/BasePlatformHookLib.inf
@@ -35,7 +35,7 @@
KabylakeSiliconPkg/SiPkg.dec [Pcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSUMESdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
index c6b9df842936..ec23c691b2fe 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
@@ -194,6 +194,7 @@
gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 !endif gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 !endifdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
index 7a5e290657f2..8bdf13b1ce11 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatf
+++ ormHookLib/BasePlatformHookLib.inf
@@ -35,7 +35,7 @@
KabylakeSiliconPkg/SiPkg.dec [Pcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSUMESdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
index 2f7765e58a69..cfd032814850 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d
+++ sc
@@ -194,6 +194,7 @@
gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 !endif gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 !endifdiff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
index 2fd6d0c50e05..2fb2e1ce58f4 100644
--- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd
+++ .dsc
@@ -117,6 +117,7 @@
#!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 #!endif+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000 #diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
index bfe299d73374..83ebc790aeb4 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/Tb
+++ tSmm.inf
@@ -49,7 +49,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES [FixedPcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES [Sources] TbtSmiHandler.hdiff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
index a7e9a41e2c34..dbe068d0c123 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.ds
+++ c
@@ -65,6 +65,7 @@
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 [PcdsFeatureFlag.common] ######################################diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
index daf5411ac358..451926d67190 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPk
+++ gPcd.dsc
@@ -65,6 +65,7 @@
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 [PcdsFeatureFlag.common] ######################################diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
index c5f10492edc8..e62e37cda036 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
@@ -42,6 +42,7 @@ gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE
[PcdsFixedAtBuild.common] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xE0000000 gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength |0x10000000+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress |0x1800 gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin |10 gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax |18diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
index 1534a24dd240..432d4c0c2656 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSi
+++ liconInitLib.inf
@@ -32,6 +32,7 @@
[Packages] MdePkg/MdePkg.dec+ IntelSiliconPkg/IntelSiliconPkg.dec CoffeelakeSiliconPkg/SiPkg.dec [Sources]@@ -42,5 +43,5 @@
gTcoWdtHobGuid ## CONSUMES [Pcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES- gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMESdiff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
index 78e212eeb0fd..61778ed5a066 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/Pei
+++ DxeSmmPmcLib.inf
@@ -32,11 +32,12 @@ BaseMemoryLib
[Packages] MdePkg/MdePkg.dec+IntelSiliconPkg/IntelSiliconPkg.dec CoffeelakeSiliconPkg/SiPkg.dec [Pcd]-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress [Sources]diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf
index 573acfc25e31..1f84337afafb 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPm
+++ cPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf
@@ -39,7 +39,7 @@ CoffeelakeSiliconPkg/SiPkg.dec
IntelSiliconPkg/IntelSiliconPkg.dec [Pcd]-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress [Sources]diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
index efc2d8788168..ca3e83bd61da 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
@@ -516,7 +516,6 @@ gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFED10000|UINT64|0x00010030
## This value is used to set the base address of PCH devices gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031 gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010034-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035 ## 32KB window gSiPkgTokenSpaceGuid.PcdMchMmioSize|0x8000|UINT32|0x50000000diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index c36d130a0197..deefdc55b5d6 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -147,6 +147,10 @@
# @Prompt Error code for VTd error. gIntelSiliconPkgTokenSpaceGuid.PcdErrorCodeVTdError|0x02008000|UINT32|0x00000005 + ## ABase I/O address.<BR><BR>+ # @Prompt ABase I/O address.+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x0|UINT16|0x0000000D+ [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] ## This is the GUID of the FFS which contains the Graphics Video BIOS Table (VBT) # The VBT content is stored as a RAW section which is consumed by GOP PEI/UEFI driver.diff --git a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc b/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc
index d980a2c5369a..ff7728279a08 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc
+++ b/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc
@@ -48,6 +48,7 @@ gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE
[PcdsFixedAtBuild.common] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xE0000000 gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength |0x10000000+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress |0x1800 # # This DSC mainly for GreenH Silicon code build so PciExpressBaseAddress can be FixedAtBuild #diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
index 3b94a02e6bf4..32205bb04f64 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSili
+++ conInitLib.inf
@@ -46,7 +46,7 @@
SiliconInitPreMem.c [Pcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMES diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf
index 1e6103f4ca38..5ae3b4d6256a 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/Pe
+++ iDxeSmmPchPmcLib.inf
@@ -30,11 +30,12 @@ PchCycleDecodingLib
[Packages] MdePkg/MdePkg.dec+IntelSiliconPkg/IntelSiliconPkg.dec KabylakeSiliconPkg/SiPkg.dec [Pcd]-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress [Sources]diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf
index a5ccf4698b7d..41eaffe52e66 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPc
+++ hPolicyLib.inf
@@ -35,7 +35,7 @@ KabylakeSiliconPkg/SiPkg.dec IntelSiliconPkg/IntelSiliconPkg.dec [Pcd]-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable gSiPkgTokenSpaceGuid.PcdSerialIoUartNumberdiff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf
index ba57c44e1e12..f912d6e76d4a 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.i
+++ nf
@@ -39,7 +39,7 @@
PeiSpiLib.c [Pcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES [Ppis] gPchSpi2PpiGuid ## PRODUCESdiff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
index d9ae9f6dfd91..6c9af567f5ee 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
+++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
@@ -497,7 +497,6 @@ gSiPkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|40|UINT8|0x0001002f
gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFED10000|UINT64|0x00010030 gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031 gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010034-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035 ## 32KB window gSiPkgTokenSpaceGuid.PcdMchMmioSize|0x8000|UINT32|0x50000000diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
index eba6db767c5c..c52a157c7d39 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
+++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmc
+++ Lib/PeiDxeSmmPmcLib.inf
@@ -31,11 +31,12 @@ BaseMemoryLib
[Packages] MdePkg/MdePkg.dec+IntelSiliconPkg/IntelSiliconPkg.dec TigerlakeSiliconPkg/SiPkg.dec [Pcd]-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress gSiPkgTokenSpaceGuid.PcdTcoBaseAddress [Sources]diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf
index 2bd57b79f035..32a4e9a07a76 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf
+++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDx
+++ eSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf
@@ -27,11 +27,12 @@ PmcLib
[Packages] MdePkg/MdePkg.dec+IntelSiliconPkg/IntelSiliconPkg.dec TigerlakeSiliconPkg/SiPkg.dec [Pcd]-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress [FixedPcd] diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec b/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec
index 7cdbb3748155..991ca1555bf7 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec
+++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec
@@ -976,7 +976,6 @@ gMeConfigSpaceGuid.PcdHeciTimeoutsEnabled|TRUE|BOOLEAN|0x50000002
## This value is used to set the base address of PCH devices gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031 gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010033-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035 ## Stack size in the temporary RAM.diff --git a/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc b/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc
index 36df41f09fb4..f11305d266cb 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc
+++ b/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc
@@ -60,6 +60,7 @@ gSiPkgTokenSpaceGuid.PcdSpaEnable |FALSE
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xC0000000 gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress |gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength |0x10000000+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress |0x1800 [PcdsDynamicDefault.common] gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength |0x10000000--
2.37.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [edk2-devel][edk2-platforms][PATCH v2 2/6] IntelSiliconPkg/Feature/SmmAccess: Implement PPI with chipset support
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 2/6] IntelSiliconPkg/Feature/SmmAccess: Implement PPI with chipset support Benjamin Doron
@ 2022-09-07 23:49 ` Isaac Oram
[not found] ` <1712B8F6079EA3A9.20240@groups.io>
1 sibling, 0 replies; 17+ messages in thread
From: Isaac Oram @ 2022-09-07 23:49 UTC (permalink / raw)
To: Benjamin Doron, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Sinha, Ankit, Ni, Ray,
Chaganty, Rangasai V
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>
-----Original Message-----
From: Benjamin Doron <benjamin.doron00@gmail.com>
Sent: Tuesday, September 6, 2022 10:02 AM
To: devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>
Subject: [edk2-devel][edk2-platforms][PATCH v2 2/6] IntelSiliconPkg/Feature/SmmAccess: Implement PPI with chipset support
SMRAM must be opened to retrieve the lockbox for S3, and SMM communication depends on this PPI. For security purposes, SMRAM lock must be performed before EndOfPei (although FSP notify performs lockdown too).
It seems to me that this library is generic and applicable to all Intel platforms in the tree using the MCH SMRAMC register.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../PeiSmmAccessLibSmramc/PeiSmmAccessLib.c | 430 ++++++++++++++++++
.../PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf | 36 ++
2 files changed, 466 insertions(+)
create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.c
create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.c b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.c
new file mode 100644
index 000000000000..5b472bf86abf
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAcce
+++ ssLibSmramc/PeiSmmAccessLib.c
@@ -0,0 +1,430 @@
+/** @file+ This is to publish the SMM Access Ppi instance.++ Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>+ SPDX-License-Identifier: BSD-2-Clause-Patent++**/+#include <Library/BaseMemoryLib.h>+#include <Library/DebugLib.h>+#include <Library/MemoryAllocationLib.h>+#include <Library/PciSegmentLib.h>+#include <Library/PeiServicesLib.h>+#include <Library/HobLib.h>+#include <Uefi/UefiBaseType.h>+#include <Guid/SmramMemoryReserve.h>++#include <Ppi/MmAccess.h>+#include <IndustryStandard/Pci22.h>++#define SMM_ACCESS_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('4', '5', 's', 'a')++///+/// Private data+///+typedef struct {+ UINTN Signature;+ EFI_HANDLE Handle;+ EFI_PEI_MM_ACCESS_PPI SmmAccess;+ //+ // Local Data for SMM Access interface goes here+ //+ UINTN NumberRegions;+ EFI_SMRAM_DESCRIPTOR *SmramDesc;+} SMM_ACCESS_PRIVATE_DATA;++#define SMM_ACCESS_PRIVATE_DATA_FROM_THIS(a) \+ CR (a, \+ SMM_ACCESS_PRIVATE_DATA, \+ SmmAccess, \+ SMM_ACCESS_PRIVATE_DATA_SIGNATURE \+ )++//+// Common registers:+//+// DEVICE 0 (Memory Controller Hub)+//+#define SA_MC_BUS 0x00+#define SA_MC_DEV 0x00+#define SA_MC_FUN 0x00+///+/// Description:+/// The SMRAMC register controls how accesses to Compatible SMRAM spaces are treated. The Open, Close and Lock bits function only when G_SMRAME bit is set to 1. Also, the Open bit must be reset before the Lock bit is set.+///+#define R_SA_SMRAMC (0x88)+#define B_SA_SMRAMC_D_LCK_MASK (0x10)+#define B_SA_SMRAMC_D_CLS_MASK (0x20)+#define B_SA_SMRAMC_D_OPEN_MASK (0x40)++/**+ This routine accepts a request to "open" a region of SMRAM. The+ region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.+ The use of "open" means that the memory is visible from all PEIM+ and SMM agents.++ @param[in] PeiServices - General purpose services available to every PEIM.+ @param[in] This - Pointer to the SMM Access Interface.+ @param[in] DescriptorIndex - Region of SMRAM to Open.++ @retval EFI_SUCCESS - The region was successfully opened.+ @retval EFI_DEVICE_ERROR - The region could not be opened because locked by+ chipset.+ @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.+**/+EFI_STATUS+EFIAPI+Open (+ IN EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_ACCESS_PPI *This,+ IN UINTN DescriptorIndex+ )+{+ SMM_ACCESS_PRIVATE_DATA *SmmAccess;+ UINT8 Index;+ UINT64 Address;+ UINT8 SmramControl;++ SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);+ if (DescriptorIndex >= SmmAccess->NumberRegions) {+ DEBUG ((DEBUG_WARN, "SMRAM region out of range\n"));++ return EFI_INVALID_PARAMETER;+ } else if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_LOCKED) {+ //+ // Cannot open a "locked" region+ //+ DEBUG ((DEBUG_WARN, "Cannot open a locked SMRAM region\n"));++ return EFI_DEVICE_ERROR;+ }++ ///+ /// BEGIN CHIPSET CODE+ ///+ ///+ /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit)+ ///+ Address = PCI_SEGMENT_LIB_ADDRESS (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC);+ SmramControl = PciSegmentRead8 (Address);+ ///+ /// Is SMRAM locked?+ ///+ if ((SmramControl & B_SA_SMRAMC_D_LCK_MASK) != 0) {+ ///+ /// Cannot Open a locked region+ ///+ for (Index = 0; Index < SmmAccess->NumberRegions; Index++) {+ SmmAccess->SmramDesc[Index].RegionState |= EFI_SMRAM_LOCKED;+ }+ DEBUG ((DEBUG_WARN, "Cannot open a locked SMRAM region\n"));+ return EFI_DEVICE_ERROR;+ }+ ///+ /// Open SMRAM region+ ///+ SmramControl |= B_SA_SMRAMC_D_OPEN_MASK;+ SmramControl &= ~(B_SA_SMRAMC_D_CLS_MASK);++ PciSegmentWrite8 (Address, SmramControl);+ ///+ /// END CHIPSET CODE+ ///++ SmmAccess->SmramDesc[DescriptorIndex].RegionState &= (UINT64) ~(EFI_SMRAM_CLOSED | EFI_ALLOCATED);+ SmmAccess->SmramDesc[DescriptorIndex].RegionState |= (UINT64) EFI_SMRAM_OPEN;+ SmmAccess->SmmAccess.OpenState = TRUE;+ return EFI_SUCCESS;+}++/**+ This routine accepts a request to "close" a region of SMRAM. This is valid for+ compatible SMRAM region.++ @param[in] PeiServices - General purpose services available to every PEIM.+ @param[in] This - Pointer to the SMM Access Interface.+ @param[in] DescriptorIndex - Region of SMRAM to Close.++ @retval EFI_SUCCESS - The region was successfully closed.+ @retval EFI_DEVICE_ERROR - The region could not be closed because locked by+ chipset.+ @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.+**/+EFI_STATUS+EFIAPI+Close (+ IN EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_ACCESS_PPI *This,+ IN UINTN DescriptorIndex+ )+{+ SMM_ACCESS_PRIVATE_DATA *SmmAccess;+ BOOLEAN OpenState;+ UINT8 Index;+ UINT64 Address;+ UINT8 SmramControl;++ SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);+ if (DescriptorIndex >= SmmAccess->NumberRegions) {+ DEBUG ((DEBUG_WARN, "SMRAM region out of range\n"));++ return EFI_INVALID_PARAMETER;+ } else if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_LOCKED) {+ //+ // Cannot close a "locked" region+ //+ DEBUG ((DEBUG_WARN, "Cannot close a locked SMRAM region\n"));++ return EFI_DEVICE_ERROR;+ }++ if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_CLOSED) {+ return EFI_DEVICE_ERROR;+ }++ ///+ /// BEGIN CHIPSET CODE+ ///+ ///+ /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit)+ ///+ Address = PCI_SEGMENT_LIB_ADDRESS (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC);+ SmramControl = PciSegmentRead8 (Address);+ ///+ /// Is SMRAM locked?+ ///+ if ((SmramControl & B_SA_SMRAMC_D_LCK_MASK) != 0) {+ ///+ /// Cannot Close a locked region+ ///+ for (Index = 0; Index < SmmAccess->NumberRegions; Index++) {+ SmmAccess->SmramDesc[Index].RegionState |= EFI_SMRAM_LOCKED;+ }+ DEBUG ((DEBUG_WARN, "Cannot close a locked SMRAM region\n"));+ return EFI_DEVICE_ERROR;+ }+ ///+ /// Close SMRAM region+ ///+ SmramControl &= ~(B_SA_SMRAMC_D_OPEN_MASK);++ PciSegmentWrite8 (Address, SmramControl);+ ///+ /// END CHIPSET CODE+ ///++ SmmAccess->SmramDesc[DescriptorIndex].RegionState &= (UINT64) ~EFI_SMRAM_OPEN;+ SmmAccess->SmramDesc[DescriptorIndex].RegionState |= (UINT64) (EFI_SMRAM_CLOSED | EFI_ALLOCATED);++ //+ // Find out if any regions are still open+ //+ OpenState = FALSE;+ for (Index = 0; Index < SmmAccess->NumberRegions; Index++) {+ if ((SmmAccess->SmramDesc[Index].RegionState & EFI_SMRAM_OPEN) == EFI_SMRAM_OPEN) {+ OpenState = TRUE;+ }+ }++ SmmAccess->SmmAccess.OpenState = OpenState;+ return EFI_SUCCESS;+}++/**+ This routine accepts a request to "lock" SMRAM. The+ region could be legacy AB or TSEG near top of physical memory.+ The use of "lock" means that the memory can no longer be opened+ to PEIM.++ @param[in] PeiServices - General purpose services available to every PEIM.+ @param[in] This - Pointer to the SMM Access Interface.+ @param[in] DescriptorIndex - Region of SMRAM to Lock.++ @retval EFI_SUCCESS - The region was successfully locked.+ @retval EFI_DEVICE_ERROR - The region could not be locked because at least+ one range is still open.+ @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.+**/+EFI_STATUS+EFIAPI+Lock (+ IN EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_ACCESS_PPI *This,+ IN UINTN DescriptorIndex+ )+{+ SMM_ACCESS_PRIVATE_DATA *SmmAccess;+ UINT64 Address;+ UINT8 SmramControl;++ SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);+ if (DescriptorIndex >= SmmAccess->NumberRegions) {+ DEBUG ((DEBUG_WARN, "SMRAM region out of range\n"));++ return EFI_INVALID_PARAMETER;+ } else if (SmmAccess->SmmAccess.OpenState) {+ DEBUG ((DEBUG_WARN, "Cannot lock SMRAM when SMRAM regions are still open\n"));++ return EFI_DEVICE_ERROR;+ }++ SmmAccess->SmramDesc[DescriptorIndex].RegionState |= (UINT64) EFI_SMRAM_LOCKED;+ SmmAccess->SmmAccess.LockState = TRUE;++ ///+ /// BEGIN CHIPSET CODE+ ///+ ///+ /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit)+ ///+ Address = PCI_SEGMENT_LIB_ADDRESS (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC);+ SmramControl = PciSegmentRead8 (Address);++ ///+ /// Lock the SMRAM+ ///+ SmramControl |= B_SA_SMRAMC_D_LCK_MASK;++ PciSegmentWrite8 (Address, SmramControl);+ ///+ /// END CHIPSET CODE+ ///++ return EFI_SUCCESS;+}++/**+ This routine services a user request to discover the SMRAM+ capabilities of this platform. This will report the possible+ ranges that are possible for SMRAM access, based upon the+ memory controller capabilities.++ @param[in] PeiServices - General purpose services available to every PEIM.+ @param[in] This - Pointer to the SMRAM Access Interface.+ @param[in, out] SmramMapSize - Pointer to the variable containing size of the+ buffer to contain the description information.+ @param[in, out] SmramMap - Buffer containing the data describing the Smram+ region descriptors.++ @retval EFI_BUFFER_TOO_SMALL - The user did not provide a sufficient buffer.+ @retval EFI_SUCCESS - The user provided a sufficiently-sized buffer.+**/+EFI_STATUS+EFIAPI+GetCapabilities (+ IN EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_ACCESS_PPI *This,+ IN OUT UINTN *SmramMapSize,+ IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap+ )+{+ EFI_STATUS Status;+ SMM_ACCESS_PRIVATE_DATA *SmmAccess;+ UINTN NecessaryBufferSize;++ SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);+ NecessaryBufferSize = SmmAccess->NumberRegions * sizeof (EFI_SMRAM_DESCRIPTOR);+ if (*SmramMapSize < NecessaryBufferSize) {+ DEBUG ((DEBUG_WARN, "SMRAM Map Buffer too small\n"));++ Status = EFI_BUFFER_TOO_SMALL;+ } else {+ CopyMem (SmramMap, SmmAccess->SmramDesc, NecessaryBufferSize);+ Status = EFI_SUCCESS;+ }++ *SmramMapSize = NecessaryBufferSize;+ return Status;+}++/**+ This function is to install an SMM Access PPI+ - <b>Introduction</b> \n+ An API to install an instance of EFI_PEI_MM_ACCESS_PPI. This PPI is commonly used to control SMM mode memory access for S3 resume.++ @retval EFI_SUCCESS - Ppi successfully started and installed.+ @retval EFI_NOT_FOUND - Ppi can't be found.+ @retval EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to initialize the driver.+**/+EFI_STATUS+EFIAPI+PeiInstallSmmAccessPpi (+ VOID+ )+{+ EFI_STATUS Status;+ UINTN Index;+ EFI_PEI_PPI_DESCRIPTOR *PpiList;+ EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *DescriptorBlock;+ SMM_ACCESS_PRIVATE_DATA *SmmAccessPrivate;+ VOID *HobList;++ //+ // Initialize private data+ //+ SmmAccessPrivate = AllocateZeroPool (sizeof (*SmmAccessPrivate));+ ASSERT (SmmAccessPrivate != NULL);+ if (SmmAccessPrivate == NULL) {+ return EFI_OUT_OF_RESOURCES;+ }+ PpiList = AllocateZeroPool (sizeof (*PpiList));+ ASSERT (PpiList != NULL);+ if (PpiList == NULL) {+ return EFI_OUT_OF_RESOURCES;+ }++ SmmAccessPrivate->Signature = SMM_ACCESS_PRIVATE_DATA_SIGNATURE;+ SmmAccessPrivate->Handle = NULL;++ //+ // Get Hob list+ //+ HobList = GetFirstGuidHob (&gEfiSmmSmramMemoryGuid);+ if (HobList == NULL) {+ DEBUG ((DEBUG_WARN, "SmramMemoryReserve HOB not found\n"));+ return EFI_NOT_FOUND;+ }++ DescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) ((UINT8 *) HobList + sizeof (EFI_HOB_GUID_TYPE));++ //+ // Alloc space for SmmAccessPrivate->SmramDesc+ //+ SmmAccessPrivate->SmramDesc = AllocateZeroPool ((DescriptorBlock->NumberOfSmmReservedRegions) * sizeof (EFI_SMRAM_DESCRIPTOR));+ if (SmmAccessPrivate->SmramDesc == NULL) {+ DEBUG ((DEBUG_WARN, "Alloc SmmAccessPrivate->SmramDesc fail.\n"));+ return EFI_OUT_OF_RESOURCES;+ }++ DEBUG ((DEBUG_INFO, "Alloc SmmAccessPrivate->SmramDesc success.\n"));++ //+ // use the hob to publish SMRAM capabilities+ //+ for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {+ SmmAccessPrivate->SmramDesc[Index].PhysicalStart = DescriptorBlock->Descriptor[Index].PhysicalStart;+ SmmAccessPrivate->SmramDesc[Index].CpuStart = DescriptorBlock->Descriptor[Index].CpuStart;+ SmmAccessPrivate->SmramDesc[Index].PhysicalSize = DescriptorBlock->Descriptor[Index].PhysicalSize;+ SmmAccessPrivate->SmramDesc[Index].RegionState = DescriptorBlock->Descriptor[Index].RegionState;+ }++ SmmAccessPrivate->NumberRegions = Index;+ SmmAccessPrivate->SmmAccess.Open = Open;+ SmmAccessPrivate->SmmAccess.Close = Close;+ SmmAccessPrivate->SmmAccess.Lock = Lock;+ SmmAccessPrivate->SmmAccess.GetCapabilities = GetCapabilities;+ SmmAccessPrivate->SmmAccess.LockState = FALSE;+ SmmAccessPrivate->SmmAccess.OpenState = FALSE;++ //+ // Install PPI+ //+ PpiList->Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);+ PpiList->Guid = &gEfiPeiMmAccessPpiGuid;+ PpiList->Ppi = &SmmAccessPrivate->SmmAccess;++ Status = PeiServicesInstallPpi (PpiList);+ ASSERT_EFI_ERROR (Status);++ return EFI_SUCCESS;+}diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf
new file mode 100644
index 000000000000..160210d429d9
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAcce
+++ ssLibSmramc/PeiSmmAccessLib.inf
@@ -0,0 +1,36 @@
+## @file+# Library description file for the SmmAccess PPI+#+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>+# SPDX-License-Identifier: BSD-2-Clause-Patent+#+##++[Defines]+ INF_VERSION = 0x00010017+ BASE_NAME = PeiSmmAccessLibSmramc+ FILE_GUID = 3D28FD4B-F46F-4E24-88AA-9DA09C51BE87+ VERSION_STRING = 1.0+ MODULE_TYPE = PEIM+ LIBRARY_CLASS = SmmAccessLib++[LibraryClasses]+ BaseMemoryLib+ MemoryAllocationLib+ DebugLib+ HobLib+ PciSegmentLib+ PeiServicesLib++[Packages]+ MdePkg/MdePkg.dec+ IntelSiliconPkg/IntelSiliconPkg.dec++[Sources]+ PeiSmmAccessLib.c++[Ppis]+ gEfiPeiMmAccessPpiGuid ## PRODUCES++[Guids]+ gEfiSmmSmramMemoryGuid--
2.37.2
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [edk2-devel][edk2-platforms][PATCH v2 3/6] IntelSiliconPkg/Feature/SmmControl: Implement PPI with chipset support
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 3/6] IntelSiliconPkg/Feature/SmmControl: " Benjamin Doron
@ 2022-09-07 23:50 ` Isaac Oram
[not found] ` <1712B905B760092F.20378@groups.io>
1 sibling, 0 replies; 17+ messages in thread
From: Isaac Oram @ 2022-09-07 23:50 UTC (permalink / raw)
To: Benjamin Doron, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Sinha, Ankit, Ni, Ray,
Chaganty, Rangasai V
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>
-----Original Message-----
From: Benjamin Doron <benjamin.doron00@gmail.com>
Sent: Tuesday, September 6, 2022 10:02 AM
To: devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>
Subject: [edk2-devel][edk2-platforms][PATCH v2 3/6] IntelSiliconPkg/Feature/SmmControl: Implement PPI with chipset support
S3 resume may require communication with SMM, for which we need the SmmControl PPI. Therefore, port the DXE drivers to a library, like there is for SMM Access.
Tested, working on Kabylake. Further testing required after the refactor for compatibility.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../PeiSmmControlLib/PeiSmmControlLib.c | 309 ++++++++++++++++++
.../PeiSmmControlLib/PeiSmmControlLib.inf | 34 ++
.../Include/Library/SmmControlLib.h | 26 ++
.../Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 4 +
4 files changed, 373 insertions(+)
create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.c
create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf
create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.c b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.c
new file mode 100644
index 000000000000..cc6c7f8fe672
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmCon
+++ trolLib/PeiSmmControlLib.c
@@ -0,0 +1,309 @@
+/** @file+ This is to publish the SMM Control Ppi instance.++ Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>+ SPDX-License-Identifier: BSD-2-Clause-Patent++**/+#include <Uefi/UefiBaseType.h>+#include <Library/DebugLib.h>+#include <Library/IoLib.h>+#include <Library/MemoryAllocationLib.h>+#include <Library/PcdLib.h>+#include <Library/PeiServicesLib.h>++#include <Ppi/MmControl.h>+#include <IndustryStandard/Pci30.h>++#define SMM_CONTROL_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('i', '4', 's', 'c')++typedef struct {+ UINTN Signature;+ EFI_HANDLE Handle;+ EFI_PEI_MM_CONTROL_PPI SmmControl;+} SMM_CONTROL_PRIVATE_DATA;++#define SMM_CONTROL_PRIVATE_DATA_FROM_THIS(a) \+ CR (a, \+ SMM_CONTROL_PRIVATE_DATA, \+ SmmControl, \+ SMM_CONTROL_DEV_SIGNATURE \+ )++//+// Common registers:+//+//+// APM Registers+//+#define R_PCH_APM_CNT 0xB2+//+// ACPI and legacy I/O register offsets from ACPIBASE+//+#define R_PCH_ACPI_PM1_STS 0x00+#define B_PCH_ACPI_PM1_STS_PRBTNOR BIT11++#define R_PCH_SMI_EN 0x30++#define R_PCH_SMI_STS 0x34+#define B_PCH_SMI_STS_APM BIT5+#define B_PCH_SMI_EN_APMC BIT5+#define B_PCH_SMI_EN_EOS BIT1+#define B_PCH_SMI_EN_GBL_SMI BIT0++/**+ Trigger the software SMI++ @param[in] Data The value to be set on the software SMI data port++ @retval EFI_SUCCESS Function completes successfully+**/+EFI_STATUS+EFIAPI+SmmTrigger (+ UINT8 Data+ )+{+ UINT16 ABase;+ UINT32 OutputData;+ UINT32 OutputPort;++ ABase = FixedPcdGet16 (PcdAcpiBaseAddress);++ ///+ /// Enable the APMC SMI+ ///+ OutputPort = ABase + R_PCH_SMI_EN;+ OutputData = IoRead32 ((UINTN) OutputPort);+ OutputData |= (B_PCH_SMI_EN_APMC | B_PCH_SMI_EN_GBL_SMI);+ DEBUG (+ (DEBUG_EVENT,+ "The SMI Control Port at address %x will be written to %x.\n",+ OutputPort,+ OutputData)+ );+ IoWrite32 (+ (UINTN) OutputPort,+ (UINT32) (OutputData)+ );++ OutputPort = R_PCH_APM_CNT;+ OutputData = Data;++ ///+ /// Generate the APMC SMI+ ///+ IoWrite8 (+ (UINTN) OutputPort,+ (UINT8) (OutputData)+ );++ return EFI_SUCCESS;+}++/**+ Clear the SMI status+++ @retval EFI_SUCCESS The function completes successfully+ @retval EFI_DEVICE_ERROR Something error occurred+**/+EFI_STATUS+EFIAPI+SmmClear (+ VOID+ )+{+ UINT16 ABase;+ UINT32 OutputData;+ UINT32 OutputPort;++ ABase = FixedPcdGet16 (PcdAcpiBaseAddress);++ ///+ /// Clear the Power Button Override Status Bit, it gates EOS from being set.+ ///+ OutputPort = ABase + R_PCH_ACPI_PM1_STS;+ OutputData = B_PCH_ACPI_PM1_STS_PRBTNOR;+ DEBUG (+ (DEBUG_EVENT,+ "The PM1 Status Port at address %x will be written to %x.\n",+ OutputPort,+ OutputData)+ );+ IoWrite16 (+ (UINTN) OutputPort,+ (UINT16) (OutputData)+ );++ ///+ /// Clear the APM SMI Status Bit+ ///+ OutputPort = ABase + R_PCH_SMI_STS;+ OutputData = B_PCH_SMI_STS_APM;+ DEBUG (+ (DEBUG_EVENT,+ "The SMI Status Port at address %x will be written to %x.\n",+ OutputPort,+ OutputData)+ );+ IoWrite32 (+ (UINTN) OutputPort,+ (UINT32) (OutputData)+ );++ ///+ /// Set the EOS Bit+ ///+ OutputPort = ABase + R_PCH_SMI_EN;+ OutputData = IoRead32 ((UINTN) OutputPort);+ OutputData |= B_PCH_SMI_EN_EOS;+ DEBUG (+ (DEBUG_EVENT,+ "The SMI Control Port at address %x will be written to %x.\n",+ OutputPort,+ OutputData)+ );+ IoWrite32 (+ (UINTN) OutputPort,+ (UINT32) (OutputData)+ );++ ///+ /// There is no need to read EOS back and check if it is set.+ /// This can lead to a reading of zero if an SMI occurs right after the SMI_EN port read+ /// but before the data is returned to the CPU.+ /// SMM Dispatcher should make sure that EOS is set after all SMI sources are processed.+ ///+ return EFI_SUCCESS;+}++/**+ This routine generates an SMI++ @param[in] This The EFI SMM Control protocol instance+ @param[in, out] ArgumentBuffer The buffer of argument+ @param[in, out] ArgumentBufferSize The size of the argument buffer+ @param[in] Periodic Periodic or not+ @param[in] ActivationInterval Interval of periodic SMI++ @retval EFI Status Describing the result of the operation+ @retval EFI_INVALID_PARAMETER Some parameter value passed is not supported+**/+EFI_STATUS+EFIAPI+Activate (+ IN EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_CONTROL_PPI * This,+ IN OUT INT8 *ArgumentBuffer OPTIONAL,+ IN OUT UINTN *ArgumentBufferSize OPTIONAL,+ IN BOOLEAN Periodic OPTIONAL,+ IN UINTN ActivationInterval OPTIONAL+ )+{+ EFI_STATUS Status;+ UINT8 Data;++ if (Periodic) {+ DEBUG ((DEBUG_WARN, "Invalid parameter\n"));+ return EFI_INVALID_PARAMETER;+ }++ // NOTE: Copied from Quark. Matches the usage in PiSmmCommunicationPei+ if (ArgumentBuffer == NULL) {+ Data = 0xFF;+ } else {+ if (ArgumentBufferSize == NULL || *ArgumentBufferSize != 1) {+ return EFI_INVALID_PARAMETER;+ }++ Data = *ArgumentBuffer;+ }+ ///+ /// Clear any pending the APM SMI+ ///+ Status = SmmClear ();+ if (EFI_ERROR (Status)) {+ return Status;+ }++ return SmmTrigger (Data);+}++/**+ This routine clears an SMI++ @param[in] This The EFI SMM Control protocol instance+ @param[in] Periodic Periodic or not++ @retval EFI Status Describing the result of the operation+ @retval EFI_INVALID_PARAMETER Some parameter value passed is not supported+**/+EFI_STATUS+EFIAPI+Deactivate (+ IN EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_CONTROL_PPI * This,+ IN BOOLEAN Periodic OPTIONAL+ )+{+ if (Periodic) {+ return EFI_INVALID_PARAMETER;+ }++ return SmmClear ();+}++/**+ This function is to install an SMM Control PPI+ - <b>Introduction</b> \n+ An API to install an instance of EFI_PEI_MM_CONTROL_PPI. This PPI provides a standard+ way for other modules to trigger software SMIs.++ @retval EFI_SUCCESS - Ppi successfully started and installed.+ @retval EFI_NOT_FOUND - Ppi can't be found.+ @retval EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to initialize the driver.+**/+EFI_STATUS+EFIAPI+PeiInstallSmmControlPpi (+ VOID+ )+{+ EFI_STATUS Status;+ EFI_PEI_PPI_DESCRIPTOR *PpiList;+ SMM_CONTROL_PRIVATE_DATA *SmmControlPrivate;++ //+ // Initialize private data+ //+ SmmControlPrivate = AllocateZeroPool (sizeof (*SmmControlPrivate));+ ASSERT (SmmControlPrivate != NULL);+ if (SmmControlPrivate == NULL) {+ return EFI_OUT_OF_RESOURCES;+ }+ PpiList = AllocateZeroPool (sizeof (*PpiList));+ ASSERT (PpiList != NULL);+ if (PpiList == NULL) {+ return EFI_OUT_OF_RESOURCES;+ }++ SmmControlPrivate->Signature = SMM_CONTROL_PRIVATE_DATA_SIGNATURE;+ SmmControlPrivate->Handle = NULL;++ SmmControlPrivate->SmmControl.Trigger = Activate;+ SmmControlPrivate->SmmControl.Clear = Deactivate;++ //+ // Install PPI+ //+ PpiList->Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);+ PpiList->Guid = &gEfiPeiMmControlPpiGuid;+ PpiList->Ppi = &SmmControlPrivate->SmmControl;++ Status = PeiServicesInstallPpi (PpiList);+ ASSERT_EFI_ERROR (Status);++ // Unlike driver, do not disable SMIs as S3 resume continues+ return EFI_SUCCESS;+}diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf
new file mode 100644
index 000000000000..91c761366446
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmCon
+++ trolLib/PeiSmmControlLib.inf
@@ -0,0 +1,34 @@
+## @file+# Library description file for the SmmControl PPI+#+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>+# SPDX-License-Identifier: BSD-2-Clause-Patent+#+##++[Defines]+ INF_VERSION = 0x00010017+ BASE_NAME = PeiSmmControlLib+ FILE_GUID = F45D521A-C0DF-4283-A3CA-65AD01B479E7+ VERSION_STRING = 1.0+ MODULE_TYPE = PEIM+ LIBRARY_CLASS = SmmControlLib++[LibraryClasses]+ IoLib+ DebugLib+ MemoryAllocationLib+ PeiServicesLib++[Packages]+ MdePkg/MdePkg.dec+ IntelSiliconPkg/IntelSiliconPkg.dec++[Sources]+ PeiSmmControlLib.c++[Pcd]+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES++[Ppis]+ gEfiPeiMmControlPpiGuid ## PRODUCESdiff --git a/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h b/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h
new file mode 100644
index 000000000000..b532dd13f373
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h
@@ -0,0 +1,26 @@
+/** @file+ This is to publish the SMM Control Ppi instance.++ Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>+ SPDX-License-Identifier: BSD-2-Clause-Patent++**/+#ifndef _SMM_CONTROL_LIB_H_+#define _SMM_CONTROL_LIB_H_++/**+ This function is to install an SMM Control PPI+ - <b>Introduction</b> \n+ An API to install an instance of EFI_PEI_MM_CONTROL_PPI. This PPI provides a standard+ way for other modules to trigger software SMIs.++ @retval EFI_SUCCESS - Ppi successfully started and installed.+ @retval EFI_NOT_FOUND - Ppi can't be found.+ @retval EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to initialize the driver.+**/+EFI_STATUS+EFIAPI+PeiInstallSmmControlPpi (+ VOID+ );+#endifdiff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index deefdc55b5d6..440c7d0255ce 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -35,6 +35,10 @@
# SmmAccessLib|Include/Library/SmmAccessLib.h + ## @libraryclass Provides services to trigger SMI+ #+ SmmControlLib|Include/Library/SmmControlLib.h+ ## @libraryclass Provides services to access config block # ConfigBlockLib|Include/Library/ConfigBlockLib.h--
2.37.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [edk2-devel][edk2-platforms][PATCH v2 4/6] S3FeaturePkg: Implement working S3 resume
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 4/6] S3FeaturePkg: Implement working S3 resume Benjamin Doron
@ 2022-09-08 0:38 ` Isaac Oram
2022-09-11 15:46 ` Benjamin Doron
0 siblings, 1 reply; 17+ messages in thread
From: Isaac Oram @ 2022-09-08 0:38 UTC (permalink / raw)
To: Benjamin Doron, devel@edk2.groups.io, Chaganty, Rangasai V
Cc: Desimone, Nathaniel L, Sinha, Ankit, Gao, Liming
It seems like:
UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
Are not S3 specific and belong with common stage 4 or 5 content. It seems many features could require them. DSC can deal with duplicates, but FDF would fail if there were collisions.
S3Feature.dsc
- Remove commented out code
Regards,
Isaac
-----Original Message-----
From: Benjamin Doron <benjamin.doron00@gmail.com>
Sent: Tuesday, September 6, 2022 10:02 AM
To: devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>
Subject: [edk2-devel][edk2-platforms][PATCH v2 4/6] S3FeaturePkg: Implement working S3 resume
Follow-up commits to MinPlatform (PeiFspWrapperHobProcessLib for
memory) and FSP-related board libraries (policy overrides) required for successful S3 resume.
Factored allocation logic into new module to avoid MinPlatform dependency on S3Feature package.
TODO: Can optimise required size.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../S3FeaturePkg/Include/PostMemory.fdf | 13 ++
.../S3FeaturePkg/Include/PreMemory.fdf | 8 +-
.../S3FeaturePkg/Include/S3Feature.dsc | 38 ++++-
.../S3FeaturePkg/S3Dxe/S3Dxe.c | 155 ++++++++++++++++++
.../S3FeaturePkg/S3Dxe/S3Dxe.inf | 49 ++++++
.../S3FeaturePkg/S3Pei/S3Pei.c | 83 +++++++++-
.../S3FeaturePkg/S3Pei/S3Pei.inf | 8 +-
.../Include/AcpiS3MemoryNvData.h | 22 +++
8 files changed, 365 insertions(+), 11 deletions(-) create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
create mode 100644 Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf
index 9e17f853c630..7f630908fa2c 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf
@@ -2,7 +2,20 @@
# FDF file for post-memory S3 advanced feature modules. # # Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>+# Copyright (c) 2022, Baruch Binyamin Doron.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # ##++## Dependencies+ INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf+ INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf++## Save-state module stack+ INF S3FeaturePkg/S3Dxe/S3Dxe.inf+ INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf+ INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf++## Restore-state module stack+ INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.infdiff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf
index fdd16a4e0356..e130fa5f098d 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf
@@ -2,9 +2,15 @@
# FDF file for pre-memory S3 advanced feature modules. # # Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>+# Copyright (c) 2022, Baruch Binyamin Doron.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # ## -INF S3FeaturePkg/S3Pei/S3Pei.inf+## Dependencies+ INF S3FeaturePkg/S3Pei/S3Pei.inf+ INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf++## Restore-state module stack+ INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.infdiff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc
index cc34e785076a..d8bfc7909413 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc
@@ -7,6 +7,7 @@
# for the build infrastructure. # # Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>+# Copyright (c) 2022, Baruch Binyamin Doron.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent #@@ -25,6 +26,10 @@
!error "DXE_ARCH must be specified to build this feature!" !endif +[PcdsFixedAtBuild]+ # Attempts to improve performance at the cost of more DRAM usage+ gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE+ ################################################################################ # # Library Class section - list of all Library Classes needed by this feature.@@ -32,7 +37,14 @@
################################################################################ [LibraryClasses.common.PEIM]- SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.inf+ #SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf+ SmmControlLib|IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf++[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_SMM_DRIVER]+ #######################################+ # Edk2 Packages+ #######################################+ S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf ################################################################################ #@@ -60,8 +72,26 @@
# S3 Feature Package ##################################### - # Add library instances here that are not included in package components and should be tested- # in the package build.- # Add components here that should be included in the package build. S3FeaturePkg/S3Pei/S3Pei.inf+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf+ UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf++#+# Feature DXE Components+#++# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzilla.tianocore.org/show_bug.cgi?id=2308+# is completed.+[Components.X64]+ #####################################+ # S3 Feature Package+ #####################################++ # Add components here that should be included in the package build.+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf+ MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf+ S3FeaturePkg/S3Dxe/S3Dxe.inf+ MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf+ UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf+ MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.infdiff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
new file mode 100644
index 000000000000..1a7ccb8eedab
--- /dev/null
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
@@ -0,0 +1,155 @@
+/** @file+ Source code file for S3 DXE module++Copyright (c) 2022, Baruch Binyamin Doron.<BR>+SPDX-License-Identifier: BSD-2-Clause-Patent++**/++#include <PiDxe.h>+#include <Library/BaseMemoryLib.h>+#include <Library/DebugLib.h>+#include <Library/PcdLib.h>+#include <Library/UefiLib.h>+#include <Library/UefiBootServicesTableLib.h>+#include <Library/UefiRuntimeServicesTableLib.h>+#include <Guid/AcpiS3Context.h>+#include <Guid/MemoryTypeInformation.h>+#include <AcpiS3MemoryNvData.h>++#define PEI_ADDITIONAL_MEMORY_SIZE (16 * EFI_PAGE_SIZE)++/**+ Get the mem size in memory type information table.++ @return the mem size in memory type information table.+**/+UINT64+EFIAPI+GetMemorySizeInMemoryTypeInformation (+ VOID+ )+{+ EFI_STATUS Status;+ EFI_MEMORY_TYPE_INFORMATION *MemoryData;+ UINT8 Index;+ UINTN TempPageNum;++ Status = EfiGetSystemConfigurationTable (&gEfiMemoryTypeInformationGuid, (VOID **) &MemoryData);++ if (EFI_ERROR (Status) || MemoryData == NULL) {+ return 0;+ }++ TempPageNum = 0;+ for (Index = 0; MemoryData[Index].Type != EfiMaxMemoryType; Index++) {+ //+ // Accumulate default memory size requirements+ //+ TempPageNum += MemoryData[Index].NumberOfPages;+ }++ return TempPageNum * EFI_PAGE_SIZE;+}++/**+ Get the mem size need to be consumed and reserved for PEI phase resume.++ @return the mem size to be reserved for PEI phase resume.+**/+UINT64+EFIAPI+GetPeiMemSize (+ VOID+ )+{+ UINT64 Size;++ Size = GetMemorySizeInMemoryTypeInformation ();++ return PcdGet32 (PcdPeiMinMemSize) + Size + PEI_ADDITIONAL_MEMORY_SIZE;+}++/**+ Allocate EfiACPIMemoryNVS below 4G memory address.++ This function allocates EfiACPIMemoryNVS below 4G memory address.++ @param Size Size of memory to allocate.++ @return Allocated address for output.++**/+VOID *+EFIAPI+AllocateAcpiNvsMemoryBelow4G (+ IN UINTN Size+ )+{+ UINTN Pages;+ EFI_PHYSICAL_ADDRESS Address;+ EFI_STATUS Status;+ VOID *Buffer;++ Pages = EFI_SIZE_TO_PAGES (Size);+ Address = 0xffffffff;++ Status = gBS->AllocatePages (+ AllocateMaxAddress,+ EfiACPIMemoryNVS,+ Pages,+ &Address+ );+ ASSERT_EFI_ERROR (Status);++ Buffer = (VOID *)(UINTN)Address;+ ZeroMem (Buffer, Size);++ return Buffer;+}++/**+ Allocates memory to use on S3 resume.++ @param[in] ImageHandle Not used.+ @param[in] SystemTable General purpose services available to every DXE driver.++ @retval EFI_SUCCESS The function completes successfully+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database+**/+EFI_STATUS+EFIAPI+S3DxeEntryPoint (+ IN EFI_HANDLE ImageHandle,+ IN EFI_SYSTEM_TABLE *SystemTable+ )+{+ UINT64 S3PeiMemSize;+ UINT64 S3PeiMemBase;+ ACPI_S3_MEMORY S3MemoryInfo;+ EFI_STATUS Status;++ DEBUG ((DEBUG_INFO, "%a() Start\n", __FUNCTION__));++ S3PeiMemSize = GetPeiMemSize ();+ S3PeiMemBase = (UINTN) AllocateAcpiNvsMemoryBelow4G (S3PeiMemSize);+ ASSERT (S3PeiMemBase != 0);++ S3MemoryInfo.S3PeiMemBase = S3PeiMemBase;+ S3MemoryInfo.S3PeiMemSize = S3PeiMemSize;++ DEBUG ((DEBUG_INFO, "S3PeiMemBase: 0x%x\n", S3PeiMemBase));+ DEBUG ((DEBUG_INFO, "S3PeiMemSize: 0x%x\n", S3PeiMemSize));++ Status = gRT->SetVariable (+ ACPI_S3_MEMORY_NV_NAME,+ &gEfiAcpiVariableGuid,+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,+ sizeof (S3MemoryInfo),+ &S3MemoryInfo+ );+ ASSERT_EFI_ERROR (Status);++ DEBUG ((DEBUG_INFO, "%a() End\n", __FUNCTION__));+ return EFI_SUCCESS;+}diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
new file mode 100644
index 000000000000..28589c2c869b
--- /dev/null
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
@@ -0,0 +1,49 @@
+### @file+# Component information file for the S3 DXE module.+#+# Copyright (c) 2022, Baruch Binyamin Doron.<BR>+#+# SPDX-License-Identifier: BSD-2-Clause-Patent+#+###++[Defines]+ INF_VERSION = 0x00010017+ BASE_NAME = S3Dxe+ FILE_GUID = 30926F92-CC83-4381-9F70-AC96EDB5BEE0+ VERSION_STRING = 1.0+ MODULE_TYPE = DXE_DRIVER+ ENTRY_POINT = S3DxeEntryPoint++[LibraryClasses]+ UefiDriverEntryPoint+ UefiBootServicesTableLib+ UefiRuntimeServicesTableLib+ BaseMemoryLib+ DebugLib+ PcdLib+ UefiLib++[Packages]+ MdePkg/MdePkg.dec+ MdeModulePkg/MdeModulePkg.dec+ MinPlatformPkg/MinPlatformPkg.dec+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec+ S3FeaturePkg/S3FeaturePkg.dec++[Sources]+ S3Dxe.c++[Pcd]+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize++[FeaturePcd]+ gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable++[Guids]+ gEfiMemoryTypeInformationGuid ## CONSUMES+ gEfiAcpiVariableGuid ## CONSUMES++[Depex]+ gEfiVariableArchProtocolGuid AND+ gEfiVariableWriteArchProtocolGuiddiff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c
index b0aaa04962c8..6acb894b6fc9 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c
@@ -2,12 +2,87 @@
Source code file for S3 PEI module Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2022, Baruch Binyamin Doron.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ +#include <PiPei.h>+#include <Library/DebugLib.h>+#include <Library/PciLib.h> #include <Library/PeiServicesLib.h> #include <Library/SmmAccessLib.h>+#include <Library/SmmControlLib.h>++// TODO: Finalise implementation factoring+#define R_SA_PAM0 (0x80)+#define R_SA_PAM5 (0x85)+#define R_SA_PAM6 (0x86)++/**+ This function is called after FspSiliconInitDone installed PPI.+ For FSP API mode, this is when FSP-M HOBs are installed into EDK2.++ @param[in] PeiServices Pointer to PEI Services Table.+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that+ caused this function to execute.+ @param[in] Ppi Pointer to the PPI data associated with this function.++ @retval EFI_STATUS Always return EFI_SUCCESS+**/+EFI_STATUS+EFIAPI+FspSiliconInitDoneNotify (+ IN EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,+ IN VOID *Ppi+ )+{+ EFI_STATUS Status;+ EFI_BOOT_MODE BootMode;+ UINT64 MchBaseAddress;++ Status = PeiServicesGetBootMode (&BootMode);+ ASSERT_EFI_ERROR (Status);++ // Enable PAM regions for AP wakeup vector (resume)+ // - CPU is finalised by PiSmmCpuDxeSmm, not FSP. So, it's safe here?+ // TODO/TEST: coreboot does this unconditionally, vendor FWs may not (test resume). Should we?+ // - It is certainly interesting that only PAM0, PAM5 and PAM6 are defined for KabylakeSiliconPkg.+ // - Also note that 0xA0000-0xFFFFF is marked "reserved" in FSP HOB - this does not mean+ // that the memory is unusable, perhaps this is precisely because it will contain+ // the AP wakeup vector.+ if (BootMode == BOOT_ON_S3_RESUME) {+ MchBaseAddress = PCI_LIB_ADDRESS (0, 0, 0, 0);+ PciWrite8 (MchBaseAddress + R_SA_PAM0, 0x30);+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 1), 0x33);+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 2), 0x33);+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 3), 0x33);+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 4), 0x33);+ PciWrite8 (MchBaseAddress + R_SA_PAM5, 0x33);+ PciWrite8 (MchBaseAddress + R_SA_PAM6, 0x33);+ }++ //+ // Install EFI_PEI_MM_ACCESS_PPI for S3 resume case+ //+ Status = PeiInstallSmmAccessPpi ();+ ASSERT_EFI_ERROR (Status);++ //+ // Install EFI_PEI_MM_CONTROL_PPI for S3 resume case+ //+ Status = PeiInstallSmmControlPpi ();+ ASSERT_EFI_ERROR (Status);++ return Status;+}++EFI_PEI_NOTIFY_DESCRIPTOR mFspSiliconInitDoneNotifyDesc = {+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),+ &gFspSiliconInitDonePpiGuid,+ FspSiliconInitDoneNotify+}; /** S3 PEI module entry point@@ -25,12 +100,10 @@ S3PeiEntryPoint (
IN CONST EFI_PEI_SERVICES **PeiServices ) {- EFI_STATUS Status;+ EFI_STATUS Status; - //- // Install EFI_PEI_MM_ACCESS_PPI for S3 resume case- //- Status = PeiInstallSmmAccessPpi ();+ Status = PeiServicesNotifyPpi (&mFspSiliconInitDoneNotifyDesc);+ ASSERT_EFI_ERROR (Status); return Status; }diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf
index e485eac9521f..173919bb881e 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf
@@ -18,10 +18,13 @@
[LibraryClasses] PeimEntryPoint PeiServicesLib+ DebugLib SmmAccessLib+ SmmControlLib [Packages] MdePkg/MdePkg.dec+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec IntelSiliconPkg/IntelSiliconPkg.dec S3FeaturePkg/S3FeaturePkg.dec @@ -31,5 +34,8 @@
[FeaturePcd] gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable +[Ppis]+ gFspSiliconInitDonePpiGuid+ [Depex]- gEfiPeiMemoryDiscoveredPpiGuid+ TRUEdiff --git a/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h b/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
new file mode 100644
index 000000000000..0d75af8e9a03
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
@@ -0,0 +1,22 @@
+/** @file
+ Header file for NV data structure definition.
+
+Copyright (c) 2021, Baruch Binyamin Doron
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __ACPI_S3_MEMORY_NV_DATA_H__
+#define __ACPI_S3_MEMORY_NV_DATA_H__
+
+//
+// NV data structure
+//
+typedef struct {
+ UINT64 S3PeiMemBase;
+ UINT64 S3PeiMemSize;
+} ACPI_S3_MEMORY;
+
+#define ACPI_S3_MEMORY_NV_NAME L"S3MemoryInfo"
+
+#endif
--
2.37.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [edk2-devel][edk2-platforms][PATCH v2 5/6] MinPlatformPkg: Implement working S3 resume
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 5/6] MinPlatformPkg: " Benjamin Doron
@ 2022-09-08 2:46 ` Isaac Oram
0 siblings, 0 replies; 17+ messages in thread
From: Isaac Oram @ 2022-09-08 2:46 UTC (permalink / raw)
To: Benjamin Doron, devel@edk2.groups.io
Cc: Chiu, Chasel, Desimone, Nathaniel L, Sinha, Ankit, Gao, Liming,
Dong, Eric
DSC and FDF should wrap performance PEIM with !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE to be consistent with the MinPlatformPkg DSC implementations. Or you could take a look at what we did in WhitleyOpenBoardPkg/Include/Dsc/ EnablePerformanceMonitoringInfrastructure.dsc. But I don't think that this is quite ready for promotion to wider use. It might fit better as an advanced feature, but I haven't had time to play with it.
That plus adding the UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf to CorePostMemoryInclude.fdf
And
UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
To CoreOsBootInclude.fdf.
I think that those are the best places. They don't need any conditional logic because they have dependencies that should enable the desired execution timing.
Regards,
Isaac
-----Original Message-----
From: Benjamin Doron <benjamin.doron00@gmail.com>
Sent: Tuesday, September 6, 2022 10:02 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>; Dong, Eric <eric.dong@intel.com>
Subject: [edk2-devel][edk2-platforms][PATCH v2 5/6] MinPlatformPkg: Implement working S3 resume
Consume S3 resume memory allocation on resume flow.
Also, include complementary FirmwarePerformanceDataTablePei module in MinPlatform FV for S3 resume performance measurement.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../FspWrapperHobProcessLib.c | 69 ++++++++++++++++++-
.../PeiFspWrapperHobProcessLib.inf | 2 +
.../Include/Dsc/CorePeiInclude.dsc | 2 +
.../Include/Fdf/CorePostMemoryInclude.fdf | 2 +
4 files changed, 74 insertions(+), 1 deletion(-)
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c
index 7ee4d3a31c49..9bd6fe6290c5 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobP
+++ rocessLib/FspWrapperHobProcessLib.c
@@ -16,14 +16,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/HobLib.h> #include <Library/PcdLib.h> #include <Library/FspWrapperPlatformLib.h>+#include <Guid/AcpiS3Context.h> #include <Guid/GuidHobFspEas.h> #include <Guid/MemoryTypeInformation.h> #include <Guid/GraphicsInfoHob.h> #include <Guid/PcdDataBaseHobGuid.h> #include <Guid/ZeroGuid.h> #include <Ppi/Capsule.h>+#include <Ppi/ReadOnlyVariable2.h> #include <FspEas.h>+#include <AcpiS3MemoryNvData.h> // // Additional pages are used by DXE memory manager.@@ -130,6 +133,55 @@ GetPeiMemSize (
return MinSize + Size + PEI_ADDITIONAL_MEMORY_SIZE; } +/**+ Get S3 PEI memory information.++ @note At this point, memory is ready, and PeiServices are available to use.+ Platform can get some data from SMRAM directly.++ @param[out] S3PeiMemSize PEI memory size to be installed in S3 phase.+ @param[out] S3PeiMemBase PEI memory base to be installed in S3 phase.++ @return If S3 PEI memory information is got successfully.+**/+EFI_STATUS+EFIAPI+GetS3MemoryInfo (+ OUT UINT64 *S3PeiMemSize,+ OUT EFI_PHYSICAL_ADDRESS *S3PeiMemBase+ )+{+ EFI_STATUS Status;+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi;+ UINTN DataSize;+ ACPI_S3_MEMORY S3MemoryInfo;++ *S3PeiMemBase = 0;+ *S3PeiMemSize = 0;++ Status = PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NULL, (VOID **) &VariablePpi);+ ASSERT_EFI_ERROR (Status);++ DataSize = sizeof (S3MemoryInfo);+ Status = VariablePpi->GetVariable (+ VariablePpi,+ ACPI_S3_MEMORY_NV_NAME,+ &gEfiAcpiVariableGuid,+ NULL,+ &DataSize,+ &S3MemoryInfo+ );+ ASSERT_EFI_ERROR (Status);++ if (EFI_ERROR (Status)) {+ return Status;+ }++ *S3PeiMemBase = S3MemoryInfo.S3PeiMemBase;+ *S3PeiMemSize = S3MemoryInfo.S3PeiMemSize;+ return EFI_SUCCESS;+}+ /** Post FSP-M HOB process for Memory Resource Descriptor. @@ -280,7 +332,7 @@ PostFspmHobProcess (
0x1000 ); -+ if (BootMode != BOOT_ON_S3_RESUME) { // // Capsule mode //@@ -337,7 +389,22 @@ PostFspmHobProcess (
if (Capsule != NULL) { Status = Capsule->CreateState ((EFI_PEI_SERVICES **)PeiServices, CapsuleBuffer, CapsuleBufferLength); }+ } else {+ Status = GetS3MemoryInfo (&PeiMemSize, &PeiMemBase);+ ASSERT_EFI_ERROR (Status); + DEBUG ((DEBUG_INFO, "S3 resume PeiMemBase : 0x%08x\n", PeiMemBase));+ DEBUG ((DEBUG_INFO, "S3 resume PeiMemSize : 0x%08x\n", PeiMemSize));++ //+ // Install efi memory+ //+ Status = PeiServicesInstallPeiMemory (+ PeiMemBase,+ PeiMemSize+ );+ ASSERT_EFI_ERROR (Status);+ } // // Create a memory allocation HOB at fixed location for MP Services PPI AP wait loop.diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
index b846e7af1d2d..e2aac36bf018 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobP
+++ rocessLib/PeiFspWrapperHobProcessLib.inf
@@ -75,7 +75,9 @@
gZeroGuid gEfiGraphicsInfoHobGuid gEfiGraphicsDeviceInfoHobGuid+ gEfiAcpiVariableGuid [Ppis] gEfiPeiCapsulePpiGuid ## CONSUMES+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES gEdkiiSiliconInitializedPpiGuid ## PRODUCESdiff --git a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc b/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
index 08e50cac075f..f271fb26b189 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
+++ b/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
@@ -41,3 +41,5 @@
NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf } !endif++ MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.infdiff --git a/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf b/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf
index 3c2716d6728a..160f02650a8c 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf
+++ b/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fd
+++ f
@@ -6,3 +6,5 @@
# SPDX-License-Identifier: BSD-2-Clause-Patent # ##++ INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf--
2.37.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [edk2-devel][edk2-platforms][PATCH v2 1/6] {Platform,Silicon}/Intel: Move PcdAcpiBaseAddress definition
2022-09-07 22:57 ` Chaganty, Rangasai V
@ 2022-09-09 21:11 ` Isaac Oram
0 siblings, 0 replies; 17+ messages in thread
From: Isaac Oram @ 2022-09-09 21:11 UTC (permalink / raw)
To: Chaganty, Rangasai V, Benjamin Doron, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Sinha, Ankit, Ni, Ray, Chiu, Chasel,
Luo, Heng
Pushed as 7f63ab7da9..b74194d8b8
-----Original Message-----
From: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>
Sent: Wednesday, September 7, 2022 3:57 PM
To: Benjamin Doron <benjamin.doron00@gmail.com>; devel@edk2.groups.io
Cc: Oram, Isaac W <isaac.w.oram@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Ni, Ray <ray.ni@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Luo, Heng <heng.luo@intel.com>
Subject: RE: [edk2-devel][edk2-platforms][PATCH v2 1/6] {Platform,Silicon}/Intel: Move PcdAcpiBaseAddress definition
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Benjamin Doron <benjamin.doron00@gmail.com>
Sent: Tuesday, September 06, 2022 10:02 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Ni, Ray <ray.ni@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Luo, Heng <heng.luo@intel.com>
Subject: [edk2-devel][edk2-platforms][PATCH v2 1/6] {Platform,Silicon}/Intel: Move PcdAcpiBaseAddress definition
All these platforms have an ABase, so move the definition to enable common silicon code in IntelSiliconPkg. Otherwise, library shims would be required, because PCDs are GUID-ed and package DEC specific.
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Heng Luo <heng.luo@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc | 1 +
.../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
.../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 1 +
.../KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
.../Library/BasePlatformHookLib/BasePlatformHookLib.inf | 2 +-
.../KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc | 1 +
.../Library/BasePlatformHookLib/BasePlatformHookLib.inf | 2 +-
.../KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 1 +
.../TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc | 1 +
.../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +-
.../WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc | 1 +
.../WhiskeylakeURvp/OpenBoardPkgPcd.dsc | 1 +
Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc | 1 +
.../Library/PeiSiliconInitLib/PeiSiliconInitLib.inf | 5 +++--
.../Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf | 3 ++-
.../PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf | 2 +-
Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec | 1 -
Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 4 ++++
Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc | 1 +
.../Library/PeiSiliconInitLib/PeiSiliconInitLib.inf | 2 +-
.../Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf | 3 ++-
.../Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf | 2 +-
.../KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf | 2 +-
Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec | 1 -
.../IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf | 3 ++-
.../PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf | 3 ++-
Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec | 1 -
Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc | 1 +
28 files changed, 34 insertions(+), 18 deletions(-)
diff --git a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
index 79924f1fda7f..81dc0747fab8 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/CometlakeOpenBoardPkg/CometlakeURvp/OpenBoardPkgPcd
+++ .dsc
@@ -65,6 +65,7 @@
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 # # PCIe Reserved Memory Space Range #diff --git a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
index e3fdd3981653..c4dd863c3ee8 100644
--- a/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+++ b/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtS
+++ mm.inf
@@ -49,7 +49,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES [FixedPcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES [Sources] TbtSmiHandler.hdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
index a4ea524e26bc..3ed7aa0a2b10 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg
+++ Pcd.dsc
@@ -241,6 +241,7 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 !endif gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
index e6c185a4bd91..13116488eaa0 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSm
+++ m.inf
@@ -46,7 +46,7 @@
gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES [FixedPcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES [Sources] TbtSmiHandler.hdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
index 1de10aa0080f..5f65f02a9f64 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatfor
+++ mHookLib/BasePlatformHookLib.inf
@@ -35,7 +35,7 @@
KabylakeSiliconPkg/SiPkg.dec [Pcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSUMESdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
index c6b9df842936..ec23c691b2fe 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
@@ -194,6 +194,7 @@
gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 !endif gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 !endifdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
index 7a5e290657f2..8bdf13b1ce11 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatf
+++ ormHookLib/BasePlatformHookLib.inf
@@ -35,7 +35,7 @@
KabylakeSiliconPkg/SiPkg.dec [Pcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSUMESdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
index 2f7765e58a69..cfd032814850 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d
+++ sc
@@ -194,6 +194,7 @@
gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 !endif gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 !endifdiff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
index 2fd6d0c50e05..2fb2e1ce58f4 100644
--- a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd
+++ .dsc
@@ -117,6 +117,7 @@
#!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 #!endif+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000 #diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
index bfe299d73374..83ebc790aeb4 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/Tb
+++ tSmm.inf
@@ -49,7 +49,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES [FixedPcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES [Sources] TbtSmiHandler.hdiff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
index a7e9a41e2c34..dbe068d0c123 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/OpenBoardPkgPcd.ds
+++ c
@@ -65,6 +65,7 @@
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 [PcdsFeatureFlag.common] ######################################diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
index daf5411ac358..451926d67190 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPk
+++ gPcd.dsc
@@ -65,6 +65,7 @@
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800 [PcdsFeatureFlag.common] ######################################diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
index c5f10492edc8..e62e37cda036 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc
@@ -42,6 +42,7 @@ gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE
[PcdsFixedAtBuild.common] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xE0000000 gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength |0x10000000+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress |0x1800 gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin |10 gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax |18diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
index 1534a24dd240..432d4c0c2656 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiliconInitLib/PeiSi
+++ liconInitLib.inf
@@ -32,6 +32,7 @@
[Packages] MdePkg/MdePkg.dec+ IntelSiliconPkg/IntelSiliconPkg.dec CoffeelakeSiliconPkg/SiPkg.dec [Sources]@@ -42,5 +43,5 @@
gTcoWdtHobGuid ## CONSUMES [Pcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES- gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMESdiff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
index 78e212eeb0fd..61778ed5a066 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/Pei
+++ DxeSmmPmcLib.inf
@@ -32,11 +32,12 @@ BaseMemoryLib
[Packages] MdePkg/MdePkg.dec+IntelSiliconPkg/IntelSiliconPkg.dec CoffeelakeSiliconPkg/SiPkg.dec [Pcd]-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress [Sources]diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf
index 573acfc25e31..1f84337afafb 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPm
+++ cPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf
@@ -39,7 +39,7 @@ CoffeelakeSiliconPkg/SiPkg.dec
IntelSiliconPkg/IntelSiliconPkg.dec [Pcd]-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress [Sources]diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
index efc2d8788168..ca3e83bd61da 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec
@@ -516,7 +516,6 @@ gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFED10000|UINT64|0x00010030
## This value is used to set the base address of PCH devices gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031 gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010034-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035 ## 32KB window gSiPkgTokenSpaceGuid.PcdMchMmioSize|0x8000|UINT32|0x50000000diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index c36d130a0197..deefdc55b5d6 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -147,6 +147,10 @@
# @Prompt Error code for VTd error. gIntelSiliconPkgTokenSpaceGuid.PcdErrorCodeVTdError|0x02008000|UINT32|0x00000005 + ## ABase I/O address.<BR><BR>+ # @Prompt ABase I/O address.+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x0|UINT16|0x0000000D+ [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] ## This is the GUID of the FFS which contains the Graphics Video BIOS Table (VBT) # The VBT content is stored as a RAW section which is consumed by GOP PEI/UEFI driver.diff --git a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc b/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc
index d980a2c5369a..ff7728279a08 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc
+++ b/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc
@@ -48,6 +48,7 @@ gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE
[PcdsFixedAtBuild.common] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xE0000000 gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength |0x10000000+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress |0x1800 # # This DSC mainly for GreenH Silicon code build so PciExpressBaseAddress can be FixedAtBuild #diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
index 3b94a02e6bf4..32205bb04f64 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconInitLib/PeiSili
+++ conInitLib.inf
@@ -46,7 +46,7 @@
SiliconInitPreMem.c [Pcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMES diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf
index 1e6103f4ca38..5ae3b4d6256a 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/Pe
+++ iDxeSmmPchPmcLib.inf
@@ -30,11 +30,12 @@ PchCycleDecodingLib
[Packages] MdePkg/MdePkg.dec+IntelSiliconPkg/IntelSiliconPkg.dec KabylakeSiliconPkg/SiPkg.dec [Pcd]-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress [Sources]diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf
index a5ccf4698b7d..41eaffe52e66 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPc
+++ hPolicyLib.inf
@@ -35,7 +35,7 @@ KabylakeSiliconPkg/SiPkg.dec IntelSiliconPkg/IntelSiliconPkg.dec [Pcd]-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable gSiPkgTokenSpaceGuid.PcdSerialIoUartNumberdiff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf
index ba57c44e1e12..f912d6e76d4a 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.i
+++ nf
@@ -39,7 +39,7 @@
PeiSpiLib.c [Pcd]- gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES [Ppis] gPchSpi2PpiGuid ## PRODUCESdiff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
index d9ae9f6dfd91..6c9af567f5ee 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
+++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec
@@ -497,7 +497,6 @@ gSiPkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|40|UINT8|0x0001002f
gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFED10000|UINT64|0x00010030 gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031 gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010034-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035 ## 32KB window gSiPkgTokenSpaceGuid.PcdMchMmioSize|0x8000|UINT32|0x50000000diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
index eba6db767c5c..c52a157c7d39 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
+++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmc
+++ Lib/PeiDxeSmmPmcLib.inf
@@ -31,11 +31,12 @@ BaseMemoryLib
[Packages] MdePkg/MdePkg.dec+IntelSiliconPkg/IntelSiliconPkg.dec TigerlakeSiliconPkg/SiPkg.dec [Pcd]-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress gSiPkgTokenSpaceGuid.PcdTcoBaseAddress [Sources]diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf
index 2bd57b79f035..32a4e9a07a76 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf
+++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDx
+++ eSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf
@@ -27,11 +27,12 @@ PmcLib
[Packages] MdePkg/MdePkg.dec+IntelSiliconPkg/IntelSiliconPkg.dec TigerlakeSiliconPkg/SiPkg.dec [Pcd]-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress [FixedPcd] diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec b/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec
index 7cdbb3748155..991ca1555bf7 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec
+++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec
@@ -976,7 +976,6 @@ gMeConfigSpaceGuid.PcdHeciTimeoutsEnabled|TRUE|BOOLEAN|0x50000002
## This value is used to set the base address of PCH devices gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031 gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010033-gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035 ## Stack size in the temporary RAM.diff --git a/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc b/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc
index 36df41f09fb4..f11305d266cb 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc
+++ b/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc
@@ -60,6 +60,7 @@ gSiPkgTokenSpaceGuid.PcdSpaEnable |FALSE
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xC0000000 gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress |gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength |0x10000000+gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress |0x1800 [PcdsDynamicDefault.common] gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength |0x10000000--
2.37.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [edk2-devel][edk2-platforms][PATCH v2 2/6] IntelSiliconPkg/Feature/SmmAccess: Implement PPI with chipset support
[not found] ` <1712B8F6079EA3A9.20240@groups.io>
@ 2022-09-09 21:13 ` Isaac Oram
0 siblings, 0 replies; 17+ messages in thread
From: Isaac Oram @ 2022-09-09 21:13 UTC (permalink / raw)
To: devel@edk2.groups.io, Oram, Isaac W, Benjamin Doron
Cc: Desimone, Nathaniel L, Sinha, Ankit, Ni, Ray,
Chaganty, Rangasai V
Pushed as b74194d8b8..b013adb40e
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Isaac Oram
Sent: Wednesday, September 7, 2022 4:49 PM
To: Benjamin Doron <benjamin.doron00@gmail.com>; devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>
Subject: Re: [edk2-devel][edk2-platforms][PATCH v2 2/6] IntelSiliconPkg/Feature/SmmAccess: Implement PPI with chipset support
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>
-----Original Message-----
From: Benjamin Doron <benjamin.doron00@gmail.com>
Sent: Tuesday, September 6, 2022 10:02 AM
To: devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>
Subject: [edk2-devel][edk2-platforms][PATCH v2 2/6] IntelSiliconPkg/Feature/SmmAccess: Implement PPI with chipset support
SMRAM must be opened to retrieve the lockbox for S3, and SMM communication depends on this PPI. For security purposes, SMRAM lock must be performed before EndOfPei (although FSP notify performs lockdown too).
It seems to me that this library is generic and applicable to all Intel platforms in the tree using the MCH SMRAMC register.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../PeiSmmAccessLibSmramc/PeiSmmAccessLib.c | 430 ++++++++++++++++++
.../PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf | 36 ++
2 files changed, 466 insertions(+)
create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.c
create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.c b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.c
new file mode 100644
index 000000000000..5b472bf86abf
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAcce
+++ ssLibSmramc/PeiSmmAccessLib.c
@@ -0,0 +1,430 @@
+/** @file+ This is to publish the SMM Access Ppi instance.++ Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>+ SPDX-License-Identifier: BSD-2-Clause-Patent++**/+#include <Library/BaseMemoryLib.h>+#include <Library/DebugLib.h>+#include <Library/MemoryAllocationLib.h>+#include <Library/PciSegmentLib.h>+#include <Library/PeiServicesLib.h>+#include <Library/HobLib.h>+#include <Uefi/UefiBaseType.h>+#include <Guid/SmramMemoryReserve.h>++#include <Ppi/MmAccess.h>+#include <IndustryStandard/Pci22.h>++#define SMM_ACCESS_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('4', '5', 's', 'a')++///+/// Private data+///+typedef struct {+ UINTN Signature;+ EFI_HANDLE Handle;+ EFI_PEI_MM_ACCESS_PPI SmmAccess;+ //+ // Local Data for SMM Access interface goes here+ //+ UINTN NumberRegions;+ EFI_SMRAM_DESCRIPTOR *SmramDesc;+} SMM_ACCESS_PRIVATE_DATA;++#define SMM_ACCESS_PRIVATE_DATA_FROM_THIS(a) \+ CR (a, \+ SMM_ACCESS_PRIVATE_DATA, \+ SmmAccess, \+ SMM_ACCESS_PRIVATE_DATA_SIGNATURE \+ )++//+// Common registers:+//+// DEVICE 0 (Memory Controller Hub)+//+#define SA_MC_BUS 0x00+#define SA_MC_DEV 0x00+#define SA_MC_FUN 0x00+///+/// Description:+/// The SMRAMC register controls how accesses to Compatible SMRAM spaces are treated. The Open, Close and Lock bits function only when G_SMRAME bit is set to 1. Also, the Open bit must be reset before the Lock bit is set.+///+#define R_SA_SMRAMC (0x88)+#define B_SA_SMRAMC_D_LCK_MASK (0x10)+#define B_SA_SMRAMC_D_CLS_MASK (0x20)+#define B_SA_SMRAMC_D_OPEN_MASK (0x40)++/**+ This routine accepts a request to "open" a region of SMRAM. The+ region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.+ The use of "open" means that the memory is visible from all PEIM+ and SMM agents.++ @param[in] PeiServices - General purpose services available to every PEIM.+ @param[in] This - Pointer to the SMM Access Interface.+ @param[in] DescriptorIndex - Region of SMRAM to Open.++ @retval EFI_SUCCESS - The region was successfully opened.+ @retval EFI_DEVICE_ERROR - The region could not be opened because locked by+ chipset.+ @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.+**/+EFI_STATUS+EFIAPI+Open (+ IN EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_ACCESS_PPI *This,+ IN UINTN DescriptorIndex+ )+{+ SMM_ACCESS_PRIVATE_DATA *SmmAccess;+ UINT8 Index;+ UINT64 Address;+ UINT8 SmramControl;++ SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);+ if (DescriptorIndex >= SmmAccess->NumberRegions) {+ DEBUG ((DEBUG_WARN, "SMRAM region out of range\n"));++ return EFI_INVALID_PARAMETER;+ } else if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_LOCKED) {+ //+ // Cannot open a "locked" region+ //+ DEBUG ((DEBUG_WARN, "Cannot open a locked SMRAM region\n"));++ return EFI_DEVICE_ERROR;+ }++ ///+ /// BEGIN CHIPSET CODE+ ///+ ///+ /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit)+ ///+ Address = PCI_SEGMENT_LIB_ADDRESS (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC);+ SmramControl = PciSegmentRead8 (Address);+ ///+ /// Is SMRAM locked?+ ///+ if ((SmramControl & B_SA_SMRAMC_D_LCK_MASK) != 0) {+ ///+ /// Cannot Open a locked region+ ///+ for (Index = 0; Index < SmmAccess->NumberRegions; Index++) {+ SmmAccess->SmramDesc[Index].RegionState |= EFI_SMRAM_LOCKED;+ }+ DEBUG ((DEBUG_WARN, "Cannot open a locked SMRAM region\n"));+ return EFI_DEVICE_ERROR;+ }+ ///+ /// Open SMRAM region+ ///+ SmramControl |= B_SA_SMRAMC_D_OPEN_MASK;+ SmramControl &= ~(B_SA_SMRAMC_D_CLS_MASK);++ PciSegmentWrite8 (Address, SmramControl);+ ///+ /// END CHIPSET CODE+ ///++ SmmAccess->SmramDesc[DescriptorIndex].RegionState &= (UINT64) ~(EFI_SMRAM_CLOSED | EFI_ALLOCATED);+ SmmAccess->SmramDesc[DescriptorIndex].RegionState |= (UINT64) EFI_SMRAM_OPEN;+ SmmAccess->SmmAccess.OpenState = TRUE;+ return EFI_SUCCESS;+}++/**+ This routine accepts a request to "close" a region of SMRAM. This is valid for+ compatible SMRAM region.++ @param[in] PeiServices - General purpose services available to every PEIM.+ @param[in] This - Pointer to the SMM Access Interface.+ @param[in] DescriptorIndex - Region of SMRAM to Close.++ @retval EFI_SUCCESS - The region was successfully closed.+ @retval EFI_DEVICE_ERROR - The region could not be closed because locked by+ chipset.+ @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.+**/+EFI_STATUS+EFIAPI+Close (+ IN EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_ACCESS_PPI *This,+ IN UINTN DescriptorIndex+ )+{+ SMM_ACCESS_PRIVATE_DATA *SmmAccess;+ BOOLEAN OpenState;+ UINT8 Index;+ UINT64 Address;+ UINT8 SmramControl;++ SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);+ if (DescriptorIndex >= SmmAccess->NumberRegions) {+ DEBUG ((DEBUG_WARN, "SMRAM region out of range\n"));++ return EFI_INVALID_PARAMETER;+ } else if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_LOCKED) {+ //+ // Cannot close a "locked" region+ //+ DEBUG ((DEBUG_WARN, "Cannot close a locked SMRAM region\n"));++ return EFI_DEVICE_ERROR;+ }++ if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_CLOSED) {+ return EFI_DEVICE_ERROR;+ }++ ///+ /// BEGIN CHIPSET CODE+ ///+ ///+ /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit)+ ///+ Address = PCI_SEGMENT_LIB_ADDRESS (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC);+ SmramControl = PciSegmentRead8 (Address);+ ///+ /// Is SMRAM locked?+ ///+ if ((SmramControl & B_SA_SMRAMC_D_LCK_MASK) != 0) {+ ///+ /// Cannot Close a locked region+ ///+ for (Index = 0; Index < SmmAccess->NumberRegions; Index++) {+ SmmAccess->SmramDesc[Index].RegionState |= EFI_SMRAM_LOCKED;+ }+ DEBUG ((DEBUG_WARN, "Cannot close a locked SMRAM region\n"));+ return EFI_DEVICE_ERROR;+ }+ ///+ /// Close SMRAM region+ ///+ SmramControl &= ~(B_SA_SMRAMC_D_OPEN_MASK);++ PciSegmentWrite8 (Address, SmramControl);+ ///+ /// END CHIPSET CODE+ ///++ SmmAccess->SmramDesc[DescriptorIndex].RegionState &= (UINT64) ~EFI_SMRAM_OPEN;+ SmmAccess->SmramDesc[DescriptorIndex].RegionState |= (UINT64) (EFI_SMRAM_CLOSED | EFI_ALLOCATED);++ //+ // Find out if any regions are still open+ //+ OpenState = FALSE;+ for (Index = 0; Index < SmmAccess->NumberRegions; Index++) {+ if ((SmmAccess->SmramDesc[Index].RegionState & EFI_SMRAM_OPEN) == EFI_SMRAM_OPEN) {+ OpenState = TRUE;+ }+ }++ SmmAccess->SmmAccess.OpenState = OpenState;+ return EFI_SUCCESS;+}++/**+ This routine accepts a request to "lock" SMRAM. The+ region could be legacy AB or TSEG near top of physical memory.+ The use of "lock" means that the memory can no longer be opened+ to PEIM.++ @param[in] PeiServices - General purpose services available to every PEIM.+ @param[in] This - Pointer to the SMM Access Interface.+ @param[in] DescriptorIndex - Region of SMRAM to Lock.++ @retval EFI_SUCCESS - The region was successfully locked.+ @retval EFI_DEVICE_ERROR - The region could not be locked because at least+ one range is still open.+ @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds.+**/+EFI_STATUS+EFIAPI+Lock (+ IN EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_ACCESS_PPI *This,+ IN UINTN DescriptorIndex+ )+{+ SMM_ACCESS_PRIVATE_DATA *SmmAccess;+ UINT64 Address;+ UINT8 SmramControl;++ SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);+ if (DescriptorIndex >= SmmAccess->NumberRegions) {+ DEBUG ((DEBUG_WARN, "SMRAM region out of range\n"));++ return EFI_INVALID_PARAMETER;+ } else if (SmmAccess->SmmAccess.OpenState) {+ DEBUG ((DEBUG_WARN, "Cannot lock SMRAM when SMRAM regions are still open\n"));++ return EFI_DEVICE_ERROR;+ }++ SmmAccess->SmramDesc[DescriptorIndex].RegionState |= (UINT64) EFI_SMRAM_LOCKED;+ SmmAccess->SmmAccess.LockState = TRUE;++ ///+ /// BEGIN CHIPSET CODE+ ///+ ///+ /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit)+ ///+ Address = PCI_SEGMENT_LIB_ADDRESS (0, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAMC);+ SmramControl = PciSegmentRead8 (Address);++ ///+ /// Lock the SMRAM+ ///+ SmramControl |= B_SA_SMRAMC_D_LCK_MASK;++ PciSegmentWrite8 (Address, SmramControl);+ ///+ /// END CHIPSET CODE+ ///++ return EFI_SUCCESS;+}++/**+ This routine services a user request to discover the SMRAM+ capabilities of this platform. This will report the possible+ ranges that are possible for SMRAM access, based upon the+ memory controller capabilities.++ @param[in] PeiServices - General purpose services available to every PEIM.+ @param[in] This - Pointer to the SMRAM Access Interface.+ @param[in, out] SmramMapSize - Pointer to the variable containing size of the+ buffer to contain the description information.+ @param[in, out] SmramMap - Buffer containing the data describing the Smram+ region descriptors.++ @retval EFI_BUFFER_TOO_SMALL - The user did not provide a sufficient buffer.+ @retval EFI_SUCCESS - The user provided a sufficiently-sized buffer.+**/+EFI_STATUS+EFIAPI+GetCapabilities (+ IN EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_ACCESS_PPI *This,+ IN OUT UINTN *SmramMapSize,+ IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap+ )+{+ EFI_STATUS Status;+ SMM_ACCESS_PRIVATE_DATA *SmmAccess;+ UINTN NecessaryBufferSize;++ SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);+ NecessaryBufferSize = SmmAccess->NumberRegions * sizeof (EFI_SMRAM_DESCRIPTOR);+ if (*SmramMapSize < NecessaryBufferSize) {+ DEBUG ((DEBUG_WARN, "SMRAM Map Buffer too small\n"));++ Status = EFI_BUFFER_TOO_SMALL;+ } else {+ CopyMem (SmramMap, SmmAccess->SmramDesc, NecessaryBufferSize);+ Status = EFI_SUCCESS;+ }++ *SmramMapSize = NecessaryBufferSize;+ return Status;+}++/**+ This function is to install an SMM Access PPI+ - <b>Introduction</b> \n+ An API to install an instance of EFI_PEI_MM_ACCESS_PPI. This PPI is commonly used to control SMM mode memory access for S3 resume.++ @retval EFI_SUCCESS - Ppi successfully started and installed.+ @retval EFI_NOT_FOUND - Ppi can't be found.+ @retval EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to initialize the driver.+**/+EFI_STATUS+EFIAPI+PeiInstallSmmAccessPpi (+ VOID+ )+{+ EFI_STATUS Status;+ UINTN Index;+ EFI_PEI_PPI_DESCRIPTOR *PpiList;+ EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *DescriptorBlock;+ SMM_ACCESS_PRIVATE_DATA *SmmAccessPrivate;+ VOID *HobList;++ //+ // Initialize private data+ //+ SmmAccessPrivate = AllocateZeroPool (sizeof (*SmmAccessPrivate));+ ASSERT (SmmAccessPrivate != NULL);+ if (SmmAccessPrivate == NULL) {+ return EFI_OUT_OF_RESOURCES;+ }+ PpiList = AllocateZeroPool (sizeof (*PpiList));+ ASSERT (PpiList != NULL);+ if (PpiList == NULL) {+ return EFI_OUT_OF_RESOURCES;+ }++ SmmAccessPrivate->Signature = SMM_ACCESS_PRIVATE_DATA_SIGNATURE;+ SmmAccessPrivate->Handle = NULL;++ //+ // Get Hob list+ //+ HobList = GetFirstGuidHob (&gEfiSmmSmramMemoryGuid);+ if (HobList == NULL) {+ DEBUG ((DEBUG_WARN, "SmramMemoryReserve HOB not found\n"));+ return EFI_NOT_FOUND;+ }++ DescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) ((UINT8 *) HobList + sizeof (EFI_HOB_GUID_TYPE));++ //+ // Alloc space for SmmAccessPrivate->SmramDesc+ //+ SmmAccessPrivate->SmramDesc = AllocateZeroPool ((DescriptorBlock->NumberOfSmmReservedRegions) * sizeof (EFI_SMRAM_DESCRIPTOR));+ if (SmmAccessPrivate->SmramDesc == NULL) {+ DEBUG ((DEBUG_WARN, "Alloc SmmAccessPrivate->SmramDesc fail.\n"));+ return EFI_OUT_OF_RESOURCES;+ }++ DEBUG ((DEBUG_INFO, "Alloc SmmAccessPrivate->SmramDesc success.\n"));++ //+ // use the hob to publish SMRAM capabilities+ //+ for (Index = 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; Index++) {+ SmmAccessPrivate->SmramDesc[Index].PhysicalStart = DescriptorBlock->Descriptor[Index].PhysicalStart;+ SmmAccessPrivate->SmramDesc[Index].CpuStart = DescriptorBlock->Descriptor[Index].CpuStart;+ SmmAccessPrivate->SmramDesc[Index].PhysicalSize = DescriptorBlock->Descriptor[Index].PhysicalSize;+ SmmAccessPrivate->SmramDesc[Index].RegionState = DescriptorBlock->Descriptor[Index].RegionState;+ }++ SmmAccessPrivate->NumberRegions = Index;+ SmmAccessPrivate->SmmAccess.Open = Open;+ SmmAccessPrivate->SmmAccess.Close = Close;+ SmmAccessPrivate->SmmAccess.Lock = Lock;+ SmmAccessPrivate->SmmAccess.GetCapabilities = GetCapabilities;+ SmmAccessPrivate->SmmAccess.LockState = FALSE;+ SmmAccessPrivate->SmmAccess.OpenState = FALSE;++ //+ // Install PPI+ //+ PpiList->Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);+ PpiList->Guid = &gEfiPeiMmAccessPpiGuid;+ PpiList->Ppi = &SmmAccessPrivate->SmmAccess;++ Status = PeiServicesInstallPpi (PpiList);+ ASSERT_EFI_ERROR (Status);++ return EFI_SUCCESS;+}diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf
new file mode 100644
index 000000000000..160210d429d9
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAcce
+++ ssLibSmramc/PeiSmmAccessLib.inf
@@ -0,0 +1,36 @@
+## @file+# Library description file for the SmmAccess PPI+#+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>+# SPDX-License-Identifier: BSD-2-Clause-Patent+#+##++[Defines]+ INF_VERSION = 0x00010017+ BASE_NAME = PeiSmmAccessLibSmramc+ FILE_GUID = 3D28FD4B-F46F-4E24-88AA-9DA09C51BE87+ VERSION_STRING = 1.0+ MODULE_TYPE = PEIM+ LIBRARY_CLASS = SmmAccessLib++[LibraryClasses]+ BaseMemoryLib+ MemoryAllocationLib+ DebugLib+ HobLib+ PciSegmentLib+ PeiServicesLib++[Packages]+ MdePkg/MdePkg.dec+ IntelSiliconPkg/IntelSiliconPkg.dec++[Sources]+ PeiSmmAccessLib.c++[Ppis]+ gEfiPeiMmAccessPpiGuid ## PRODUCES++[Guids]+ gEfiSmmSmramMemoryGuid--
2.37.2
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [edk2-devel][edk2-platforms][PATCH v2 3/6] IntelSiliconPkg/Feature/SmmControl: Implement PPI with chipset support
[not found] ` <1712B905B760092F.20378@groups.io>
@ 2022-09-09 21:16 ` Isaac Oram
0 siblings, 0 replies; 17+ messages in thread
From: Isaac Oram @ 2022-09-09 21:16 UTC (permalink / raw)
To: devel@edk2.groups.io, Oram, Isaac W, Benjamin Doron
Cc: Desimone, Nathaniel L, Sinha, Ankit, Ni, Ray,
Chaganty, Rangasai V
Pushed as b013adb40e..1b02220269
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Isaac Oram
Sent: Wednesday, September 7, 2022 4:51 PM
To: Benjamin Doron <benjamin.doron00@gmail.com>; devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>
Subject: Re: [edk2-devel][edk2-platforms][PATCH v2 3/6] IntelSiliconPkg/Feature/SmmControl: Implement PPI with chipset support
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>
-----Original Message-----
From: Benjamin Doron <benjamin.doron00@gmail.com>
Sent: Tuesday, September 6, 2022 10:02 AM
To: devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>
Subject: [edk2-devel][edk2-platforms][PATCH v2 3/6] IntelSiliconPkg/Feature/SmmControl: Implement PPI with chipset support
S3 resume may require communication with SMM, for which we need the SmmControl PPI. Therefore, port the DXE drivers to a library, like there is for SMM Access.
Tested, working on Kabylake. Further testing required after the refactor for compatibility.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../PeiSmmControlLib/PeiSmmControlLib.c | 309 ++++++++++++++++++
.../PeiSmmControlLib/PeiSmmControlLib.inf | 34 ++
.../Include/Library/SmmControlLib.h | 26 ++
.../Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 4 +
4 files changed, 373 insertions(+)
create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.c
create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf
create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h
diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.c b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.c
new file mode 100644
index 000000000000..cc6c7f8fe672
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmCon
+++ trolLib/PeiSmmControlLib.c
@@ -0,0 +1,309 @@
+/** @file+ This is to publish the SMM Control Ppi instance.++ Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>+ SPDX-License-Identifier: BSD-2-Clause-Patent++**/+#include <Uefi/UefiBaseType.h>+#include <Library/DebugLib.h>+#include <Library/IoLib.h>+#include <Library/MemoryAllocationLib.h>+#include <Library/PcdLib.h>+#include <Library/PeiServicesLib.h>++#include <Ppi/MmControl.h>+#include <IndustryStandard/Pci30.h>++#define SMM_CONTROL_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('i', '4', 's', 'c')++typedef struct {+ UINTN Signature;+ EFI_HANDLE Handle;+ EFI_PEI_MM_CONTROL_PPI SmmControl;+} SMM_CONTROL_PRIVATE_DATA;++#define SMM_CONTROL_PRIVATE_DATA_FROM_THIS(a) \+ CR (a, \+ SMM_CONTROL_PRIVATE_DATA, \+ SmmControl, \+ SMM_CONTROL_DEV_SIGNATURE \+ )++//+// Common registers:+//+//+// APM Registers+//+#define R_PCH_APM_CNT 0xB2+//+// ACPI and legacy I/O register offsets from ACPIBASE+//+#define R_PCH_ACPI_PM1_STS 0x00+#define B_PCH_ACPI_PM1_STS_PRBTNOR BIT11++#define R_PCH_SMI_EN 0x30++#define R_PCH_SMI_STS 0x34+#define B_PCH_SMI_STS_APM BIT5+#define B_PCH_SMI_EN_APMC BIT5+#define B_PCH_SMI_EN_EOS BIT1+#define B_PCH_SMI_EN_GBL_SMI BIT0++/**+ Trigger the software SMI++ @param[in] Data The value to be set on the software SMI data port++ @retval EFI_SUCCESS Function completes successfully+**/+EFI_STATUS+EFIAPI+SmmTrigger (+ UINT8 Data+ )+{+ UINT16 ABase;+ UINT32 OutputData;+ UINT32 OutputPort;++ ABase = FixedPcdGet16 (PcdAcpiBaseAddress);++ ///+ /// Enable the APMC SMI+ ///+ OutputPort = ABase + R_PCH_SMI_EN;+ OutputData = IoRead32 ((UINTN) OutputPort);+ OutputData |= (B_PCH_SMI_EN_APMC | B_PCH_SMI_EN_GBL_SMI);+ DEBUG (+ (DEBUG_EVENT,+ "The SMI Control Port at address %x will be written to %x.\n",+ OutputPort,+ OutputData)+ );+ IoWrite32 (+ (UINTN) OutputPort,+ (UINT32) (OutputData)+ );++ OutputPort = R_PCH_APM_CNT;+ OutputData = Data;++ ///+ /// Generate the APMC SMI+ ///+ IoWrite8 (+ (UINTN) OutputPort,+ (UINT8) (OutputData)+ );++ return EFI_SUCCESS;+}++/**+ Clear the SMI status+++ @retval EFI_SUCCESS The function completes successfully+ @retval EFI_DEVICE_ERROR Something error occurred+**/+EFI_STATUS+EFIAPI+SmmClear (+ VOID+ )+{+ UINT16 ABase;+ UINT32 OutputData;+ UINT32 OutputPort;++ ABase = FixedPcdGet16 (PcdAcpiBaseAddress);++ ///+ /// Clear the Power Button Override Status Bit, it gates EOS from being set.+ ///+ OutputPort = ABase + R_PCH_ACPI_PM1_STS;+ OutputData = B_PCH_ACPI_PM1_STS_PRBTNOR;+ DEBUG (+ (DEBUG_EVENT,+ "The PM1 Status Port at address %x will be written to %x.\n",+ OutputPort,+ OutputData)+ );+ IoWrite16 (+ (UINTN) OutputPort,+ (UINT16) (OutputData)+ );++ ///+ /// Clear the APM SMI Status Bit+ ///+ OutputPort = ABase + R_PCH_SMI_STS;+ OutputData = B_PCH_SMI_STS_APM;+ DEBUG (+ (DEBUG_EVENT,+ "The SMI Status Port at address %x will be written to %x.\n",+ OutputPort,+ OutputData)+ );+ IoWrite32 (+ (UINTN) OutputPort,+ (UINT32) (OutputData)+ );++ ///+ /// Set the EOS Bit+ ///+ OutputPort = ABase + R_PCH_SMI_EN;+ OutputData = IoRead32 ((UINTN) OutputPort);+ OutputData |= B_PCH_SMI_EN_EOS;+ DEBUG (+ (DEBUG_EVENT,+ "The SMI Control Port at address %x will be written to %x.\n",+ OutputPort,+ OutputData)+ );+ IoWrite32 (+ (UINTN) OutputPort,+ (UINT32) (OutputData)+ );++ ///+ /// There is no need to read EOS back and check if it is set.+ /// This can lead to a reading of zero if an SMI occurs right after the SMI_EN port read+ /// but before the data is returned to the CPU.+ /// SMM Dispatcher should make sure that EOS is set after all SMI sources are processed.+ ///+ return EFI_SUCCESS;+}++/**+ This routine generates an SMI++ @param[in] This The EFI SMM Control protocol instance+ @param[in, out] ArgumentBuffer The buffer of argument+ @param[in, out] ArgumentBufferSize The size of the argument buffer+ @param[in] Periodic Periodic or not+ @param[in] ActivationInterval Interval of periodic SMI++ @retval EFI Status Describing the result of the operation+ @retval EFI_INVALID_PARAMETER Some parameter value passed is not supported+**/+EFI_STATUS+EFIAPI+Activate (+ IN EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_CONTROL_PPI * This,+ IN OUT INT8 *ArgumentBuffer OPTIONAL,+ IN OUT UINTN *ArgumentBufferSize OPTIONAL,+ IN BOOLEAN Periodic OPTIONAL,+ IN UINTN ActivationInterval OPTIONAL+ )+{+ EFI_STATUS Status;+ UINT8 Data;++ if (Periodic) {+ DEBUG ((DEBUG_WARN, "Invalid parameter\n"));+ return EFI_INVALID_PARAMETER;+ }++ // NOTE: Copied from Quark. Matches the usage in PiSmmCommunicationPei+ if (ArgumentBuffer == NULL) {+ Data = 0xFF;+ } else {+ if (ArgumentBufferSize == NULL || *ArgumentBufferSize != 1) {+ return EFI_INVALID_PARAMETER;+ }++ Data = *ArgumentBuffer;+ }+ ///+ /// Clear any pending the APM SMI+ ///+ Status = SmmClear ();+ if (EFI_ERROR (Status)) {+ return Status;+ }++ return SmmTrigger (Data);+}++/**+ This routine clears an SMI++ @param[in] This The EFI SMM Control protocol instance+ @param[in] Periodic Periodic or not++ @retval EFI Status Describing the result of the operation+ @retval EFI_INVALID_PARAMETER Some parameter value passed is not supported+**/+EFI_STATUS+EFIAPI+Deactivate (+ IN EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_MM_CONTROL_PPI * This,+ IN BOOLEAN Periodic OPTIONAL+ )+{+ if (Periodic) {+ return EFI_INVALID_PARAMETER;+ }++ return SmmClear ();+}++/**+ This function is to install an SMM Control PPI+ - <b>Introduction</b> \n+ An API to install an instance of EFI_PEI_MM_CONTROL_PPI. This PPI provides a standard+ way for other modules to trigger software SMIs.++ @retval EFI_SUCCESS - Ppi successfully started and installed.+ @retval EFI_NOT_FOUND - Ppi can't be found.+ @retval EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to initialize the driver.+**/+EFI_STATUS+EFIAPI+PeiInstallSmmControlPpi (+ VOID+ )+{+ EFI_STATUS Status;+ EFI_PEI_PPI_DESCRIPTOR *PpiList;+ SMM_CONTROL_PRIVATE_DATA *SmmControlPrivate;++ //+ // Initialize private data+ //+ SmmControlPrivate = AllocateZeroPool (sizeof (*SmmControlPrivate));+ ASSERT (SmmControlPrivate != NULL);+ if (SmmControlPrivate == NULL) {+ return EFI_OUT_OF_RESOURCES;+ }+ PpiList = AllocateZeroPool (sizeof (*PpiList));+ ASSERT (PpiList != NULL);+ if (PpiList == NULL) {+ return EFI_OUT_OF_RESOURCES;+ }++ SmmControlPrivate->Signature = SMM_CONTROL_PRIVATE_DATA_SIGNATURE;+ SmmControlPrivate->Handle = NULL;++ SmmControlPrivate->SmmControl.Trigger = Activate;+ SmmControlPrivate->SmmControl.Clear = Deactivate;++ //+ // Install PPI+ //+ PpiList->Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);+ PpiList->Guid = &gEfiPeiMmControlPpiGuid;+ PpiList->Ppi = &SmmControlPrivate->SmmControl;++ Status = PeiServicesInstallPpi (PpiList);+ ASSERT_EFI_ERROR (Status);++ // Unlike driver, do not disable SMIs as S3 resume continues+ return EFI_SUCCESS;+}diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf
new file mode 100644
index 000000000000..91c761366446
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmCon
+++ trolLib/PeiSmmControlLib.inf
@@ -0,0 +1,34 @@
+## @file+# Library description file for the SmmControl PPI+#+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>+# SPDX-License-Identifier: BSD-2-Clause-Patent+#+##++[Defines]+ INF_VERSION = 0x00010017+ BASE_NAME = PeiSmmControlLib+ FILE_GUID = F45D521A-C0DF-4283-A3CA-65AD01B479E7+ VERSION_STRING = 1.0+ MODULE_TYPE = PEIM+ LIBRARY_CLASS = SmmControlLib++[LibraryClasses]+ IoLib+ DebugLib+ MemoryAllocationLib+ PeiServicesLib++[Packages]+ MdePkg/MdePkg.dec+ IntelSiliconPkg/IntelSiliconPkg.dec++[Sources]+ PeiSmmControlLib.c++[Pcd]+ gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES++[Ppis]+ gEfiPeiMmControlPpiGuid ## PRODUCESdiff --git a/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h b/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h
new file mode 100644
index 000000000000..b532dd13f373
--- /dev/null
+++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h
@@ -0,0 +1,26 @@
+/** @file+ This is to publish the SMM Control Ppi instance.++ Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>+ SPDX-License-Identifier: BSD-2-Clause-Patent++**/+#ifndef _SMM_CONTROL_LIB_H_+#define _SMM_CONTROL_LIB_H_++/**+ This function is to install an SMM Control PPI+ - <b>Introduction</b> \n+ An API to install an instance of EFI_PEI_MM_CONTROL_PPI. This PPI provides a standard+ way for other modules to trigger software SMIs.++ @retval EFI_SUCCESS - Ppi successfully started and installed.+ @retval EFI_NOT_FOUND - Ppi can't be found.+ @retval EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to initialize the driver.+**/+EFI_STATUS+EFIAPI+PeiInstallSmmControlPpi (+ VOID+ );+#endifdiff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
index deefdc55b5d6..440c7d0255ce 100644
--- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
+++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec
@@ -35,6 +35,10 @@
# SmmAccessLib|Include/Library/SmmAccessLib.h + ## @libraryclass Provides services to trigger SMI+ #+ SmmControlLib|Include/Library/SmmControlLib.h+ ## @libraryclass Provides services to access config block # ConfigBlockLib|Include/Library/ConfigBlockLib.h--
2.37.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [edk2-devel][edk2-platforms][PATCH v2 4/6] S3FeaturePkg: Implement working S3 resume
2022-09-08 0:38 ` Isaac Oram
@ 2022-09-11 15:46 ` Benjamin Doron
0 siblings, 0 replies; 17+ messages in thread
From: Benjamin Doron @ 2022-09-11 15:46 UTC (permalink / raw)
To: Oram, Isaac W
Cc: devel@edk2.groups.io, Chaganty, Rangasai V, Desimone, Nathaniel L,
Sinha, Ankit, Gao, Liming
[-- Attachment #1: Type: text/plain, Size: 18482 bytes --]
Hi Isaac,
These SMM communication modules are S3 specific:
- PiSmmCommunicationPei exits with EFI_UNSUPPORTED if BootMode !=
BOOT_ON_S3_RESUME (
https://github.com/tianocore/edk2/blob/master/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.c#L380-L383
).
- PiSmmCommunicationSmm installs an SMI handler that can be found in the
SMM config table, GUID-ed as "Pei...Ppi" (
https://github.com/tianocore/edk2/blob/master/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.c#L38-L43
).
So, those modules are for S3 resume. I can push a patch that adds
SmmLockBox to MinPlatform. Maybe stage 5 makes sense?
Best regards,
Benjamin
On Wed, 7 Sept 2022 at 20:38, Oram, Isaac W <isaac.w.oram@intel.com> wrote:
> It seems like:
> UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
> UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
> MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
>
> Are not S3 specific and belong with common stage 4 or 5 content. It seems
> many features could require them. DSC can deal with duplicates, but FDF
> would fail if there were collisions.
>
> S3Feature.dsc
> - Remove commented out code
>
> Regards,
> Isaac
>
> -----Original Message-----
> From: Benjamin Doron <benjamin.doron00@gmail.com>
> Sent: Tuesday, September 6, 2022 10:02 AM
> To: devel@edk2.groups.io
> Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <
> ankit.sinha@intel.com>; Chaganty, Rangasai V <
> rangasai.v.chaganty@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>;
> Gao, Liming <gaoliming@byosoft.com.cn>
> Subject: [edk2-devel][edk2-platforms][PATCH v2 4/6] S3FeaturePkg:
> Implement working S3 resume
>
> Follow-up commits to MinPlatform (PeiFspWrapperHobProcessLib for
> memory) and FSP-related board libraries (policy overrides) required for
> successful S3 resume.
>
> Factored allocation logic into new module to avoid MinPlatform dependency
> on S3Feature package.
>
> TODO: Can optimise required size.
>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> Cc: Isaac Oram <isaac.w.oram@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
> ---
> .../S3FeaturePkg/Include/PostMemory.fdf | 13 ++
> .../S3FeaturePkg/Include/PreMemory.fdf | 8 +-
> .../S3FeaturePkg/Include/S3Feature.dsc | 38 ++++-
> .../S3FeaturePkg/S3Dxe/S3Dxe.c | 155 ++++++++++++++++++
> .../S3FeaturePkg/S3Dxe/S3Dxe.inf | 49 ++++++
> .../S3FeaturePkg/S3Pei/S3Pei.c | 83 +++++++++-
> .../S3FeaturePkg/S3Pei/S3Pei.inf | 8 +-
> .../Include/AcpiS3MemoryNvData.h | 22 +++
> 8 files changed, 365 insertions(+), 11 deletions(-) create mode 100644
> Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
> create mode 100644
> Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
> create mode 100644
> Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
>
> diff --git
> a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf
> b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf
> index 9e17f853c630..7f630908fa2c 100644
> --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf
> +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf
> @@ -2,7 +2,20 @@
> # FDF file for post-memory S3 advanced feature modules. # # Copyright
> (c) 2019, Intel Corporation. All rights reserved.<BR>+# Copyright (c) 2022,
> Baruch Binyamin Doron.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent
> # ##++## Dependencies+ INF
> UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf+ INF
> MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf++## Save-state
> module stack+ INF S3FeaturePkg/S3Dxe/S3Dxe.inf+ INF
> MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf+ INF
> UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf++## Restore-state module stack+
> INF
> MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.infdiff
> --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf
> b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf
> index fdd16a4e0356..e130fa5f098d 100644
> --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf
> +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf
> @@ -2,9 +2,15 @@
> # FDF file for pre-memory S3 advanced feature modules. # # Copyright (c)
> 2019, Intel Corporation. All rights reserved.<BR>+# Copyright (c) 2022,
> Baruch Binyamin Doron.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent
> # ## -INF S3FeaturePkg/S3Pei/S3Pei.inf+## Dependencies+ INF
> S3FeaturePkg/S3Pei/S3Pei.inf+ INF
> UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf++## Restore-state
> module stack+ INF
> UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.infdiff --git
> a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc
> b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc
> index cc34e785076a..d8bfc7909413 100644
> --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc
> +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc
> @@ -7,6 +7,7 @@
> # for the build infrastructure. # # Copyright (c) 2019 - 2021, Intel
> Corporation. All rights reserved.<BR>+# Copyright (c) 2022, Baruch Binyamin
> Doron.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent #@@ -25,6
> +26,10 @@
> !error "DXE_ARCH must be specified to build this feature!" !endif
> +[PcdsFixedAtBuild]+ # Attempts to improve performance at the cost of more
> DRAM usage+ gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE+
> ################################################################################
> # # Library Class section - list of all Library Classes needed by this
> feature.@@ -32,7 +37,14 @@
> ################################################################################
> [LibraryClasses.common.PEIM]-
> SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.inf+
> #SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf+
> SmmControlLib|IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf++[LibraryClasses.common.DXE_DRIVER,
> LibraryClasses.common.DXE_SMM_DRIVER]+
> #######################################+ # Edk2 Packages+
> #######################################+
> S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf
> ################################################################################
> #@@ -60,8 +72,26 @@
> # S3 Feature Package ##################################### - # Add
> library instances here that are not included in package components and
> should be tested- # in the package build.- # Add components here that
> should be included in the package build. S3FeaturePkg/S3Pei/S3Pei.inf+
> UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf+
> UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf++#+# Feature DXE
> Components+#++# @todo: Change below line to [Components.$(DXE_ARCH)] after
> https://bugzilla.tianocore.org/show_bug.cgi?id=2308+# is
> completed.+[Components.X64]+ #####################################+ # S3
> Feature Package+ #####################################++ # Add components
> here that should be included in the package build.+
> UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf+
> MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf+
> S3FeaturePkg/S3Dxe/S3Dxe.inf+
> MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf+
> UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf+
> MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.infdiff
> --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
> b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
> new file mode 100644
> index 000000000000..1a7ccb8eedab
> --- /dev/null
> +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
> @@ -0,0 +1,155 @@
> +/** @file+ Source code file for S3 DXE module++Copyright (c) 2022,
> Baruch Binyamin Doron.<BR>+SPDX-License-Identifier:
> BSD-2-Clause-Patent++**/++#include <PiDxe.h>+#include
> <Library/BaseMemoryLib.h>+#include <Library/DebugLib.h>+#include
> <Library/PcdLib.h>+#include <Library/UefiLib.h>+#include
> <Library/UefiBootServicesTableLib.h>+#include
> <Library/UefiRuntimeServicesTableLib.h>+#include
> <Guid/AcpiS3Context.h>+#include <Guid/MemoryTypeInformation.h>+#include
> <AcpiS3MemoryNvData.h>++#define PEI_ADDITIONAL_MEMORY_SIZE (16 *
> EFI_PAGE_SIZE)++/**+ Get the mem size in memory type information table.++
> @return the mem size in memory type information
> table.+**/+UINT64+EFIAPI+GetMemorySizeInMemoryTypeInformation (+ VOID+
> )+{+ EFI_STATUS Status;+ EFI_MEMORY_TYPE_INFORMATION
> *MemoryData;+ UINT8 Index;+ UINTN
> TempPageNum;++ Status = EfiGetSystemConfigurationTable
> (&gEfiMemoryTypeInformationGuid, (VOID **) &MemoryData);++ if (EFI_ERROR
> (Status) || MemoryData == NULL) {+ return 0;+ }++ TempPageNum = 0;+
> for (Index = 0; MemoryData[Index].Type != EfiMaxMemoryType; Index++) {+
> //+ // Accumulate default memory size requirements+ //+
> TempPageNum += MemoryData[Index].NumberOfPages;+ }++ return TempPageNum *
> EFI_PAGE_SIZE;+}++/**+ Get the mem size need to be consumed and reserved
> for PEI phase resume.++ @return the mem size to be reserved for PEI phase
> resume.+**/+UINT64+EFIAPI+GetPeiMemSize (+ VOID+ )+{+ UINT64 Size;++
> Size = GetMemorySizeInMemoryTypeInformation ();++ return PcdGet32
> (PcdPeiMinMemSize) + Size + PEI_ADDITIONAL_MEMORY_SIZE;+}++/**+ Allocate
> EfiACPIMemoryNVS below 4G memory address.++ This function allocates
> EfiACPIMemoryNVS below 4G memory address.++ @param Size Size of
> memory to allocate.++ @return Allocated address for output.++**/+VOID
> *+EFIAPI+AllocateAcpiNvsMemoryBelow4G (+ IN UINTN Size+ )+{+ UINTN
> Pages;+ EFI_PHYSICAL_ADDRESS Address;+ EFI_STATUS
> Status;+ VOID *Buffer;++ Pages = EFI_SIZE_TO_PAGES
> (Size);+ Address = 0xffffffff;++ Status = gBS->AllocatePages (+
> AllocateMaxAddress,+ EfiACPIMemoryNVS,+
> Pages,+ &Address+ );+
> ASSERT_EFI_ERROR (Status);++ Buffer = (VOID *)(UINTN)Address;+ ZeroMem
> (Buffer, Size);++ return Buffer;+}++/**+ Allocates memory to use on S3
> resume.++ @param[in] ImageHandle Not used.+ @param[in]
> SystemTable General purpose services available to every DXE
> driver.++ @retval EFI_SUCCESS The function completes
> successfully+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to
> create database+**/+EFI_STATUS+EFIAPI+S3DxeEntryPoint (+ IN EFI_HANDLE
> ImageHandle,+ IN EFI_SYSTEM_TABLE *SystemTable+ )+{+ UINT64
> S3PeiMemSize;+ UINT64 S3PeiMemBase;+ ACPI_S3_MEMORY
> S3MemoryInfo;+ EFI_STATUS Status;++ DEBUG ((DEBUG_INFO, "%a()
> Start\n", __FUNCTION__));++ S3PeiMemSize = GetPeiMemSize ();+
> S3PeiMemBase = (UINTN) AllocateAcpiNvsMemoryBelow4G (S3PeiMemSize);+
> ASSERT (S3PeiMemBase != 0);++ S3MemoryInfo.S3PeiMemBase = S3PeiMemBase;+
> S3MemoryInfo.S3PeiMemSize = S3PeiMemSize;++ DEBUG ((DEBUG_INFO,
> "S3PeiMemBase: 0x%x\n", S3PeiMemBase));+ DEBUG ((DEBUG_INFO,
> "S3PeiMemSize: 0x%x\n", S3PeiMemSize));++ Status = gRT->SetVariable (+
> ACPI_S3_MEMORY_NV_NAME,+
> &gEfiAcpiVariableGuid,+ EFI_VARIABLE_NON_VOLATILE |
> EFI_VARIABLE_BOOTSERVICE_ACCESS,+ sizeof (S3MemoryInfo),+
> &S3MemoryInfo+ );+ ASSERT_EFI_ERROR
> (Status);++ DEBUG ((DEBUG_INFO, "%a() End\n", __FUNCTION__));+ return
> EFI_SUCCESS;+}diff --git
> a/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
> b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
> new file mode 100644
> index 000000000000..28589c2c869b
> --- /dev/null
> +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
> @@ -0,0 +1,49 @@
> +### @file+# Component information file for the S3 DXE module.+#+#
> Copyright (c) 2022, Baruch Binyamin Doron.<BR>+#+# SPDX-License-Identifier:
> BSD-2-Clause-Patent+#+###++[Defines]+ INF_VERSION = 0x00010017+
> BASE_NAME = S3Dxe+ FILE_GUID =
> 30926F92-CC83-4381-9F70-AC96EDB5BEE0+ VERSION_STRING = 1.0+
> MODULE_TYPE = DXE_DRIVER+ ENTRY_POINT =
> S3DxeEntryPoint++[LibraryClasses]+ UefiDriverEntryPoint+
> UefiBootServicesTableLib+ UefiRuntimeServicesTableLib+ BaseMemoryLib+
> DebugLib+ PcdLib+ UefiLib++[Packages]+ MdePkg/MdePkg.dec+
> MdeModulePkg/MdeModulePkg.dec+ MinPlatformPkg/MinPlatformPkg.dec+
> IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec+
> S3FeaturePkg/S3FeaturePkg.dec++[Sources]+ S3Dxe.c++[Pcd]+
> gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize++[FeaturePcd]+
> gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable++[Guids]+
> gEfiMemoryTypeInformationGuid ## CONSUMES+ gEfiAcpiVariableGuid
> ## CONSUMES++[Depex]+ gEfiVariableArchProtocolGuid AND+
> gEfiVariableWriteArchProtocolGuiddiff --git
> a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c
> b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c
> index b0aaa04962c8..6acb894b6fc9 100644
> --- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c
> +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c
> @@ -2,12 +2,87 @@
> Source code file for S3 PEI module Copyright (c) 2019, Intel
> Corporation. All rights reserved.<BR>+Copyright (c) 2022, Baruch Binyamin
> Doron.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ +#include
> <PiPei.h>+#include <Library/DebugLib.h>+#include <Library/PciLib.h>
> #include <Library/PeiServicesLib.h> #include
> <Library/SmmAccessLib.h>+#include <Library/SmmControlLib.h>++// TODO:
> Finalise implementation factoring+#define R_SA_PAM0 (0x80)+#define
> R_SA_PAM5 (0x85)+#define R_SA_PAM6 (0x86)++/**+ This function is called
> after FspSiliconInitDone installed PPI.+ For FSP API mode, this is when
> FSP-M HOBs are installed into EDK2.++ @param[in] PeiServices Pointer to
> PEI Services Table.+ @param[in] NotifyDesc Pointer to the descriptor
> for the Notification event that+ caused this
> function to execute.+ @param[in] Ppi Pointer to the PPI data
> associated with this function.++ @retval EFI_STATUS Always return
> EFI_SUCCESS+**/+EFI_STATUS+EFIAPI+FspSiliconInitDoneNotify (+ IN
> EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_NOTIFY_DESCRIPTOR
> *NotifyDesc,+ IN VOID *Ppi+ )+{+ EFI_STATUS
> Status;+ EFI_BOOT_MODE BootMode;+ UINT64 MchBaseAddress;++
> Status = PeiServicesGetBootMode (&BootMode);+ ASSERT_EFI_ERROR
> (Status);++ // Enable PAM regions for AP wakeup vector (resume)+ // - CPU
> is finalised by PiSmmCpuDxeSmm, not FSP. So, it's safe here?+ //
> TODO/TEST: coreboot does this unconditionally, vendor FWs may not (test
> resume). Should we?+ // - It is certainly interesting that only PAM0, PAM5
> and PAM6 are defined for KabylakeSiliconPkg.+ // - Also note that
> 0xA0000-0xFFFFF is marked "reserved" in FSP HOB - this does not mean+ //
> that the memory is unusable, perhaps this is precisely because it will
> contain+ // the AP wakeup vector.+ if (BootMode == BOOT_ON_S3_RESUME)
> {+ MchBaseAddress = PCI_LIB_ADDRESS (0, 0, 0, 0);+ PciWrite8
> (MchBaseAddress + R_SA_PAM0, 0x30);+ PciWrite8 (MchBaseAddress +
> (R_SA_PAM0 + 1), 0x33);+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 2),
> 0x33);+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 3), 0x33);+
> PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 4), 0x33);+ PciWrite8
> (MchBaseAddress + R_SA_PAM5, 0x33);+ PciWrite8 (MchBaseAddress +
> R_SA_PAM6, 0x33);+ }++ //+ // Install EFI_PEI_MM_ACCESS_PPI for S3
> resume case+ //+ Status = PeiInstallSmmAccessPpi ();+ ASSERT_EFI_ERROR
> (Status);++ //+ // Install EFI_PEI_MM_CONTROL_PPI for S3 resume case+
> //+ Status = PeiInstallSmmControlPpi ();+ ASSERT_EFI_ERROR (Status);++
> return Status;+}++EFI_PEI_NOTIFY_DESCRIPTOR mFspSiliconInitDoneNotifyDesc
> = {+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),+ &gFspSiliconInitDonePpiGuid,+
> FspSiliconInitDoneNotify+}; /** S3 PEI module entry point@@ -25,12
> +100,10 @@ S3PeiEntryPoint (
> IN CONST EFI_PEI_SERVICES **PeiServices ) {- EFI_STATUS
> Status;+ EFI_STATUS Status; - //- // Install EFI_PEI_MM_ACCESS_PPI for
> S3 resume case- //- Status = PeiInstallSmmAccessPpi ();+ Status =
> PeiServicesNotifyPpi (&mFspSiliconInitDoneNotifyDesc);+ ASSERT_EFI_ERROR
> (Status); return Status; }diff --git
> a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf
> b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf
> index e485eac9521f..173919bb881e 100644
> --- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf
> +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf
> @@ -18,10 +18,13 @@
> [LibraryClasses] PeimEntryPoint PeiServicesLib+ DebugLib
> SmmAccessLib+ SmmControlLib [Packages] MdePkg/MdePkg.dec+
> IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
> IntelSiliconPkg/IntelSiliconPkg.dec S3FeaturePkg/S3FeaturePkg.dec @@
> -31,5 +34,8 @@
> [FeaturePcd] gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable +[Ppis]+
> gFspSiliconInitDonePpiGuid+ [Depex]- gEfiPeiMemoryDiscoveredPpiGuid+
> TRUEdiff --git a/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
> b/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
> new file mode 100644
> index 000000000000..0d75af8e9a03
> --- /dev/null
> +++ b/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
> @@ -0,0 +1,22 @@
> +/** @file
> + Header file for NV data structure definition.
> +
> +Copyright (c) 2021, Baruch Binyamin Doron
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef __ACPI_S3_MEMORY_NV_DATA_H__
> +#define __ACPI_S3_MEMORY_NV_DATA_H__
> +
> +//
> +// NV data structure
> +//
> +typedef struct {
> + UINT64 S3PeiMemBase;
> + UINT64 S3PeiMemSize;
> +} ACPI_S3_MEMORY;
> +
> +#define ACPI_S3_MEMORY_NV_NAME L"S3MemoryInfo"
> +
> +#endif
> --
> 2.37.2
>
>
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2022-09-06 17:02 [edk2-devel][edk2-platforms][PATCH v2 0/6] Implement S3 resume Benjamin Doron
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 1/6] {Platform,Silicon}/Intel: Move PcdAcpiBaseAddress definition Benjamin Doron
2022-09-07 22:50 ` Isaac Oram
2022-09-07 22:57 ` Chaganty, Rangasai V
2022-09-09 21:11 ` Isaac Oram
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 2/6] IntelSiliconPkg/Feature/SmmAccess: Implement PPI with chipset support Benjamin Doron
2022-09-07 23:49 ` Isaac Oram
[not found] ` <1712B8F6079EA3A9.20240@groups.io>
2022-09-09 21:13 ` Isaac Oram
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 3/6] IntelSiliconPkg/Feature/SmmControl: " Benjamin Doron
2022-09-07 23:50 ` Isaac Oram
[not found] ` <1712B905B760092F.20378@groups.io>
2022-09-09 21:16 ` Isaac Oram
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 4/6] S3FeaturePkg: Implement working S3 resume Benjamin Doron
2022-09-08 0:38 ` Isaac Oram
2022-09-11 15:46 ` Benjamin Doron
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 5/6] MinPlatformPkg: " Benjamin Doron
2022-09-08 2:46 ` Isaac Oram
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 6/6] KabylakeOpenBoardPkg: Example of board S3 Benjamin Doron
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