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Tue, 15 Dec 2020 18:17:04 +0000 Received: from SJ0PR05MB7580.namprd05.prod.outlook.com ([fe80::ad1c:9900:1bea:47cf]) by SJ0PR05MB7580.namprd05.prod.outlook.com ([fe80::ad1c:9900:1bea:47cf%6]) with mapi id 15.20.3654.025; Tue, 15 Dec 2020 18:17:04 +0000 From: "Andrei Warkentin" To: "devel@edk2.groups.io" , "jeremy.linton@arm.com" CC: "ard.biesheuvel@arm.com" , "leif@nuviainc.com" , "pete@akeo.ie" , "andrey.warkentin@gmail.com" , "samer.el-haj-mahmoud@arm.com" Subject: Re: [edk2-devel] [PATCH 3/7] Platform/RaspberryPi: Split MMC register defintions Thread-Topic: [edk2-devel] [PATCH 3/7] Platform/RaspberryPi: Split MMC register defintions Thread-Index: AQHW0nA1D/uKjmfXl0e30qWD/yqFu6n4d+jH Date: Tue, 15 Dec 2020 18:17:03 +0000 Message-ID: References: <20201214232350.1192387-1-jeremy.linton@arm.com>,<20201214232350.1192387-4-jeremy.linton@arm.com> In-Reply-To: <20201214232350.1192387-4-jeremy.linton@arm.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: edk2.groups.io; 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x-ms-exchange-antispam-messagedata: =?us-ascii?Q?rk6c0nPyynYpDbfEql1WsvFDNcbFSGGdVq0AHNvn6PTu2xY4GwO7J99uRLu2?= =?us-ascii?Q?YpOXBwyuBPlPBO5uZfiwFhE6WljrlN/eWMxevzq9zrn3ElMvlx03/oAwuRza?= =?us-ascii?Q?B9nQ0+h6Yebv/frbMvOHkr9pe+r4u4r54lACwsu92r1T2vnR6C1aRVLtgGGu?= =?us-ascii?Q?LGlkIh04MaLlnTA9jc0Iyl1ei9d2KcsmZtRU1w+ktjATKBtdqajg4T57DrM7?= =?us-ascii?Q?ZjAuIbhcdZgodYKuXfLM3BV/c19lUPxsxTh9ciIgB+MAikKYgsknkHfkPooh?= =?us-ascii?Q?hZGA/L4ItdgdhhbJBNSAE+kTqRvug7R2yqItEXdGEqQIpEWGvCcY87Agj9ML?= =?us-ascii?Q?Au+1RqFVCWsbL6EjZ3cwPvKYHgm3dDEP+PQgRw6ilvlhRgcMdzeL40mJX/te?= =?us-ascii?Q?NlNClbXwiOldlrAjb/yiIOqgV1pcOlWIz1Pr7ZLKTYrRzCTL8dMUAuaxfksa?= =?us-ascii?Q?rZa5fehk1Jls6Anw14rBTJTF+dtMOenuoCJNsGczTmFJ3inbw0J7vS0hYXW+?= =?us-ascii?Q?peaPW8OXRtV7NQSYGb8q2+KYgB7PxdDPK4iQbe8Dcr8JO0PlWoh23b8/QAdn?= =?us-ascii?Q?Ceq3TbuZl60eyQ1TJk+bT8QR8hVoQVGPa8MZPC9oVF58V6kswh3zyVlaL+lh?= =?us-ascii?Q?0sUqoqIQlFn5kpgShn+hHsopelolQpSZLYWqZfV1V4SkOThv9fmsx6ntZt2w?= =?us-ascii?Q?ZEj8hX9ATH1WlYh6kAc2/hi5PL8Ttbec3RGz3j0Hg+IDH8GriqPOEuy7TtkH?= =?us-ascii?Q?7qbLK5B4tqZ3EdCWyh6DAnucuqHC9+sSdQzENgWPa5m4oeOIFGtKaHUi9enz?= =?us-ascii?Q?h76vY3DOeFYXn12oxR/1aBqcCpE4ucO1MkUu7yjwy3qYEh5ssxg4IRNlDrRO?= =?us-ascii?Q?sUnpGCk8CkBH7iRNwwqdRFD5rGg500dFAjwVDep3mWrVpuvYJiSy9sxu+RqO?= =?us-ascii?Q?kRs/X+vvSl5GfCG4Ov7kq0QCJ4jsOe1RqN8R6Mq1eRE=3D?= x-ms-exchange-transport-forked: True MIME-Version: 1.0 X-OriginatorOrg: vmware.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SJ0PR05MB7580.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4a9d5f35-1f60-4833-74a9-08d8a1259fe9 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Dec 2020 18:17:03.9085 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b39138ca-3cee-4b4a-a4d6-cd83d9dd62f0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: z8U8/Z8EPmfh+No75Rca4WfiIkrM7/YuK2UvtdFYyphNqLgmt/ibnUCc/qMCf+goD+zyVDWOi9e3dMCw+anehw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR05MB7754 Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_SJ0PR05MB75804B16E507AC695A0DFAEDB9C60SJ0PR05MB7580namp_" --_000_SJ0PR05MB75804B16E507AC695A0DFAEDB9C60SJ0PR05MB7580namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable LGTM. This is the same approach I took last time I looked at this (unsucces= sfully...) Reviewed-by: Andrei Warkentin ________________________________ From: devel@edk2.groups.io on behalf of Jeremy Linto= n via groups.io Sent: Monday, December 14, 2020 5:23 PM To: devel@edk2.groups.io Cc: ard.biesheuvel@arm.com ; leif@nuviainc.com ; pete@akeo.ie ; andrey.warkentin@gmail.com ; samer.el-haj-mahmoud@arm.com ; Jeremy Linton Subject: [edk2-devel] [PATCH 3/7] Platform/RaspberryPi: Split MMC register = defintions The current MMC (really SDHCI) defintions are tied to the arasan controller. As we intend to reuse the definitions lets make the base address configurable when the driver loads. This assumes we won't ever want to run both the emmc2 and arasan sdhci controller at the same time. Signed-off-by: Jeremy Linton --- .../Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c | 9 ++++- .../Bcm283x/Include/IndustryStandard/Bcm2836Sdio.h | 42 ++++++++++++------= ---- 2 files changed, 32 insertions(+), 19 deletions(-) diff --git a/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe= .c b/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c index 88e9126e35..0cb7e85b38 100644 --- a/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c +++ b/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c @@ -16,6 +16,7 @@ STATIC CARD_DETECT_STATE mCardDetectState =3D CardDetectR= equired; UINT32 LastExecutedCommand =3D (UINT32) -1; STATIC RASPBERRY_PI_FIRMWARE_PROTOCOL *mFwProtocol; +STATIC UINTN MMCHS_BASE; /** These SD commands are optional, according to the SD Spec @@ -763,7 +764,13 @@ MMCInitialize ( DEBUG ((DEBUG_MMCHOST_SD, "ArasanMMCHost: MMCInitialize()\n")); - if (!PcdGet32 (PcdSdIsArasan)) { + if (PcdGet32 (PcdSdIsArasan)) { + DEBUG ((DEBUG_INFO, "SD is routed to Arasan\n")); + MMCHS_BASE =3D MMCHS1_BASE; + } else if (RPI_MODEL =3D=3D 4) { + DEBUG ((DEBUG_INFO, "SD is routed to emmc2\n")); + MMCHS_BASE =3D MMCHS2_BASE; + } else { DEBUG ((DEBUG_INFO, "SD is not routed to Arasan\n")); return EFI_REQUEST_UNLOAD_IMAGE; } diff --git a/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Sdio.= h b/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Sdio.h index fd07b47170..e6892d36cf 100644 --- a/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Sdio.h +++ b/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Sdio.h @@ -13,15 +13,18 @@ // MMC/SD/SDIO1 register definitions. #define MMCHS1_OFFSET 0x00300000 +#define MMCHS2_OFFSET 0x00340000 #define MMCHS1_BASE (BCM2836_SOC_REGISTERS + MMCHS1_OFFSET) +#define MMCHS2_BASE (BCM2836_SOC_REGISTERS + MMCHS2_OFFSET) #define MMCHS1_LENGTH 0x00000100 +#define MMCHS2_LENGTH 0x00000100 -#define MMCHS_BLK (MMCHS1_BASE + 0x4) +#define MMCHS_BLK (MMCHS_BASE + 0x4) #define BLEN_512BYTES (0x200UL << 0) -#define MMCHS_ARG (MMCHS1_BASE + 0x8) +#define MMCHS_ARG (MMCHS_BASE + 0x8) -#define MMCHS_CMD (MMCHS1_BASE + 0xC) +#define MMCHS_CMD (MMCHS_BASE + 0xC) #define BCE_ENABLE BIT1 #define DDIR_READ BIT4 #define DDIR_WRITE (0x0UL << 4) @@ -43,13 +46,13 @@ #define INDX(CMD_INDX) (TYPE(CMD_TYPE_NORMAL) | _INDX(CMD_INDX)) #define INDX_ABORT(CMD_INDX) (TYPE(CMD_TYPE_ABORT) | _INDX(CMD_INDX)) -#define MMCHS_RSP10 (MMCHS1_BASE + 0x10) -#define MMCHS_RSP32 (MMCHS1_BASE + 0x14) -#define MMCHS_RSP54 (MMCHS1_BASE + 0x18) -#define MMCHS_RSP76 (MMCHS1_BASE + 0x1C) -#define MMCHS_DATA (MMCHS1_BASE + 0x20) +#define MMCHS_RSP10 (MMCHS_BASE + 0x10) +#define MMCHS_RSP32 (MMCHS_BASE + 0x14) +#define MMCHS_RSP54 (MMCHS_BASE + 0x18) +#define MMCHS_RSP76 (MMCHS_BASE + 0x1C) +#define MMCHS_DATA (MMCHS_BASE + 0x20) -#define MMCHS_PRES_STATE (MMCHS1_BASE + 0x24) +#define MMCHS_PRES_STATE (MMCHS_BASE + 0x24) #define CMDI_MASK BIT0 #define CMDI_ALLOWED (0x0UL << 0) #define CMDI_NOT_ALLOWED BIT0 @@ -58,17 +61,19 @@ #define DATI_NOT_ALLOWED BIT1 #define WRITE_PROTECT_OFF BIT19 -#define MMCHS_HCTL (MMCHS1_BASE + 0x28) +#define MMCHS_HCTL (MMCHS_BASE + 0x28) #define DTW_1_BIT (0x0UL << 1) #define DTW_4_BIT BIT1 #define SDBP_MASK BIT8 #define SDBP_OFF (0x0UL << 8) #define SDBP_ON BIT8 +#define SDVS_MASK (0x7UL << 9) #define SDVS_1_8_V (0x5UL << 9) #define SDVS_3_0_V (0x6UL << 9) +#define SDVS_3_3_V (0x7UL << 9) #define IWE BIT24 -#define MMCHS_SYSCTL (MMCHS1_BASE + 0x2C) +#define MMCHS_SYSCTL (MMCHS_BASE + 0x2C) #define ICE BIT0 #define ICS_MASK BIT1 #define ICS BIT1 @@ -84,7 +89,7 @@ #define SRC BIT25 #define SRD BIT26 -#define MMCHS_INT_STAT (MMCHS1_BASE + 0x30) +#define MMCHS_INT_STAT (MMCHS_BASE + 0x30) #define CC BIT0 #define TC BIT1 #define BWR BIT4 @@ -96,7 +101,7 @@ #define DCRC BIT21 #define DEB BIT22 -#define MMCHS_IE (MMCHS1_BASE + 0x34) +#define MMCHS_IE (MMCHS_BASE + 0x34) #define CC_EN BIT0 #define TC_EN BIT1 #define BWR_EN BIT4 @@ -112,7 +117,7 @@ #define BADA_EN BIT29 #define ALL_EN 0xFFFFFFFF -#define MMCHS_ISE (MMCHS1_BASE + 0x38) +#define MMCHS_ISE (MMCHS_BASE + 0x38) #define CC_SIGEN BIT0 #define TC_SIGEN BIT1 #define BWR_SIGEN BIT4 @@ -127,14 +132,15 @@ #define CERR_SIGEN BIT28 #define BADA_SIGEN BIT29 -#define MMCHS_AC12 (MMCHS1_BASE + 0x3C) +#define MMCHS_AC12 (MMCHS_BASE + 0x3C) +#define MMCHS_HC2R (MMCHS_BASE + 0x3E) -#define MMCHS_CAPA (MMCHS1_BASE + 0x40) +#define MMCHS_CAPA (MMCHS_BASE + 0x40) #define VS30 BIT25 #define VS18 BIT26 -#define MMCHS_CUR_CAPA (MMCHS1_BASE + 0x48) -#define MMCHS_REV (MMCHS1_BASE + 0xFC) +#define MMCHS_CUR_CAPA (MMCHS_BASE + 0x48) +#define MMCHS_REV (MMCHS_BASE + 0xFC) #define BLOCK_COUNT_SHIFT 16 #define RCA_SHIFT 16 -- 2.13.7 -=3D-=3D-=3D-=3D-=3D-=3D Groups.io Links: You receive all messages sent to this group. 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LGTM. T= his is the same approach I took last time I looked at this (unsuccessfully.= ..)

Reviewed-by: Andrei Warkentin <= awarkentin@vmware.com>

From: devel@edk2.groups.io = <devel@edk2.groups.io> on behalf of Jeremy Linton via groups.io <j= eremy.linton=3Darm.com@groups.io>
Sent: Monday, December 14, 2020 5:23 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: ard.biesheuvel@arm.com <ard.biesheuvel@arm.com>; leif@nuvi= ainc.com <leif@nuviainc.com>; pete@akeo.ie <pete@akeo.ie>; andr= ey.warkentin@gmail.com <andrey.warkentin@gmail.com>; samer.el-haj-mah= moud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com>
Subject: [edk2-devel] [PATCH 3/7] Platform/RaspberryPi: Split MMC re= gister defintions
 
The current MMC (really SDHCI) defintions are tied= to the
arasan controller. As we intend to reuse the definitions lets
make the base address configurable when the driver loads.

This assumes we won't ever want to run both the emmc2
and arasan sdhci controller at the same time.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
 .../Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c    |&n= bsp; 9 ++++-
 .../Bcm283x/Include/IndustryStandard/Bcm2836Sdio.h | 42 ++++++++++++-= ---------
 2 files changed, 32 insertions(+), 19 deletions(-)

diff --git a/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe= .c b/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c
index 88e9126e35..0cb7e85b38 100644
--- a/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c
+++ b/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c
@@ -16,6 +16,7 @@ STATIC CARD_DETECT_STATE mCardDetectState =3D CardDetectR= equired;
 UINT32 LastExecutedCommand =3D (UINT32) -1;

 

 STATIC RASPBERRY_PI_FIRMWARE_PROTOCOL *mFwProtocol;

+STATIC UINTN MMCHS_BASE;

 

 /**

    These SD commands are optional, according to the SD Spec=

@@ -763,7 +764,13 @@ MMCInitialize (
 

   DEBUG ((DEBUG_MMCHOST_SD, "ArasanMMCHost: MMCInitialize()= \n"));

 

-  if (!PcdGet32 (PcdSdIsArasan)) {

+  if (PcdGet32 (PcdSdIsArasan)) {

+    DEBUG ((DEBUG_INFO, "SD is routed to Arasan\n"= ;));

+    MMCHS_BASE =3D MMCHS1_BASE;

+  } else if (RPI_MODEL =3D=3D 4) {

+    DEBUG ((DEBUG_INFO, "SD is routed to emmc2\n"= ));

+    MMCHS_BASE =3D MMCHS2_BASE;

+  } else {

     DEBUG ((DEBUG_INFO, "SD is not routed to Aras= an\n"));

     return EFI_REQUEST_UNLOAD_IMAGE;

   }

diff --git a/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Sdio.= h b/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Sdio.h
index fd07b47170..e6892d36cf 100644
--- a/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Sdio.h
+++ b/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2836Sdio.h
@@ -13,15 +13,18 @@
 

 // MMC/SD/SDIO1 register definitions.

 #define MMCHS1_OFFSET     0x00300000

+#define MMCHS2_OFFSET     0x00340000

 #define MMCHS1_BASE       (BCM2836_SOC_= REGISTERS + MMCHS1_OFFSET)

+#define MMCHS2_BASE       (BCM2836_SOC_REGIS= TERS + MMCHS2_OFFSET)

 #define MMCHS1_LENGTH     0x00000100

+#define MMCHS2_LENGTH     0x00000100

 

-#define MMCHS_BLK         (MMCHS1_= BASE + 0x4)

+#define MMCHS_BLK         (MMCHS_B= ASE + 0x4)

 #define BLEN_512BYTES     (0x200UL << 0)
 

-#define MMCHS_ARG         (MMCHS1_= BASE + 0x8)

+#define MMCHS_ARG         (MMCHS_B= ASE + 0x8)

 

-#define MMCHS_CMD         (MMCHS1_= BASE + 0xC)

+#define MMCHS_CMD         (MMCHS_B= ASE + 0xC)

 #define BCE_ENABLE        BIT1

 #define DDIR_READ         BIT= 4

 #define DDIR_WRITE        (0x0UL &= lt;< 4)

@@ -43,13 +46,13 @@
 #define INDX(CMD_INDX)       (TYPE(CMD_= TYPE_NORMAL) | _INDX(CMD_INDX))

 #define INDX_ABORT(CMD_INDX) (TYPE(CMD_TYPE_ABORT) | _INDX(CMD_INDX))=

 

-#define MMCHS_RSP10       (MMCHS1_BASE + 0x1= 0)

-#define MMCHS_RSP32       (MMCHS1_BASE + 0x1= 4)

-#define MMCHS_RSP54       (MMCHS1_BASE + 0x1= 8)

-#define MMCHS_RSP76       (MMCHS1_BASE + 0x1= C)

-#define MMCHS_DATA        (MMCHS1_BASE = + 0x20)

+#define MMCHS_RSP10       (MMCHS_BASE + 0x10= )

+#define MMCHS_RSP32       (MMCHS_BASE + 0x14= )

+#define MMCHS_RSP54       (MMCHS_BASE + 0x18= )

+#define MMCHS_RSP76       (MMCHS_BASE + 0x1C= )

+#define MMCHS_DATA        (MMCHS_BASE += 0x20)

 

-#define MMCHS_PRES_STATE  (MMCHS1_BASE + 0x24)

+#define MMCHS_PRES_STATE  (MMCHS_BASE + 0x24)

 #define CMDI_MASK         BIT= 0

 #define CMDI_ALLOWED      (0x0UL << 0)=

 #define CMDI_NOT_ALLOWED  BIT0

@@ -58,17 +61,19 @@
 #define DATI_NOT_ALLOWED  BIT1

 #define WRITE_PROTECT_OFF BIT19

 

-#define MMCHS_HCTL        (MMCHS1_BASE = + 0x28)

+#define MMCHS_HCTL        (MMCHS_BASE += 0x28)

 #define DTW_1_BIT         (0x= 0UL << 1)

 #define DTW_4_BIT         BIT= 1

 #define SDBP_MASK         BIT= 8

 #define SDBP_OFF         = ; (0x0UL << 8)

 #define SDBP_ON         =   BIT8

+#define SDVS_MASK         (0x7UL &= lt;< 9)

 #define SDVS_1_8_V        (0x5UL &= lt;< 9)

 #define SDVS_3_0_V        (0x6UL &= lt;< 9)

+#define SDVS_3_3_V        (0x7UL <&l= t; 9)

 #define IWE         &nbs= p;     BIT24

 

-#define MMCHS_SYSCTL      (MMCHS1_BASE + 0x2C)
+#define MMCHS_SYSCTL      (MMCHS_BASE + 0x2C)

 #define ICE         &nbs= p;     BIT0

 #define ICS_MASK         = ; BIT1

 #define ICS         &nbs= p;     BIT1

@@ -84,7 +89,7 @@
 #define SRC         &nbs= p;     BIT25

 #define SRD         &nbs= p;     BIT26

 

-#define MMCHS_INT_STAT    (MMCHS1_BASE + 0x30)

+#define MMCHS_INT_STAT    (MMCHS_BASE + 0x30)

 #define CC          = ;      BIT0

 #define TC          = ;      BIT1

 #define BWR         &nbs= p;     BIT4

@@ -96,7 +101,7 @@
 #define DCRC         &nb= sp;    BIT21

 #define DEB         &nbs= p;     BIT22

 

-#define MMCHS_IE          (MM= CHS1_BASE + 0x34)

+#define MMCHS_IE          (MM= CHS_BASE + 0x34)

 #define CC_EN         &n= bsp;   BIT0

 #define TC_EN         &n= bsp;   BIT1

 #define BWR_EN         &= nbsp;  BIT4

@@ -112,7 +117,7 @@
 #define BADA_EN         =   BIT29

 #define ALL_EN         &= nbsp;  0xFFFFFFFF

 

-#define MMCHS_ISE         (MMCHS1_= BASE + 0x38)

+#define MMCHS_ISE         (MMCHS_B= ASE + 0x38)

 #define CC_SIGEN         = ; BIT0

 #define TC_SIGEN         = ; BIT1

 #define BWR_SIGEN         BIT= 4

@@ -127,14 +132,15 @@
 #define CERR_SIGEN        BIT28
 #define BADA_SIGEN        BIT29
 

-#define MMCHS_AC12        (MMCHS1_BASE = + 0x3C)

+#define MMCHS_AC12        (MMCHS_BASE += 0x3C)

+#define MMCHS_HC2R        (MMCHS_BASE += 0x3E)

 

-#define MMCHS_CAPA        (MMCHS1_BASE = + 0x40)

+#define MMCHS_CAPA        (MMCHS_BASE += 0x40)

 #define VS30         &nb= sp;    BIT25

 #define VS18         &nb= sp;    BIT26

 

-#define MMCHS_CUR_CAPA    (MMCHS1_BASE + 0x48)

-#define MMCHS_REV         (MMCHS1_= BASE + 0xFC)

+#define MMCHS_CUR_CAPA    (MMCHS_BASE + 0x48)

+#define MMCHS_REV         (MMCHS_B= ASE + 0xFC)

 

 #define BLOCK_COUNT_SHIFT 16

 #define RCA_SHIFT         16<= br>
--
2.13.7



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