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x-ms-exchange-antispam-messagedata: =?us-ascii?Q?m6wn/Q2emNa3xhoNZufEIWmEXnMOWV3NiNDv3M+PZ1sUFWosGCIaUxhqR64A?= =?us-ascii?Q?vr7HrDy5dxk3CLJDmjhtKX5jaRFtpto+2xa571glKK2XbpNfPYayPWkeGQUq?= =?us-ascii?Q?iphh0XGNOZEqgEC4nBAqUPY2XbihbJhFJ6Gof6dcHev2YrS6tBHWwYVvOBAK?= =?us-ascii?Q?0KaqcicYPCXdFy6Idbw2YMEZVKjgMHjkFk4yCDciBysrMWKphisJL/Q7BZwd?= =?us-ascii?Q?525OpR2tW4QD43aWDX6l9cQAVaUO1YIDVFK5OQUBUbAOkU+vJdx3swWUKOYQ?= =?us-ascii?Q?XCoV2CV2ZAlwNE9s9+DAUUynCS2VQw9HznrCVaMtuDmfg1Q/KXxZMCmFa/wJ?= =?us-ascii?Q?4RLoXEhq6RtXjBCniW7LYEZjobHKgYADUqQQSgHYrVDCqwGEkJ9/l74tbZma?= =?us-ascii?Q?UJjVP2tpoEnLfqF3/qYDF36lazf0lBDYBWYlrzyJdas2loqeUV1Ug1kv2c3W?= =?us-ascii?Q?3RcLtf308grt5JbohbeL0/uG2nCwWvFgVhKa0kRa+pb4FbM3m3BvcJXjcnPW?= =?us-ascii?Q?w7RJng4gGS2frrDMbCp7N+PF2SxSO+NtmLmI0QccSRDs3PrCGh2LqUiseMEO?= =?us-ascii?Q?iZbSd8CF9Bxsp7xXq41CW3tg7EYiOAGwqOLB0Fv22rQYUlDo24IA/NoymMLD?= =?us-ascii?Q?NVvGr+CSZZ1WQE/rC8JoPhxInHIVDIR3c8R32Nsrqw7LQ9/BgJUnuWjB8Z5Z?= =?us-ascii?Q?x7+MN/s/S9HLSAWe+epb0rZ9hydPwNKwE+Ju426Oi1fPE7FXAgv5STvOY6hT?= =?us-ascii?Q?AMjtaw5xpN3hiiZC0L+qlBVfh86RVLYX4njU54wQfgwoTVljdOhS5DsrvVF0?= =?us-ascii?Q?8Tim1dzIQ5s0qU/YIUs6nmxj/VMdIna+LtsN+csTj6/4pDR7D34q+Qd1vTlo?= =?us-ascii?Q?srvkVCCkMR0VsRYIfMC589e1h3Ygk8WtEd6feYS/roC/r9sWyXmKCludFhei?= =?us-ascii?Q?XTTFL7aEijhbBnTM+caJc6rHB07cnnXRWVUrf4S13fE=3D?= x-ms-exchange-transport-forked: True MIME-Version: 1.0 X-OriginatorOrg: vmware.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SJ0PR05MB7580.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 154d3517-cb7b-4d9d-bce8-08d8a126e0f4 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Dec 2020 18:26:02.7282 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b39138ca-3cee-4b4a-a4d6-cd83d9dd62f0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: C86X2cbPUIAumAe42t3lRy5JhE16sT/o3/fmM1EdeX2xD750aNzJmUsJj/qgOn/ErYRkFInZNMcgjcin/tgURw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR05MB6771 Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_SJ0PR05MB7580764A0287E5449F19B83DB9C60SJ0PR05MB7580namp_" --_000_SJ0PR05MB7580764A0287E5449F19B83DB9C60SJ0PR05MB7580namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable I believe that applies only to the Arasan integration, not MMC2. I'm trying to recollect why I thought this didn't matter (or how it was ge= tting mitigated), but i'm drawing a blank. I'm okay doing it. Reviewed-by: Andrei Warkentin ________________________________ From: devel@edk2.groups.io on behalf of Jeremy Linto= n via groups.io Sent: Monday, December 14, 2020 5:23 PM To: devel@edk2.groups.io Cc: ard.biesheuvel@arm.com ; leif@nuviainc.com ; pete@akeo.ie ; andrey.warkentin@gmail.com ; samer.el-haj-mahmoud@arm.com ; Jeremy Linton Subject: [edk2-devel] [PATCH 4/7] Platform/RaspberryPi/Arasan: Add write de= lay and voltage/clock config The uboot and linux drivers have notes that there is a clock domain crossin= g problem that happens with back to back writes to the sd controllers on the rpi. Its not clear if this is still applicable to the rpi4/emmc2 but it seems wise to add it. Futher, we need to assure that the card voltage is set to 3.3V, and we should try and follow some of the SDHCI docs when it comes to changing the clock. Signed-off-by: Jeremy Linton --- .../Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c | 112 +++++++++++++++++= ---- .../Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.h | 1 + 2 files changed, 93 insertions(+), 20 deletions(-) diff --git a/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe= .c b/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c index 0cb7e85b38..a7b538a91a 100644 --- a/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c +++ b/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c @@ -18,6 +18,56 @@ UINT32 LastExecutedCommand =3D (UINT32) -1; STATIC RASPBERRY_PI_FIRMWARE_PROTOCOL *mFwProtocol; STATIC UINTN MMCHS_BASE; +STATIC +UINT32 +EFIAPI +SdMmioWrite32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + UINT32 ret; + ret =3D (UINT32)MmioWrite32 (Address, Value); + // There is a bug about clock domain crossing on writes, delay to avoid = it + gBS->Stall (STALL_AFTER_REG_WRITE_US); + return ret; +} + +STATIC +UINT32 +EFIAPI +SdMmioOr32 ( + IN UINTN Address, + IN UINT32 OrData + ) +{ + return SdMmioWrite32 (Address, MmioRead32 (Address) | OrData); +} + +STATIC +UINT32 +EFIAPI +SdMmioAnd32 ( + IN UINTN Address, + IN UINT32 AndData + ) +{ + return SdMmioWrite32 (Address, MmioRead32 (Address) & AndData); +} + +STATIC +UINT32 +EFIAPI +SdMmioAndThenOr32 ( + IN UINTN Address, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return SdMmioWrite32 (Address, (MmioRead32 (Address) & AndData) | OrData= ); +} + + /** These SD commands are optional, according to the SD Spec **/ @@ -175,7 +225,9 @@ SoftReset ( IN UINT32 Mask ) { - MmioOr32 (MMCHS_SYSCTL, Mask); + DEBUG ((DEBUG_MMCHOST_SD, "SoftReset with mask 0x%x\n", Mask)); + + SdMmioOr32 (MMCHS_SYSCTL, Mask); if (PollRegisterWithMask (MMCHS_SYSCTL, Mask, 0) =3D=3D EFI_TIMEOUT) { DEBUG ((DEBUG_ERROR, "Failed to SoftReset with mask 0x%x\n", Mask)); return EFI_TIMEOUT; @@ -326,29 +378,29 @@ MMCSendCommand ( } if (IsAppCmd && MmcCmd =3D=3D ACMD22) { - MmioWrite32 (MMCHS_BLK, 4); + SdMmioWrite32 (MMCHS_BLK, 4); } else if (IsAppCmd && MmcCmd =3D=3D ACMD51) { - MmioWrite32 (MMCHS_BLK, 8); + SdMmioWrite32 (MMCHS_BLK, 8); } else if (!IsAppCmd && MmcCmd =3D=3D CMD6) { - MmioWrite32 (MMCHS_BLK, 64); + SdMmioWrite32 (MMCHS_BLK, 64); } else if (IsADTCCmd) { - MmioWrite32 (MMCHS_BLK, BLEN_512BYTES); + SdMmioWrite32 (MMCHS_BLK, BLEN_512BYTES); } // Set Data timeout counter value to max value. - MmioAndThenOr32 (MMCHS_SYSCTL, (UINT32) ~DTO_MASK, DTO_VAL); + SdMmioAndThenOr32 (MMCHS_SYSCTL, (UINT32) ~DTO_MASK, DTO_VAL); // // Clear Interrupt Status Register, but not the Card Inserted bit // to avoid messing with card detection logic. // - MmioWrite32 (MMCHS_INT_STAT, ALL_EN & ~(CARD_INS)); + SdMmioWrite32 (MMCHS_INT_STAT, ALL_EN & ~(CARD_INS)); // Set command argument register - MmioWrite32 (MMCHS_ARG, Argument); + SdMmioWrite32 (MMCHS_ARG, Argument); // Send the command - MmioWrite32 (MMCHS_CMD, MmcCmd); + SdMmioWrite32 (MMCHS_CMD, MmcCmd); // Check for the command status. while (RetryCount < MAX_RETRY_COUNT) { @@ -373,7 +425,7 @@ MMCSendCommand ( // Check if command is completed. if ((MmcStatus & CC) =3D=3D CC) { - MmioWrite32 (MMCHS_INT_STAT, CC); + SdMmioWrite32 (MMCHS_INT_STAT, CC); break; } @@ -428,6 +480,21 @@ MMCNotifyState ( return Status; } + DEBUG ((DEBUG_MMCHOST_SD, "ArasanMMCHost: CAP %X CAPH %X\n", MmioRea= d32(MMCHS_CAPA),MmioRead32(MMCHS_CUR_CAPA))); + + // Lets switch to card detect test mode. + SdMmioOr32 (MMCHS_HCTL, BIT7|BIT6); + + // set card voltage + SdMmioAnd32 (MMCHS_HCTL, ~SDBP_ON); + SdMmioAndThenOr32 (MMCHS_HCTL, (UINT32) ~SDBP_MASK, SDVS_3_3_V); + SdMmioOr32 (MMCHS_HCTL, SDBP_ON); + + DEBUG ((DEBUG_MMCHOST_SD, "ArasanMMCHost: AC12 %X HCTL %X\n", MmioRe= ad32(MMCHS_AC12),MmioRead32(MMCHS_HCTL))); + + // First turn off the clock + SdMmioAnd32 (MMCHS_SYSCTL, ~CEN); + // Attempt to set the clock to 400Khz which is the expected initiali= zation speed Status =3D CalculateClockFrequencyDivisor (400000, &Divisor, NULL); if (EFI_ERROR (Status)) { @@ -436,10 +503,15 @@ MMCNotifyState ( } // Set Data Timeout Counter value, set clock frequency, enable inter= nal clock - MmioOr32 (MMCHS_SYSCTL, DTO_VAL | Divisor | CEN | ICS | ICE); + SdMmioOr32 (MMCHS_SYSCTL, DTO_VAL | Divisor | CEN | ICS | ICE); + SdMmioOr32 (MMCHS_HCTL, SDBP_ON); + // wait for ICS + while ((MmioRead32 (MMCHS_SYSCTL) & ICS_MASK) !=3D ICS); + + DEBUG ((DEBUG_MMCHOST_SD, "ArasanMMCHost: AC12 %X HCTL %X\n", MmioRe= ad32(MMCHS_AC12),MmioRead32(MMCHS_HCTL))); // Enable interrupts - MmioWrite32 (MMCHS_IE, ALL_EN); + SdMmioWrite32 (MMCHS_IE, ALL_EN); } break; case MmcIdleState: @@ -452,7 +524,7 @@ MMCNotifyState ( ClockFrequency =3D 25000000; // First turn off the clock - MmioAnd32 (MMCHS_SYSCTL, ~CEN); + SdMmioAnd32 (MMCHS_SYSCTL, ~CEN); Status =3D CalculateClockFrequencyDivisor (ClockFrequency, &Divisor, N= ULL); if (EFI_ERROR (Status)) { @@ -462,13 +534,13 @@ MMCNotifyState ( } // Setup new divisor - MmioAndThenOr32 (MMCHS_SYSCTL, (UINT32) ~CLKD_MASK, Divisor); + SdMmioAndThenOr32 (MMCHS_SYSCTL, (UINT32) ~CLKD_MASK, Divisor); // Wait for the clock to stabilise while ((MmioRead32 (MMCHS_SYSCTL) & ICS_MASK) !=3D ICS); // Set Data Timeout Counter value, set clock frequency, enable interna= l clock - MmioOr32 (MMCHS_SYSCTL, CEN); + SdMmioOr32 (MMCHS_SYSCTL, CEN); break; case MmcTransferState: break; @@ -635,7 +707,7 @@ MMCReadBlockData ( while (RetryCount < MAX_RETRY_COUNT) { MmcStatus =3D MmioRead32 (MMCHS_INT_STAT); if ((MmcStatus & BRR) !=3D 0) { - MmioWrite32 (MMCHS_INT_STAT, BRR); + SdMmioWrite32 (MMCHS_INT_STAT, BRR); /* * Data is ready. */ @@ -662,7 +734,7 @@ MMCReadBlockData ( gBS->Stall (STALL_AFTER_READ_US); } - MmioWrite32 (MMCHS_INT_STAT, BRR); + SdMmioWrite32 (MMCHS_INT_STAT, BRR); return EFI_SUCCESS; } @@ -699,13 +771,13 @@ MMCWriteBlockData ( while (RetryCount < MAX_RETRY_COUNT) { MmcStatus =3D MmioRead32 (MMCHS_INT_STAT); if ((MmcStatus & BWR) !=3D 0) { - MmioWrite32 (MMCHS_INT_STAT, BWR); + SdMmioWrite32 (MMCHS_INT_STAT, BWR); /* * Can write data. */ mFwProtocol->SetLed (TRUE); for (Count =3D 0; Count < BlockLen; Count +=3D 4, Buffer++) { - MmioWrite32 (MMCHS_DATA, *Buffer); + SdMmioWrite32 (MMCHS_DATA, *Buffer); } mFwProtocol->SetLed (FALSE); @@ -726,7 +798,7 @@ MMCWriteBlockData ( gBS->Stall (STALL_AFTER_WRITE_US); } - MmioWrite32 (MMCHS_INT_STAT, BWR); + SdMmioWrite32 (MMCHS_INT_STAT, BWR); return EFI_SUCCESS; } diff --git a/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe= .h b/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.h index 6cd600f738..e94606cc5b 100644 --- a/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.h +++ b/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.h @@ -37,6 +37,7 @@ #define STALL_AFTER_REC_RESP_US (50) #define STALL_AFTER_WRITE_US (200) #define STALL_AFTER_READ_US (20) +#define STALL_AFTER_REG_WRITE_US (10) #define STALL_AFTER_RETRY_US (20) #define MAX_DIVISOR_VALUE 1023 -- 2.13.7 -=3D-=3D-=3D-=3D-=3D-=3D Groups.io Links: You receive all messages sent to this group. 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I believe that applies only to the Arasan integration, not MMC2.

I'm trying to recollect why I thought this didn't matter  (or how it w= as getting mitigated), but i'm drawing a blank. I'm okay doing it.

Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
From: devel@edk2.groups.io = <devel@edk2.groups.io> on behalf of Jeremy Linton via groups.io <j= eremy.linton=3Darm.com@groups.io>
Sent: Monday, December 14, 2020 5:23 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: ard.biesheuvel@arm.com <ard.biesheuvel@arm.com>; leif@nuvi= ainc.com <leif@nuviainc.com>; pete@akeo.ie <pete@akeo.ie>; andr= ey.warkentin@gmail.com <andrey.warkentin@gmail.com>; samer.el-haj-mah= moud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com>
Subject: [edk2-devel] [PATCH 4/7] Platform/RaspberryPi/Arasan: Add w= rite delay and voltage/clock config
 
The uboot and linux drivers have notes that there = is a clock domain crossing
problem that happens with back to back writes to the sd controllers on the<= br> rpi. Its not clear if this is still applicable to the rpi4/emmc2 but
it seems wise to add it.

Futher, we need to assure that the card voltage is set to 3.3V, and
we should try and follow some of the SDHCI docs when it comes to
changing the clock.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
 .../Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c    | 1= 12 +++++++++++++++++----
 .../Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.h    |&n= bsp;  1 +
 2 files changed, 93 insertions(+), 20 deletions(-)

diff --git a/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe= .c b/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c
index 0cb7e85b38..a7b538a91a 100644
--- a/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c
+++ b/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.c
@@ -18,6 +18,56 @@ UINT32 LastExecutedCommand =3D (UINT32) -1;
 STATIC RASPBERRY_PI_FIRMWARE_PROTOCOL *mFwProtocol;

 STATIC UINTN MMCHS_BASE;

 

+STATIC

+UINT32

+EFIAPI

+SdMmioWrite32 (

+  IN      UINTN     = ;            &n= bsp;   Address,

+  IN      UINT32    &nbs= p;            &= nbsp;  Value

+  )

+{

+  UINT32 ret;

+  ret =3D (UINT32)MmioWrite32 (Address, Value);

+  // There is a bug about clock domain crossing on writes, delay to a= void it

+  gBS->Stall (STALL_AFTER_REG_WRITE_US);

+  return ret;

+}

+

+STATIC

+UINT32

+EFIAPI

+SdMmioOr32 (

+  IN      UINTN     = ;            &n= bsp;   Address,

+  IN      UINT32    &nbs= p;            &= nbsp;  OrData

+  )

+{

+  return SdMmioWrite32 (Address, MmioRead32 (Address) | OrData);

+}

+

+STATIC

+UINT32

+EFIAPI

+SdMmioAnd32 (

+  IN      UINTN     = ;            &n= bsp;   Address,

+  IN      UINT32    &nbs= p;            &= nbsp;  AndData

+  )

+{

+  return SdMmioWrite32 (Address, MmioRead32 (Address) & AndData);=

+}

+

+STATIC

+UINT32

+EFIAPI

+SdMmioAndThenOr32 (

+  IN      UINTN     = ;            &n= bsp;   Address,

+  IN      UINT32    &nbs= p;            &= nbsp;  AndData,

+  IN      UINT32    &nbs= p;            &= nbsp;  OrData

+  )

+{

+  return SdMmioWrite32 (Address, (MmioRead32 (Address) & AndData)= | OrData);

+}

+

+

 /**

    These SD commands are optional, according to the SD Spec=

 **/

@@ -175,7 +225,9 @@ SoftReset (
   IN UINT32 Mask

   )

 {

-  MmioOr32 (MMCHS_SYSCTL, Mask);

+  DEBUG ((DEBUG_MMCHOST_SD, "SoftReset with mask 0x%x\n", M= ask));

+

+  SdMmioOr32 (MMCHS_SYSCTL, Mask);

   if (PollRegisterWithMask (MMCHS_SYSCTL, Mask, 0) =3D=3D EFI_TI= MEOUT) {

     DEBUG ((DEBUG_ERROR, "Failed to SoftReset wit= h mask 0x%x\n", Mask));

     return EFI_TIMEOUT;

@@ -326,29 +378,29 @@ MMCSendCommand (
   }

 

   if (IsAppCmd && MmcCmd =3D=3D ACMD22) {

-    MmioWrite32 (MMCHS_BLK, 4);

+    SdMmioWrite32 (MMCHS_BLK, 4);

   } else if (IsAppCmd && MmcCmd =3D=3D ACMD51) {

-    MmioWrite32 (MMCHS_BLK, 8);

+    SdMmioWrite32 (MMCHS_BLK, 8);

   } else if (!IsAppCmd && MmcCmd =3D=3D CMD6) {

-    MmioWrite32 (MMCHS_BLK, 64);

+    SdMmioWrite32 (MMCHS_BLK, 64);

   } else if (IsADTCCmd) {

-    MmioWrite32 (MMCHS_BLK, BLEN_512BYTES);

+    SdMmioWrite32 (MMCHS_BLK, BLEN_512BYTES);

   }

 

   // Set Data timeout counter value to max value.

-  MmioAndThenOr32 (MMCHS_SYSCTL, (UINT32) ~DTO_MASK, DTO_VAL);

+  SdMmioAndThenOr32 (MMCHS_SYSCTL, (UINT32) ~DTO_MASK, DTO_VAL);

 

   //

   // Clear Interrupt Status Register, but not the Card Inserted = bit

   // to avoid messing with card detection logic.

   //

-  MmioWrite32 (MMCHS_INT_STAT, ALL_EN & ~(CARD_INS));

+  SdMmioWrite32 (MMCHS_INT_STAT, ALL_EN & ~(CARD_INS));

 

   // Set command argument register

-  MmioWrite32 (MMCHS_ARG, Argument);

+  SdMmioWrite32 (MMCHS_ARG, Argument);

 

   // Send the command

-  MmioWrite32 (MMCHS_CMD, MmcCmd);

+  SdMmioWrite32 (MMCHS_CMD, MmcCmd);

 

   // Check for the command status.

   while (RetryCount < MAX_RETRY_COUNT) {

@@ -373,7 +425,7 @@ MMCSendCommand (
 

     // Check if command is completed.

     if ((MmcStatus & CC) =3D=3D CC) {

-      MmioWrite32 (MMCHS_INT_STAT, CC);

+      SdMmioWrite32 (MMCHS_INT_STAT, CC);

       break;

     }

 

@@ -428,6 +480,21 @@ MMCNotifyState (
         return Status;

       }

 

+      DEBUG ((DEBUG_MMCHOST_SD, "ArasanMMCHo= st: CAP %X CAPH %X\n", MmioRead32(MMCHS_CAPA),MmioRead32(MMCHS_CUR_CAP= A)));

+

+      // Lets switch to card detect test mode.
+      SdMmioOr32 (MMCHS_HCTL, BIT7|BIT6);

+

+      // set card voltage

+      SdMmioAnd32 (MMCHS_HCTL, ~SDBP_ON);

+      SdMmioAndThenOr32 (MMCHS_HCTL, (UINT32) ~SD= BP_MASK, SDVS_3_3_V);

+      SdMmioOr32 (MMCHS_HCTL, SDBP_ON);

+

+      DEBUG ((DEBUG_MMCHOST_SD, "ArasanMMCHo= st: AC12 %X HCTL %X\n", MmioRead32(MMCHS_AC12),MmioRead32(MMCHS_HCTL))= );

+

+      // First turn off the clock

+      SdMmioAnd32 (MMCHS_SYSCTL, ~CEN);

+

       // Attempt to set the clock to 400Khz = which is the expected initialization speed

       Status =3D CalculateClockFrequencyDivi= sor (400000, &Divisor, NULL);

       if (EFI_ERROR (Status)) {

@@ -436,10 +503,15 @@ MMCNotifyState (
       }

 

       // Set Data Timeout Counter value, set= clock frequency, enable internal clock

-      MmioOr32 (MMCHS_SYSCTL, DTO_VAL | Divisor |= CEN | ICS | ICE);

+      SdMmioOr32 (MMCHS_SYSCTL, DTO_VAL | Divisor= | CEN | ICS | ICE);

+      SdMmioOr32 (MMCHS_HCTL, SDBP_ON);

+      // wait for ICS

+      while ((MmioRead32 (MMCHS_SYSCTL) & ICS= _MASK) !=3D ICS);

+

+      DEBUG ((DEBUG_MMCHOST_SD, "ArasanMMCHo= st: AC12 %X HCTL %X\n", MmioRead32(MMCHS_AC12),MmioRead32(MMCHS_HCTL))= );

 

       // Enable interrupts

-      MmioWrite32 (MMCHS_IE, ALL_EN);

+      SdMmioWrite32 (MMCHS_IE, ALL_EN);

     }

     break;

   case MmcIdleState:

@@ -452,7 +524,7 @@ MMCNotifyState (
     ClockFrequency =3D 25000000;

 

     // First turn off the clock

-    MmioAnd32 (MMCHS_SYSCTL, ~CEN);

+    SdMmioAnd32 (MMCHS_SYSCTL, ~CEN);

 

     Status =3D CalculateClockFrequencyDivisor (ClockFr= equency, &Divisor, NULL);

     if (EFI_ERROR (Status)) {

@@ -462,13 +534,13 @@ MMCNotifyState (
     }

 

     // Setup new divisor

-    MmioAndThenOr32 (MMCHS_SYSCTL, (UINT32) ~CLKD_MASK, Div= isor);

+    SdMmioAndThenOr32 (MMCHS_SYSCTL, (UINT32) ~CLKD_MASK, D= ivisor);

 

     // Wait for the clock to stabilise

     while ((MmioRead32 (MMCHS_SYSCTL) & ICS_MASK) = !=3D ICS);

 

     // Set Data Timeout Counter value, set clock frequ= ency, enable internal clock

-    MmioOr32 (MMCHS_SYSCTL, CEN);

+    SdMmioOr32 (MMCHS_SYSCTL, CEN);

     break;

   case MmcTransferState:

     break;

@@ -635,7 +707,7 @@ MMCReadBlockData (
     while (RetryCount < MAX_RETRY_COUNT) {

       MmcStatus =3D MmioRead32 (MMCHS_INT_ST= AT);

       if ((MmcStatus & BRR) !=3D 0) {
-        MmioWrite32 (MMCHS_INT_STAT, BR= R);

+        SdMmioWrite32 (MMCHS_INT_STAT, = BRR);

         /*

          * Data is ready.

          */

@@ -662,7 +734,7 @@ MMCReadBlockData (
     gBS->Stall (STALL_AFTER_READ_US);

   }

 

-  MmioWrite32 (MMCHS_INT_STAT, BRR);

+  SdMmioWrite32 (MMCHS_INT_STAT, BRR);

   return EFI_SUCCESS;

 }

 

@@ -699,13 +771,13 @@ MMCWriteBlockData (
     while (RetryCount < MAX_RETRY_COUNT) {

       MmcStatus =3D MmioRead32 (MMCHS_INT_ST= AT);

       if ((MmcStatus & BWR) !=3D 0) {
-        MmioWrite32 (MMCHS_INT_STAT, BW= R);

+        SdMmioWrite32 (MMCHS_INT_STAT, = BWR);

         /*

          * Can write data.
          */

         mFwProtocol->SetLed (TR= UE);

         for (Count =3D 0; Count &l= t; BlockLen; Count +=3D 4, Buffer++) {

-          MmioWrite32 (MMCHS_= DATA, *Buffer);

+          SdMmioWrite32 (MMCH= S_DATA, *Buffer);

         }

 

         mFwProtocol->SetLed (FA= LSE);

@@ -726,7 +798,7 @@ MMCWriteBlockData (
     gBS->Stall (STALL_AFTER_WRITE_US);

   }

 

-  MmioWrite32 (MMCHS_INT_STAT, BWR);

+  SdMmioWrite32 (MMCHS_INT_STAT, BWR);

   return EFI_SUCCESS;

 }

 

diff --git a/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe= .h b/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.h
index 6cd600f738..e94606cc5b 100644
--- a/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.h
+++ b/Platform/RaspberryPi/Drivers/ArasanMmcHostDxe/ArasanMmcHostDxe.h
@@ -37,6 +37,7 @@
 #define STALL_AFTER_REC_RESP_US (50)

 #define STALL_AFTER_WRITE_US (200)

 #define STALL_AFTER_READ_US (20)

+#define STALL_AFTER_REG_WRITE_US (10)

 #define STALL_AFTER_RETRY_US (20)

 

 #define MAX_DIVISOR_VALUE 1023

--
2.13.7



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