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Thread-Topic: [Patch V4] UefiCpuPkg/MpInitLib: Enable execute disable bit. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,yuanhao.xie@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: dTQnqHpY2AHR2g7IYd6ARvh8x7686176AA= Content-Language: en-US Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=JtRa2Fl1; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}"); dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Hi Gerd, In v4 , InterlockedIncrement called is after RestoreVolatileRegisters to en= sure that "finished" reporting from the APs is as later as possible. Here is V3=1B$B!'=1B(B GetProcessorNumber (CpuMpData, &ProcessorNumber); - RestoreVolatileRegisters (&CpuMpData->CpuData[0].VolatileRegisters, FALS= E); InterlockedIncrement ((UINT32 *)&CpuMpData->FinishedCount); + + if (CpuMpData->EnableExecuteDisableForSwitchContext) { + EferMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_EFER); + EferMsr.Bits.NXE =3D 1; + AsmWriteMsr64 (MSR_IA32_EFER, EferMsr.Uint64); + } + + RestoreVolatileRegisters (&CpuMpData->CpuData[0].VolatileRegisters, FALS= E); Regards, Yuanhao -----Original Message----- From: Gerd Hoffmann =20 Sent: Monday, November 13, 2023 6:54 PM To: Xie, Yuanhao Cc: devel@edk2.groups.io; Dong, Eric ; Ni, Ray ; Kumar, Rahul R Subject: Re: [Patch V4] UefiCpuPkg/MpInitLib: Enable execute disable bit. > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c=20 > b/UefiCpuPkg/Library/MpInitLib/MpLib.c > index 9a6ec5db5c..f29e66a14f 100644 > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c > @@ -910,9 +910,16 @@ DxeApEntryPoint ( > CPU_MP_DATA *CpuMpData > ) > { > - UINTN ProcessorNumber; > + UINTN ProcessorNumber; > + MSR_IA32_EFER_REGISTER EferMsr; > =20 > GetProcessorNumber (CpuMpData, &ProcessorNumber); > + if (CpuMpData->EnableExecuteDisableForSwitchContext) { > + EferMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_EFER); > + EferMsr.Bits.NXE =3D 1; > + AsmWriteMsr64 (MSR_IA32_EFER, EferMsr.Uint64); } It helps reviewers if you document changes from one version to the next. This code block was moved (compared to v3). Why? take care, Gerd -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#111141): https://edk2.groups.io/g/devel/message/111141 Mute This Topic: https://groups.io/mt/102556608/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-