* [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0 @ 2021-07-22 11:46 Digant H Solanki 2021-07-23 13:55 ` Digant H Solanki 2021-07-28 17:47 ` Chaganty, Rangasai V 0 siblings, 2 replies; 6+ messages in thread From: Digant H Solanki @ 2021-07-22 11:46 UTC (permalink / raw) To: devel; +Cc: Digant H Solanki, Ray Ni, Rangasai V Chaganty, Ashraf Ali S REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3426 - There are many OpRegion fields obsoleted in MBOX1 - MBOX2 is re-purposed for Backlight related fields for dual LFP. - Backlight related fields moved to MBOX2 from MBOX3 and some fields are obsoleted in MBOX3. Signed-off-by: Digant H Solanki <digant.h.solanki@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> --- Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h | 101 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h new file mode 100644 index 0000000000..c9948ab55f --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h @@ -0,0 +1,101 @@ +/** @file + IGD OpRegion definition from Intel Integrated Graphics Device OpRegion + Specification based on version 3.0. + + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _IGD_OPREGION_3_0_H_ +#define _IGD_OPREGION_3_0_H_ + +#include "IgdOpRegion.h" + +#define IGD_OPREGION_HEADER_MBOX2_VER_3_0 BIT5 + +#pragma pack(1) +/// +/// OpRegion Mailbox 1 - Public ACPI Methods +/// Offset 0x100, Size 0x100 +/// +typedef struct { + UINT32 DRDY; ///< Offset 0x100 Driver Readiness + UINT32 CSTS; ///< Offset 0x104 Status + UINT32 CEVT; ///< Offset 0x108 Current Event + UINT8 RM11[0x14]; ///< Offset 0x10C Reserved Must be Zero + UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List + UINT32 CPDL[8]; ///< Offset 0x140 obsolete + UINT32 CADL[8]; ///< Offset 0x160 obsolete + UINT32 NADL[8]; ///< Offset 0x180 obsolete + UINT32 ASLP; ///< Offset 0x1A0 ASL Sleep Time Out + UINT32 TIDX; ///< Offset 0x1A4 obsolete + UINT32 CHPD; ///< Offset 0x1A8 obsolete + UINT32 CLID; ///< Offset 0x1AC Current Lid State Indicator + UINT32 CDCK; ///< Offset 0x1B0 Current Docking State Indicator + UINT32 SXSW; ///< Offset 0x1B4 obsolete + UINT32 EVTS; ///< Offset 0x1B8 obsolete + UINT32 CNOT; ///< Offset 0x1BC obsolete + UINT32 NRDY; ///< Offset 0x1C0 Driver Status + UINT8 DID2[0x1C]; ///< Offset 0x1C4 Extended Supported Devices ID List (DOD) + UINT8 CPD2[0x1C]; ///< Offset 0x1E0 obsolete + UINT8 RM12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero +} IGD_OPREGION_MBOX1_VER_3_0; + +/// +/// OpRegion Mailbox 2 - Backlight communication +/// Offset 0x200, Size 0x100 +/// +typedef struct { + UINT32 BCL1; ///< Offset 0x200 Backlight Brightness for LFP1 + UINT32 BCL2; ///< Offset 0x204 Backlight Brightness for LFP2 + UINT32 CBL1; ///< Offset 0x208 Current User Brightness Level for LFP1 + UINT32 CBL2; ///< Offset 0x20C Current User Brightness Level for LFP2 + UINT32 BCM1[0x1E]; ///< Offset 0x210 Backlight Brightness Levels Duty Cycle Mapping Table for LFP1 + UINT32 BCM2[0x1E]; ///< Offset 0x288 Backlight Brightness Levels Duty Cycle Mapping Table for LFP2 +} IGD_OPREGION_MBOX2_VER_3_0; + +/// +/// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support +/// Offset 0x300, Size 0x100 +/// +typedef struct { + UINT32 ARDY; ///< Offset 0x300 obsolete + UINT32 ASLC; ///< Offset 0x304 obsolete + UINT32 TCHE; ///< Offset 0x308 obsolete + UINT32 ALSI; ///< Offset 0x30C obsolete + UINT32 BCLP; ///< Offset 0x310 obsoleted in ver 3.0, moved to Mailbox 2. + UINT32 PFIT; ///< Offset 0x314 obsolete + UINT32 CBLV; ///< Offset 0x318 obsoleted in ver 3.0, moved to Mailbox 2. + UINT16 BCLM[0x14]; ///< Offset 0x31C obsoleted in ver 3.0, moved to Mailbox 2. + UINT32 CPFM; ///< Offset 0x344 obsolete + UINT32 EPFM; ///< Offset 0x348 obsolete + UINT8 PLUT[0x4A]; ///< Offset 0x34C obsolete + UINT32 PFMB; ///< Offset 0x396 obsolete + UINT32 CCDV; ///< Offset 0x39A obsolete + UINT32 PCFT; ///< Offset 0x39E obsolete + UINT32 SROT; ///< Offset 0x3A2 obsolete + UINT32 IUER; ///< Offset 0x3A6 obsolete + UINT64 FDSS; ///< Offset 0x3AA obsolete + UINT32 FDSP; ///< Offset 0x3B2 obsolete + UINT32 STAT; ///< Offset 0x3B6 obsolete + UINT64 RVDA; ///< Offset 0x3BA Physical address of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB. + UINT32 RVDS; ///< Offset 0x3C2 Size of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB. + UINT8 VRSR; ///< Offset 0x3C6 Video RAM Self Refresh + UINT64 DLHP; ///< Offset 0x3C7 Dual LFP Hinge Alignment Parameters + UINT8 RM32[0x31]; ///< Offset 0x3CF - 0x3FF Reserved Must be zero. +} IGD_OPREGION_MBOX3_VER_3_0; + +/// +/// IGD OpRegion Structure +/// +typedef struct { + IGD_OPREGION_HEADER Header; ///< OpRegion header (Offset 0x0, Size 0x100) + IGD_OPREGION_MBOX1_VER_3_0 MBox1; ///< Mailbox 1: Public ACPI Methods (Offset 0x100, Size 0x100) + IGD_OPREGION_MBOX2_VER_3_0 MBox2; ///< Mailbox 2: Backlight communication (Offset 0x200, Size 0x100) + IGD_OPREGION_MBOX3_VER_3_0 MBox3; ///< Mailbox 3: BIOS to Driver Notification (Offset 0x300, Size 0x100) + IGD_OPREGION_MBOX4 MBox4; ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1800) + IGD_OPREGION_MBOX5 MBox5; ///< Mailbox 5: BIOS to Driver Notification Extension (Offset 0x1C00, Size 0x400) +} IGD_OPREGION_STRUCTURE_VER_3_0; +#pragma pack() + +#endif -- 2.30.2.windows.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0 2021-07-22 11:46 [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0 Digant H Solanki @ 2021-07-23 13:55 ` Digant H Solanki 2021-07-28 6:44 ` Digant H Solanki 2021-07-28 17:47 ` Chaganty, Rangasai V 1 sibling, 1 reply; 6+ messages in thread From: Digant H Solanki @ 2021-07-23 13:55 UTC (permalink / raw) To: devel@edk2.groups.io; +Cc: Ni, Ray, Chaganty, Rangasai V, S, Ashraf Ali Gentle reminder to review this patch pls. Thanks..!! -----Original Message----- From: Solanki, Digant H <digant.h.solanki@intel.com> Sent: Thursday, July 22, 2021 5:17 PM To: devel@edk2.groups.io Cc: Solanki, Digant H <digant.h.solanki@intel.com>; Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; S, Ashraf Ali <ashraf.ali.s@intel.com> Subject: [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0 REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3426 - There are many OpRegion fields obsoleted in MBOX1 - MBOX2 is re-purposed for Backlight related fields for dual LFP. - Backlight related fields moved to MBOX2 from MBOX3 and some fields are obsoleted in MBOX3. Signed-off-by: Digant H Solanki <digant.h.solanki@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> --- Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h | 101 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h new file mode 100644 index 0000000000..c9948ab55f --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion +++ 30.h @@ -0,0 +1,101 @@ +/** @file + IGD OpRegion definition from Intel Integrated Graphics Device +OpRegion + Specification based on version 3.0. + + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _IGD_OPREGION_3_0_H_ +#define _IGD_OPREGION_3_0_H_ + +#include "IgdOpRegion.h" + +#define IGD_OPREGION_HEADER_MBOX2_VER_3_0 BIT5 + +#pragma pack(1) +/// +/// OpRegion Mailbox 1 - Public ACPI Methods /// Offset 0x100, Size +0x100 /// typedef struct { + UINT32 DRDY; ///< Offset 0x100 Driver Readiness + UINT32 CSTS; ///< Offset 0x104 Status + UINT32 CEVT; ///< Offset 0x108 Current Event + UINT8 RM11[0x14]; ///< Offset 0x10C Reserved Must be Zero + UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List + UINT32 CPDL[8]; ///< Offset 0x140 obsolete + UINT32 CADL[8]; ///< Offset 0x160 obsolete + UINT32 NADL[8]; ///< Offset 0x180 obsolete + UINT32 ASLP; ///< Offset 0x1A0 ASL Sleep Time Out + UINT32 TIDX; ///< Offset 0x1A4 obsolete + UINT32 CHPD; ///< Offset 0x1A8 obsolete + UINT32 CLID; ///< Offset 0x1AC Current Lid State Indicator + UINT32 CDCK; ///< Offset 0x1B0 Current Docking State Indicator + UINT32 SXSW; ///< Offset 0x1B4 obsolete + UINT32 EVTS; ///< Offset 0x1B8 obsolete + UINT32 CNOT; ///< Offset 0x1BC obsolete + UINT32 NRDY; ///< Offset 0x1C0 Driver Status + UINT8 DID2[0x1C]; ///< Offset 0x1C4 Extended Supported Devices ID List (DOD) + UINT8 CPD2[0x1C]; ///< Offset 0x1E0 obsolete + UINT8 RM12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero +} IGD_OPREGION_MBOX1_VER_3_0; + +/// +/// OpRegion Mailbox 2 - Backlight communication /// Offset 0x200, Size +0x100 /// typedef struct { + UINT32 BCL1; ///< Offset 0x200 Backlight Brightness for LFP1 + UINT32 BCL2; ///< Offset 0x204 Backlight Brightness for LFP2 + UINT32 CBL1; ///< Offset 0x208 Current User Brightness Level for LFP1 + UINT32 CBL2; ///< Offset 0x20C Current User Brightness Level for LFP2 + UINT32 BCM1[0x1E]; ///< Offset 0x210 Backlight Brightness Levels Duty Cycle Mapping Table for LFP1 + UINT32 BCM2[0x1E]; ///< Offset 0x288 Backlight Brightness Levels Duty Cycle Mapping Table for LFP2 +} IGD_OPREGION_MBOX2_VER_3_0; + +/// +/// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support /// +Offset 0x300, Size 0x100 /// typedef struct { + UINT32 ARDY; ///< Offset 0x300 obsolete + UINT32 ASLC; ///< Offset 0x304 obsolete + UINT32 TCHE; ///< Offset 0x308 obsolete + UINT32 ALSI; ///< Offset 0x30C obsolete + UINT32 BCLP; ///< Offset 0x310 obsoleted in ver 3.0, moved to Mailbox 2. + UINT32 PFIT; ///< Offset 0x314 obsolete + UINT32 CBLV; ///< Offset 0x318 obsoleted in ver 3.0, moved to Mailbox 2. + UINT16 BCLM[0x14]; ///< Offset 0x31C obsoleted in ver 3.0, moved to Mailbox 2. + UINT32 CPFM; ///< Offset 0x344 obsolete + UINT32 EPFM; ///< Offset 0x348 obsolete + UINT8 PLUT[0x4A]; ///< Offset 0x34C obsolete + UINT32 PFMB; ///< Offset 0x396 obsolete + UINT32 CCDV; ///< Offset 0x39A obsolete + UINT32 PCFT; ///< Offset 0x39E obsolete + UINT32 SROT; ///< Offset 0x3A2 obsolete + UINT32 IUER; ///< Offset 0x3A6 obsolete + UINT64 FDSS; ///< Offset 0x3AA obsolete + UINT32 FDSP; ///< Offset 0x3B2 obsolete + UINT32 STAT; ///< Offset 0x3B6 obsolete + UINT64 RVDA; ///< Offset 0x3BA Physical address of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB. + UINT32 RVDS; ///< Offset 0x3C2 Size of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB. + UINT8 VRSR; ///< Offset 0x3C6 Video RAM Self Refresh + UINT64 DLHP; ///< Offset 0x3C7 Dual LFP Hinge Alignment Parameters + UINT8 RM32[0x31]; ///< Offset 0x3CF - 0x3FF Reserved Must be zero. +} IGD_OPREGION_MBOX3_VER_3_0; + +/// +/// IGD OpRegion Structure +/// +typedef struct { + IGD_OPREGION_HEADER Header; ///< OpRegion header (Offset 0x0, Size 0x100) + IGD_OPREGION_MBOX1_VER_3_0 MBox1; ///< Mailbox 1: Public ACPI +Methods (Offset 0x100, Size 0x100) + IGD_OPREGION_MBOX2_VER_3_0 MBox2; ///< Mailbox 2: Backlight +communication (Offset 0x200, Size 0x100) + IGD_OPREGION_MBOX3_VER_3_0 MBox3; ///< Mailbox 3: BIOS to Driver Notification (Offset 0x300, Size 0x100) + IGD_OPREGION_MBOX4 MBox4; ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1800) + IGD_OPREGION_MBOX5 MBox5; ///< Mailbox 5: BIOS to Driver Notification Extension (Offset 0x1C00, Size 0x400) +} IGD_OPREGION_STRUCTURE_VER_3_0; +#pragma pack() + +#endif -- 2.30.2.windows.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0 2021-07-23 13:55 ` Digant H Solanki @ 2021-07-28 6:44 ` Digant H Solanki 0 siblings, 0 replies; 6+ messages in thread From: Digant H Solanki @ 2021-07-28 6:44 UTC (permalink / raw) To: devel@edk2.groups.io; +Cc: Ni, Ray, Chaganty, Rangasai V, S, Ashraf Ali Please help review this patch to make it official soon. Thanks..!! -----Original Message----- From: Solanki, Digant H Sent: Friday, July 23, 2021 7:25 PM To: devel@edk2.groups.io Cc: Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; S, Ashraf Ali <ashraf.ali.s@intel.com> Subject: RE: [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0 Gentle reminder to review this patch pls. Thanks..!! -----Original Message----- From: Solanki, Digant H <digant.h.solanki@intel.com> Sent: Thursday, July 22, 2021 5:17 PM To: devel@edk2.groups.io Cc: Solanki, Digant H <digant.h.solanki@intel.com>; Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; S, Ashraf Ali <ashraf.ali.s@intel.com> Subject: [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0 REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3426 - There are many OpRegion fields obsoleted in MBOX1 - MBOX2 is re-purposed for Backlight related fields for dual LFP. - Backlight related fields moved to MBOX2 from MBOX3 and some fields are obsoleted in MBOX3. Signed-off-by: Digant H Solanki <digant.h.solanki@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> --- Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h | 101 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h new file mode 100644 index 0000000000..c9948ab55f --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion +++ 30.h @@ -0,0 +1,101 @@ +/** @file + IGD OpRegion definition from Intel Integrated Graphics Device +OpRegion + Specification based on version 3.0. + + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _IGD_OPREGION_3_0_H_ +#define _IGD_OPREGION_3_0_H_ + +#include "IgdOpRegion.h" + +#define IGD_OPREGION_HEADER_MBOX2_VER_3_0 BIT5 + +#pragma pack(1) +/// +/// OpRegion Mailbox 1 - Public ACPI Methods /// Offset 0x100, Size +0x100 /// typedef struct { + UINT32 DRDY; ///< Offset 0x100 Driver Readiness + UINT32 CSTS; ///< Offset 0x104 Status + UINT32 CEVT; ///< Offset 0x108 Current Event + UINT8 RM11[0x14]; ///< Offset 0x10C Reserved Must be Zero + UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List + UINT32 CPDL[8]; ///< Offset 0x140 obsolete + UINT32 CADL[8]; ///< Offset 0x160 obsolete + UINT32 NADL[8]; ///< Offset 0x180 obsolete + UINT32 ASLP; ///< Offset 0x1A0 ASL Sleep Time Out + UINT32 TIDX; ///< Offset 0x1A4 obsolete + UINT32 CHPD; ///< Offset 0x1A8 obsolete + UINT32 CLID; ///< Offset 0x1AC Current Lid State Indicator + UINT32 CDCK; ///< Offset 0x1B0 Current Docking State Indicator + UINT32 SXSW; ///< Offset 0x1B4 obsolete + UINT32 EVTS; ///< Offset 0x1B8 obsolete + UINT32 CNOT; ///< Offset 0x1BC obsolete + UINT32 NRDY; ///< Offset 0x1C0 Driver Status + UINT8 DID2[0x1C]; ///< Offset 0x1C4 Extended Supported Devices ID List (DOD) + UINT8 CPD2[0x1C]; ///< Offset 0x1E0 obsolete + UINT8 RM12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero +} IGD_OPREGION_MBOX1_VER_3_0; + +/// +/// OpRegion Mailbox 2 - Backlight communication /// Offset 0x200, Size +0x100 /// typedef struct { + UINT32 BCL1; ///< Offset 0x200 Backlight Brightness for LFP1 + UINT32 BCL2; ///< Offset 0x204 Backlight Brightness for LFP2 + UINT32 CBL1; ///< Offset 0x208 Current User Brightness Level for LFP1 + UINT32 CBL2; ///< Offset 0x20C Current User Brightness Level for LFP2 + UINT32 BCM1[0x1E]; ///< Offset 0x210 Backlight Brightness Levels Duty Cycle Mapping Table for LFP1 + UINT32 BCM2[0x1E]; ///< Offset 0x288 Backlight Brightness Levels Duty Cycle Mapping Table for LFP2 +} IGD_OPREGION_MBOX2_VER_3_0; + +/// +/// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support /// +Offset 0x300, Size 0x100 /// typedef struct { + UINT32 ARDY; ///< Offset 0x300 obsolete + UINT32 ASLC; ///< Offset 0x304 obsolete + UINT32 TCHE; ///< Offset 0x308 obsolete + UINT32 ALSI; ///< Offset 0x30C obsolete + UINT32 BCLP; ///< Offset 0x310 obsoleted in ver 3.0, moved to Mailbox 2. + UINT32 PFIT; ///< Offset 0x314 obsolete + UINT32 CBLV; ///< Offset 0x318 obsoleted in ver 3.0, moved to Mailbox 2. + UINT16 BCLM[0x14]; ///< Offset 0x31C obsoleted in ver 3.0, moved to Mailbox 2. + UINT32 CPFM; ///< Offset 0x344 obsolete + UINT32 EPFM; ///< Offset 0x348 obsolete + UINT8 PLUT[0x4A]; ///< Offset 0x34C obsolete + UINT32 PFMB; ///< Offset 0x396 obsolete + UINT32 CCDV; ///< Offset 0x39A obsolete + UINT32 PCFT; ///< Offset 0x39E obsolete + UINT32 SROT; ///< Offset 0x3A2 obsolete + UINT32 IUER; ///< Offset 0x3A6 obsolete + UINT64 FDSS; ///< Offset 0x3AA obsolete + UINT32 FDSP; ///< Offset 0x3B2 obsolete + UINT32 STAT; ///< Offset 0x3B6 obsolete + UINT64 RVDA; ///< Offset 0x3BA Physical address of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB. + UINT32 RVDS; ///< Offset 0x3C2 Size of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB. + UINT8 VRSR; ///< Offset 0x3C6 Video RAM Self Refresh + UINT64 DLHP; ///< Offset 0x3C7 Dual LFP Hinge Alignment Parameters + UINT8 RM32[0x31]; ///< Offset 0x3CF - 0x3FF Reserved Must be zero. +} IGD_OPREGION_MBOX3_VER_3_0; + +/// +/// IGD OpRegion Structure +/// +typedef struct { + IGD_OPREGION_HEADER Header; ///< OpRegion header (Offset 0x0, Size 0x100) + IGD_OPREGION_MBOX1_VER_3_0 MBox1; ///< Mailbox 1: Public ACPI +Methods (Offset 0x100, Size 0x100) + IGD_OPREGION_MBOX2_VER_3_0 MBox2; ///< Mailbox 2: Backlight +communication (Offset 0x200, Size 0x100) + IGD_OPREGION_MBOX3_VER_3_0 MBox3; ///< Mailbox 3: BIOS to Driver Notification (Offset 0x300, Size 0x100) + IGD_OPREGION_MBOX4 MBox4; ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1800) + IGD_OPREGION_MBOX5 MBox5; ///< Mailbox 5: BIOS to Driver Notification Extension (Offset 0x1C00, Size 0x400) +} IGD_OPREGION_STRUCTURE_VER_3_0; +#pragma pack() + +#endif -- 2.30.2.windows.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0 2021-07-22 11:46 [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0 Digant H Solanki 2021-07-23 13:55 ` Digant H Solanki @ 2021-07-28 17:47 ` Chaganty, Rangasai V 2021-07-28 17:54 ` Chaganty, Rangasai V 1 sibling, 1 reply; 6+ messages in thread From: Chaganty, Rangasai V @ 2021-07-28 17:47 UTC (permalink / raw) To: Solanki, Digant H, devel@edk2.groups.io; +Cc: Ni, Ray, S, Ashraf Ali Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com> -----Original Message----- From: Solanki, Digant H <digant.h.solanki@intel.com> Sent: Thursday, July 22, 2021 4:47 AM To: devel@edk2.groups.io Cc: Solanki, Digant H <digant.h.solanki@intel.com>; Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; S, Ashraf Ali <ashraf.ali.s@intel.com> Subject: [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0 REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3426 - There are many OpRegion fields obsoleted in MBOX1 - MBOX2 is re-purposed for Backlight related fields for dual LFP. - Backlight related fields moved to MBOX2 from MBOX3 and some fields are obsoleted in MBOX3. Signed-off-by: Digant H Solanki <digant.h.solanki@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> --- Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h | 101 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h new file mode 100644 index 0000000000..c9948ab55f --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion +++ 30.h @@ -0,0 +1,101 @@ +/** @file + IGD OpRegion definition from Intel Integrated Graphics Device +OpRegion + Specification based on version 3.0. + + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _IGD_OPREGION_3_0_H_ +#define _IGD_OPREGION_3_0_H_ + +#include "IgdOpRegion.h" + +#define IGD_OPREGION_HEADER_MBOX2_VER_3_0 BIT5 + +#pragma pack(1) +/// +/// OpRegion Mailbox 1 - Public ACPI Methods /// Offset 0x100, Size +0x100 /// typedef struct { + UINT32 DRDY; ///< Offset 0x100 Driver Readiness + UINT32 CSTS; ///< Offset 0x104 Status + UINT32 CEVT; ///< Offset 0x108 Current Event + UINT8 RM11[0x14]; ///< Offset 0x10C Reserved Must be Zero + UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List + UINT32 CPDL[8]; ///< Offset 0x140 obsolete + UINT32 CADL[8]; ///< Offset 0x160 obsolete + UINT32 NADL[8]; ///< Offset 0x180 obsolete + UINT32 ASLP; ///< Offset 0x1A0 ASL Sleep Time Out + UINT32 TIDX; ///< Offset 0x1A4 obsolete + UINT32 CHPD; ///< Offset 0x1A8 obsolete + UINT32 CLID; ///< Offset 0x1AC Current Lid State Indicator + UINT32 CDCK; ///< Offset 0x1B0 Current Docking State Indicator + UINT32 SXSW; ///< Offset 0x1B4 obsolete + UINT32 EVTS; ///< Offset 0x1B8 obsolete + UINT32 CNOT; ///< Offset 0x1BC obsolete + UINT32 NRDY; ///< Offset 0x1C0 Driver Status + UINT8 DID2[0x1C]; ///< Offset 0x1C4 Extended Supported Devices ID List (DOD) + UINT8 CPD2[0x1C]; ///< Offset 0x1E0 obsolete + UINT8 RM12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero +} IGD_OPREGION_MBOX1_VER_3_0; + +/// +/// OpRegion Mailbox 2 - Backlight communication /// Offset 0x200, Size +0x100 /// typedef struct { + UINT32 BCL1; ///< Offset 0x200 Backlight Brightness for LFP1 + UINT32 BCL2; ///< Offset 0x204 Backlight Brightness for LFP2 + UINT32 CBL1; ///< Offset 0x208 Current User Brightness Level for LFP1 + UINT32 CBL2; ///< Offset 0x20C Current User Brightness Level for LFP2 + UINT32 BCM1[0x1E]; ///< Offset 0x210 Backlight Brightness Levels Duty Cycle Mapping Table for LFP1 + UINT32 BCM2[0x1E]; ///< Offset 0x288 Backlight Brightness Levels Duty Cycle Mapping Table for LFP2 +} IGD_OPREGION_MBOX2_VER_3_0; + +/// +/// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support /// +Offset 0x300, Size 0x100 /// typedef struct { + UINT32 ARDY; ///< Offset 0x300 obsolete + UINT32 ASLC; ///< Offset 0x304 obsolete + UINT32 TCHE; ///< Offset 0x308 obsolete + UINT32 ALSI; ///< Offset 0x30C obsolete + UINT32 BCLP; ///< Offset 0x310 obsoleted in ver 3.0, moved to Mailbox 2. + UINT32 PFIT; ///< Offset 0x314 obsolete + UINT32 CBLV; ///< Offset 0x318 obsoleted in ver 3.0, moved to Mailbox 2. + UINT16 BCLM[0x14]; ///< Offset 0x31C obsoleted in ver 3.0, moved to Mailbox 2. + UINT32 CPFM; ///< Offset 0x344 obsolete + UINT32 EPFM; ///< Offset 0x348 obsolete + UINT8 PLUT[0x4A]; ///< Offset 0x34C obsolete + UINT32 PFMB; ///< Offset 0x396 obsolete + UINT32 CCDV; ///< Offset 0x39A obsolete + UINT32 PCFT; ///< Offset 0x39E obsolete + UINT32 SROT; ///< Offset 0x3A2 obsolete + UINT32 IUER; ///< Offset 0x3A6 obsolete + UINT64 FDSS; ///< Offset 0x3AA obsolete + UINT32 FDSP; ///< Offset 0x3B2 obsolete + UINT32 STAT; ///< Offset 0x3B6 obsolete + UINT64 RVDA; ///< Offset 0x3BA Physical address of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB. + UINT32 RVDS; ///< Offset 0x3C2 Size of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB. + UINT8 VRSR; ///< Offset 0x3C6 Video RAM Self Refresh + UINT64 DLHP; ///< Offset 0x3C7 Dual LFP Hinge Alignment Parameters + UINT8 RM32[0x31]; ///< Offset 0x3CF - 0x3FF Reserved Must be zero. +} IGD_OPREGION_MBOX3_VER_3_0; + +/// +/// IGD OpRegion Structure +/// +typedef struct { + IGD_OPREGION_HEADER Header; ///< OpRegion header (Offset 0x0, Size 0x100) + IGD_OPREGION_MBOX1_VER_3_0 MBox1; ///< Mailbox 1: Public ACPI +Methods (Offset 0x100, Size 0x100) + IGD_OPREGION_MBOX2_VER_3_0 MBox2; ///< Mailbox 2: Backlight +communication (Offset 0x200, Size 0x100) + IGD_OPREGION_MBOX3_VER_3_0 MBox3; ///< Mailbox 3: BIOS to Driver Notification (Offset 0x300, Size 0x100) + IGD_OPREGION_MBOX4 MBox4; ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1800) + IGD_OPREGION_MBOX5 MBox5; ///< Mailbox 5: BIOS to Driver Notification Extension (Offset 0x1C00, Size 0x400) +} IGD_OPREGION_STRUCTURE_VER_3_0; +#pragma pack() + +#endif -- 2.30.2.windows.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0 2021-07-28 17:47 ` Chaganty, Rangasai V @ 2021-07-28 17:54 ` Chaganty, Rangasai V 2021-07-29 4:53 ` Digant H Solanki 0 siblings, 1 reply; 6+ messages in thread From: Chaganty, Rangasai V @ 2021-07-28 17:54 UTC (permalink / raw) To: Solanki, Digant H, devel@edk2.groups.io; +Cc: Ni, Ray, S, Ashraf Ali Digant, The notation "PATCH 3/3" indicates part 3 of a 3 patch series. However since this is a single patch, the subject line could simply indicate [PATCH v3]. Something to consider for future reviews. Thanks, Sai -----Original Message----- From: Chaganty, Rangasai V Sent: Wednesday, July 28, 2021 10:48 AM To: Solanki, Digant H <digant.h.solanki@intel.com>; devel@edk2.groups.io Cc: Ni, Ray <ray.ni@intel.com>; S, Ashraf Ali <ashraf.ali.s@intel.com> Subject: RE: [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0 Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com> -----Original Message----- From: Solanki, Digant H <digant.h.solanki@intel.com> Sent: Thursday, July 22, 2021 4:47 AM To: devel@edk2.groups.io Cc: Solanki, Digant H <digant.h.solanki@intel.com>; Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; S, Ashraf Ali <ashraf.ali.s@intel.com> Subject: [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0 REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3426 - There are many OpRegion fields obsoleted in MBOX1 - MBOX2 is re-purposed for Backlight related fields for dual LFP. - Backlight related fields moved to MBOX2 from MBOX3 and some fields are obsoleted in MBOX3. Signed-off-by: Digant H Solanki <digant.h.solanki@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> --- Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h | 101 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h new file mode 100644 index 0000000000..c9948ab55f --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion +++ 30.h @@ -0,0 +1,101 @@ +/** @file + IGD OpRegion definition from Intel Integrated Graphics Device +OpRegion + Specification based on version 3.0. + + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _IGD_OPREGION_3_0_H_ +#define _IGD_OPREGION_3_0_H_ + +#include "IgdOpRegion.h" + +#define IGD_OPREGION_HEADER_MBOX2_VER_3_0 BIT5 + +#pragma pack(1) +/// +/// OpRegion Mailbox 1 - Public ACPI Methods /// Offset 0x100, Size +0x100 /// typedef struct { + UINT32 DRDY; ///< Offset 0x100 Driver Readiness + UINT32 CSTS; ///< Offset 0x104 Status + UINT32 CEVT; ///< Offset 0x108 Current Event + UINT8 RM11[0x14]; ///< Offset 0x10C Reserved Must be Zero + UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List + UINT32 CPDL[8]; ///< Offset 0x140 obsolete + UINT32 CADL[8]; ///< Offset 0x160 obsolete + UINT32 NADL[8]; ///< Offset 0x180 obsolete + UINT32 ASLP; ///< Offset 0x1A0 ASL Sleep Time Out + UINT32 TIDX; ///< Offset 0x1A4 obsolete + UINT32 CHPD; ///< Offset 0x1A8 obsolete + UINT32 CLID; ///< Offset 0x1AC Current Lid State Indicator + UINT32 CDCK; ///< Offset 0x1B0 Current Docking State Indicator + UINT32 SXSW; ///< Offset 0x1B4 obsolete + UINT32 EVTS; ///< Offset 0x1B8 obsolete + UINT32 CNOT; ///< Offset 0x1BC obsolete + UINT32 NRDY; ///< Offset 0x1C0 Driver Status + UINT8 DID2[0x1C]; ///< Offset 0x1C4 Extended Supported Devices ID List (DOD) + UINT8 CPD2[0x1C]; ///< Offset 0x1E0 obsolete + UINT8 RM12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero +} IGD_OPREGION_MBOX1_VER_3_0; + +/// +/// OpRegion Mailbox 2 - Backlight communication /// Offset 0x200, Size +0x100 /// typedef struct { + UINT32 BCL1; ///< Offset 0x200 Backlight Brightness for LFP1 + UINT32 BCL2; ///< Offset 0x204 Backlight Brightness for LFP2 + UINT32 CBL1; ///< Offset 0x208 Current User Brightness Level for LFP1 + UINT32 CBL2; ///< Offset 0x20C Current User Brightness Level for LFP2 + UINT32 BCM1[0x1E]; ///< Offset 0x210 Backlight Brightness Levels Duty Cycle Mapping Table for LFP1 + UINT32 BCM2[0x1E]; ///< Offset 0x288 Backlight Brightness Levels Duty Cycle Mapping Table for LFP2 +} IGD_OPREGION_MBOX2_VER_3_0; + +/// +/// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support /// +Offset 0x300, Size 0x100 /// typedef struct { + UINT32 ARDY; ///< Offset 0x300 obsolete + UINT32 ASLC; ///< Offset 0x304 obsolete + UINT32 TCHE; ///< Offset 0x308 obsolete + UINT32 ALSI; ///< Offset 0x30C obsolete + UINT32 BCLP; ///< Offset 0x310 obsoleted in ver 3.0, moved to Mailbox 2. + UINT32 PFIT; ///< Offset 0x314 obsolete + UINT32 CBLV; ///< Offset 0x318 obsoleted in ver 3.0, moved to Mailbox 2. + UINT16 BCLM[0x14]; ///< Offset 0x31C obsoleted in ver 3.0, moved to Mailbox 2. + UINT32 CPFM; ///< Offset 0x344 obsolete + UINT32 EPFM; ///< Offset 0x348 obsolete + UINT8 PLUT[0x4A]; ///< Offset 0x34C obsolete + UINT32 PFMB; ///< Offset 0x396 obsolete + UINT32 CCDV; ///< Offset 0x39A obsolete + UINT32 PCFT; ///< Offset 0x39E obsolete + UINT32 SROT; ///< Offset 0x3A2 obsolete + UINT32 IUER; ///< Offset 0x3A6 obsolete + UINT64 FDSS; ///< Offset 0x3AA obsolete + UINT32 FDSP; ///< Offset 0x3B2 obsolete + UINT32 STAT; ///< Offset 0x3B6 obsolete + UINT64 RVDA; ///< Offset 0x3BA Physical address of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB. + UINT32 RVDS; ///< Offset 0x3C2 Size of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB. + UINT8 VRSR; ///< Offset 0x3C6 Video RAM Self Refresh + UINT64 DLHP; ///< Offset 0x3C7 Dual LFP Hinge Alignment Parameters + UINT8 RM32[0x31]; ///< Offset 0x3CF - 0x3FF Reserved Must be zero. +} IGD_OPREGION_MBOX3_VER_3_0; + +/// +/// IGD OpRegion Structure +/// +typedef struct { + IGD_OPREGION_HEADER Header; ///< OpRegion header (Offset 0x0, Size 0x100) + IGD_OPREGION_MBOX1_VER_3_0 MBox1; ///< Mailbox 1: Public ACPI +Methods (Offset 0x100, Size 0x100) + IGD_OPREGION_MBOX2_VER_3_0 MBox2; ///< Mailbox 2: Backlight +communication (Offset 0x200, Size 0x100) + IGD_OPREGION_MBOX3_VER_3_0 MBox3; ///< Mailbox 3: BIOS to Driver Notification (Offset 0x300, Size 0x100) + IGD_OPREGION_MBOX4 MBox4; ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1800) + IGD_OPREGION_MBOX5 MBox5; ///< Mailbox 5: BIOS to Driver Notification Extension (Offset 0x1C00, Size 0x400) +} IGD_OPREGION_STRUCTURE_VER_3_0; +#pragma pack() + +#endif -- 2.30.2.windows.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0 2021-07-28 17:54 ` Chaganty, Rangasai V @ 2021-07-29 4:53 ` Digant H Solanki 0 siblings, 0 replies; 6+ messages in thread From: Digant H Solanki @ 2021-07-29 4:53 UTC (permalink / raw) To: Chaganty, Rangasai V, devel@edk2.groups.io; +Cc: Ni, Ray, S, Ashraf Ali Thanks for review and suggestion, Sai..!! -----Original Message----- From: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com> Sent: Wednesday, July 28, 2021 11:24 PM To: Solanki, Digant H <digant.h.solanki@intel.com>; devel@edk2.groups.io Cc: Ni, Ray <ray.ni@intel.com>; S, Ashraf Ali <ashraf.ali.s@intel.com> Subject: RE: [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0 Digant, The notation "PATCH 3/3" indicates part 3 of a 3 patch series. However since this is a single patch, the subject line could simply indicate [PATCH v3]. Something to consider for future reviews. Thanks, Sai -----Original Message----- From: Chaganty, Rangasai V Sent: Wednesday, July 28, 2021 10:48 AM To: Solanki, Digant H <digant.h.solanki@intel.com>; devel@edk2.groups.io Cc: Ni, Ray <ray.ni@intel.com>; S, Ashraf Ali <ashraf.ali.s@intel.com> Subject: RE: [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0 Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com> -----Original Message----- From: Solanki, Digant H <digant.h.solanki@intel.com> Sent: Thursday, July 22, 2021 4:47 AM To: devel@edk2.groups.io Cc: Solanki, Digant H <digant.h.solanki@intel.com>; Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; S, Ashraf Ali <ashraf.ali.s@intel.com> Subject: [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0 REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3426 - There are many OpRegion fields obsoleted in MBOX1 - MBOX2 is re-purposed for Backlight related fields for dual LFP. - Backlight related fields moved to MBOX2 from MBOX3 and some fields are obsoleted in MBOX3. Signed-off-by: Digant H Solanki <digant.h.solanki@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> --- Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h | 101 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h new file mode 100644 index 0000000000..c9948ab55f --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion +++ 30.h @@ -0,0 +1,101 @@ +/** @file + IGD OpRegion definition from Intel Integrated Graphics Device +OpRegion + Specification based on version 3.0. + + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _IGD_OPREGION_3_0_H_ +#define _IGD_OPREGION_3_0_H_ + +#include "IgdOpRegion.h" + +#define IGD_OPREGION_HEADER_MBOX2_VER_3_0 BIT5 + +#pragma pack(1) +/// +/// OpRegion Mailbox 1 - Public ACPI Methods /// Offset 0x100, Size +0x100 /// typedef struct { + UINT32 DRDY; ///< Offset 0x100 Driver Readiness + UINT32 CSTS; ///< Offset 0x104 Status + UINT32 CEVT; ///< Offset 0x108 Current Event + UINT8 RM11[0x14]; ///< Offset 0x10C Reserved Must be Zero + UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List + UINT32 CPDL[8]; ///< Offset 0x140 obsolete + UINT32 CADL[8]; ///< Offset 0x160 obsolete + UINT32 NADL[8]; ///< Offset 0x180 obsolete + UINT32 ASLP; ///< Offset 0x1A0 ASL Sleep Time Out + UINT32 TIDX; ///< Offset 0x1A4 obsolete + UINT32 CHPD; ///< Offset 0x1A8 obsolete + UINT32 CLID; ///< Offset 0x1AC Current Lid State Indicator + UINT32 CDCK; ///< Offset 0x1B0 Current Docking State Indicator + UINT32 SXSW; ///< Offset 0x1B4 obsolete + UINT32 EVTS; ///< Offset 0x1B8 obsolete + UINT32 CNOT; ///< Offset 0x1BC obsolete + UINT32 NRDY; ///< Offset 0x1C0 Driver Status + UINT8 DID2[0x1C]; ///< Offset 0x1C4 Extended Supported Devices ID List (DOD) + UINT8 CPD2[0x1C]; ///< Offset 0x1E0 obsolete + UINT8 RM12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero +} IGD_OPREGION_MBOX1_VER_3_0; + +/// +/// OpRegion Mailbox 2 - Backlight communication /// Offset 0x200, Size +0x100 /// typedef struct { + UINT32 BCL1; ///< Offset 0x200 Backlight Brightness for LFP1 + UINT32 BCL2; ///< Offset 0x204 Backlight Brightness for LFP2 + UINT32 CBL1; ///< Offset 0x208 Current User Brightness Level for LFP1 + UINT32 CBL2; ///< Offset 0x20C Current User Brightness Level for LFP2 + UINT32 BCM1[0x1E]; ///< Offset 0x210 Backlight Brightness Levels Duty Cycle Mapping Table for LFP1 + UINT32 BCM2[0x1E]; ///< Offset 0x288 Backlight Brightness Levels Duty Cycle Mapping Table for LFP2 +} IGD_OPREGION_MBOX2_VER_3_0; + +/// +/// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support /// +Offset 0x300, Size 0x100 /// typedef struct { + UINT32 ARDY; ///< Offset 0x300 obsolete + UINT32 ASLC; ///< Offset 0x304 obsolete + UINT32 TCHE; ///< Offset 0x308 obsolete + UINT32 ALSI; ///< Offset 0x30C obsolete + UINT32 BCLP; ///< Offset 0x310 obsoleted in ver 3.0, moved to Mailbox 2. + UINT32 PFIT; ///< Offset 0x314 obsolete + UINT32 CBLV; ///< Offset 0x318 obsoleted in ver 3.0, moved to Mailbox 2. + UINT16 BCLM[0x14]; ///< Offset 0x31C obsoleted in ver 3.0, moved to Mailbox 2. + UINT32 CPFM; ///< Offset 0x344 obsolete + UINT32 EPFM; ///< Offset 0x348 obsolete + UINT8 PLUT[0x4A]; ///< Offset 0x34C obsolete + UINT32 PFMB; ///< Offset 0x396 obsolete + UINT32 CCDV; ///< Offset 0x39A obsolete + UINT32 PCFT; ///< Offset 0x39E obsolete + UINT32 SROT; ///< Offset 0x3A2 obsolete + UINT32 IUER; ///< Offset 0x3A6 obsolete + UINT64 FDSS; ///< Offset 0x3AA obsolete + UINT32 FDSP; ///< Offset 0x3B2 obsolete + UINT32 STAT; ///< Offset 0x3B6 obsolete + UINT64 RVDA; ///< Offset 0x3BA Physical address of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB. + UINT32 RVDS; ///< Offset 0x3C2 Size of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB. + UINT8 VRSR; ///< Offset 0x3C6 Video RAM Self Refresh + UINT64 DLHP; ///< Offset 0x3C7 Dual LFP Hinge Alignment Parameters + UINT8 RM32[0x31]; ///< Offset 0x3CF - 0x3FF Reserved Must be zero. +} IGD_OPREGION_MBOX3_VER_3_0; + +/// +/// IGD OpRegion Structure +/// +typedef struct { + IGD_OPREGION_HEADER Header; ///< OpRegion header (Offset 0x0, Size 0x100) + IGD_OPREGION_MBOX1_VER_3_0 MBox1; ///< Mailbox 1: Public ACPI +Methods (Offset 0x100, Size 0x100) + IGD_OPREGION_MBOX2_VER_3_0 MBox2; ///< Mailbox 2: Backlight +communication (Offset 0x200, Size 0x100) + IGD_OPREGION_MBOX3_VER_3_0 MBox3; ///< Mailbox 3: BIOS to Driver Notification (Offset 0x300, Size 0x100) + IGD_OPREGION_MBOX4 MBox4; ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1800) + IGD_OPREGION_MBOX5 MBox5; ///< Mailbox 5: BIOS to Driver Notification Extension (Offset 0x1C00, Size 0x400) +} IGD_OPREGION_STRUCTURE_VER_3_0; +#pragma pack() + +#endif -- 2.30.2.windows.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-07-29 4:53 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-07-22 11:46 [PATCH 3/3] IntelSiliconPkg: Add IgdOpRegion30.h to support IGD OpRegion v3.0 Digant H Solanki 2021-07-23 13:55 ` Digant H Solanki 2021-07-28 6:44 ` Digant H Solanki 2021-07-28 17:47 ` Chaganty, Rangasai V 2021-07-28 17:54 ` Chaganty, Rangasai V 2021-07-29 4:53 ` Digant H Solanki
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