From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id 6015FD8065A for ; Wed, 24 Jul 2024 17:50:26 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=6gyLhz8tl5/gzO0HLQXeXyfXi+zHGrWVsJ9g4Y9oMNs=; c=relaxed/simple; d=groups.io; h=From:To:Subject:Thread-Topic:Thread-Index:Date:Message-ID:Accept-Language:msip_labels:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type; s=20240206; t=1721843426; v=1; b=VAJTIteJPryAIiaihgjPqvVHNVNQnRwsd0m0aDOTiwfO0+geixIKYyjanY364LQCHg3wCin8 jrcQGoKcEN+PDENZgujYN7LGAMD8d9jczbhHtaFjvr656dRugii104PvtAYJO2KNHBjRVeUU4go VmweoD2uevYgjGTVX7vuVibQXo7VI22MCfeyodq7Nn2duBtY7am6mhxfugW5HvlQ2fXI7bcS19r XAW06jxznrAWqVWsg6O0RLLAXBGMiAXnKNLzvloFXj6wbIBhTLF3Tnr1/ocknYMEBNsWWQ24sQe dp3YxY3XqpyaqF4395h+sdvrcQ5nf2fmX0hNjjnlepfog== X-Received: by 127.0.0.2 with SMTP id 1W5YYY7687511xoLFVFEf1BO; Wed, 24 Jul 2024 10:50:24 -0700 X-Received: from NAM11-BN8-obe.outbound.protection.outlook.com (NAM11-BN8-obe.outbound.protection.outlook.com [40.92.20.97]) by mx.groups.io with SMTP id smtpd.web10.13665.1721834983657736853 for ; Wed, 24 Jul 2024 08:29:44 -0700 X-Received: from SJ0PR12MB6926.namprd12.prod.outlook.com (2603:10b6:a03:485::8) by DM3PR12MB9327.namprd12.prod.outlook.com (2603:10b6:0:42::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7784.16; Wed, 24 Jul 2024 15:29:40 +0000 X-Received: from SJ0PR12MB6926.namprd12.prod.outlook.com ([fe80::58b4:3ef5:8613:3b28]) by SJ0PR12MB6926.namprd12.prod.outlook.com ([fe80::58b4:3ef5:8613:3b28%7]) with mapi id 15.20.7784.020; Wed, 24 Jul 2024 15:29:40 +0000 From: "Arminder Singh" To: "devel@edk2.groups.io" Subject: [edk2-devel] [Question] How do you set PCIe host bridge address space granularity for a PCI host bridge defined with PciHostBridgeLib? Thread-Topic: [Question] How do you set PCIe host bridge address space granularity for a PCI host bridge defined with PciHostBridgeLib? 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contact devel+owner@edk2.groups.io Resent-Date: Wed, 24 Jul 2024 10:50:19 -0700 Resent-From: arminders208@outlook.com Reply-To: devel@edk2.groups.io,arminders208@outlook.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: P7YVieXHj6IqzwsB2vpt70VVx7686176AA= Content-Language: en-US Content-Type: multipart/mixed; boundary="_004_SJ0PR12MB6926A2164541379115C26D7A9FAA2SJ0PR12MB6926namp_" X-Spam-Flag: yes X-Spam-Level: ************ X-GND-Spam-Score: 190 X-GND-Status: SPAM Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=VAJTIteJ; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=outlook.com (policy=none) --_004_SJ0PR12MB6926A2164541379115C26D7A9FAA2SJ0PR12MB6926namp_ Content-Type: multipart/alternative; boundary="_000_SJ0PR12MB6926A2164541379115C26D7A9FAA2SJ0PR12MB6926namp_" --_000_SJ0PR12MB6926A2164541379115C26D7A9FAA2SJ0PR12MB6926namp_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hello, I'm bringing up EDK2 (technically Project Mu, but the parts I'm concerned a= bout are pretty much the exact same as in base EDK2 so it should be mostly = the same) on a platform (platforms repo here: https://github.com/AppleWOA/a= pple_silicon_platforms_mu, PciHostBridgeLib is in Silicon/Apple/AppleSilico= nPkg/Library/AppleSiliconPciHostBridgeLib), and I'm having some trouble wit= h the PCIe Host Bridge and the PciHostBridgeDxe. Following the example of J= unoPkg in edk2-platforms, I'm making a PcieHostBridgeLib for my platform, b= ut for some reason, it's assuming the address space granularity to be 32 bi= t (it should be in 64 bit address space as default, the platform i'm bringi= ng up on does have a 32-bit aperture, but adding the translation to make th= at work in PciHostBridgeLib isn't working either, hitting an ASSERT in a ba= se EDK2 component), which is causing the platform to do an invalid memory a= ccess. Is there a way I can set the host bridge's address space granularity and fo= rce it to be 64-bit? I tried defining the bridge in the DSDT, but it didn't= seem to really have any effect, and looking at the base EDK2 PciHostBridge= Dxe and PciBusDxe drivers seems to show that the address space granularity = is defined when an autogenerated ACPI descriptor is made, so i'm not sure h= ow I would safely change it. Any help would be appreciated. Boot log from DXE core onwards attached for convenience, part I'm concerned= about is around when it says to SubmitResources for PciRoot(0x0) Thanks, Arminder -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#120026): https://edk2.groups.io/g/devel/message/120026 Mute This Topic: https://groups.io/mt/107528139/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --_000_SJ0PR12MB6926A2164541379115C26D7A9FAA2SJ0PR12MB6926namp_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable
Hello,

I'm bringing up EDK2 (technically Project Mu, but the parts I'm concerned a= bout are pretty much the exact same as in base EDK2 so it should be mostly = the same) on a platform (platforms repo here: https://github.com/AppleWOA/apple_silicon_platforms_mu, PciHostBridgeLi= b is in Silicon/Apple/AppleSiliconPkg/Library/AppleSiliconPciHostBridgeLib)= , and I'm having some trouble with the PCIe Host Bridge and the PciHostBrid= geDxe. Following the example of JunoPkg in edk2-platforms, I'm making a PcieHostBridgeLib for my platform,= but for some reason, it's assuming the address space granularity to be 32 = bit (it should be in 64 bit address space as default, the platform i'm brin= ging up on does have a 32-bit aperture, but adding the translation to make that work in PciHostBridgeLib isn't wor= king either, hitting an ASSERT in a base EDK2 component), which is causing = the platform to do an invalid memory access.

Is there a way I can set the host bridge's address space granularity and fo= rce it to be 64-bit? I tried defining the bridge in the DSDT, but it didn't= seem to really have any effect, and looking at the base EDK2 PciHostBridge= Dxe and PciBusDxe drivers seems to show that the address space granularity is defined when an autogenerate= d ACPI descriptor is made, so i'm not sure how I would safely change it. An= y help would be appreciated.

Boot log from DXE core onwards attached for convenience, part I'm concerned= about is around when it says to SubmitResources for PciRoot(0x0)

Thanks,
Arminder
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